Photoelectric conversion device and device

Abstract

To provide a technique advantageous in improving an imaging performance while realizing a global electronic shutter function.SOLUTION: A photoelectric conversion device includes a plurality of pixels and a processing circuit that processes a signal read from the plurality of pixels, and a plurality of semiconductor substrates are stacked. Each pixel includes a photoelectric conversion element, an amplification part that amplifies a signal from the photoelectric conversion element, and a holding capacitor that holds an output of the amplification part, and further includes a bias generation part that supplies a bias potential for operating the amplification part to the amplification part. The plurality of semiconductor substrates include a first semiconductor substrate on which the photoelectric conversion element is disposed, a second semiconductor substrate on which the holding capacitor is disposed, and a third semiconductor substrate on which the processing circuit is disposed, and the second semiconductor substrate is disposed between the first semiconductor substrate and the third semiconductor substrate. The amplification part includes an element disposed on the first semiconductor substrate and an element disposed on the second semiconductor substrate, and the bias generation part is disposed on the third semiconductor substrate.SELECTED DRAWING: Figure 20

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and an apparatus. [Background technology]

[0002] It has been proposed that a photoelectric conversion device perform a global electronic shutter operation that simultaneously resets the photoelectric conversion elements arranged in each of a plurality of pixels and reads out charges from the photoelectric conversion elements. Patent Document 1 shows an image sensor equipped with a voltage-holding global electronic shutter function that converts signal charges into voltage and holds them. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-051548 Summary of the Invention [Problem to be solved by the invention]

[0004] In order to improve the imaging performance of a photoelectric conversion device, it is conceivable to stack a plurality of semiconductor substrates and disperse each component of the photoelectric conversion device on each substrate.

[0005] An object of the present invention is to provide a technique that is advantageous in improving imaging performance while realizing a global electronic shutter function. [Means for solving the problem]

[0006] In view of the above problems, a photoelectric conversion device according to an embodiment of the present invention is a photoelectric conversion device comprising a plurality of pixels and a processing circuit that processes signals read out from the plurality of pixels, and in which a plurality of semiconductor substrates are stacked, wherein each of the plurality of pixels comprises a photoelectric conversion element, an amplifier unit that amplifies a signal from the photoelectric conversion element, and a storage capacitor that stores the output of the amplifier unit, the photoelectric conversion device further comprises a bias generation unit that supplies a bias potential to the amplifier unit for operating the amplifier unit, the plurality of semiconductor substrates comprising a first semiconductor substrate on which the photoelectric conversion element is arranged, a second semiconductor substrate on which the storage capacitor is arranged, and a third semiconductor substrate on which the processing circuit is arranged, the second semiconductor substrate being arranged between the first semiconductor substrate and the third semiconductor substrate, the amplifier unit including an element arranged on the first semiconductor substrate and an element arranged on the second semiconductor substrate, and the bias generation unit being arranged on the third semiconductor substrate. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a technique that is advantageous for improving the performance of a photoelectric conversion device. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a photoelectric conversion device according to an embodiment of the present invention. [Figure 2] 2 is a circuit diagram showing an example of the configuration of a pixel and a processing circuit of the photoelectric conversion device of FIG. 1. [Figure 3] FIG. 2 is a diagram illustrating the drive timing of the photoelectric conversion device of FIG. 1. [Figure 4] 2 is a circuit diagram showing an example of the configuration of a pixel and a processing circuit of the photoelectric conversion device of FIG. 1. [Figure 5] FIG. 2 is a diagram showing an example of the configuration of a stacked structure of the photoelectric conversion device of FIG. 1. [Figure 6] 2 is a circuit diagram showing an example of the configuration of a pixel and a processing circuit of the photoelectric conversion device of FIG. 1. [Figure 7] FIG. 2 is a diagram showing an example of the configuration of a stacked structure of the photoelectric conversion device of FIG. 1. [Figure 8] 2 is a circuit diagram showing an example of the configuration of a pixel and a processing circuit of the photoelectric conversion device of FIG. 1. [Figure 9] FIG. 2 is a diagram showing an example of the configuration of a stacked structure of the photoelectric conversion device of FIG. 1. [Figure 10] 2 is a circuit diagram showing an example of the configuration of a pixel and a processing circuit of the photoelectric conversion device of FIG. 1. [Figure 11] FIG. 2 is a diagram showing an example of the configuration of a stacked structure of the photoelectric conversion device of FIG. 1. [Figure 12] FIG. 2 is a diagram showing an example of the configuration of a stacked structure of the photoelectric conversion device of FIG. 1. [Figure 13] 2 is a circuit diagram showing an example of the configuration of a pixel and a processing circuit of the photoelectric conversion device of FIG. 1. [Figure 14] FIG. 2 is a diagram showing an example of the configuration of a stacked structure of the photoelectric conversion device of FIG. 1. [Figure 15] FIG. 2 is a diagram showing an example of the configuration of a stacked structure of the photoelectric conversion device of FIG. 1. [Figure 16] 2 is a circuit diagram showing an example of the configuration of a pixel and a processing circuit of the photoelectric conversion device of FIG. 1. [Figure 17] FIG. 2 is a diagram showing an example of the configuration of a stacked structure of the photoelectric conversion device of FIG. 1. [Figure 18] 2 is a circuit diagram showing an example of the configuration of a pixel and a processing circuit of the photoelectric conversion device of FIG. 1. [Figure 19] FIG. 2 is a diagram showing an example of the configuration of a stacked structure of the photoelectric conversion device of FIG. 1. [Figure 20] 2 is a circuit diagram showing an example of the configuration of a pixel and a processing circuit of the photoelectric conversion device of FIG. 1. [Figure 21] FIG. 2 is a diagram showing an example of the configuration of a stacked structure of the photoelectric conversion device of FIG. 1. [Figure 22] 2 is a circuit diagram showing an example of the configuration of a pixel and a processing circuit of the photoelectric conversion device of FIG. 1. [Figure 23] FIG. 2 is a diagram showing an example of the configuration of a stacked structure of the photoelectric conversion device of FIG. 1. [Figure 24] FIG. 2 is a diagram showing an example of the configuration of a device incorporating the photoelectric conversion device of FIG. 1. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0010] A photoelectric conversion device according to an embodiment of the present disclosure will be described with reference to FIGS. 1 to 23. FIG. 1 is a schematic diagram of a photoelectric conversion device 1 according to this embodiment. The photoelectric conversion device 1 photoelectrically converts a received subject image, performs analog-to-digital (AD) conversion on the resulting electrical signal, and outputs it as a digital signal. The photoelectric conversion device 1 includes a pixel unit 10, a timing generation unit 20, a drive control unit 30, an amplifier unit 40, an AD conversion unit 50, a memory unit 60, a readout scanning unit 70, a digital signal processing unit 80, and an output unit 90. The pixel unit 10 includes a plurality of pixels 11 arranged in a two-dimensional matrix to form a plurality of rows and a plurality of columns. Bias generation units 12, 41, and 51 are connected to the pixel unit 10, the amplifier unit 40, and the AD conversion unit 50, respectively, and bias potentials for the operation of the pixel unit 10, the amplifier unit 40, and the AD conversion unit 50 are supplied. The amplifier 40 and AD converter 50 that process signals read out from the plurality of pixels 11, more specifically, analog signals, may hereinafter be referred to as a processing circuit.

[0011] The pixels 11 accumulate charges corresponding to incident light through photoelectric conversion, convert the charge signals to voltages, and output them as pixel signals. The drive control unit 30 controls the resetting of the pixels 11, the transfer of signals within the pixels 11, and the selection of pixel rows in the pixel unit 10 from which signals are to be output via pixel control lines 31. Detailed operations of the pixels 11 will be described later. The amplifier unit 40 is, for example, a current load, and together with the amplifying transistors provided in the pixels 11, constitutes an amplifier such as a source follower circuit. The amplifier unit 40 amplifies pixel signals input from the pixel unit 10 via pixel output lines 14 and outputs the amplified signals to the AD conversion unit 50. The AD conversion unit 50 converts the pixel signals output from the amplifier unit 40 into analog signals and outputs them to the memory unit 60. The memory unit 60 stores the converted pixel signals as digital data. The pixel signals stored in the memory unit 60 are transferred to the digital signal processing unit 80 under the control of the readout scanning unit 70. The digital signal processing unit 80 performs digital signal processing on the transferred pixel signals, such as addition and subtraction between data, digital gain, offset addition and subtraction, decoding, and data scrambling. The digitally processed pixel signals are output from the output unit 90. The output unit 90 may have a configuration that outputs a voltage from a single terminal, such as a buffer circuit, or may have a Low Voltage Differential Signaling (LVDS) configuration with two differential terminals. The output unit 90 may also have a parallel / serial conversion function. The timing generation unit 20 controls the operation timing of each component of the photoelectric conversion device 1.

[0012] 2 is an equivalent circuit diagram illustrating the basic configuration of a pixel 11, a processing circuit (amplifier unit 40, AD converter unit 50), and bias generators 12, 41, and 51 that supply bias potentials to the pixel 11 and the processing circuit. The pixel 11 includes photoelectric conversion elements PD1 and PD2, transfer transistors 101 and 102, a reset transistor 103, a capacitance selection transistor 104, an amplification transistor 105, a selection transistor 106, and a capacitance element 107. The pixel 11 also includes storage capacitors 108 to 110, sample-and-hold (SH) transistors 111 to 113, a reset transistor 114, a cascode transistor 115, a current source transistor 116, and a switch 117. The pixel 11 also includes an amplification transistor 118 and a selection transistor 119. Hereinafter, the node to which the gate electrode of the amplification transistor 105 is connected may be referred to as node FD, and the node to which the gate electrode of the amplification transistor 118 is connected may be referred to as node CH.

[0013] The drive control unit 30 controls the pixels 11 via the pixel control lines 31 as described above. The control signals used by the drive control unit 30 to control the pixels 11 are reset pulses RES1 and RES2, transfer pulses TX1 and TX2, selection pulses SEL1 and SEL2, SH pulses GTX0 to GTX2, a bias selection pulse S1, and a capacitance selection signal FI. The reset pulse RES1 controls the operation of the reset transistor 103. The reset pulse RES2 controls the operation of the reset transistor 114. The transfer pulse TX1 controls the operation of the transfer transistor 101. The transfer pulse TX2 controls the operation of the transfer transistor 102. The selection pulse SEL1 controls the operation of the selection transistor 106. The selection pulse SEL2 controls the operation of the selection transistor 119. The SH pulse GTX0 controls the operation of the SH transistor 111. The SH pulse GTX1 controls the operation of the SH transistor 112. The SH pulse GTX2 controls the operation of the SH transistor 113. The bias selection pulse S1 controls the operation of the switch 117. The capacitance selection signal FI controls the operation of the capacitance selection transistor 104.

[0014] The cascode transistor 115 and the current source transistor 116, together with the amplifier transistor 105, form a source follower (SF) circuit, which functions as an amplifier that amplifies signals from the photoelectric conversion elements PD1 and PD2. In this embodiment, the cascode transistor 115 is provided as the SF circuit, but the cascode transistor 115 is not necessarily provided. The bias generation unit 12 generates bias potentials VG1 and VB1 and supplies them to the gate electrodes of the cascode transistor 115 and the current source transistor 116, respectively. In other words, the bias generation unit 12 supplies the bias potentials for operating the SF circuit, which functions as an amplifier that amplifies signals from the photoelectric conversion elements PD1 and PD2. The bias potential VB1 is generated by the diode-connected current generation transistor 201 and current source 202, and is supplied to the gate electrode of the current source transistor 116 via the bias line 13. The bias adjustment unit 203 adjusts the bias potential VB1 by, for example, controlling the current value of the current source 202, thereby adjusting the driving force of the SF circuit including the amplification transistor 105 and the current source transistor 116. The bias potential VG1 may be generated, for example, in the bias generation unit 12 using a current source and a current generation transistor, similar to the bias potential VB1. Therefore, the details of the generation of the bias potential VG1 will be omitted here.

[0015] The amplifier 40 constituting the processing circuit includes a cascode transistor 401, a current source transistor 402, and a switch 403. The cascode transistor 401 and the current source transistor 402, together with the amplifier transistor 118 arranged in the pixel 11, constitute an SF circuit and function as an amplifier that amplifies signals read from the storage capacitors 108 to 110. In this embodiment, the cascode transistor 401 is arranged as the SF circuit, but the cascode transistor 401 is not necessarily arranged. The bias generation unit 41 generates bias potentials VG2 and VB2 and supplies them to the gate electrodes of the cascode transistor 401 and the current source transistor 402, respectively. In other words, the bias generation unit 41 supplies a bias potential for operating the SF circuit that functions as an amplifier that amplifies signals read from the storage capacitors 108 to 110. The bias potential VB2 is generated by a diode-connected current generation transistor 404 and a current source 405 and is supplied to the gate electrode of the current source transistor 402 via a bias line 42. The bias adjustment unit 406 adjusts the bias potential VB2 by, for example, controlling the current value of the current source 405, thereby adjusting the driving force of the SF circuit including the amplifying transistor 118 and the current source transistor 402. The bias potential VG2 may be generated, for example, in the bias generation unit 41 using a current source and a current generation transistor, similar to the bias potential VB2. Therefore, details of the generation of the bias potential VG2 will be omitted here.

[0016] The AD conversion unit 50 constituting the processing circuit includes an AD conversion circuit 53. The bias generation unit 51 generates a bias potential for operating the AD conversion circuit 53. The bias potential generated by the bias generation unit 51 is supplied to the AD conversion unit 50 (AD conversion circuit 53) via a bias line 52.

[0017] Power supply lines VDD1 to VDD6 and ground lines GND1 to GND6 are provided as power supply lines for the pixels 11, bias generation unit 12, amplifier unit 40, bias generation unit 41, AD conversion unit 50, and bias generation unit 51. These power supply lines may or may not be connected to each other.

[0018] For example, the power supply line VDD1 arranged in the pixel 11 and the power supply line VDD2 arranged in the bias generation unit 12 may be connected to each other, as may the ground line GND1 arranged in the pixel 11 and the ground line GND2 arranged in the bias generation unit 12. In this case, the SF circuit, which functions as an amplifier that amplifies signals from the photoelectric conversion elements PD1 and PD2 and includes the amplifier transistor 105 and the current source transistor 116, and the bias generation unit 12 are supplied with power from a common power supply line. This allows the current source transistor 116 arranged in the pixel 11 and the current generation transistor 201 arranged in the bias generation unit 12 to have the same operating point and temporal fluctuations. As a result, the accuracy and stability of the current value of the SF circuit, which includes the amplifier transistor 105 and the current source transistor 116, can be improved.

[0019] On the other hand, the power supply line VDD1 arranged in the pixel 11 and the power supply line VDD5 arranged in the AD conversion unit 50, and similarly the ground line GND1 arranged in the pixel 11 and the ground line GND5 arranged in the AD conversion unit 50, may be separated from each other. In this case, the SF circuit including the amplification transistor 105 and the current source transistor 116, which functions as an amplifier unit that amplifies signals from the photoelectric conversion elements PD1 and PD2, and the AD conversion circuit 53 arranged in the AD conversion unit 50 are supplied with power from different power supply lines. This can reduce the effects of crosstalk associated with the respective operations.

[0020] In this way, the connection relationships of the power supply lines VDD1 to VDD6 and the ground lines GND1 to GND6 can be determined taking into consideration the operation timing, the power supply voltage to be used, crosstalk, and the operating point. Although elements connected to the power supply lines VDD3, VDD6, and the ground line GND6 are not shown in Fig. 2, elements not shown are actually connected to these lines. Furthermore, in the drawings described from Fig. 2 onwards, the power supply lines VDD1 to VDD6 and the ground lines GND1 to GND6 may be omitted.

[0021] Next, the operation of each circuit in the photoelectric conversion device 1 during one frame period will be described using FIG. 3. FIG. 3 illustrates a period T1 during which charge signals generated in the photoelectric conversion elements PD1 and PD2 are held as voltage signals in the holding capacitors 108 to 111, and a period T2 during which the voltage signals held in the holding capacitors 108 to 111 are read out to the amplifier 40 and AD converted by the AD conversion unit 50. In FIG. 3, when a control signal supplied from the drive control unit 30 is high, each transistor operates on (conducts), and when the control signal is low, each transistor operates off (does not conduct). The relationship between each control signal and the transistor operated by the control signal is as described above. The charge signals generated in the photoelectric conversion elements PD1 and PD2 and the voltage signals held at the holding voltages may be collectively referred to as pixel signals.

[0022] During period T1, the selection transistor 106 and switch 117 are turned on, enabling the output from the photoelectric conversion elements PD1 and PD2 to be supplied to node CH via an SF circuit including an amplifier transistor 105 and a current source transistor 116, which function as an amplifier. First, during the period from time t0 to t1, the reset transistor 103 is turned on, and during the period from time t2 to t3, the capacitance selection transistor 104 is turned on. This resets node FD to a potential level based on the power supply VDD1. At the same time, the capacitance element 107 is also reset. This is referred to as the first reset period. Here, time t0 and time t2 may occur at the same time. Similarly, time t1 and time t3 may occur at the same time.

[0023] After the first reset period is completed, during the period from time t4 to t5, the transfer transistor 101 is turned on, and the charge signal of the photoelectric conversion element PD1 is supplied to the node CH via the SF circuit including the amplification transistor 105 and the current source transistor 116. This period is referred to as the first transfer period. Similarly, during the period from time t6 to t7, the transfer transistor 102 is turned on, and the charge signal of the photoelectric conversion element PD2 is supplied to the node CH via the SF circuit including the amplification transistor 105 and the current source transistor 116. This period is referred to as the second transfer period.

[0024] In the example shown in FIG. 3, the capacitance selection transistor 104 is driven to turn off at time t3. However, this is not limiting, and the capacitance selection transistor 104 may be turned on during each of the first reset period, the first transfer period, and the second transfer period, thereby adjusting the potential of the node FD. For example, during the first transfer period, the charge signal of the photoelectric conversion element PD1 is converted into a voltage by the capacitance of the node FD, so by turning on the capacitance selection transistor 104, the potential can be determined according to the capacitance value. The operation of the capacitance selection transistor 104 can be appropriately selected depending on the dynamic range of the SF circuit including the amplification transistor 105 and the current source transistor 116 and subsequent circuits, relative to the amount of charge accumulated by the photoelectric conversion elements PD1 and PD2.

[0025] Next, the control of the SH transistors 111-113 and the voltage signals held in the holding capacitors 108-110 will be described. After the end of the first reset period, during the period from time t8 to t9, the reset state potential of the node FD (hereinafter, sometimes referred to as the N level) is supplied to the node CH via the SF circuit including the amplifier transistor 105 and the current source transistor 116. During this period, the SH pulse GTX0 is set high at time t8 to turn on the SH transistor 111, thereby sampling the N level in the holding capacitor 108 and holding it at time t9. The period from time t10 to t11 is the first transfer period, during which the node CH is supplied with a potential (hereinafter, sometimes referred to as the S1 level) based on the charge signal of the photoelectric conversion element PD1 at the node FD via the SF circuit including the amplifier transistor 105 and the current source transistor 116. During this period, the SH pulse GTX1 is set high at time t10, turning on the SH transistor 112, thereby sampling the S1 level in the holding capacitor 109 and holding it at time t11. Similarly, the period from time t12 to t13 is a second transfer period, during which a potential (hereinafter sometimes referred to as the S2 level) based on the charge signal of the photoelectric conversion element PD2 at node FD is connected to the node CH via an SF circuit including the amplification transistor 105 and the current source transistor 116. During this period, the SH pulse GTX2 is set high at time t12, turning on the SH transistor 113, thereby sampling the S2 level in the holding capacitor 110 and holding it at time t12. Through these operations, the N level, S1 level, and S2 level are held as voltage signals in the holding capacitors 108 to 110. Here, the period during which the voltage signals are sampled and held in the holding capacitors 108 to 110 is referred to as a voltage holding operation period.

[0026] This series of operations from the first reset period to the voltage holding operation period is called the pixel signal voltage holding operation. By simultaneously performing the pixel signal voltage holding operation on all pixels, a global electronic shutter operation can be realized. Of the multiple pixels 11 arranged in the pixel unit 10, the pixel signal voltage holding operation may be performed on all pixels 11, or on some of the pixels 11. For example, the pixel signal voltage holding operation may be performed sequentially in units of multiple pixel rows or multiple pixel columns. Alternatively, the pixel signal voltage holding operation may be performed row by row.

[0027] After the pixel signal voltage holding operation, the voltage signals held in the holding capacitors 108-110 are read out to the amplifier 40 and the AD converter 50. During period T2 shown in FIG. 3, the selection transistor 106 and the switch 117 are turned off. This causes the amplifier transistor 105 and the cascode transistor 115 to be disconnected. Furthermore, the switch 117 being turned off cuts off the current supplied by the current source transistor 116, causing the SF circuit including the amplifier transistor 105 and the current source transistor 116 to be in an inactive state. This causes the node CH to float. Meanwhile, at time t14, the selection transistor 119 is turned on, and at time t15, the switch 403 is turned on. This causes the node CH to be connected to the AD converter 53 via the SF circuit including the amplifier transistor 118 and the current source transistor 402, which functions as an amplifier that amplifies the signals read out from the holding capacitors 108-110. Note that time t14 and time t15 may occur at the same time.

[0028] During the period from time t16 to t17, the reset transistor 114 is turned on, and the node CH is reset to the potential level based on the power supply line VDD1. This period is referred to as a second reset period.

[0029] After the second reset period, during the period from time t18 to t19, the SH pulse GTX0 is set high, turning on the SH transistor 111, thereby outputting the voltage signal held in the storage capacitor 108 to the node CH. The AD conversion circuit 53 performs AD conversion on the voltage signal held in the storage capacitor 108, which is read via the SF circuit including the amplifier transistor 118 and the current source transistor 402, i.e., the voltage based on the N level. This period is referred to as the first AD conversion period. The potential of the node CH is determined by the ratio of the capacitance of the node CH, such as the capacitance of the wiring pattern, the diffusion capacitance of the SH transistors 111 to 113, and the gate electrode of the amplifier transistor 118, to the capacitance of the storage capacitors 108 to 110, and the potential difference between the nodes. Therefore, in the operation shown in FIG. 3, a second reset period is provided to reset the node CH to a constant potential before reading out the voltages held in the storage capacitors 108 to 110.

[0030] After a second reset period from time t20 to t21, during a period from time t22 to t23, the SH pulse GTX1 is set high to turn on the SH transistor 112, thereby outputting the voltage signal held in the holding capacitor 109 to the node CH. The AD conversion circuit 53 performs AD conversion on the voltage signal held in the holding capacitor 109 that is read out via the SF circuit including the amplification transistor 118 and the current source transistor 402, i.e., the voltage based on the S1 level. This is referred to as a second AD conversion period.

[0031] Furthermore, after a second reset period from time t24 to t25, during a period from time t26 to t27, the SH pulse GTX2 is set high to turn on the SH transistor 113, thereby outputting the voltage signal held in the holding capacitor 110 to the node CH. The AD conversion circuit 53 performs AD conversion on the voltage signal held in the holding capacitor 110 that is read out via the SF circuit including the amplification transistor 118 and the current source transistor 402, i.e., the voltage based on the S2 level. This is referred to as a third AD conversion period.

[0032] After the third AD conversion period, period T2 ends, and the selection transistor 119 and the switch 403 are turned off. This causes the amplification transistor 118 and the cascode transistor 401 to be in a disconnected state. Furthermore, by turning off the switch 403, the current supplied by the current source transistor 402 is cut off, and the SF circuit including the amplification transistor 118 and the current source transistor 402 is in a non-operating state.

[0033] 3 does not explicitly state the reset operation of the photoelectric conversion elements PD1 and PD2, but the accumulation start time may be set to, for example, after the first transfer period or the second transfer period. Furthermore, the transfer transistor 101, the transfer transistor 102, the reset transistor 103, and the capacitance selection transistor 104 are turned on in accordance with control signals during period T2 or at a timing other than periods T1 and T2 (not shown). This may reset the photoelectric conversion elements PD1 and PD2 to a potential based on the power supply VDD1.

[0034] The pixel 11 shown in FIG. 2 includes two photoelectric conversion elements PD1 and PD2. In this case, phase difference detection or stereoscopic image generation may be performed based on output difference information between the photoelectric conversion elements PD1 and PD2. A sensitivity difference may be provided between the photoelectric conversion elements PD1 and PD2, and a high dynamic range image may be generated by combining or selectively using the outputs of the two photoelectric conversion elements PD1 and PD2 for bright and dark areas of the same captured image. The sensitivity difference between the photoelectric conversion elements PD1 and PD2 may be achieved by, for example, changing the light transmittance using a color filter, microlens, metal layer, or the like disposed on the light incident side of the photoelectric conversion elements PD1 and PD2. The sensitivity difference between the photoelectric conversion elements PD1 and PD2 may be achieved by, for example, changing the size of the photoelectric conversion elements PD1 and PD2. The pixel 11 may also include only one photoelectric conversion element.

[0035] FIG. 4 is an equivalent circuit diagram illustrating a configuration example in which the pixels 11, processing circuits (amplifier unit 40, AD converter unit 50), and bias generation units 12, 41, and 51 are distributed across multiple semiconductor substrates in this embodiment. The pixels 11, amplifier unit 40, AD converter unit 50, and bias generation units 12, 41, and 51 described in FIG. 2 may be disposed on a single semiconductor substrate. The drive control unit 30, memory unit 60, readout scanning unit 70, digital signal processing unit 80, and output unit 90 described with reference to FIG. 1 may also be disposed on the same single semiconductor substrate. When the pixels 11, processing circuits (amplifier unit 40, AD converter unit 50), and bias generation units 12, 41, and 51 are disposed on a single semiconductor substrate, the length of the pixel output line 14 connecting the pixels 11 and the processing circuits (amplifier unit 40, AD converter unit 50) increases in proportion to the size of the pixel unit 10. Therefore, the parasitic capacitance load of the long pixel output line 14 increases the readout time and also increases the chip area, for example.

[0036] 4, a bias generation unit 12 is disposed on a semiconductor substrate 1000, and the bias generation unit 12 supplies a bias potential for operating an SF circuit functioning as an amplifier including the pixel unit 10 and the amplifier transistor 105 and current source transistor 116 of the pixel 11. Furthermore, a processing circuit (amplification unit 40, AD conversion unit 50) and bias generation units 41 and 51 for supplying a bias potential for operating the processing circuit are disposed on a semiconductor substrate 2000 separate from the semiconductor substrate 1000. The semiconductor substrates 1000 and 2000 are stacked, and the pixel output line 14 is electrically connected between the semiconductor substrates 1000 and 2000 via a connection unit HB1 using, for example, hybrid bonding. The connection unit HB1 is not limited to hybrid bonding, and the semiconductor substrates 1000 and 2000 may be connected using a conductive via, a bump, or the like.

[0037] FIG. 5 is a three-dimensional view of the configuration shown in FIG. 4. As shown in FIG. 5, the photoelectric conversion device 1 has a configuration in which multiple semiconductor substrates, including semiconductor substrates 1000 and 2000, are stacked. FIG. 5 shows a configuration in which the amplifier unit 40 and AD conversion unit 50 arranged on the semiconductor substrate 2000 are located directly below the pixel unit 10 arranged on the semiconductor substrate 1000. The configuration shown in FIG. 5 makes it possible to shorten the pixel output line 14 compared to when the pixel unit 10 and the processing circuit (the amplifier unit 40 and the AD conversion unit 50) are arranged on a single semiconductor substrate. This reduces the parasitic capacitance of the pixel output line 14 and shortens the readout time for reading signals from the pixel unit 10 (pixels 11). Furthermore, an increase in chip area can be suppressed. In other words, the imaging performance of the photoelectric conversion device 1 can be improved.

[0038] The drive control unit 30, memory unit 60, readout scanning unit 70, digital signal processing unit 80, and output unit 90 described above may also be arranged on the semiconductor substrate 2000. Furthermore, some or all of the drive control unit 30, memory unit 60, readout scanning unit 70, digital signal processing unit 80, and output unit 90 may be arranged on a semiconductor substrate separate from the semiconductor substrates 1000 and 2000. This can further suppress an increase in chip area.

[0039] In the configurations shown in FIGS. 4 and 5, the pixel unit 10 (pixel 11) and the bias generation unit 12 for operating the amplifier unit arranged in the pixel 11 are arranged on the same semiconductor substrate 1000. Furthermore, the processing circuit (amplification unit 40, AD conversion unit 50) and the bias generation units 41 and 51 for operating the processing circuit are arranged on the same semiconductor substrate 2000. As described with reference to FIG. 2, a bias potential VB1 is supplied to the gate electrode of the current source transistor 116 of the pixel 11 from the current generation transistor 201 of the bias generation unit 12. The current generation transistor 201 forms a so-called current mirror with the current source transistor 116, and the accuracy of the current is determined by the pairing between the current source transistor 116 and the current generation transistor 201. Arranging the current source transistor 116 and the current generation transistor 201 on the same semiconductor substrate 1000 is a factor that improves this pairing. During global electronic shutter operation, the SF circuit including the amplifier transistor 105 and the current source transistor 116 operates in all pixels 11, increasing power consumption on the semiconductor substrate 1000. Therefore, the accuracy of the current generated by the current source transistor 116, which determines the drive current of the SF circuit including the amplifier transistor 105 and the current source transistor 116, is important for improving accuracy in power consumption design. By arranging the pixel unit 10 and the bias generation unit 12 on the same semiconductor substrate 1000 as shown in FIGS. 4 and 5 , the accuracy of the current generated by the current source transistor 116, which serves as a current source for constituting the SF circuit together with the amplifier transistor 105, can be improved. Similarly, the amplifier unit 40, the AD conversion unit 50, and the bias generation units 41 and 51 are arranged on the semiconductor substrate 2000. This improves the accuracy in power consumption design for each unit. As a result, the imaging performance of the photoelectric conversion device 1 can be improved.

[0040] In the configurations shown in FIGS. 4 and 5, one bias generation unit 12 is provided for the pixel unit 10. However, this is not limited thereto, and multiple bias generation units 12 may be provided for the pixel unit 10. This can improve responsiveness even when a transient fluctuation occurs in the bias line 13 due to kickback via parasitic capacitance when all pixels 11 are driven. Furthermore, when crosstalk occurs between pixels 11 via the bias line 13 common to all pixels 11, the crosstalk between pixels 11 can be reduced by providing multiple bias generation units 12 and separating the bias line 13 for each bias generation unit 12. Using these configurations can improve the imaging performance and image quality of the photoelectric conversion device 1.

[0041] 6 is an equivalent circuit diagram illustrating an example configuration in which the pixel 11, processing circuits (amplifier unit 40, AD conversion unit 50), and bias generation units 12, 41, and 51 are distributed across multiple semiconductor substrates in this embodiment, and is a modified example of the configuration shown in FIG. 4. In the configuration shown in FIG. 6, the bias generation unit 12 is disposed on a semiconductor substrate 2000. A bias line 13 connecting the bias generation unit 12 and the gate electrode of the current source transistor 116 is electrically connected between the semiconductor substrate 1000 and the semiconductor substrate 2000 via a connection unit HB2. FIG. 7 is a three-dimensional view of the configuration shown in FIG. 6.

[0042] The size of the photoelectric conversion device 1 may be determined by the size of the semiconductor substrate 1000, in other words, the size of the pixel section 10, in other words, the size of the pixels 11 and the number of pixels 11. In the configurations shown in FIGS. 4 and 5 , the bias generation unit 12 needs to be disposed in a region of the semiconductor substrate 1000 separate from the region in which the pixel section 10 is disposed. Therefore, disposing the bias generation unit 12 on the semiconductor substrate 1000 may increase the chip area of ​​the semiconductor substrate 1000 and, in turn, the chip area of ​​the photoelectric conversion device 1. Therefore, disposing the bias generation unit 12 on the semiconductor substrate 2000 may roughly determine the size of the semiconductor substrate 1000 by the size of the pixel section 10. Although it also depends on the size and number of pixels 11 required for the photoelectric conversion device 1, disposing the bias generation unit 12 on the semiconductor substrate 2000 may potentially suppress an increase in the chip area of ​​the photoelectric conversion device 1.

[0043] Furthermore, depending on the types of elements constituting the pixels 11 and the types of elements constituting the bias generation unit 12, it may be more appropriate to arrange the bias generation unit 12 on the semiconductor substrate 2000. For example, forming elements, passive elements, active elements, etc. that operate on multiple power supply voltages on the same semiconductor substrate may complicate the semiconductor manufacturing process, which may affect cost and performance constraints. The semiconductor substrate 2000 is provided with multiple functional blocks, including the amplifier unit 40 and the AD conversion unit 50. Therefore, the semiconductor substrate 2000 must be provided with elements, passive elements, active elements, etc. that operate on multiple power supply voltages. Therefore, the bias generation unit 12 or a portion of the bias generation unit 12 is arranged on the semiconductor substrate 2000. This may enable optimization of the manufacturing process for the semiconductor substrate 1000 and the semiconductor substrate 2000. For example, the semiconductor manufacturing process may be optimized by applying a process specialized for improving the performance of the photoelectric conversion elements PD1 and PD2 to the semiconductor substrate 1000. This may improve the imaging performance of the photoelectric conversion device 1.

[0044] Fig. 8 is an equivalent circuit diagram illustrating an example of a configuration in this embodiment in which the pixels 11, processing circuits (amplifiers 40, AD converters 50), and bias generators 12, 41, and 51 are distributed across multiple semiconductor substrates, and is a modified example of the configurations shown in Fig. 4 and Fig. 6. Fig. 9 is a three-dimensional view of the configuration shown in Fig. 8.

[0045] As shown in FIG. 8 , the bias generation unit 12 includes elements arranged on the semiconductor substrate 1000 and elements arranged on the semiconductor substrate 2000. The bias generation unit 12a, which is arranged on the semiconductor substrate 1000, includes a current generation transistor 201 and a current source 202. The bias generation unit 12b, which is arranged on the semiconductor substrate 2000, includes a bias adjustment unit 203. The bias generation units 12a and 12b are electrically connected by a bias adjustment control line 15 via a connection HB3. This configuration maintains the pairing of the current mirror configuration between the current source transistor 116 and the current generation transistor 201. Furthermore, by arranging the bias generation unit 12b on the semiconductor substrate 2000, the number of elements arranged on the semiconductor substrate 1000 can be reduced compared to the configurations shown in FIGS. 4 and 5 . Meanwhile, the bias adjustment unit 203 is arranged on the semiconductor substrate 2000. This allows the bias adjustment unit 203 to be configured using logic circuits and elements that operate on a plurality of power supply voltages.

[0046] Furthermore, for example, when the current source 202 is configured with a passive element such as a resistor, the current source 202 may be disposed on the semiconductor substrate 2000. In order to suppress noise in the SF circuit including the amplifying transistor 105 and the current source transistor 116, it is possible to increase the gate area of ​​the current generating transistor 201. From a similar perspective, it is possible to adjust the LW ratio of the gate electrode and increase the mirror ratio of the current generating transistor 201 to the current source transistor 116. For example, if the area of ​​the gate electrode of the current generating transistor 201 is increased by A times while keeping the LW ratio of the gate electrode of the current generating transistor 201 unchanged, the random noise generated in the current generating transistor 201 can be reduced by approximately 1 / √A times. Therefore, for example, the bias generating unit 12a disposed on the semiconductor substrate 1000 is configured so that only the current generating transistor 201 is disposed. This allows the area of ​​the gate electrode of the current generating transistor 201 to be increased compared to a configuration in which the current source 202, bias adjusting unit 203, and the like are disposed on the semiconductor substrate 1000, as shown in FIG. 4 . Furthermore, the degree of freedom in designing the L / W ratio of the gate electrode of the current generating transistor 201 is increased, and noise in the SF circuit including the amplifying transistor 105 and the current source transistor 116 is reduced, resulting in low-noise pixel signals. The combination of the multiple elements constituting the bias generating unit 12, arranged on the semiconductor substrate 1000 and the semiconductor substrate 2000, is not limited to the above and may be designed as appropriate.

[0047] As described above, the bias generation units 12 that drive the current source transistors 116 of the pixels 11 are arranged on the same semiconductor substrate or on separate semiconductor substrates, taking into consideration the type of element, power supply voltage, current accuracy, noise performance, area, etc. This makes it possible to improve the imaging performance of the photoelectric conversion device 1, such as by improving performance through optimization of the semiconductor manufacturing process and reducing noise in pixel signals through increased design freedom.

[0048] 10 is an equivalent circuit diagram illustrating a configuration example in this embodiment in which the pixels 11, processing circuits (amplifier unit 40, AD conversion unit 50), and bias generation units 12 and 51 are distributed across multiple semiconductor substrates. The configuration for supplying a bias potential for operating the amplifier unit 40 differs from the above-described embodiments. The following description will focus on configurations that differ from the above-described embodiments, and descriptions of configurations that may be similar will be omitted where appropriate.

[0049] In the configuration shown in FIG. 10 , the bias generation unit 12 is arranged on a semiconductor substrate 1000. The bias potential generated by the bias generation unit 12 is supplied via a bias line 13 to a current source transistor 116 arranged in a pixel 11, as in the above-described embodiments. Furthermore, as shown in FIG. 10 , the bias line 13 connected to the bias generation unit 12 is connected via a connection part HB4 to a current source transistor 402 of an amplifier unit 40 arranged on a semiconductor substrate 2000. As a result, the bias generation unit 12 supplies a bias potential not only to the current source transistor 116 but also to the current source transistor 402. FIG. 11 is a three-dimensional view of the configuration shown in FIG. 10 .

[0050] As described with reference to FIG. 3 , the drive timing in one frame period is divided into period T1, during which charge signals generated by photoelectric conversion elements PD1 and PD2 are held as voltage signals, and period T2, during which the held voltage signals are read out. The SF circuit including the amplifier transistor 105 and current source transistor 116 arranged in pixel 11 is driven during period T1. The SF circuit including the amplifier transistor 118 arranged in pixel 11 and the current source transistor 402 arranged in the amplifier unit 40 is driven during period T2. In the above-described embodiment, the bias generation unit 12, which operates the SF circuit including the amplifier transistor 105 and current source transistor 116, and the bias generation unit 41, which operates the SF circuit including the amplifier transistor 118 and current source transistor 402, are separately arranged. This is because, for example, each SF circuit is driven separately, each SF circuit has a different driving force, each SF circuit has a different driving force, and each SF circuit operates to suppress crosstalk due to the operation of each SF circuit. However, the drive timing of each SF circuit is different between period T1 and period T2. Therefore, by controlling the driving force using the bias adjustment unit 203 during each of the periods T1 and T2, it is possible to share one bias generation unit 12 between the SF circuit including the amplifier transistor 105 and the current source transistor 116 and the SF circuit including the amplifier transistor 118 and the current source transistor 402. In other words, the bias generation unit can be shared between multiple blocks, thereby reducing power consumption and area.

[0051] 10, the pixel unit 10 (bias generation unit 12) and the amplifier unit 40 (bias generation unit 41) are configured to share a single bias generation unit. However, this is not limited to this, and the pixel unit 10 (bias generation unit 12) and the AD conversion unit 50 (bias generation unit 51) may share a single bias generation unit, or the amplifier unit 40 (bias generation unit 41) and the AD conversion unit 50 (bias generation unit 51) may share a single bias generation unit. Furthermore, the pixel unit 10, the amplifier unit 40, and the AD conversion unit 50 may share a single bias generation unit.

[0052] Fig. 12 is a diagram showing a modification of Fig. 11. In Fig. 12, the bias generation unit 12 is arranged on a semiconductor substrate 2000. This makes it possible to reduce the chip area and optimize the semiconductor manufacturing process, similar to the configuration shown in Fig. 6.

[0053] 13 is an equivalent circuit diagram illustrating an example configuration in this embodiment in which the pixel 11, processing circuits (amplifier unit 40, AD converter unit 50), and bias generation units 12, 41, and 51 are distributed across multiple semiconductor substrates. In the configuration shown in FIG. 13, similar to the configuration described using FIG. 8, the bias generation unit 12 includes elements arranged on the semiconductor substrate 1000 and elements arranged on the semiconductor substrate 2000. In addition, in the configuration shown in FIG. 13, similar to the configuration shown in FIG. 10, one bias generation unit 12 is shared by the pixel unit 10 (pixel 11) and the amplifier unit 40.

[0054] Fig. 14 is a three-dimensional view of the configuration shown in Fig. 13. Fig. 15 is a view showing a modified example of Fig. 14. The position where the bias generation unit 12b is arranged is different between Fig. 14 and Fig. 15. The configuration shown in Fig. 15 is an example in which the bias generation unit 12b is arranged at the location where the bias generation unit 41 shown in Fig. 5 is arranged.

[0055] 13 to 15, the bias generation unit 12 is shared by multiple blocks. Furthermore, the bias generation unit 12 is distributed over the semiconductor substrate 1000 and the semiconductor substrate 2000. This provides the effects of reducing power consumption and area, and improving the degree of freedom in layout planning, as described above with reference to FIGS.

[0056] 16 is an equivalent circuit diagram illustrating a configuration example in this embodiment in which the pixels 11, processing circuits (amplifier unit 40, AD converter unit 50), and bias generation units 12, 41, and 51 are distributed across multiple semiconductor substrates. In the configuration shown in FIG. 16, three semiconductor substrates 3000, 4000, and 2000 are stacked, and the pixels 11, processing circuits (amplifier unit 40, AD converter unit 50), and bias generation units 12, 41, and 51 are distributed across the three semiconductor substrates 3000, 4000, and 2000. The following description will focus on configurations that are different from the above-described embodiments, and descriptions of configurations that may be similar will be omitted as appropriate.

[0057] When a single pixel 11 includes many elements, if the pixel unit 10 (pixel 11) is arranged on a single semiconductor substrate 1000 as in the above-described embodiment, the maximum amount of charge stored in the photoelectric conversion elements PD1 and PD2 may be limited, for example, due to area constraints. Furthermore, there may be size constraints on transistors such as the amplifier transistor 105 and the current source transistor 116. In other words, there may be constraints on the circuit noise design. Therefore, in the configuration shown in FIG. 16 , a portion of the pixel 11 is arranged on the semiconductor substrate 3000 and the semiconductor substrate 4000, respectively, and the elements constituting the pixel 11 arranged on the semiconductor substrates 3000 and 4000 are electrically connected using a connection part HB5.

[0058] The pixel 11a of the pixels 11 is disposed on the semiconductor substrate 3000. The pixel 11a includes photoelectric conversion elements PD1 and PD2, transfer transistors 101 and 102, a reset transistor 103, a capacitance selection transistor 104, an amplification transistor 105, a selection transistor 106, and a capacitance element 107. The pixel 11a also includes a cascode transistor 115, a current source transistor 116, and a switch 117. As described above, the amplification transistor 105, the cascode transistor 115, and the current source transistor 116 configure an SF circuit that functions as an amplifier that amplifies signals from the photoelectric conversion elements PD1 and PD2. The cascode transistor 115 does not necessarily have to be disposed. In this embodiment, the SF circuit that functions as an amplifier that amplifies signals from the photoelectric conversion elements PD1 and PD2 is entirely disposed on the semiconductor substrate 3000. In the configuration shown in FIG. 16, the bias generation unit 12 is also disposed on the semiconductor substrate 3000.

[0059] Of the pixels 11, pixel 11b is arranged on the semiconductor substrate 4000. Pixel 11b includes storage capacitors 108-110, SH transistors 111-113, a reset transistor 114, an amplification transistor 118, and a selection transistor 119. As described above, the amplification transistor 118, the cascode transistor 401 of the amplification unit 40, and the current source transistor 402 constitute an SF circuit that functions as an amplification unit that amplifies signals read out from the storage capacitors 108-110.

[0060] The semiconductor substrates 3000 and 4000 are electrically connected to a node CH via a connection part HB5 between the output node of the SF circuit including the amplifier transistor 105 and the current source transistor 116. The processing circuits (amplifier unit 40, AD converter unit 50) are disposed on the semiconductor substrate 2000, as in the above-described embodiments. The configuration of the semiconductor substrate 2000 may be the same as that shown in FIG. 4, for example, and detailed description thereof will be omitted. However, the semiconductor substrates 4000 and 2000 are connected via a connection part HB1. With this configuration, the pixel output line 14 and the AD converter circuit 53 are electrically connected via the connection part HB1. In the configuration shown in FIG. 16, the bias generation units 41 and 51 are disposed on the semiconductor substrate 2000. In FIG. 16, the power supply line VDD and ground line GND of the pixel 11 are indicated as the power supply line VDD1 and ground line GND1 for the pixel 11a, and as the power supply line VDD7 and ground line GND7 for the pixel 11b. However, as described above, they may or may not be connected to each other. For example, the power supply line VDD1 arranged in pixel 11a and the power supply line VDD7 arranged in pixel 11b may be connected to each other, and similarly, the ground line GND1 arranged in pixel 11a and the ground line GND7 arranged in pixel 11b may be connected to each other. Also, for example, the power supply line VDD1 arranged in pixel 11a and the power supply line VDD2 arranged in bias generation unit 12 may be connected to each other, and similarly, the ground line GND1 arranged in pixel 11a and the ground line GND2 arranged in bias generation unit 12 may be connected to each other.

[0061] Fig. 17 is a three-dimensional view of the configuration shown in Fig. 16. The pixel section 10 includes a pixel section 10a arranged on a semiconductor substrate 3000 and a pixel section 10b arranged on a semiconductor substrate 4000, corresponding to the pixels 11a and 11b.

[0062] In the configurations shown in FIGS. 16 and 17, the current source transistor 116 and the bias generation unit 12 are arranged on the same semiconductor substrate 3000. This improves the accuracy of the current value generated by the current source transistor 116. Furthermore, by arranging the pixels 11a and 11b on separate semiconductor substrates 3000 and 4000, it becomes possible to improve the design flexibility of the area and layout of the elements constituting the pixel 11. For example, the area of ​​the photoelectric conversion elements PD1 and PD2 can be increased to increase the maximum amount of stored charge, or the area of ​​the gate electrodes of the amplifier transistors 105 and 118 can be increased to reduce noise. Furthermore, kT / C noise, which is inversely proportional to the capacitance values ​​of the storage capacitors 108 to 110 during the hold operation of the SH transistors 111 to 113, can be reduced by increasing the size of the storage capacitors 108 to 110.

[0063] Fig. 18 is a diagram showing a modified example of the configuration shown in Fig. 16. In the configuration shown in Fig. 18, the configuration of the pixels 11a and 11b and the arrangement of the bias generation unit 12 are different from the configuration shown in Fig. 16.

[0064] Pixel 11a on semiconductor substrate 3000 is provided with photoelectric conversion elements PD1 and PD2, transfer transistors 101 and 102, a reset transistor 103, a capacitance selection transistor 104, an amplification transistor 105, a selection transistor 106, and a capacitance element 107. Pixel 11b on semiconductor substrate 4000 is provided with a cascode transistor 115, a current source transistor 116, and a switch 117. Pixel 11b also is provided with storage capacitors 108-110, SH transistors 111-113, a reset transistor 114, an amplification transistor 118, and a selection transistor 119. The amplifier section that amplifies signals from photoelectric conversion elements PD1 and PD2 can be said to include an amplification transistor 105 that is provided on semiconductor substrate 3000 and has a gate electrode connected to node FD, which is the output node of photoelectric conversion elements PD1 and PD2, and a current source transistor 116 that is provided on semiconductor substrate 4000 and serves as a current source that, together with amplification transistor 105, constitutes an SF circuit. In the configuration shown in FIG. 18, the bias generating section 12 is disposed on the semiconductor substrate 4000.

[0065] FIG. 19 is a three-dimensional view of the configuration shown in FIG. 18. In the configurations shown in FIGS. 18 and 19, similar to the configuration described using FIG. 6, a process specialized for improving the performance of the photoelectric conversion elements PD1 and PD2 can be applied to the manufacture of the semiconductor substrate 3000. Furthermore, by arranging the cascode transistor 115, the current source transistor 116, and the switch 117 in the pixel 11b of the semiconductor substrate 4000, the degree of freedom in adjusting the sizes of the photoelectric conversion elements PD1 and PD2 and the amplifying transistor 105 is improved. Furthermore, the current source transistor 116 and the bias generation unit 12 are arranged on the same semiconductor substrate 4000. This can also improve the accuracy of the current value generated by the current source transistor 116.

[0066] The configuration shown in FIG. 20 is an example of a configuration in which the bias generation unit 12 is arranged on the semiconductor substrate 2000, as compared to the configuration shown in FIG. 18. The bias line 13 connecting the bias generation unit 12 and the gate electrode of the current source transistor 116 is electrically connected between the semiconductor substrate 4000 and the semiconductor substrate 2000 via a connection part HB6. FIG. 21 is a three-dimensional view of the configuration shown in FIG. 20. In the configurations shown in FIGS. 20 and 21, similar to the configuration described using FIG. 6, the bias generation unit 12 is arranged on the semiconductor substrate 2000 when the chip size of the photoelectric conversion element 1 is determined by the size and number of pixels 11 (pixels 11a, 11b). This makes it possible to suppress an increase in the chip size of the photoelectric conversion device 1.

[0067] The configuration shown in FIG. 22 is an example of a configuration in which the bias generation unit 12 includes elements arranged on the semiconductor substrate 4000 and elements arranged on the semiconductor substrate 2000, in contrast to the configuration shown in FIG. 20. The bias generation unit 12a of the bias generation unit 12 is arranged on the semiconductor substrate 4000, and the bias generation unit 12b of the bias generation unit 12 is arranged on the semiconductor substrate 2000. For example, the bias generation unit 12a may include a current generation transistor 201 and a current source 202, and the bias generation unit 12b may include a bias adjustment unit 203. The bias generation units 12a and 12b are electrically connected by a bias adjustment control line 15 via a connection unit HB7. FIG. 23 is a three-dimensional view of the configuration shown in FIG. 22.

[0068] 22 and 23 can also achieve the same effect as that described above with reference to FIG. 8. That is, the configurations shown in FIGS. 22 and 23 can also maintain the pairing of the current mirror configuration between the current source transistor 116 and the current generation transistor 201. Furthermore, the number of elements arranged on the semiconductor substrate 4000 can be reduced compared to the configurations shown in FIGS. 18 and 19. Meanwhile, the bias adjustment unit 203 is arranged on the semiconductor substrate 2000. As a result, the bias adjustment unit 203, together with the bias generation unit 41 and the like, can be configured using logic circuits and elements that operate on multiple power supply voltages.

[0069] 16 to 23, as described with reference to FIGS. 10 to 15, a bias generation unit may be shared between the pixel section 10 (pixel 11) and the amplifier section 40, etc. In this case, the semiconductor substrates on which the bias generation units are arranged and their positions on the respective semiconductor substrates can be determined as appropriate, as described above. Furthermore, the bias generation unit shared between the pixel section 10 (pixel 11) and the amplifier section 40, etc., may be distributed and arranged on two or more semiconductor substrates, similar to the configuration shown in FIG.

[0070] As described above, the pixels 11 are distributed and stacked on multiple semiconductor substrates 3000 and 4000. This provides the same effects as when the pixels 11 are arranged on one semiconductor substrate 1000, while improving the imaging performance of the photoelectric conversion device 1, such as increasing the maximum charge storage amount of the photoelectric conversion elements PD1 and PD2 and reducing noise in the constituent devices.

[0071] It will be understood that the above-described embodiments can be combined as appropriate, and that when combined, some components may be omitted. As described above, the drive control unit 30, memory unit 60, readout scanning unit 70, digital signal processing unit 80, and output unit 90 of the photoelectric conversion device 1 may be disposed on the semiconductor substrate 2000, or may be disposed on a semiconductor substrate separate from the semiconductor substrate 2000. That is, the drive control unit 30, memory unit 60, readout scanning unit 70, digital signal processing unit 80, and output unit 90 may be disposed on a semiconductor substrate separate from the semiconductor substrates 1000 to 4000 described above. As a result, the photoelectric conversion device 1 may be configured by stacking three, four, or more semiconductor substrates. In addition, in the above-described embodiments, an example has been shown in which the processing circuits (amplification unit 40, AD conversion unit 50) are disposed on a single semiconductor substrate 2000, but the processing circuits may be distributed across multiple stacked semiconductor substrates. For example, the amplifier section 40 and the AD conversion section 50 may be disposed on separate semiconductor substrates.

[0072] An application example of the photoelectric conversion device 1 of this embodiment will now be described with reference to Fig. 24. Fig. 24 is a schematic diagram of an apparatus 9191 including the photoelectric conversion device 1. As shown in Fig. 24, the photoelectric conversion device 1 is housed in a package 920. The package 920 can include a base to which the photoelectric conversion device 1 is fixed, and a lid such as glass that faces the photoelectric conversion device 1. The package 920 can further include bonding members such as bonding wires and bumps that connect terminals provided on the base to pads provided on the photoelectric conversion device 1.

[0073] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the photoelectric conversion device 1. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0074] The processing device 960 processes the signal output from the photoelectric conversion device 1. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device 1. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device 1. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0075] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the photoelectric conversion device 1 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 may further include a storage device 980 and a processing device 960 in addition to the storage circuit and arithmetic circuit provided in the photoelectric conversion device 1. The mechanical device 990 may be controlled based on the signal output from the photoelectric conversion device 1.

[0076] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operations. Alternatively, the mechanical device 990 in the camera can move the photoelectric conversion device 1 for vibration isolation operations.

[0077] The device 9191 can also be applied to an on-board camera mounted on transportation equipment such as a vehicle, a ship, an airplane, or an industrial robot. The mechanical device 990 in transportation equipment can be used as a mobile device. The device 9191 as transportation equipment is suitable for transporting the photoelectric conversion device 1 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a mobile device based on information obtained by the photoelectric conversion device 1. The device 9191 incorporating the photoelectric conversion device 1 is not limited to transportation equipment, but can be widely applied to equipment that uses object recognition, such as an intelligent transport system (ITS). Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, or an office machine such as a copier.

[0078] The disclosure of this specification includes the following photoelectric conversion devices and instruments.

[0079] (Item 1) A photoelectric conversion device including a plurality of pixels and a processing circuit that processes signals read from the plurality of pixels, and in which a plurality of semiconductor substrates are stacked, each of the plurality of pixels includes a photoelectric conversion element, an amplifier that amplifies a signal from the photoelectric conversion element, and a storage capacitor that stores an output of the amplifier; the photoelectric conversion device further includes a bias generating unit that supplies a bias potential to the amplifier unit for operating the amplifier unit; the plurality of semiconductor substrates include a first semiconductor substrate on which the photoelectric conversion element is arranged, a second semiconductor substrate on which the storage capacitor is arranged, and a third semiconductor substrate on which the processing circuit is arranged, the second semiconductor substrate being arranged between the first semiconductor substrate and the third semiconductor substrate; the amplifier unit includes an element disposed on the first semiconductor substrate and an element disposed on the second semiconductor substrate, The photoelectric conversion device, wherein the bias generation unit is disposed on the third semiconductor substrate.

[0080] (Item 2) A photoelectric conversion device including a plurality of pixels and a processing circuit that processes signals read from the plurality of pixels, and in which a plurality of semiconductor substrates are stacked, each of the plurality of pixels includes a photoelectric conversion element, an amplifier that amplifies a signal from the photoelectric conversion element, and a storage capacitor that stores an output of the amplifier; the photoelectric conversion device further includes a bias generating unit that supplies a bias potential to the amplifier unit for operating the amplifier unit; the plurality of semiconductor substrates include a first semiconductor substrate on which the photoelectric conversion element is arranged, a second semiconductor substrate on which the storage capacitor is arranged, and a third semiconductor substrate on which the processing circuit is arranged, the second semiconductor substrate being arranged between the first semiconductor substrate and the third semiconductor substrate; the amplifier unit includes an element disposed on the first semiconductor substrate and an element disposed on the second semiconductor substrate, The photoelectric conversion device, wherein the bias generation unit is disposed on the second semiconductor substrate.

[0081] (Item 3) A photoelectric conversion device including a plurality of pixels and a processing circuit that processes signals read from the plurality of pixels, and in which a plurality of semiconductor substrates are stacked, each of the plurality of pixels includes a photoelectric conversion element, an amplifier that amplifies a signal from the photoelectric conversion element, and a storage capacitor that stores an output of the amplifier; the photoelectric conversion device further includes a bias generating unit that supplies a bias potential to the amplifier unit for operating the amplifier unit; the plurality of semiconductor substrates include a first semiconductor substrate on which the photoelectric conversion element is arranged, a second semiconductor substrate on which the storage capacitor is arranged, and a third semiconductor substrate on which the processing circuit is arranged, the second semiconductor substrate being arranged between the first semiconductor substrate and the third semiconductor substrate; the amplifier unit includes an element disposed on the first semiconductor substrate and an element disposed on the second semiconductor substrate, The photoelectric conversion device, wherein the bias generation unit includes an element disposed on the second semiconductor substrate and an element disposed on the third semiconductor substrate.

[0082] (Item 4) The photoelectric conversion device described in any one of items 1 to 3, characterized in that the amplification unit includes a first transistor arranged on the first semiconductor substrate and having a gate electrode connected to an output node of the photoelectric conversion element, and a second transistor arranged on the second semiconductor substrate and serving as a current source that forms a source follower circuit together with the first transistor.

[0083] (Item 5) 5. The photoelectric conversion device according to item 4, wherein the bias generating section supplies the bias potential to the gate electrode of the second transistor.

[0084] (Item 6) the amplifier unit includes a first transistor disposed on the first semiconductor substrate and having a gate electrode connected to an output node of the photoelectric conversion element, and a second transistor disposed on the second semiconductor substrate and serving as a current source that configures a source follower circuit together with the first transistor, the bias generating unit includes a third transistor that forms a current mirror with the second transistor to supply the bias potential to a gate electrode of the second transistor; 4. The photoelectric conversion device according to item 3, wherein the third transistor is disposed on the second semiconductor substrate.

[0085] (Item 7) 7. The photoelectric conversion device according to any one of items 1 to 6, wherein the amplifier section and the bias generation section are supplied with power from a common power supply line.

[0086] (Item 8) 8. The photoelectric conversion device according to any one of items 1 to 7, wherein the processing circuit includes an AD conversion circuit.

[0087] (Item 9) 9. The photoelectric conversion device according to item 8, wherein the amplifier section and the AD conversion circuit are supplied with power from different power supply lines.

[0088] (Item 10) the amplifier unit as a first amplifier unit, and the bias generation unit as a first bias generation unit, the processing circuit includes a second amplifier that amplifies the signal read from the storage capacitor; The photoelectric conversion device described in any one of items 1 to 9, further comprising a second bias generation unit that supplies a bias potential to the second amplification unit for operating the second amplification unit.

[0089] (Item 11) 11. The photoelectric conversion device according to item 10, wherein the second bias generating section is disposed on the third semiconductor substrate.

[0090] (Item 12) The amplifier unit is a first amplifier unit, the processing circuit includes a second amplifier that amplifies the signal read from the storage capacitor; 10. The photoelectric conversion device according to any one of items 1 to 9, wherein the bias generating section supplies a bias potential to the second amplifying section for operating the second amplifying section.

[0091] (Item 13) A photoelectric conversion device including a plurality of pixels and a processing circuit that processes signals read from the plurality of pixels, and in which a plurality of semiconductor substrates are stacked, each of the plurality of pixels includes a photoelectric conversion element, an amplifier that amplifies a signal from the photoelectric conversion element, and a storage capacitor that stores an output of the amplifier; the photoelectric conversion device further includes a bias generating unit that supplies a bias potential to the amplifier unit for operating the amplifier unit; The photoelectric conversion device is characterized in that the plurality of semiconductor substrates include a first semiconductor substrate on which the photoelectric conversion element, the amplifier unit, and the bias generation unit are arranged, a second semiconductor substrate on which the storage capacitor is arranged, and a third semiconductor substrate on which the processing circuit is arranged, and the second semiconductor substrate is arranged between the first semiconductor substrate and the third semiconductor substrate.

[0092] (Item 14) A photoelectric conversion device including a plurality of pixels and a processing circuit that processes signals read from the plurality of pixels, and in which a plurality of semiconductor substrates are stacked, each of the plurality of pixels includes a photoelectric conversion element, an amplifier, the amplifier that amplifies a signal from the photoelectric conversion element, and a storage capacitor that stores an output of the amplifier; the photoelectric conversion device further includes a bias generating unit that supplies a bias potential to the amplifier unit for operating the amplifier unit; the plurality of pixels are arranged on a first semiconductor substrate among the plurality of semiconductor substrates, the processing circuit is disposed on a semiconductor substrate other than the first semiconductor substrate among the plurality of semiconductor substrates; The photoelectric conversion device, wherein at least a portion of the bias generating section is disposed on the first semiconductor substrate.

[0093] (Item 15) A photoelectric conversion device including a plurality of pixels and a processing circuit that processes signals read from the plurality of pixels, and in which a plurality of semiconductor substrates are stacked, each of the plurality of pixels includes a photoelectric conversion element, an amplifier that amplifies a signal from the photoelectric conversion element, and a storage capacitor that stores an output of the amplifier; the photoelectric conversion device further includes a bias generating unit that supplies a bias potential to the amplifier unit for operating the amplifier unit; the plurality of pixels are arranged on a first semiconductor substrate among the plurality of semiconductor substrates, The photoelectric conversion device, wherein the processing circuit and the bias generation unit are disposed on a semiconductor substrate other than the first semiconductor substrate among the plurality of semiconductor substrates.

[0094] (Item 16) A photoelectric conversion device according to any one of items 1 to 15, a processing device that processes a signal output from the photoelectric conversion device; An apparatus characterized by comprising:

[0095] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0096] 1: photoelectric conversion device, 11: pixel, 12: bias generation unit, 108 to 110: storage capacitor, 1000, 2000, 3000, 4000: semiconductor substrate, PD1, PD2: photoelectric conversion element

Claims

1. A photoelectric conversion device including a plurality of pixels and a processing circuit that processes signals read from the plurality of pixels, and in which a plurality of semiconductor substrates are stacked, each of the plurality of pixels includes a photoelectric conversion element, an amplifier that amplifies a signal from the photoelectric conversion element, and a storage capacitor that stores an output of the amplifier; the photoelectric conversion device further includes a bias generating unit that supplies a bias potential to the amplifier unit for operating the amplifier unit; the plurality of semiconductor substrates include a first semiconductor substrate on which the photoelectric conversion element is arranged, a second semiconductor substrate on which the storage capacitor is arranged, and a third semiconductor substrate on which the processing circuit is arranged, the second semiconductor substrate being arranged between the first semiconductor substrate and the third semiconductor substrate; the amplifier unit includes an element disposed on the first semiconductor substrate and an element disposed on the second semiconductor substrate, The photoelectric conversion device, wherein the bias generating section is disposed on the third semiconductor substrate.

2. A photoelectric conversion device including a plurality of pixels and a processing circuit that processes signals read from the plurality of pixels, and in which a plurality of semiconductor substrates are stacked, each of the plurality of pixels includes a photoelectric conversion element, an amplifier that amplifies a signal from the photoelectric conversion element, and a storage capacitor that stores an output of the amplifier; the photoelectric conversion device further includes a bias generating unit that supplies a bias potential to the amplifier unit for operating the amplifier unit; the plurality of semiconductor substrates include a first semiconductor substrate on which the photoelectric conversion element is arranged, a second semiconductor substrate on which the storage capacitor is arranged, and a third semiconductor substrate on which the processing circuit is arranged, the second semiconductor substrate being arranged between the first semiconductor substrate and the third semiconductor substrate; the amplifier unit includes an element disposed on the first semiconductor substrate and an element disposed on the second semiconductor substrate, The photoelectric conversion device, wherein the bias generating section is disposed on the second semiconductor substrate.

3. A photoelectric conversion device including a plurality of pixels and a processing circuit that processes signals read from the plurality of pixels, and in which a plurality of semiconductor substrates are stacked, each of the plurality of pixels includes a photoelectric conversion element, an amplifier that amplifies a signal from the photoelectric conversion element, and a storage capacitor that stores an output of the amplifier; the photoelectric conversion device further includes a bias generating unit that supplies a bias potential to the amplifier unit for operating the amplifier unit; the plurality of semiconductor substrates include a first semiconductor substrate on which the photoelectric conversion element is arranged, a second semiconductor substrate on which the storage capacitor is arranged, and a third semiconductor substrate on which the processing circuit is arranged, the second semiconductor substrate being arranged between the first semiconductor substrate and the third semiconductor substrate; the amplifier unit includes an element disposed on the first semiconductor substrate and an element disposed on the second semiconductor substrate, The photoelectric conversion device, wherein the bias generation unit includes an element disposed on the second semiconductor substrate and an element disposed on the third semiconductor substrate.

4. The photoelectric conversion device according to claim 1, characterized in that the amplifier section includes a first transistor arranged on the first semiconductor substrate and having a gate electrode connected to an output node of the photoelectric conversion element, and a second transistor arranged on the second semiconductor substrate and serving as a current source that forms a source follower circuit together with the first transistor.

5. 5. The photoelectric conversion device according to claim 4, wherein the bias generating section supplies the bias potential to a gate electrode of the second transistor.

6. the amplifier unit includes: a first transistor disposed on the first semiconductor substrate and having a gate electrode connected to an output node of the photoelectric conversion element; and a second transistor disposed on the second semiconductor substrate and serving as a current source that configures a source follower circuit together with the first transistor; the bias generating unit includes a third transistor that forms a current mirror with the second transistor to supply the bias potential to a gate electrode of the second transistor; The photoelectric conversion device according to claim 3 , wherein the third transistor is disposed on the second semiconductor substrate.

7. 2. The photoelectric conversion device according to claim 1, wherein the amplifier and the bias generator are supplied with power from a common power supply line.

8. 2. The photoelectric conversion device according to claim 1, wherein the processing circuit includes an AD conversion circuit.

9. 9. The photoelectric conversion device according to claim 8, wherein the amplifier section and the AD conversion circuit are supplied with power from different power supply lines.

10. the amplifier unit is a first amplifier unit, and the bias generation unit is a first bias generation unit, the processing circuit includes a second amplifier that amplifies the signal read from the storage capacitor; 2. The photoelectric conversion device according to claim 1, further comprising a second bias generating unit that supplies a bias potential for operating the second amplifier unit to the second amplifier unit.

11. The photoelectric conversion device according to claim 10 , wherein the second bias generating unit is disposed on the third semiconductor substrate.

12. The amplifier unit is a first amplifier unit, the processing circuit includes a second amplifier that amplifies the signal read from the storage capacitor; 2. The photoelectric conversion device according to claim 1, wherein the bias generating section supplies a bias potential to the second amplifying section for operating the second amplifying section.

13. A photoelectric conversion device including a plurality of pixels and a processing circuit that processes signals read from the plurality of pixels, and in which a plurality of semiconductor substrates are stacked, each of the plurality of pixels includes a photoelectric conversion element, an amplifier that amplifies a signal from the photoelectric conversion element, and a storage capacitor that stores an output of the amplifier; the photoelectric conversion device further includes a bias generating unit that supplies a bias potential to the amplifier unit for operating the amplifier unit; The photoelectric conversion device is characterized in that the plurality of semiconductor substrates include a first semiconductor substrate on which the photoelectric conversion element, the amplifier unit, and the bias generation unit are arranged, a second semiconductor substrate on which the storage capacitor is arranged, and a third semiconductor substrate on which the processing circuit is arranged, and the second semiconductor substrate is arranged between the first semiconductor substrate and the third semiconductor substrate.

14. A photoelectric conversion device including a plurality of pixels and a processing circuit that processes signals read from the plurality of pixels, and in which a plurality of semiconductor substrates are stacked, each of the plurality of pixels includes a photoelectric conversion element, an amplifier, the amplifier that amplifies a signal from the photoelectric conversion element, and a storage capacitor that stores an output of the amplifier; the photoelectric conversion device further includes a bias generating unit that supplies a bias potential to the amplifier unit for operating the amplifier unit; the plurality of pixels are arranged on a first semiconductor substrate among the plurality of semiconductor substrates, the processing circuit is disposed on a semiconductor substrate other than the first semiconductor substrate among the plurality of semiconductor substrates; The photoelectric conversion device, wherein at least a portion of the bias generating section is disposed on the first semiconductor substrate.

15. A photoelectric conversion device including a plurality of pixels and a processing circuit that processes signals read from the plurality of pixels, and in which a plurality of semiconductor substrates are stacked, each of the plurality of pixels includes a photoelectric conversion element, an amplifier that amplifies a signal from the photoelectric conversion element, and a storage capacitor that stores an output of the amplifier; the photoelectric conversion device further includes a bias generating unit that supplies a bias potential to the amplifier unit for operating the amplifier unit; the plurality of pixels are arranged on a first semiconductor substrate among the plurality of semiconductor substrates, The photoelectric conversion device, wherein the processing circuit and the bias generation unit are disposed on a semiconductor substrate other than the first semiconductor substrate among the plurality of semiconductor substrates.

16. The photoelectric conversion device according to any one of claims 1 to 15, a processing device that processes a signal output from the photoelectric conversion device; An apparatus characterized by comprising:

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