Semiconductor device

Abstract

To provide a semiconductor device that consumes less power.SOLUTION: The semiconductor device has a first transistor, a second transistor, and a capacitance. The first transistor has a first gate and a first back gate. The second transistor has a second gate and a second back gate. A gate insulation layer for the first back gate has ferroelectricity. The first transistor has a function of holding a first potential in accordance with first data when in an off state. The second transistor has a function of flowing an output current across a source and a drain of the second transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] Currently, active development is underway on integrated circuits that mimic the workings of the human brain. These integrated circuits incorporate the workings of the brain as electronic circuits, and have circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brainmorphic," or "brain-inspired." These integrated circuits have a non-von Neumann architecture, and are expected to be able to perform parallel processing with significantly less power consumption than von Neumann architectures, which consume more power as processing speed increases.

[0004] An information processing model that mimics a neural network with "neurons" and "synapses" is called an artificial neural network (ANN). By using an artificial neural network, it is possible to make inferences with accuracy comparable to or even exceeding that of humans. In an artificial neural network, the main operation is the weighted sum of neuron outputs, i.e., the sum-of-products operation.

[0005] Non-Patent Document 1 proposes a product-sum circuit using non-volatile memory cells. In this product-sum circuit, each memory cell utilizes the subthreshold operation of a transistor having silicon in its channel formation region to output a current corresponding to the multiplication of data corresponding to a multiplier stored in the memory cell and input data corresponding to a multiplicand. Furthermore, data corresponding to the product-sum operation is obtained by summing the currents output by the memory cells in each column. Because this product-sum circuit has internal memory cells, it is not necessary to read or write data from an external memory during multiplication and addition. This reduces the number of data transfers due to reads, writes, etc., and is therefore expected to reduce power consumption. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] X. Guo et al., “Fast, Energy-Efficient, Robust, and Reproducible Mixed-Signal Neuromorphic Classifier Based on Embedded NOR Flash Memory Technology” IEDM2017, pp.151-154. Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a semiconductor device that can retain data for a long time.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a novel semiconductor device or the like.

[0008] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but it is sufficient that it can solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a capacitor. The first transistor has a first gate and a first back gate. The second transistor has a second gate and a second back gate. A gate insulating layer for the first back gate is ferroelectric. The first transistor has a function of holding a first potential corresponding to first data provided to the second back gate via the first transistor when in an off state. The capacitor has a function of changing the first potential held in the second back gate to a second potential in response to a change in potential corresponding to second data provided to one electrode of the capacitor. The second transistor has a function of flowing an output current corresponding to the potential of the second back gate between a source and a drain of the second transistor. The output current is a current that flows when the second transistor operates in a subthreshold region. A constant potential is applied to the second gate.

[0010] Alternatively, one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a capacitor, wherein the first transistor has a first gate and a first back gate, the second transistor has a second gate and a second back gate, a gate insulating layer for the first back gate having ferroelectricity, one electrode of the capacitor being electrically connected to the second gate, and a constant potential being applied to the other electrode of the capacitor, the first transistor having a function of holding a first potential corresponding to first data applied to the second gate via the first transistor when in an off state, and the second transistor having a function of flowing an output current corresponding to the potential of the second gate between a source and a drain of the second transistor, the output current being a current that flows when the second transistor operates in a subthreshold region.

[0011] Alternatively, one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a capacitor, wherein the first transistor has a first gate and a first back gate, and the second transistor has a second gate and a second back gate, a gate insulating layer for the first back gate has ferroelectricity, one electrode of the capacitor is electrically connected to the second back gate, and a constant potential is applied to the other electrode of the capacitor, the first transistor has a function of holding a first potential corresponding to first data applied to the second back gate via the first transistor when in an off state, and the second transistor has a function of flowing an output current corresponding to the potential of the second back gate between a source and a drain of the second transistor, the output current being a current that flows when the second transistor operates in a subthreshold region.

[0012] Alternatively, in the above-described embodiment, the semiconductor device may include a circuit electrically connected to the first gate, and the circuit may have a function of generating a signal that controls on / off of the first transistor.

[0013] Alternatively, in the above embodiment, the gate insulating layer for the first back gate may have an oxide containing one or both of hafnium and zirconium.

[0014] Alternatively, one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and a ferroelectric capacitor, each of the first to third transistors having a gate and a back gate, one of a source or a drain of the first transistor electrically connected to one of a source or a drain of the second transistor and one electrode of the first capacitor, the other of the source or the drain of the first transistor electrically connected to the back gate of the second transistor and the other electrode of the first capacitor, the back gate of the first transistor electrically connected to one of a source or a drain of the third transistor, the back gate of the third transistor, and one of a source or a drain of the fourth transistor, the gate of the third transistor electrically connected to one electrode of the ferroelectric capacitor, and the other of the source or the drain of the fourth transistor electrically connected to the other electrode of the ferroelectric capacitor and one electrode of the second capacitor.

[0015] Alternatively, in the above embodiment, a constant potential may be applied to the gate of the second transistor.

[0016] Alternatively, one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and a ferroelectric capacitor, each of the first to third transistors having a gate and a back gate, one of a source or a drain of the first transistor electrically connected to one of a source or a drain of the second transistor, the other of the source or the drain of the first transistor electrically connected to a gate of the second transistor and one electrode of the first capacitor, the back gate of the first transistor electrically connected to one of a source or a drain of the third transistor, the back gate of the third transistor, and one of a source or a drain of the fourth transistor, the gate of the third transistor electrically connected to one electrode of the ferroelectric capacitor, and the other of the source or the drain of the fourth transistor electrically connected to the other electrode of the ferroelectric capacitor and one electrode of the second capacitor.

[0017] Alternatively, one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and a ferroelectric capacitor, each of the first to third transistors having a gate and a back gate, one of a source or a drain of the first transistor electrically connected to one of a source or a drain of the second transistor, the other of the source or the drain of the first transistor electrically connected to the back gate of the second transistor and one electrode of the first capacitor, the back gate of the first transistor electrically connected to one of a source or a drain of the third transistor, the back gate of the third transistor, and one of a source or a drain of the fourth transistor, the gate of the third transistor electrically connected to one electrode of the ferroelectric capacitor, and the other of the source or the drain of the fourth transistor electrically connected to the other electrode of the ferroelectric capacitor and one electrode of the second capacitor.

[0018] Alternatively, in the above embodiment, a constant potential may be applied to the other electrode of the first capacitor.

[0019] Alternatively, in the above-described embodiment, the semiconductor device may include a circuit electrically connected to a gate of the first transistor, and the circuit may have a function of generating a signal for controlling the on / off of the first transistor.

[0020] Alternatively, in the above-described embodiment, the ferroelectric capacitor may have a dielectric layer, and the dielectric layer may have an oxide containing one or both of hafnium and zirconium.

[0021] Alternatively, in the above embodiment, the first transistor may have a semiconductor layer having a metal oxide in a channel formation region.

[0022] Alternatively, in the above embodiment, the metal oxide may contain In, Ga, and Zn.

[0023] Alternatively, in the above embodiment, the second transistor may have a semiconductor layer having silicon in a channel formation region.

[0024] Another embodiment of the present invention is an electronic device that includes a semiconductor device according to one embodiment of the present invention and a housing and performs neural network calculations using the semiconductor device.

[0025] Other aspects of the present invention will be described in the following embodiments and in the drawings. [Effects of the Invention]

[0026] According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can retain data for a long time can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device or the like can be provided.

[0027] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the exemplified effects. Furthermore, problems, effects, and novel features of one embodiment of the present invention other than those described above will become apparent from the description and drawings of this specification. [Brief explanation of the drawings]

[0028] [Figure 1] 1A and 1B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 2] 2A and 2B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 3] 3A and 3B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 4] 4A and 4B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 5] 5A and 5B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 6] 6A and 6B are diagrams illustrating a configuration example of a semiconductor device. [Figure 7] 7A and 7B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 8] 8A and 8B are diagrams illustrating an example of a method of operating a semiconductor device. [Figure 9] 9A and 9B are diagrams illustrating an example of a method of operating a semiconductor device. [Figure 10] 10A and 10B are diagrams illustrating an example of a method of operating a semiconductor device. [Figure 11] 11A and 11B are diagrams illustrating an example of a method of operating a semiconductor device. [Figure 12] 12A and 12B are diagrams illustrating an example of a method of operating a semiconductor device. [Figure 13] FIG. 13 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 14] FIG. 14 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 15] FIG. 15 is a diagram illustrating a configuration example of a semiconductor device. [Figure 16] FIG. 16 is a diagram illustrating an example of the configuration of an arithmetic circuit. [Figure 17] 17A, 17B, and 17C are diagrams for explaining configuration examples of arithmetic circuits. [Figure 18] 18A, 18B, 18C, and 18D are diagrams for explaining configuration examples of arithmetic circuits. [Figure 19] 19A, 19B, and 19C are diagrams for explaining configuration examples of arithmetic circuits. [Figure 20] FIG. 20 is a diagram illustrating an example of the configuration of an arithmetic circuit. [Figure 21] 21, 21A and 21B are diagrams illustrating a neural network. [Figure 22] Fig. 22A is a diagram illustrating a configuration example of a semiconductor device, and Fig. 22B and Fig. 22C are diagrams illustrating configuration examples of a transistor. [Figure 23] 23A and 23B are diagrams illustrating examples of the configuration of a transistor. [Figure 24] FIG. 24 is a diagram illustrating an example of the configuration of a transistor. [Figure 25] 25A to 25C illustrate examples of the structure of a transistor. [Figure 26] Figure 26A is a diagram explaining the classification of IGZO crystal structures, Figure 26B is a diagram explaining the XRD spectrum of crystalline IGZO, and Figure 26C is a diagram explaining the micro-electron beam diffraction pattern of crystalline IGZO. [Figure 27] FIG. 27 is a diagram illustrating an example of the configuration of an integrated circuit. [Figure 28] 28A and 28B are diagrams illustrating an application example of an integrated circuit. [Figure 29] 29A and 29B are diagrams illustrating an application example of an integrated circuit. [Figure 30] 30A, 30B, and 30C are diagrams illustrating an application example of an integrated circuit. [Figure 31] FIG. 31 is a diagram illustrating an application example of an integrated circuit. DETAILED DESCRIPTION OF THE INVENTION

[0029] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0030] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0031] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0032] In this specification, for example, the power supply potential VDD may be abbreviated to potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0033] In addition, when the same symbol is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "_2", "_n", or "_m,n" may be added to the symbol.

[0034] (Embodiment 1) The structure, operation, and the like of a semiconductor device according to one embodiment of the present invention will be described.

[0035] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0036] FIG. 1A is a diagram illustrating a semiconductor device 10A1 according to one aspect of the present invention.

[0037] The semiconductor device 10A1 has a reference cell 21(1) and a calculation cell 31(1). The reference cell 21(1) has a transistor 22, a transistor 24, and a capacitor 25. The calculation cell 31(1) has a transistor 32, a transistor 34, and a capacitor 35. The transistor 22, the transistor 24, the transistor 32, and the transistor 34 each have a gate and a back gate.

[0038] In this specification and the like, for example, when a transistor having a function as a switch has a gate and a back gate, the transistor can be turned on and off by controlling the potential of the gate, and the threshold voltage of the transistor can be controlled by controlling the potential of the back gate.

[0039] The transistors and capacitors of the reference cell 21(1) and the calculation cell 31(1) are connected to at least one of the wiring WSL, the wiring XCL, the wiring WCL, and the wiring that applies the ground potential, as shown in FIG.

[0040] The reference cell 21(1) has the function of causing the arithmetic cell 31(1) to perform an arithmetic operation by passing a set current when writing data and when reading data. Specifically, when writing data, a reference current is passed through the reference cell 21(1) to maintain a reference potential, and then, when reading data, a current corresponding to the input data (X) given to the arithmetic cell 31(1) is passed through the reference cell 21(1) to control the current flowing through the arithmetic cell 31(1). Note that the reference cell 21(1) may also be simply referred to as a cell.

[0041] Next, the connections within the reference cell 21(1) will be described.

[0042] The gate of the transistor 22 is electrically connected to a wiring WSL. One of the source or drain of the transistor 22 is electrically connected to one of the source or drain of the transistor 24 and is also electrically connected to one electrode of the capacitor 25 via a wiring XCL. The other of the source or drain of the transistor 22 is electrically connected to the backgate of the transistor 24 and the other electrode of the capacitor 25. When writing data, the transistor 22 is turned on to write a reference potential to a retention node (the backgate of the transistor 24) in the reference cell 21(1). When the transistor 22 is turned off, the reference potential can be retained in the reference cell 21(1). Note that the node to which the backgate of the transistor 24, the other of the source or drain of the transistor 22, and the other electrode of the capacitor 25 are connected is also referred to as a retention node. The retention node can be set to a potential according to the current flowing through the transistor 24.

[0043] Here, the threshold voltage of the transistor 22 can be controlled by controlling the potential of the back gate of the transistor 22. Specifically, the threshold voltage of the transistor 22 can be lowered by increasing the potential of the back gate of the transistor 22. On the other hand, the threshold voltage of the transistor 22 can be increased by decreasing the potential of the back gate of the transistor 22. Therefore, increasing the potential of the back gate of the transistor 22 when the transistor 22 is on can increase the on-state current of the transistor 22, and decreasing the potential of the back gate of the transistor 22 when the transistor 22 is off can decrease the off-state current of the transistor 22.

[0044] The gate of the transistor 24 and the other of the source and drain of the transistor 24 are connected to a wiring that applies a constant potential such as a low power supply potential (for example, a ground potential). The wiring that applies the ground potential functions as a wiring for flowing a current between the source and drain of the transistor 24.

[0045] The capacitor 25 changes the potential of one electrode in response to a change in the potential applied to the other electrode when the other electrode is in an electrically floating state.

[0046] When writing data, the arithmetic cell 31(1) has the function of passing a current corresponding to the weight data (W) held in the arithmetic cell 31(1) and holding a voltage corresponding to the current. When reading data, the arithmetic cell 31(1) has the function of passing a current corresponding to the calculation of the weight data and input data by boosting the voltage held when writing data according to the current flowing through the reference cell 21(1). The weight data may be referred to as first data, and the input data may be referred to as second data. The arithmetic cell 31(1) may also be simply referred to as a cell. The weight data may be data (weight data) corresponding to weight parameters used in product-sum calculations of an artificial neural network, for example.

[0047] Next, the connections within the operation cell 31(1) will be explained.

[0048] The gate of the transistor 32 is electrically connected to the wiring WSL. One of the source or drain of the transistor 32 is electrically connected to one of the source or drain of the transistor 34 and the wiring WCL. One electrode of the capacitor 35 is electrically connected to the wiring XCL. The other of the source or drain of the transistor 32 is electrically connected to the backgate of the transistor 34 and the other electrode of the capacitor 35. When data is written, the transistor 32 is turned on to write a voltage corresponding to weight data into the arithmetic cell 31(1), and when the transistor 32 is turned off, the voltage corresponding to the weight data can be held in the arithmetic cell 31(1). Note that a node to which the backgate of the transistor 34, the other of the source or drain of the transistor 32, and the other electrode of the capacitor 35 are connected is also referred to as a holding node.

[0049] Here, the threshold voltage of the transistor 32 can be controlled by controlling the potential of the back gate of the transistor 32. Specifically, the threshold voltage of the transistor 32 can be lowered by increasing the potential of the back gate of the transistor 32. On the other hand, the threshold voltage of the transistor 32 can be increased by decreasing the potential of the back gate of the transistor 32. Therefore, increasing the potential of the back gate of the transistor 32 when the transistor 32 is on can increase the on-state current of the transistor 32, and decreasing the potential of the back gate of the transistor 32 when the transistor 32 is off can decrease the off-state current of the transistor 32.

[0050] The gate of the transistor 34 and the other of the source and drain of the transistor 34 are connected to a wiring that applies a constant potential such as a low power supply potential (for example, a ground potential). The wiring that applies the ground potential functions as a wiring for flowing a current between the source and drain of the transistor 34.

[0051] The capacitor 35 changes the potential of one electrode in response to a change in the potential applied to the other electrode when the other electrode is in an electrically floating state.

[0052] Next, the transistors included in the reference cell 21(1) and the operation cell 31(1) will be described.

[0053] Unless otherwise specified, the transistors 24 and 34 operate in the subthreshold region. The drain current Id of a transistor operating in the subthreshold region can be expressed by equation (1).

[0054]

number

[0055] In equation (1), I0 is V g =V th The drain current when , q is the elementary charge, V g is the gate voltage, V th is the threshold voltage, η is a coefficient determined by the device structure, etc., and k B is the Boltzmann constant, and T is temperature. As shown in equation (1), the drain current Id of a transistor operating in the subthreshold region does not depend on the drain voltage. The current flowing through transistors 24 and 34 is the same as the current flowing when they operate in the subthreshold region. The current in the subthreshold region of transistors 24 and 34 can reduce the influence of drain voltage variations. This can improve the accuracy of the data obtained by calculation.

[0056] In this specification, the subthreshold region refers to the region where the gate voltage is lower than the threshold voltage in a graph showing the gate voltage (Vg)-drain current (Id) characteristics of a transistor. Alternatively, the subthreshold region refers to the region where current flows due to carrier diffusion, which deviates from the gradual channel approximation (a model that only considers drift current). Alternatively, the subthreshold region refers to the region where the drain current increases exponentially with increasing gate voltage. Alternatively, the subthreshold region includes the regions that can be considered as the regions described above.

[0057] The drain current when a transistor operates in the subthreshold region is called the subthreshold current. The subthreshold current increases exponentially with gate voltage, regardless of drain voltage. Circuit operation using the subthreshold current can reduce the effect of drain voltage variations.

[0058] When the transistor 22 and the transistor 32 are turned off, they maintain the potentials of the back gates of the transistors 24 and 34. Specifically, they maintain a reference potential applied to the back gate of the transistor 24 via the transistor 22. They also maintain a potential corresponding to data applied to the back gate of the transistor 34 via the transistor 32. For example, the transistors 22 and 32 are preferably transistors having a metal oxide in a channel formation region (also referred to as OS transistors). For example, the channel formation regions of the transistors 22 and 32 are more preferably oxides containing at least one of indium, gallium, and zinc. Alternatively, an oxide containing at least one of indium, an element M (e.g., the element M can be one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.), and zinc may be used instead of the oxide.

[0059] The OS transistor has an extremely small leakage current, i.e., a current flowing between the source and drain in the off state. Therefore, using an OS transistor as transistor 22 and / or transistor 32 can suppress the leakage current of transistor 22 and / or transistor 32, thereby reducing the power consumption of semiconductor device 10A1. Specifically, fluctuations in the potentials held at the back gates of transistors 24 and 34 can be significantly reduced, thereby reducing the number of refresh operations for the potentials. Furthermore, reducing the number of refresh operations can reduce the power consumption of semiconductor device 10A1. Furthermore, significantly reducing the leakage current from the retention node to wiring WCL or wiring XCL allows the cell to retain the potential of the retention node for a long time.

[0060] In addition, when the gate voltage is lower than the threshold voltage of the OS transistor, the -20 Less than A, 1 x 10 -22 Less than A or 1 x 10 -24 The OS transistor can pass an extremely small drain current per 1 μm of channel width, less than 1.0 × 10 A. When the gate voltage is the threshold voltage of the transistor, -8 A or less, 1.0×10 -12 A or less, or 1.0 x 10 -15 A or less per 1 μm of channel width can flow. Therefore, OS transistors can flow subthreshold currents of different magnitudes within the range of gate voltages in which they operate in the subthreshold region. In other words, OS transistors can operate in a wide range of gate voltages in the subthreshold region. Specifically, if the threshold voltage of an OS transistor is V th In the subthreshold region, (V th -1.0V) or more V th Below, or (V th -0.5V) or more V th The circuit can operate using gate voltages in the following voltage ranges:

[0061] Because the band gap of metal oxides that function as oxide semiconductors is 2.5 eV or more, OS transistors have extremely small off-state currents. For example, when the source-drain voltage is 3.5 V and the temperature is room temperature (25°C), the off-state current per 1 μm of channel width is 1×10 -20 Less than A, 1 x 10 -22 Less than A or 1 x 10 -24 Therefore, the OS memory has an extremely small amount of charge leaking from the retention node through the OS transistor.

[0062] Metal oxides suitable for OS transistors include Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (where M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). Metal oxides using Ga as M are particularly preferred for OS transistors because they can provide transistors with excellent electrical properties, such as field-effect mobility, by adjusting the ratio of elements. Furthermore, the oxide containing indium and zinc may contain one or more elements selected from the group consisting of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

[0063] To improve the reliability and electrical characteristics of an OS transistor, the metal oxide used in the semiconductor layer is preferably a metal oxide having a crystalline portion, such as CAAC-OS, CAC-OS, or nc-OS. CAAC-OS is an abbreviation for c-axis-aligned crystalline oxide semiconductor. CAC-OS is an abbreviation for cloud-aligned composite oxide semiconductor. nc-OS is an abbreviation for nanocrystalline oxide semiconductor.

[0064] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distorted crystal structure refers to the change in the lattice orientation between regions with a uniform lattice arrangement and regions with a different uniform lattice arrangement in the regions where multiple nanocrystals are connected.

[0065] CAC-OS has the function of both allowing electrons (or holes) to flow and preventing electrons from flowing. By separating the electron flow function from the electron blocking function, both functions can be maximized. In other words, using CAC-OS in the channel formation region of an OS transistor can achieve both a high on-state current and an extremely low off-state current.

[0066] OS transistors are accumulation-mode transistors that use electrons as majority carriers. Therefore, they are less susceptible to drain-induced barrier lowering (DIBL), a short-channel effect, compared to inversion-mode transistors with pn junctions. In other words, OS transistors have higher resistance to short-channel effects than Si transistors.

[0067] Furthermore, by using OS transistors for the transistors 24 and 34, the transistors can operate over a wide current range in the subthreshold region, thereby reducing current consumption. Furthermore, by using OS transistors for the transistors 24 and 34, the transistors can be manufactured simultaneously with the transistors 22 and 32, which may shorten the manufacturing process of the arithmetic circuit.

[0068] Note that the transistor 22, the transistor 24, the transistor 32, and the transistor 34 do not necessarily have to be OS transistors. For example, the transistor 22, the transistor 24, the transistor 32, and the transistor 34 can be Si transistors. As silicon, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon, or the like can be used.

[0069] 1 are n-channel transistors, the semiconductor device of one embodiment of the present invention is not limited thereto. For example, some or all of the transistors 22, 24, 32, and 34 may be replaced with p-channel transistors. Note that when some or all of the transistors 22, 24, 32, and 34 are replaced with p-channel transistors, the voltages applied to the wirings may be changed as necessary so that the transistors 22, 24, 32, and 34 operate as desired.

[0070] The above-described examples of changes in the structure and polarity of the transistors are not limited to the transistors 22, 24, 32, and 34. For example, the structure, polarity, etc. of transistors described elsewhere in the specification or illustrated in other drawings may also be changed in a similar manner.

[0071] Next, the wiring WSL, the wiring XCL, and the wiring WCL connected to the reference cell 21(1) and the processing cell 31(1) will be described.

[0072] A signal that controls the on / off of the transistor 22 and the transistor 32, which function as switches, is applied to the wiring WSL. The wiring WSL functions as a write word line when writing data to the reference cell 21(1) and the processing cell 31(1). Here, data is written to the reference cell 21(1) or the processing cell 31(1) by passing a current corresponding to desired data through the wiring XCL or the wiring WCL. Data is written to the reference cell 21(1) or the processing cell 31(1) by applying a potential corresponding to desired data to the wiring XCL or the wiring WCL. Data is written to the reference cell 21(1) by turning on the transistor 22, and to the processing cell 31(1) by turning on the transistor 32. The transistors 22 and 32 can be turned on by setting the wiring WSL to an H level (high-level potential). Data is retained in the reference cell 21(1) by turning off the transistor 22, and to the processing cell 31(1) by turning off the transistor 32. The transistor 22 and the transistor 32 can be turned off by setting the wiring WSL to the L level (low-level potential).

[0073] The wiring WCL supplies a current (weight current or current I) of an amount corresponding to weight data (also referred to as first data or first input data) to the operation cell 31(1). Wut ) or a function of applying a constant potential to cause a current to flow according to the potential held in the processing cell 31(1).

[0074] The wiring XCL supplies a current amount (reference current or current I) corresponding to the reference data to the reference cell 21(1) and the operation cell 31(1). Xut ), or the amount of current (input current or current I X ) has the function of flowing.

[0075] 1B is a diagram illustrating a semiconductor device 10B1 according to one embodiment of the present invention. In the semiconductor device 10B1, the gate insulating layer for the back gate of the transistor 22 and the gate insulating layer for the back gate of the transistor 32 included in the semiconductor device 10A1 contain a material that can have ferroelectricity.

[0076] In the circuit diagrams in this specification and elsewhere, the gate insulating layer for the back gate of a transistor is shown to have a material that may have ferroelectric properties by adding a diagonal line to the back gate.

[0077] In this specification, ferroelectricity refers to the property of maintaining a polarized state even after application of a voltage has been stopped, whereas paraelectricity refers to the property of not maintaining a polarized state but disappearing when application of a voltage has been stopped.

[0078] Materials that can have ferroelectric properties include hafnium oxide, zirconium oxide, and HfZrO X (X is a real number greater than 0), materials in which element J1 (here, element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to hafnium oxide, and materials in which element J2 (here, element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to zirconium oxide. Furthermore, materials that may have ferroelectricity include PbTiO XPiezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used. Ferroelectric materials may be, for example, a plurality of materials selected from the above-listed materials, or a laminated structure made of a plurality of materials selected from the above-listed materials. Incidentally, hafnium oxide, zirconium oxide, HfZrO X and materials in which the element J1 is added to hafnium oxide, etc., may have crystal structures (characteristics) that can change not only depending on the film formation conditions but also on various processes, etc., and therefore are referred to in this specification as materials that may have ferroelectricity.

[0079] Among these, hafnium oxide or a material containing hafnium oxide and zirconium oxide is preferable as a material that can have ferroelectricity, since it can be processed into a thin film of several nm and still have ferroelectricity.

[0080] The film thickness of the material that can have ferroelectricity can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically 2 nm or more and 9 nm or less). X When using the above, it is preferable to form the film by atomic layer deposition (ALD), particularly by thermal ALD.

[0081] Furthermore, when a film of a material that may have ferroelectricity is formed using a thermal ALD method, it is preferable to use a material that does not contain hydrocarbons (also called Hydro Carbon, HC) as a precursor. If the material that may have ferroelectricity contains either or both of hydrogen and carbon, this may hinder the crystallization of the material that may have ferroelectricity. For this reason, as described above, it is preferable to use a precursor that does not contain hydrocarbons to reduce the concentration of either or both of hydrogen and carbon in the material that may have ferroelectricity. For example, a chlorine-based material can be used as a precursor that does not contain hydrocarbons. Note that a material that contains hafnium oxide and zirconium oxide (HfZrO x ) is used, HfCl4 and / or ZrCl4 may be used as the precursor.

[0082] Furthermore, when a film of a material that may have ferroelectricity is formed using a thermal ALD method, HO or O can be used as the oxidizing agent. However, the oxidizing agent used in the thermal ALD method is not limited to these. For example, the oxidizing agent used in the thermal ALD method may include one or more selected from O, O, N, NO, HO, and HO.

[0083] Furthermore, the crystal structure of the material that can have ferroelectricity is not particularly limited. For example, the crystal structure of the material that can have ferroelectricity may be one or more selected from cubic, tetragonal, orthorhombic, and monoclinic. In particular, the material that can have ferroelectricity has an orthorhombic crystal structure, which is preferable because it exhibits ferroelectricity. Alternatively, the material that can have ferroelectricity may have a composite structure having an amorphous structure and a crystalline structure.

[0084] Examples of materials that can have paraelectricity include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, etc. Silicon oxide and silicon oxynitride are particularly preferred because they are stable to heat.

[0085] In the semiconductor device 10B1, the polarization state of the gate insulating layer relative to the back gate of the transistor 22 can be controlled by controlling the potential of the back gate of the transistor 22. This allows the threshold voltage of the transistor 22 to be controlled. Similarly, the polarization state of the gate insulating layer relative to the back gate of the transistor 32 can be controlled by controlling the potential of the back gate of the transistor 32, thereby allowing the threshold voltage of the transistor 32 to be controlled.

[0086] Furthermore, in the semiconductor device 10B1, after the gate insulating layer for the back gate of the transistor 22 or the transistor 32 is polarized, the gate insulating layer can maintain the polarized state even if the supply of potential to the back gate is stopped. Therefore, it is not necessary to continue supplying potential to the back gates of the transistors 22 and 32. Therefore, the semiconductor device 10B1 can be a semiconductor device with low power consumption.

[0087] 2A is a diagram illustrating a semiconductor device 10A2 according to one embodiment of the present invention. In the following description of the semiconductor device 10A2, the description of the same configuration as that of the semiconductor device 10A1 may be omitted.

[0088] The semiconductor device 10A2 has a reference cell 21(2) and a calculation cell 31(2). Like the reference cell 21(1), the reference cell 21(2) has a transistor 22, a transistor 24, and a capacitor 25. Like the calculation cell 31(1), the calculation cell 31(2) has a transistor 32, a transistor 34, and a capacitor 35.

[0089] The gate of the transistor 22 is electrically connected to the wiring WSL. One of the source or drain of the transistor 22 is electrically connected to one of the source or drain of the transistor 24 and the wiring XCL. The other of the source or drain of the transistor 22 is electrically connected to the gate of the transistor 24 and one electrode of the capacitor 25. When writing data, the transistor 22 is turned on to write a reference potential to a retention node (the gate of the transistor 24) in the reference cell 21(2). When the transistor 22 is turned off, the reference potential can be retained in the reference cell 21(2). Note that the node to which the gate of the transistor 24, the other of the source or drain of the transistor 22, and one electrode of the capacitor 25 are connected is also referred to as a retention node. The retention node can be set to a potential according to the current flowing through the transistor 24.

[0090] The other of the source or drain of the transistor 24 and the other electrode of the capacitor 25 are connected to a wiring that applies a constant potential such as a low power supply potential (for example, ground potential). The wiring that applies the ground potential functions as a wiring for causing a current to flow between the source and drain of the transistor 24. The back gate of the transistor 24 is electrically connected to the wiring XCL.

[0091] Next, the connections within the operation cell 31(2) will be explained.

[0092] The gate of the transistor 32 is electrically connected to the wiring WSL. One of the source or drain of the transistor 32 is electrically connected to one of the source or drain of the transistor 34 and the wiring WCL. The other of the source or drain of the transistor 32 is electrically connected to the gate of the transistor 34 and one electrode of the capacitor 35. When data is written, the transistor 32 is turned on to write a voltage corresponding to weight data into the arithmetic cell 31(2), and when turned off, the voltage corresponding to the weight data can be held in the arithmetic cell 31(2). Note that a node to which the gate of the transistor 34, the other of the source or drain of the transistor 32, and one electrode of the capacitor 35 are connected is also referred to as a holding node.

[0093] The other of the source and the drain of the transistor 34 is connected to a wiring that applies a constant potential such as a low power supply potential (for example, a ground potential). The wiring that applies the ground potential functions as a wiring for flowing a current between the source and the drain of the transistor 34. The back gate of the transistor 34 is electrically connected to the wiring XCL.

[0094] Next, the transistors included in the reference cell 21(2) and the operation cell 31(2) will be described.

[0095] When the transistor 22 and the transistor 32 are turned off, they have a function of holding the potentials of the gates of the transistors 24 and 34. Specifically, they have a function of holding a reference potential applied to the gate of the transistor 24 through the transistor 22. They also have a function of holding a potential according to data applied to the gate of the transistor 34 through the transistor 32.

[0096] As described above, an OS transistor has an extremely small leakage current, i.e., a current flowing between the source and drain in an off state. Therefore, using an OS transistor as transistor 22 and / or transistor 32 can suppress the leakage current of transistor 22 and / or transistor 32, thereby reducing the power consumption of semiconductor device 10A2. Specifically, fluctuations in the potentials held at the gates of transistors 24 and 34 can be significantly reduced, thereby reducing the number of refresh operations for the potentials. Furthermore, reducing the number of refresh operations can reduce the power consumption of semiconductor device 10A2. Furthermore, significantly reducing the leakage current from the retention node to wiring WCL or wiring XCL allows the cell to retain the potential of the retention node for a long time.

[0097] 2B is a diagram illustrating a semiconductor device 10B2 according to one embodiment of the present invention, in which the gate insulating layer for the back gate of the transistor 22 and the gate insulating layer for the back gate of the transistor 32 included in the semiconductor device 10A2 contain a material that can have ferroelectricity.

[0098] 3A is a diagram illustrating a semiconductor device 10A3 according to one embodiment of the present invention. In the following description of the semiconductor device 10A3, the description of the same configuration as that of the semiconductor device 10A1 may be omitted.

[0099] Semiconductor device 10A3 has a reference cell 21(3) and a calculation cell 31(3). Like reference cell 21(1), reference cell 21(3) has a transistor 22, a transistor 24, and a capacitor 25. Like calculation cell 31(1), calculation cell 31(3) has a transistor 32, a transistor 34, and a capacitor 35. Transistor 22, transistor 24, transistor 32, and transistor 34 each have a gate and a back gate.

[0100] The gate of the transistor 22 is electrically connected to the wiring WSL. One of the source or drain of the transistor 22 is electrically connected to one of the source or drain of the transistor 24 and the wiring XCL. The other of the source or drain of the transistor 22 is electrically connected to the backgate of the transistor 24 and one electrode of the capacitor 25. When writing data, the transistor 22 is turned on to write a reference potential to a retention node (the backgate of the transistor 24) in the reference cell 21(3). By turning off the transistor 22, the reference potential can be retained in the reference cell 21(3). Note that the node to which the backgate of the transistor 24, the other of the source or drain of the transistor 22, and one electrode of the capacitor 25 are connected is also referred to as a retention node. The retention node can be set to a potential according to the current flowing through the transistor 24.

[0101] The other of the source or drain of the transistor 24 and the other electrode of the capacitor 25 are connected to a wiring that applies a constant potential such as a low power supply potential (for example, ground potential). The wiring that applies the ground potential functions as a wiring for causing a current to flow between the source and drain of the transistor 24. The gate of the transistor 24 is electrically connected to a wiring XCL.

[0102] Next, the connections within the operation cell 31(3) will be explained.

[0103] The gate of the transistor 32 is electrically connected to the wiring WSL. One of the source or drain of the transistor 32 is electrically connected to one of the source or drain of the transistor 34 and the wiring WCL. The other of the source or drain of the transistor 32 is electrically connected to the backgate of the transistor 34 and one electrode of the capacitor 35. When data is written, the transistor 32 is turned on to write a voltage corresponding to weight data into the arithmetic cell 31(3), and when turned off, the voltage corresponding to the weight data can be held in the arithmetic cell 31(3). Note that a node to which the backgate of the transistor 34, the other of the source or drain of the transistor 32, and one electrode of the capacitor 35 are connected is also referred to as a holding node.

[0104] The other of the source and the drain of the transistor 34 is connected to a wiring that applies a constant potential such as a low power supply potential (for example, a ground potential). The wiring that applies the ground potential functions as a wiring for causing a current to flow between the source and the drain of the transistor 34. The gate of the transistor 34 is electrically connected to the wiring XCL.

[0105] Next, the transistors included in the reference cell 21(3) and the operation cell 31(3) will be described.

[0106] When the transistor 22 and the transistor 32 are turned off, they have a function of holding the potentials of the back gates of the transistors 24 and 34. Specifically, they have a function of holding a reference potential applied to the back gate of the transistor 24 through the transistor 22. They also have a function of holding a potential according to data applied to the back gate of the transistor 34 through the transistor 32.

[0107] As described above, an OS transistor has an extremely small leakage current, i.e., a current flowing between the source and drain in an off state. Therefore, using an OS transistor as transistor 22 and / or transistor 32 can suppress the leakage current of transistor 22 and / or transistor 32, thereby reducing the power consumption of semiconductor device 10A3. Specifically, fluctuations in the potentials held at the back gates of transistors 24 and 34 can be significantly reduced, thereby reducing the number of refresh operations for the potentials. Furthermore, reducing the number of refresh operations can reduce the power consumption of semiconductor device 10A3. Furthermore, significantly reducing the leakage current from the retention node to wiring WCL or wiring XCL allows the cell to retain the potential of the retention node for a long time.

[0108] 3B is a diagram illustrating a semiconductor device 10B3 according to one embodiment of the present invention, in which the gate insulating layer for the back gate of the transistor 22 and the gate insulating layer for the back gate of the transistor 32 included in the semiconductor device 10A3 contain a material that can have ferroelectricity.

[0109] FIG. 4A is a diagram illustrating a semiconductor device 10C1 according to one embodiment of the present invention, FIG. 5A is a diagram illustrating a semiconductor device 10C2 according to one embodiment of the present invention, and FIG. 6A is a diagram illustrating a semiconductor device 10C3 according to one embodiment of the present invention. In the semiconductor device 10C1, the back gates of the transistors 22 and 32 included in the semiconductor device 10A1 are electrically connected to the circuit HC. In the semiconductor device 10C2, the back gates of the transistors 22 and 32 included in the semiconductor device 10A2 are electrically connected to the circuit HC. In the semiconductor device 10C3, the back gates of the transistors 22 and 32 included in the semiconductor device 10A3 are electrically connected to the circuit HC.

[0110] The circuit HC functions as a holding circuit for holding the potential of the back gate of the transistor 22 and the potential of the back gate of the transistor 32. The circuit HC includes a transistor M1, a transistor M2, a capacitor C1, and a capacitor FEC1. The transistor M1 and the transistor M2 each have a gate and a back gate.

[0111] The transistors M1 and M2 are preferably OS transistors. As described above, OS transistors have extremely low off-state current. Therefore, by using OS transistors as the transistors M1 and M2, the back-gate potentials of the transistors 22 and 32 can be held for a long time.

[0112] The capacitor FEC1 is a capacitor that uses a material that can have ferroelectricity as a dielectric. In this specification and the like, a capacitor that uses a material that can have ferroelectricity as a dielectric is called a ferroelectric capacitor.

[0113] In this specification and the like, the circuit symbol for a ferroelectric capacitor (for example, capacitance FEC1) is a circuit symbol for a capacitance with diagonal lines added, as shown in Figures 4A, 5A, and 6A. Alternatively, as shown in Figures 4B, 5B, and 6B, a different circuit symbol may be a circuit symbol for a capacitance with multiple diagonal lines added between two parallel lines.

[0114] The circuit HC is electrically connected to the reference cell 21 and the calculation cell 31. Specifically, the back gates of the transistors 22 and 32 are electrically connected to one of the source and drain of the transistor M1, the back gate of the transistor M1, and one of the source and drain of the transistor M2. The other of the source and drain of the transistor M1 is electrically connected to a wiring VIL. The gate of the transistor M1 is electrically connected to one electrode of the capacitor FEC1. The other of the source and drain of the transistor M2 is electrically connected to the other electrode of the capacitor FEC1 and one electrode of the capacitor C1. The gate of the transistor M2 is electrically connected to a wiring VGL. The other electrode of the capacitor C1 is electrically connected to a wiring VCL.

[0115] In this specification and the like, the electrical connection point between the gate of transistor M1 and one electrode of capacitor FEC1 is referred to as node N1. Furthermore, the electrical connection point between the other electrode of capacitor FEC1, one electrode of capacitor C1, and the other of the source or drain of transistor M2 is referred to as node N2. Furthermore, the electrical connection point between the source or drain of transistor M1, the back gate of transistor M1, and the source or drain of transistor M2 is referred to as node NBG. In other words, the potential of node NBG can be applied to the back gates of transistors 22 and 32.

[0116] Note that node N1 is not electrically connected to any circuit elements, terminals, wiring, etc. other than the gate of transistor M1 and one electrode of capacitor FEC1, and therefore no voltage is directly input to node N1 from a voltage source, etc. Therefore, node N1 is in a floating state. The initial potential of node N1 can be determined during fabrication of the semiconductor device (specifically, for example, during formation of circuit HC, etc.).

[0117] The wiring VIL functions as a wiring that applies a constant potential. For example, the constant potential can be a low-level potential, ground potential, a negative potential, or the like when the threshold voltages of the transistors 22 and 32 are shifted to the positive side. For example, the constant potential can be a high-level potential, a positive potential, or the like when the threshold voltages of the transistors 22 and 32 are shifted to the negative side.

[0118] The wiring VCL functions as wiring for applying a potential to polarize the material contained in the capacitor FEC1 that may have ferroelectricity. For example, if the direction of the electric field generated within the material as a result of polarization of the material is to be directed from one electrode of the capacitor FEC1 to the other electrode, the potential may be a positive potential or the like. Also, if the direction of the electric field generated within the material as a result of polarization of the material is to be directed from the other electrode of the capacitor FEC1 to one electrode, the potential may be a negative potential or the like. Furthermore, the wiring VCL may be supplied with a potential that does not polarize the material contained in the capacitor FEC1 that may have ferroelectricity.

[0119] The wiring VGL functions as a wiring that supplies a signal potential for controlling switching between an on state and an off state of the transistor M2. For example, the transistor M2 can be turned on by setting the potential of the wiring VGL to a high level, and the transistor M2 can be turned off by setting the potential of the wiring VGL to a low level.

[0120] Next, a configuration including a plurality of reference cells 21 and operation cells 31 will be described with reference to Figures 7A and 7B. Figure 7A shows an overview of the operation when writing data, and Figure 7B shows an overview of the operation when reading data.

[0121] 7A and 7B, a reference cell section 20 includes a plurality of reference cells 21_1 to 21_m (corresponding to the reference cell 21 in FIG. 1A, etc.), and a calculation cell section 30 includes a plurality of calculation cells 31_1,1 to 31_m,n (corresponding to the calculation cell 31 in FIG. 1A, etc.). Also, in FIGS. 7A and 7B, a plurality of wirings XCL are illustrated as wirings XCL_1 to XCL_m. Also, in FIGS. 7A and 7B, a plurality of wirings WCL are illustrated as wirings WCL_1 to WCL_n. Note that both m and n are integers equal to or greater than 1.

[0122] 7A and 7B, the cells in the reference cell unit 20 and the calculation cell unit 30 are arranged in a matrix with n+1 cells in the row direction and m cells in the column direction. The cells in the reference cell unit 20 and the calculation cell unit 30 may be arranged in a matrix with two or more cells in the row direction and one or more cells in the column direction.

[0123] 7A and 7B, the reference cell 21 and the operation cell 31 are shown in a simplified form for the sake of explanation. P 1A, the back gate of the transistor 24 in FIG. 2A, or the gate of the transistor 24 in FIG. 3A. W 1A, 2A, 3A, etc. corresponds to a terminal to which one of the source or drain of the transistor 22 and one of the source or drain of the transistor 24 are connected. P corresponds to one electrode of the capacitor 35 in FIG. 1A, the back gate of the transistor 34 in FIG. 2A, or the gate of the transistor 34 in FIG. 3A. X corresponds to a terminal to which one of the source or drain of the transistor 32 and one of the source or drain of the transistor 34 in FIGS. 1A, 2A, 3A, etc. are connected.

[0124] In the data write operation shown in FIG. 7A, a current I XutThe current given to each row is the normalized current I Xut and are equal. Current I Xut corresponds to the amount of current (reference current) corresponding to the reference data. Since the arithmetic cells 31 in each row are connected via capacitance, no current flows. The reference cells 21 operate to maintain a voltage corresponding to the current flowing.

[0125] In addition, in the data write operation shown in FIG. 7A, a current I W1 ~I Wn (I W ) is applied to each column. The current given to each column is the normalized current I Wut is equivalent to the current amount obtained by multiplying the weight data w (I W =wI Wut ). current I W1 ~I Wn may be different for each column.

[0126] In the data read operation shown in FIG. 7B, a current I X1 ~I Xm (I x ) is applied to each row. X1 ~I Xm is the normalized current I Xut is equivalent to the current amount obtained by multiplying the input data x (I X =xI Xut ). current I X1 ~I Xm may differ for each row. Xut is the current I Wut is preferably equal to

[0127] In the data read operation shown in FIG. 7B, the current I X1 ~I Xm The voltage held in the reference cell 21 is boosted by this voltage boost. In response to this boost, the voltages of the wires XCL_1 to XCL_m are also boosted, so that the voltage held in the processing cell 31 is boosted by the capacitive coupling of the capacitor 35. Then, the potential of the wires WCL_1 to WCL_n is set to the voltage Vd. At this time, the current I ris the current value (I w ) and the current value (I x ) and the product of (current I r11 ~I rmn ) The current I r11 ~I rm By estimating the sum of the input data and the weight data, it is possible to output data equivalent to the result of the sum of the products of the input data and the weight data.

[0128] It is preferable that the sizes (e.g., channel length, channel width, transistor configuration, etc.) of the transistors 22 and 24 included in each cell of the reference cell section 20 are equal to each other. It is also preferable that the sizes of the transistors 32 and 34 included in each cell of the calculation cell section 30 are equal to each other. It is also preferable that the sizes of the transistors 22 and 32 are equal to each other. It is also preferable that the sizes of the transistors 24 and 34 are equal to each other.

[0129] By making the transistors equal in size, the electrical characteristics of each transistor can be made approximately equal. Therefore, by making the size of the transistor 22 included in each of the reference cells 21_1,1 to 21_m,n equal and making the size of the transistor 24 included in each of the reference cells 21_1,1 to 21_m,n equal, each of the reference cells 21_1,1 to 21_m,n can perform approximately the same operation under the same conditions. Here, the same conditions refer to, for example, the same input potentials to the source, drain, gate, etc. of the transistor 22, the input potentials to the source, drain, gate, etc. of the transistor 24, and the voltages held in each of the reference cells 21_1,1 to 21_m,n. Furthermore, by making the size of the transistor 32 included in each of the arithmetic cells 31_1 to 31_m equal and making the size of the transistor 34 included in each of the arithmetic cells 31_1 to 31_m equal, for example, the arithmetic cells 31_1 to 31_m can perform substantially the same operation and obtain substantially the same results. When the conditions are the same, the arithmetic cells can perform substantially the same operation. Here, the conditions being the same means, for example, that the input potentials to the source, drain, gate, etc. of the transistor 32, the input potentials to the source, drain, gate, etc. of the transistor 34, and the voltages held in each of the arithmetic cells 31_1 to 31_m are equal.

[0130] The operations of the reference cell 21(1) and the operation cell 31(1) during data writing will be described with reference to FIG. 8A.

[0131] The wiring WSL is set to H level, and the transistors 22 and 32 are turned on (ON). A current I corresponding to the reference current flows through the wiring XCL. Xut In addition, the current I W The current I W is the current I normalized to the weight data w Wut The current multiplied by (in the figure, I w =wI Wut ) is equivalent to

[0132] In the reference cell 21(1), the transistor 22 is turned on. The potential of the retention node to which the back gate of the transistor 24 is electrically connected is set to a value equal to or lower than the threshold voltage of the transistor 24, V th1 As a result, the transistor 24 flows a current I Xut A current of I can flow between the source and drain of the transistor 24. Specifically, when the current flowing between the source and drain of the transistor 24 is I Xut In this specification, such an operation is referred to as "the current flowing between the source and drain of the transistor 24 of the reference cell 21(1) is I Xut It may be expressed as "setting (programming)".

[0133] In the operation cell 31(1), the transistor 32 is turned on. The potential of the hold node to which the back gate of the transistor 34 is electrically connected is set to a value when the threshold voltage of the transistor 34 is V th2 As a result, the current flowing between the source and drain of the transistor 34 of the processing cell 31(1) becomes I w Specifically, the current flowing between the source and drain of the transistor 34 is set to I w The threshold voltage of transistor 34 is set so that:

[0134] When writing data, the current I is applied to the reference cell 21(1) via the wiring XCL. Xut can be expressed by the following equation (2): Here, the gate of the transistor 24 and the other of the source and drain of the transistor 24 are set to the ground potential.

[0135]

number

[0136] When writing data, the current IW can be expressed by equation (3): Here, it is assumed that the gate of the transistor 34 and the other of the source and drain of the transistor 34 are supplied with the ground potential.

[0137]

number

[0138] As shown in equation (3), the current I w is the weight data w and the normalized current I Wut It can be expressed as a product of

[0139] The operation of the reference cell 21(1) and the calculation cell 31(1) during data read will be described with reference to FIG. 8B. A period during which a set current is held can be set between the time when data is written and the time when data is read. During the period during which the set current is held, the transistors 22 and 32 are turned off (OFF). By configuring the transistors 22 and 32 as OS transistors, the potential of the holding node corresponding to the set current can be held.

[0140] In the reference cell 21(1), the line WSL is set to the L level, and the transistor 22 is set to the OFF state. A current I x The current I X is the current I normalized to the input data x xut The current multiplied by (in the figure, I X =xI xut The potential of the hold node to which the back gate of the transistor 24 is electrically connected corresponds to the potential at which the transistor 24 is driven by a current I X When the voltage V flows, the threshold voltage of the transistor 24 fluctuates due to capacitive coupling via the capacitor 25. th1 +ΔV th At the same time, the potential of the wiring XCL also fluctuates.

[0141] In the processing cell 31(1), the wiring WSL is set to the L level, and the transistor 32 is turned off (OFF). Therefore, the storage node of the processing cell 31(1) is in an electrically floating state. The potential of the storage node of the processing cell 31(1) fluctuates due to the capacitive coupling of the capacitor 35 accompanying the fluctuation in the potential of the wiring XCL caused by the operation of the reference cell 21(1), and the threshold voltage of the transistor 34 becomes V th2 +ΔV th As a result, a current I flows between the source and drain of the transistor 34. r is playing.

[0142] When reading data, the current I is applied to the reference cell 21(1) via the wiring XCL. X can be expressed by equation (4): Here, the gate of the transistor 24 and the other of the source and drain of the transistor 24 are set to the ground potential.

[0143]

number

[0144] In equation (4), the input data x can be expressed by equation (5).

[0145]

number

[0146] From equations (4) and (5), the current I X is the input data x and the normalized current I Xut It can be expressed as a product of

[0147] When reading data, the wiring WCL is set to a voltage V d Then, the threshold voltage of the transistor 34 of the processing cell 31(1) is set to V th2 +ΔV th , the current I flowing through the transistor 34 rcan be expressed by equation (6): Here, the gate of the transistor 34 and the other of the source and drain of the transistor 34 are set to the ground potential.

[0148]

number

[0149] I in Equation (3), Equation (5) and Equation (6) r can be estimated as a current equivalent to the product of the weight data w and the input data x. The currents flowing through the arithmetic cells 31(1) of each row can be added together, so that by outputting the current flowing through the wiring WCL to the outside, a signal corresponding to the calculation result of the sum-of-products calculation process according to the weight data w and the input data x can be output.

[0150] 9A, the operation of the reference cell 21(2) and the operation cell 31(2) during data write will be described. Note that in the following description of the operation, when the potential applied to the back gate of the transistor 24 is equal to the potential applied to the back gate of the transistor 34, the threshold voltage of the transistor 24 is equal to the threshold voltage of the transistor 34.

[0151] The wiring WSL is set to H level, and the transistors 22 and 32 are turned on (ON). A current I corresponding to the reference current flows through the wiring XCL. Xut In addition, the current I W As mentioned above, the current I W is the current I normalized to the weight data w Wut The current multiplied by (in the figure, I w =wI Wut ) is equivalent to

[0152] In the reference cell 21(2), the transistor 22 is turned on. The potential of the retention node to which the gate of the transistor 24 is electrically connected is V g1 The potential of the back gate of the transistor 24 is Vth1 As a result, the transistor 24 generates a current I Xut can flow between the source and drain of transistor 24.

[0153] In the operation cell 31(2), the transistor 32 is turned on. The potential of the holding node to which the gate of the transistor 34 is electrically connected is V g2 The potential of the back gate of the transistor 34 is V th2 As a result, the current flowing between the source and drain of the transistor 34 of the processing cell 31(2) is I w is set to

[0154] When writing data, the current I is applied to the reference cell 21(2) via the wiring XCL. Xut can be expressed by equation (7): Here, the other of the source and drain of the transistor 24 is set to the ground potential.

[0155]

number

[0156] When writing data, the current I is applied to the processing cell 31(2) via the wiring WCL. W can be expressed by equation (8): Here, the other of the source and drain of the transistor 34 is set to the ground potential.

[0157]

number

[0158] As shown in equation (8), the current I w is the weight data w and the normalized current I Wut It can be expressed as a product of

[0159] The operations of the reference cell 21(2) and the operation cell 31(2) during data read will be described with reference to FIG. 9B.

[0160] In the reference cell 21(2), the line WSL is set to the L level, and the transistor 22 is set to the OFF state. A current I x As mentioned above, the current I X is the current I normalized to the input data x xut The current multiplied by (in the figure, I X =xI xut The potential of the back gate of the transistor 24 is equivalent to the current I X flows, causing the threshold voltage of transistor 24 to rise to V th1 +ΔV th At the same time, the potential of the wiring XCL also changes.

[0161] In the calculation cell 31(2), the wiring WSL is set to the L level, and the transistor 32 is set to the off state (OFF). As the potential of the wiring XCL changes due to the operation of the reference cell 21(2), the potential of the back gate of the transistor 34 also changes, and the threshold voltage of the transistor 34 becomes V th2 +ΔV th As a result, a current I flows between the source and drain of the transistor 34. r is playing.

[0162] When reading data, the current I is applied to the reference cell 21(2) via the wiring XCL. X can be expressed by equation (9): Here, the other of the source and drain of the transistor 24 is set to the ground potential.

[0163]

number

[0164] In equation (9), the input data x can be expressed by equation (10).

[0165]

number

[0166] From equations (9) and (10), the current I X is the input data x and the normalized current I Xut It can be expressed as a product of

[0167] When reading data, the wiring WCL is set to a voltage V d Then, the threshold voltage of the transistor 34 of the processing cell 31(2) is set to V th2 +ΔV th , the current I flowing through the transistor 34 of the processing cell 31(2) r can be expressed by equation (11): Here, the other of the source and drain of the transistor 34 is set to the ground potential.

[0168]

number

[0169] I in Equation (8), Equation (10) and Equation (11) r can be estimated as a current equivalent to the product of the weight data w and the input data x. The currents flowing through the arithmetic cells 31(2) of each row can be added together, so that by outputting the current flowing through the wiring WCL to the outside, it is possible to output a signal corresponding to the calculation result of the sum-of-products calculation process according to the weight data w and the input data x.

[0170] The operations of the reference cell 21(3) and the operation cell 31(3) during data writing will be described with reference to FIG. 10A.

[0171] The wiring WSL is set to H level, and the transistors 22 and 32 are turned on (ON). A current I corresponding to the reference current flows through the wiring XCL. Xut In addition, the current I W As mentioned above, the current I Wis the current I normalized to the weight data w Wut The current multiplied by (in the figure, I w =wI Wut ) is equivalent to

[0172] In the reference cell 21(3), the transistor 22 is turned on. The potential of the retention node to which the back gate of the transistor 24 is electrically connected is set to a value equal to or lower than the threshold voltage of the transistor 24, V th1 The potential of the gate of the transistor 24 is V g As a result, the transistor 24 outputs a current I Xut A current of V can flow between the source and drain of the transistor 24. Specifically, when the potential of the gate of the transistor 24 is V g When the current flowing between the source and drain of the transistor 24 is I Xut The threshold voltage of transistor 24 can be set so that:

[0173] In the operation cell 31(3), the transistor 32 is turned on. The potential of the hold node to which the back gate of the transistor 34 is electrically connected is set to a value equal to or lower than the threshold voltage of the transistor 24 (V th2 The potential of the gate of the transistor 34 is V g As a result, the current flowing between the source and drain of the transistor 34 of the processing cell 31(3) is I w Specifically, the potential of the gate of the transistor 34 is set to V g When the current flowing between the source and drain of the transistor 34 is I w The threshold voltage of transistor 34 is set so that:

[0174] When writing data, the current I is applied to the reference cell 21(3) via the wiring XCL. Xut can be expressed by equation (12): Here, the other of the source and drain of the transistor 24 is set to the ground potential.

[0175]

number

[0176] When writing data, the current I is applied to the processing cell 31(3) via the wiring WCL. W can be expressed by equation (13): Here, the other of the source and drain of the transistor 34 is set to the ground potential.

[0177]

number

[0178] As shown in equation (13), the current I w is the weight data w and the normalized current I Wut It can be expressed as a product of

[0179] The operations of the reference cell 21(3) and the operation cell 31(3) during data read will be described with reference to FIG. 10B.

[0180] In the reference cell 21(3), the line WSL is set to the L level, and the transistor 22 is set to the OFF state. A current I x As mentioned above, the current I X is the current I normalized to the input data x xut The current multiplied by (in the figure, I X =xI xut The potential at the gate of transistor 24 is equivalent to driving transistor 24 through a current I x By flowing, V g +ΔV g At the same time, the potential of the wiring XCL also fluctuates.

[0181] In the operation cell 31(3), the wiring WSL is set to the L level, and the transistor 32 is set to the OFF state. As the potential of the wiring XCL changes due to the operation of the reference cell 21(3), the potential of the gate of the transistor 34 also changes, and V g +ΔV gThe potential of the gate of the transistor 34 is V g +ΔV g As a result, a current I flows between the source and drain of the transistor 34 of the processing cell 31(3). r is playing.

[0182] When reading data, the current I is applied to the reference cell 21(3) via the wiring XCL. X can be expressed by equation (14): Here, the other of the source and drain of the transistor 24 is set to the ground potential.

[0183]

number

[0184] In equation (14), the input data x can be expressed by equation (15).

[0185]

number

[0186] From equations (14) and (15), the current I X is the input data x and the normalized current I Xut It can be expressed as a product of

[0187] When reading data, the wiring WCL is set to a voltage V d Then, the potential of the gate of the transistor 34 in the processing cell 31(3) is set to V g +ΔV g , the current I flowing through the transistor 34 of the processing cell 31(3) r can be expressed by equation (16): Here, the other of the source and drain of the transistor 34 is set to the ground potential.

[0188]

number

[0189] I in equations (13), (15) and (16) r can be estimated as a current equivalent to the product of the weight data w and the input data x. The currents flowing through the arithmetic cells 31(3) in each row can be added together, so by outputting the current flowing through the wiring WCL to the outside, it is possible to output a signal corresponding to the calculation result of the sum-of-products calculation process according to the weight data w and the input data x.

[0190] An example of the operation of the circuit HC included in the semiconductor device 10C1, the semiconductor device 10C2, and the semiconductor device 10C3 will be described below. Fig. 11A is a timing chart showing an example of the operation of the circuit HC, illustrating changes in the potentials of the wiring VCL, the wiring VGL, the wiring VIL, the node N1, the node N2, and the node NBG from time T11 to time T16 and at times around those times. In particular, Fig. 11A shows an example of the operation of writing a potential to the capacitor FEC1. In Fig. 11A, a high-level potential is represented as "High" and a low-level potential is represented as "Low."

[0191] Between time T11 and time T12, potentials are applied to the wirings VCL, VGL, and VIL electrically connected to the circuit HC as an initial state. FC1 A high level potential is applied to the wiring VGL, and a potential V IN1 is given. Note that V FC1 can be, for example, a positive potential, a high-level potential, a ground potential, etc., and V IN1 For example, the potential may be a positive potential, a high level potential, a ground potential, or the like.

[0192] In addition, the potential V of the node N1 11 is the potential V of node N2 21 The voltage between the first and second terminals of the capacitor FEC1 is V 11 -V 12However, at this voltage, polarization does not occur in the dielectric material contained in the capacitor FEC1 that may have ferroelectricity. Also, between time T11 and time T12, as long as polarization does not occur in the dielectric material contained in the capacitor FEC1 that may have ferroelectricity, the potential V 11 is the potential V of node N2 21 potential V 21 potential equal to, or potential V 21 It may be a potential higher than

[0193] Since the high-level potential from the wiring VGL is applied to the gate of the transistor M2, the transistor M2 is turned on. Therefore, electrical continuity is established between the node N2 and the node NBG, and the potential V BG1 is the potential V of node N2 21 is approximately equal to

[0194] A low-level potential is applied to the wiring VGL from time T12 to time T13, so that the low-level potential from the wiring VGL is applied to the gate of the transistor M2, turning the transistor M2 off.

[0195] Furthermore, when the transistor M2 is turned off, the node N2 is brought into a floating state.

[0196] Between time T13 and time T14, the potential V FC1 is the potential V FC2 The potential V FC2 is V FC1 The potential is set to be lower than the potential at which polarization occurs in the dielectric material contained in the capacitor FEC1 that may have ferroelectricity.

[0197] Since the node N2 is in a floating state, the potential given by the wiring VCL is V FC1 From V FC2In this example of operation, the potential of the node N2 changes from V to V due to capacitive coupling at the capacitor C1. 21 From V 22 The potential V FC2 is V FC1 Since the potential is lower than 22 is V 21 The potential is lower than

[0198] In addition, since the node N1 is also in a floating state, the potential of the node N2 is V 21 From V 22 However, since there is a gate capacitance between the gate and the first terminal of the transistor M1 between the node N1 and the wiring VIL, and there is a gate capacitance between the gate and the second terminal of the transistor M1 between the node N1 and the node NBG, the voltage change at the node N1 is proportional to the voltage change V 21 -V 22 At this time, the potential of the node N1 may be smaller than V 11 From V 12 It is assumed that the value changes to

[0199] At this time, the voltage between the first and second terminals of the capacitor FEC1 is V 12 -V 22 In the capacitor FEC1, polarization occurs in the dielectric material that may have ferroelectricity and is included in the capacitor FEC1. In other words, a write operation to the capacitor FEC1 is performed at this timing.

[0200] In addition, the potential V given by the wiring VIL IN1 is a positive potential, a high-level potential, etc., and the potential V IN1 By applying the voltage V between the first terminal and the second terminal of the capacitor FEC1, the potential of the node N1 can be increased via the gate and the first terminal of the transistor M1.12 -V 22 can be increased, and polarization may easily occur in the dielectric material, which may have ferroelectricity, included in the capacitor FEC1.

[0201] Between time T14 and time T15, the potential V FC2 V FC1 In other words, the potential applied to the wiring VCL from time T14 to time T15 is equal to the potential applied to the wiring VCL at a time before time T13.

[0202] Since the node N2 is in a floating state after time T12, the potential V FC2 V FC1 The potential at node N2 changes to V 22 From V 21 Return to.

[0203] The potential of node N2 is V 22 From V 21 , the potential V of the node N1 changes due to the capacitive coupling of the capacitor FEC1. 12 Note that, due to the operation from time T13 to time T14, polarization occurs in the dielectric material that may have ferroelectricity included in the capacitor FEC1, and therefore the potential of the node N1 returns to the original potential V 11 It does not return to the potential V 12 higher than the potential V 11 In this operation example, the potential of the node N1 is lower than the potential V 12 to potential V 13 It is assumed that the value changes to

[0204] In addition, the potential V 13 is the potential V 21 , and potential V IN1 Here, the gate-source voltage V of the transistor M1 is 13 -V IN1becomes lower than the threshold voltage of transistor M1, and transistor M1 is turned off.

[0205] A high-level potential is applied to the wiring VGL from time T15 to time T16, so that the high-level potential from the wiring VGL is applied to the gate of the transistor M2, turning on the transistor M2.

[0206] By the above operation, a potential can be written to the capacitor FEC1.

[0207] 11B is a timing chart showing an example of the operation of the circuit HC, and shows changes in the potentials of the wirings VCL, VGL, VIL, node N1, node N2, and node NBG from time T21 to time T24 and at times around those times. In particular, FIG. 11B shows an example of the operation of writing potentials to the back gates of the transistors 22 and 32. In FIG. 11B, a high-level potential is represented as "High" and a low-level potential is represented as "Low."

[0208] Time T21 is a time after time T16 in the timing chart of FIG. 11A. Therefore, between time T21 and time T22, the potential V FC1 A high level potential is applied to the wiring VGL, and a potential V IN1 The potential of node N1 is V 13 The potential of node N2 is V 21 The node NBG is V BG1 (=V 21 )

[0209] Between time T22 and time T23, the potential V IN1 is the potential V IN2 The potential V IN2 is V IN1 The potential is lower than the potential V IN2can be, for example, a negative potential, a low-level potential, or the like.

[0210] The first terminal of the transistor M1 is connected to the line VIL via the potential V IN2 is given, the gate-source voltage of transistor M1 is V 13 -V IN2 Here, V 13 -V IN2 is a voltage higher than the threshold voltage of the transistor M1.

[0211] V 13 -V IN2 is higher than the threshold voltage of the transistor M1, the transistor M1 is turned on. In addition, a high-level potential is applied to the wiring VGL, and the transistor M2 is also turned on. Therefore, the potential from the wiring VIL is supplied to the node N2 from the wiring VIL through the transistor M1, the node NBG, and the transistor M2.

[0212] Specifically, the potentials of the nodes N2 and NBG are V 21 In this operation example, the potentials of the nodes N2 and NBG decrease from V 21 to voltage ΔV BG The potentials of the nodes N2 and NBG are decreased by ΔV BG V BG2 It shall be as follows.

[0213] In addition, the potential of node N2 is V 21 From V BG2 As a result, the potential V of the node N1 decreases due to the capacitive coupling of the capacitor FEC1. 13 In this operation example, the potential of the node N1 is V 13 -αΔV BG Here, α is the capacitive coupling coefficient in the capacity FEC1.

[0214] Between time T23 and time T24, the potential V IN2 V IN1 In other words, the potential applied to the wiring VIL from time T23 to time T24 is equal to the potential applied to the wiring VIL at a time before time T22.

[0215] At this time, the first terminal of the transistor M1 receives the potential V IN1 is given, the gate-source voltage of transistor M1 is V 13 -αΔV BG -V IN1 In addition, V 13 -αΔV BG is V 13 is lower than V 13 is V IN1 The potential is lower than V 13 -V IN1 is lower than the threshold voltage of transistor M1, so V 13 -αΔV BG -V IN1 This causes the transistor M1 to be in an off state between time T23 and time T24.

[0216] By the above operation, the voltage V BG2 In particular, V IN2 By making V a negative potential, BG2 can be set to a negative potential, and VBG2 can be written as a negative potential to the node NBG of the circuit HC. In addition, the gate-source voltage of the transistor M1 can be set lower than the threshold voltage to turn off the transistor M1, so that the negative potential V BG2 As a result, the negative potential V BG2 Depending on the situation, a similar operation may be performed to refresh the negative potential held at the node NBG.

[0217] Next, an example of operation in which the potential of the node NBG is rewritten after time T24 in the example of operation in FIG. 11B will be described.

[0218] [When lowering the potential of node NBG] To lower the potential of the node NBG, for example, the circuit HC may be operated as shown in the timing chart of Fig. 12A. The timing chart of Fig. 12A shows changes in the potentials of the wirings VCL, VGL, VIL, node N1, node N2, and node NBG from time T31 to time T34 and at times around those times. In Fig. 12A, a high-level potential is represented as "High," and a low-level potential is represented as "Low."

[0219] Time T31 is a time after time T24 in the timing chart of FIG. 11B. Therefore, between time T31 and time T32, the potential V FC1 A high level potential is applied to the wiring VGL, and a potential V IN1 The potential of node N1 is V 13 -αΔV BG The potential of node N2 is V BG2 The node NBG is V BG2 It is as follows.

[0220] Between time T32 and time T33, the potential V IN1 is the potential V IN3 The potential V IN3 is V IN2 The potential is lower than the potential V IN3 For example, V IN2 It may be a negative potential, a low level potential, or the like lower than the reference potential.

[0221] The first terminal of the transistor M1 is connected to the line VIL via the potential V IN3 is given, the gate-source voltage of transistor M1 is V 13 -V IN3 By the way, V13 -V IN2 is higher than the threshold voltage of transistor M1, and V IN3 is V IN2 Since the potential is lower than V 13 -V IN3 The voltage is higher than the threshold voltage of the transistor M1.

[0222] V 13 -V IN3 is higher than the threshold voltage of the transistor M1, the transistor M1 is turned on. In addition, a high-level potential is applied to the wiring VGL, and the transistor M2 is also turned on. Therefore, the potential from the wiring VIL is supplied to the node N2 from the wiring VIL through the transistor M1, the node NBG, and the transistor M2.

[0223] Specifically, the potentials of the nodes N2 and NBG are V BG2 In this operation example, the potentials of the nodes N2 and NBG decrease from V BG2 to voltage ΔV BGN The potentials of the nodes N2 and NBG are decreased by ΔV BGN The potential drops by V BG3 It shall be as follows.

[0224] In addition, the potential of node N2 is V BG2 From V BG3 As a result, the potential V of the node N1 decreases due to the capacitive coupling of the capacitor FEC1. 13 -αΔV BG In this example of operation, the potential of the node N1 is V 13 -α(ΔV BG +ΔV BGN ) shall be

[0225] Between time T33 and time T34, the potential V IN3 V IN1In other words, the potential applied to the wiring VCL from time T33 to time T34 is equal to the potential applied to the wiring VIL at a time before time T32.

[0226] At this time, the first terminal of the transistor M1 receives the potential V IN1 is given, the gate-source voltage of transistor M1 is V 13 -α(ΔV BG +ΔV BGN )-V IN1 In addition, V 13 -α(ΔV BG +ΔV BGN ) is V 13 is lower than V 13 is V IN1 The potential is lower than V 13 -V IN1 is lower than the threshold voltage of transistor M1, so V 13 -α(ΔV BG +ΔV BGN )-V IN1 This causes the transistor M1 to be in an off state between time T33 and time T34.

[0227] By making the circuit HC perform the operation example of FIG. 12B, the voltage written to the node NBG in the operation example of FIG. 11B can be rewritten to a smaller voltage.

[0228] [When increasing the potential of node NBG] To increase the potential of the node NBG, for example, the circuit HC may be operated as shown in the timing chart of Figure 12B. The timing chart of Figure 12B shows changes in the potentials of the wirings VCL, VGL, VIL, node N1, node N2, and node NBG from time T41 to time T45 and at times around those times. In Figure 12B, a high-level potential is represented as "High," and a low-level potential is represented as "Low."

[0229] Time T41 is a time after time T24 in the timing chart of FIG. 11B. Therefore, between time T41 and time T42, the potential V FC1 A high level potential is applied to the wiring VGL, and a potential V IN1 The potential of node N1 is V 13 -αΔV BG The potential of node N2 is V BG2 The node NBG is V BG2 It is as follows.

[0230] Between time T42 and time T43, the potential V FC1 is the potential V FC3 The potential V FC3 is V FC1 is a higher potential than

[0231] When the node N2 and the node NBG are in a floating state, the potential given by the wiring VCL is V FC1 From V FC3 In this example of operation, the potentials of the node N2 and the node NBG change from V to V due to capacitive coupling at the capacitor C1. BG2 to voltage ΔV BGP The potentials of the nodes N2 and NBG rise by ΔV BGP The potential drops by V BG4 It shall be as follows.

[0232] In addition, since the node N1 is also in a floating state, the potential of the node N2 is V BG2 From V BG4 In this example of operation, the potential of the node N1 changes according to the voltage change due to capacitive coupling in the capacitor FEC1. 13 -αΔV BG From V 13 -α(ΔV BG -ΔVBGP )

[0233] It is assumed that the voltage between the node N1 and the node N2 from time T42 to time T43 does not cause polarization reversal in the dielectric material, which may have ferroelectricity, included in the capacitor FEC1. In other words, the potential V FC1 to potential V FC3 The voltage changed to a voltage that does not cause polarization reversal in the dielectric.

[0234] The first terminal of the transistor M1 is connected to the potential V IN1 is given, the gate-source voltage of transistor M1 is V 13 -α(ΔV BG -ΔV BGP )-V IN1 Between time T41 and time T42, the gate-source voltage of the transistor M1 is V 13 -αΔV BG -V IN1 Therefore, the operation from time T42 to time T43 (the potential given by the wiring VCL is V FC1 From V FC3 The gate-source voltage of transistor M1 changes to ΔV BGP This means that the price has increased by just

[0235] where V 13 -α(ΔV BG -ΔV BGP )-V IN1 is smaller than the threshold voltage of the transistor M1, so that the transistor M1 is in an off state.

[0236] Between time T43 and time T44, the potential V IN1 is the potential V IN4 The potential V IN4 is V IN1 and the potential V IN2 The potential is higher than the potential V IN4 For example, V IN1lower than V IN2 It may be a negative potential higher than the reference potential, a low level potential, or the like.

[0237] The first terminal of the transistor M1 is connected to the potential V IN4 is given, the gate-source voltage of transistor M1 is V 13 -α(ΔV BG -ΔV BGP )-V IN4 Here, V 13 -α(ΔV BG -ΔV BGP )-V IN4 is a voltage higher than the threshold voltage of the transistor M1.

[0238] V 13 -α(ΔV BG -ΔV BGP )-V IN4 is higher than the threshold voltage of the transistor M1, the transistor M1 is turned on. In addition, a high-level potential is applied to the wiring VGL, and the transistor M2 is also turned on. Therefore, the potential from the wiring VIL is supplied to the node N2 from the wiring VIL through the transistor M1, the node NBG, and the transistor M2.

[0239] Specifically, the potentials of the nodes N2 and NBG are V BG4 In this operation example, the potentials of the nodes N2 and NBG decrease from V BG4 to voltage ΔV BGQ The potentials of the nodes N2 and NBG are decreased by ΔV BGQ The potential drops by V BG5 It shall be as follows.

[0240] In addition, the potential of node N2 is V BG4 From V BG5 As a result, the potential V of the node N1 decreases due to the capacitive coupling of the capacitor FEC1. 13 -α(ΔV BGN -ΔVBGP ) also decreases. In this operation example, the potential of the node N1 decreases from time T43 to time T44. 13 -α(ΔV BGN -ΔV BGP +ΔV BGQ ) shall be

[0241] Between time T44 and time T45, the potential V IN4 V IN1 In other words, the potential applied to the wiring VIL from time T44 to time T45 is equal to the potential applied to the wiring VIL at a time before time T43.

[0242] At this time, the first terminal of the transistor M1 receives the potential V IN1 is given, the gate-source voltage of transistor M1 is V 13 -α(ΔV BGN -ΔV BGP +ΔV BGQ )-V IN1 In addition, V 13 -α(ΔV BGN -ΔV BGP +ΔV BGQ ) is V 13 is lower than V 13 is V IN1 The potential is lower than V 13 -V IN1 is lower than the threshold voltage of transistor M1, so V 13 -α(ΔV BGN -ΔV BGP +ΔV BGQ )-V IN1 This causes the transistor M1 to be in an off state between time T44 and time T45.

[0243] By the above operation, the voltage V BG2 voltage V BG5 In addition, since the transistor M1 is in an off state, the negative potential VBG5 , which allows the back gates of the transistors 22 and 32 to be supplied with the negative potential V BG5 can be given.

[0244] The operation of the timing charts of FIGS. 12A and 12B reduces the voltage V written to the node NBG of the circuit HC. BG2 can be rewritten as a different potential.

[0245] 13 is a diagram illustrating a semiconductor device 10D1 having a reference cell 21(1) and a calculation cell 31(1), FIG. 14 is a diagram illustrating a semiconductor device 10D2 having a reference cell 21(2) and a calculation cell 31(2), and FIG. 15 is a diagram illustrating a semiconductor device 10D3 having a reference cell 21(3) and a calculation cell 31(3). The reference cell 21(1) of the semiconductor device 10D1, the reference cell 21(2) of the semiconductor device 10D2, and the reference cell 21(3) of the semiconductor device 10D3 each have a transistor 23 in addition to a transistor 22, a transistor 24, and a capacitor 25. The calculation cell 31(1) of the semiconductor device 10D1, the calculation cell 31(2) of the semiconductor device 10D2, and the calculation cell 31(3) of the semiconductor device 10D3 each have a transistor 33 in addition to a transistor 32, a transistor 34, and a capacitor 35.

[0246] One of the source or drain of the transistor 23 is electrically connected to one of the source or drain of the transistor 22 and the wiring XCL. The other of the source or drain of the transistor 23 is electrically connected to one of the source or drain of the transistor 24. One of the source or drain of the transistor 33 is electrically connected to one of the source or drain of the transistor 32 and the wiring WCL. The other of the source or drain of the transistor 33 is electrically connected to one of the source or drain of the transistor 34. The gates of the transistors 23 and 33 are electrically connected to the wiring VBL. A constant potential such as a low power supply potential (e.g., ground potential) can be applied to the back gates of the transistors 23 and 33. Note that the potentials of the back gates of the transistors 23 and 33 may be variable.

[0247] A bias potential is applied to the wiring VBL. Specifically, a potential for operating the transistors 23 and 33 in the saturation region is applied to the wiring VBL. This allows the transistors 23 and 33 to function as constant current sources and thus as bias transistors. As described above, applying a bias potential to the gates of the transistors 23 and 33 can reduce fluctuations in the potential of either the source or drain of the transistor 24 and the potential of either the source or drain of the transistor 34. This can suppress fluctuations in the threshold voltage of the transistor 24 and the threshold voltage of the transistor 34 due to DIBL. As a result, the accuracy of data obtained by calculation can be improved.

[0248] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0249] (Embodiment 2) In this embodiment, an example of an arithmetic device to which the semiconductor device of one embodiment of the present invention can be applied will be described. The arithmetic device includes a circuit capable of performing a product-sum operation. The arithmetic device may also be referred to as an arithmetic circuit.

[0250] <Configuration example of the computing device> Fig. 16 shows an example of the configuration of an arithmetic device that performs a product-sum operation on first data and second data. The arithmetic device MAC1 shown in Fig. 16 is a circuit that performs a product-sum operation on first data (weight data) corresponding to the potential held in each cell and input second data (input data), and calculates an activation function using the result of the product-sum operation. Note that the first data and the second data can be, for example, analog data or multi-valued data (discrete data).

[0251] The arithmetic unit MAC1 has a circuit WCS, a circuit XCS, a circuit WSD, a circuit SWS1, a circuit SWS2, a cell array CA, and conversion circuits ITRZ_1 to ITRZ_n.

[0252] The cell array CA includes calculation cells 31_1,1 through 31_m,n and reference cells 21_1 through 21_m. Each of the calculation cells 31_1,1 through 31_m,n includes, for example, a transistor 32, a transistor 34, and a capacitor 35, similar to the calculation cell 31 described in the above embodiment. Each of the reference cells 21_1 through 21_m includes, for example, a transistor 22, a transistor 24, and a capacitor 25, similar to the reference cell 21 described in the above embodiment. In the following description, the "one of the source or the drain" described in the first embodiment may be referred to as a "first terminal," and the "other of the source or the drain" may be referred to as a "second terminal." In the following description, the "one electrode" of a capacitor may be referred to as a "first terminal," and the "other electrode" may be referred to as a "second terminal."

[0253] 16, in the processing cell 31_1,1, the connection point between the first terminal of the transistor 32, the back gate of the transistor 34, and the first terminal of the capacitor 35 is designated as node NN_11. Similarly, in FIG. 16, in the processing cells 31_1,n, 31_m,1, and 31_m,n, the same connection points are designated as nodes NN_1n, NN_m1, and NN_mn. Similarly, in FIG. 16, in the reference cells 21_1 and 21_m, the same connection points are designated as nodes NN_ref1 and NNref_m. Note that nodes NN_11 to NN_mn and nodes NNref_1 to NNref_m function as the storage nodes of the respective cells.

[0254] The circuit SWS1 includes, for example, transistors F3_1 to F3_n. A first terminal of the transistor F3_1 is electrically connected to the wiring WCL_1, a second terminal of the transistor F3_1 is electrically connected to the circuit WCS, and a gate of the transistor F3_1 is electrically connected to the wiring SWL1. A first terminal of the transistor F3_n is electrically connected to the wiring WCL_n, a second terminal of the transistor F3_n is electrically connected to the circuit WCS, and a gate of the transistor F3_n is electrically connected to the wiring SWL1.

[0255] For example, a transistor applicable to the transistors included in the cell array CA can be used as each of the transistors F3_1 to F3_n. In particular, it is preferable to use an OS transistor as each of the transistors F3_1 to F3_n.

[0256] The circuit SWS1 functions as a circuit that brings the circuit WCS and each of the wirings WCL_1 to WCL_n into a conductive state or a non-conductive state.

[0257] The circuit SWS2 includes, for example, transistors F4_1 to F4_n. A first terminal of the transistor F4_1 is electrically connected to the wiring WCL_1, a second terminal of the transistor F4_1 is electrically connected to the input terminal of the conversion circuit ITRZ_1, and a gate of the transistor F4_1 is electrically connected to the wiring SWL2. A first terminal of the transistor F4_n is electrically connected to the wiring WCL_n, a second terminal of the transistor F4_n is electrically connected to the input terminal of the conversion circuit ITRZ_n, and a gate of the transistor F4_n is electrically connected to the wiring SWL2.

[0258] For example, a transistor applicable to the transistors included in the cell array CA can be used as each of the transistors F4_1 to F4_n. In particular, it is preferable to use an OS transistor as each of the transistors F4_1 to F4_n.

[0259] The circuit SWS2 has a function of bringing the wiring WCL_1 and the conversion circuit ITRZ_1, and the wiring WCL_n and the conversion circuit ITRZ_n into a conductive state or a non-conductive state.

[0260] The circuit WCS has a function of supplying data to be stored in each cell of the cell array CA.

[0261] The circuit XCS is electrically connected to the wirings XCL_1 to XCL_m and has a function of supplying a current of an amount corresponding to reference data or second data to each of the reference cells 21_1 and 21_m included in the cell array CA.

[0262] The circuit WSD is electrically connected to the wirings WSL_1 to WSL_m. When writing first data to the processing cells 31_1,1 to 31_m,n, the circuit WSD has a function of selecting a row of the cell array CA to which the first data is to be written by supplying a predetermined signal to the wirings WSL_1 to WSL_m. Specifically, the circuit WSD has a function of generating signals that control the on / off of the transistors 22 and 32 and applying the signals to the gates of the transistors 22 and 32. In other words, the wirings WSL_1 to WSL_m function as write word lines.

[0263] For example, the circuit WSD is electrically connected to a wiring SWL1 and a wiring SWL2. The circuit WSD has a function of bringing the circuit WCS and the cell array CA into a conductive state or a non-conductive state by supplying a predetermined signal to the wiring SWL1, and a function of bringing the conversion circuits ITRZ_1 to ITRZ_n and the cell array CA into a conductive state or a non-conductive state by supplying a predetermined signal to the wiring SWL2.

[0264] Each of the conversion circuits ITRZ_1 to ITRZ_n has, for example, an input terminal and an output terminal. For example, the output terminal of the conversion circuit ITRZ_1 is electrically connected to the wiring OL_1, and the output terminal of the conversion circuit ITRZ_n is electrically connected to the wiring OL_n.

[0265] Each of the conversion circuits ITRZ_1 to ITRZ_n has a function of converting a current input to an input terminal into a voltage corresponding to the amount of the current and outputting the voltage from an output terminal. The voltage may be, for example, an analog voltage, a digital voltage, or the like. Each of the conversion circuits ITRZ_1 to ITRZ_n may also have a function-based arithmetic circuit. In this case, for example, the arithmetic circuit may perform a function calculation using the converted voltage, and the calculation result may be output to the wirings OL_1 to OL_n.

[0266] In particular, when performing calculations on a hierarchical neural network, the above-mentioned functions may be, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, or the like.

[0267] <<Circuit WCS, Circuit XCS>> Here, specific examples of the circuit WCS and the circuit XCS will be described.

[0268] First, the circuit WCS will be described. Fig. 17A is a block diagram showing an example of the circuit WCS. Note that Fig. 17A also shows a circuit SWS1, a transistor F3, a wiring SWL1, and a wiring WCL in order to show the electrical connection of the circuit WCS with peripheral circuits. The transistor F3 is any one of the transistors F3_1 to F3_n included in the arithmetic device MAC1 of Fig. 16, and the wiring WCL is any one of the wirings WCL_1 to WCL_n included in the arithmetic device MAC1 of Fig. 16.

[0269] The circuit WCS shown in FIG. 17A includes, as an example, a switch SWW. A first terminal of the switch SWW is electrically connected to a second terminal of the transistor F3, and a second terminal of the switch SWW is electrically connected to a wiring VINIL1. The wiring VINIL1 functions as a wiring that applies an initialization potential to the wiring WCL, and the initialization potential can be a ground potential (GND), a low-level potential, a high-level potential, or the like. Note that the switch SWW is turned on only when the initialization potential is applied to the wiring WCL, and is turned off otherwise.

[0270] The switch SWW may be, for example, an electrical switch such as an analog switch or a transistor. When a transistor is used as the switch SWW, the transistor may be, for example, a transistor that can be used as a transistor included in the cell array CA. In addition to an electrical switch, a mechanical switch may also be used.

[0271] 17A has a plurality of current sources CS. Specifically, the circuit WCS has K bits (2 K In this case, the circuit WCS has a function of outputting the first data of the value (K is an integer of 1 or more) as a current. K The circuit WCS has one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and two current sources CS that output information corresponding to the value of the K-th bit as a current. K-1 There are individual ones.

[0272] 17A, each current source CS has a terminal T1 and a terminal T2. The terminal T1 of each current source CS is electrically connected to the second terminal of the transistor F3 of the circuit SWS1. The terminal T2 of one current source CS is electrically connected to a wiring DW_1, and the terminals T2 of the two current sources CS are electrically connected to a wiring DW_2. K-1 Each of the terminals T2 of the current sources CS is electrically connected to the wiring DW_K.

[0273] The multiple current sources CS in the circuit WCS each have the same constant current I Wut It has the function of outputting a constant current I from terminal T1. Wut is the normalized current I Wut In reality, during the manufacturing stage of the arithmetic unit MAC1, errors may occur due to variations in the electrical characteristics of the transistors included in each current source CS. Therefore, the constant current I output from each of the terminals T1 of the multiple current sources CS may be Wut The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the constant current I output from the terminal T1 of each of the multiple current sources CS included in the circuit WCS is Wut The following explanation will be given assuming that there is no error.

[0274] The wirings DW_1 to DW_K are electrically connected to a current source CS, which supplies a constant current IWut Specifically, for example, when a high-level potential is applied to the wiring DW_1, the current source CS electrically connected to the wiring DW_1 outputs a constant current I Wut flows to the second terminal of the transistor F3, and when a low-level potential is applied to the wiring DW_1, the current source CS electrically connected to the wiring DW_1 flows as follows: Wut Do not output.

[0275] The current flowing from one current source CS electrically connected to wiring DW_1 corresponds to the value of the first bit, the current flowing from two current sources CS electrically connected to wiring DW_2 corresponds to the value of the second bit, and the current flowing from K current sources CS electrically connected to wiring DW_K corresponds to the value of the Kth bit.

[0276] 17A illustrates the circuit WCS when K is an integer equal to or greater than 3, but when K is 1, the circuit WCS in FIG. 17A may be configured without a current source CS electrically connected to the wirings DW_2 to DW_K. When K is 2, the circuit WCS in FIG. 17A may be configured without a current source CS electrically connected to the wirings DW_3 to DW_K.

[0277] Next, a specific example of the configuration of the current source CS will be described.

[0278] The current source CS1 shown in FIG. 18A is a circuit that can be applied to the current source CS included in the circuit WCS in FIG. 17A, and the current source CS1 has a transistor Tr1 and a transistor Tr2.

[0279] A first terminal of the transistor Tr1 is electrically connected to the wiring VDDL, and a second terminal of the transistor Tr1 is electrically connected to the gate of the transistor Tr1, the back gate of the transistor Tr1, and the first terminal of the transistor Tr2. A second terminal of the transistor Tr2 is electrically connected to the terminal T1, and a gate of the transistor Tr2 is electrically connected to the terminal T2. The terminal T2 is also electrically connected to the wiring DW.

[0280] The wiring DW is any one of the wirings DW_1 to DW_K in FIG. 17A.

[0281] The line VDDL functions as a line that applies a constant potential, which may be, for example, a high-level potential.

[0282] When the constant potential provided by the wiring VDDL is set to a high-level potential, a high-level potential is input to the first terminal of the transistor Tr1. The potential of the second terminal of the transistor Tr1 is set to a potential lower than the high-level potential. At this time, the first terminal of the transistor Tr1 functions as a drain, and the second terminal of the transistor Tr1 functions as a source. Since the gate of the transistor Tr1 and the second terminal of the transistor Tr1 are electrically connected, the gate-source voltage of the transistor Tr1 is 0 V. Therefore, when the threshold voltage of the transistor Tr1 is within an appropriate range, a current (drain current) in the subthreshold region current range flows between the first terminal and the second terminal of the transistor Tr1. When the transistor Tr1 is an OS transistor, the amount of this current is, for example, 1.0×10 -8 A or less, and 1.0 × 10 -12 A or less is more preferable, and 1.0 × 10 -15 It is more preferable that the current is less than or equal to I. Also, for example, it is more preferable that the current is in a range that increases exponentially with respect to the gate-source voltage. In other words, the transistor Tr1 functions as a current source for supplying a current in the current range when operating in the subthreshold region. Note that the current is the above-mentioned IWut , or I, as described below. Xut is equivalent to

[0283] Transistor Tr2 functions as a switching element. When the potential of the first terminal of transistor Tr2 is higher than the potential of the second terminal of transistor Tr2, the first terminal of transistor Tr2 functions as a drain, and the second terminal of transistor Tr2 functions as a source. Because the back gate of transistor Tr2 and the second terminal of transistor Tr2 are electrically connected, the back gate-source voltage is 0 V. Therefore, when the threshold voltage of transistor Tr2 is within an appropriate range, transistor Tr2 is turned on when a high-level potential is input to the gate of transistor Tr2, and turned off when a low-level potential is input to the gate of transistor Tr2. Specifically, when transistor Tr2 is on, a current in the subthreshold region flows from the second terminal of transistor Tr1 to terminal T1. When transistor Tr2 is off, the current does not flow from the second terminal of transistor Tr1 to terminal T1.

[0284] Note that the circuit applicable to the current source CS included in the circuit WCS of FIG. 17A is not limited to the current source CS1 of FIG. 18A. For example, the current source CS1 is configured such that the back gate of the transistor Tr2 is electrically connected to the second terminal of the transistor Tr2. However, the back gate of the transistor Tr2 may be electrically connected to a separate wiring. An example of such a configuration is shown in FIG. 18B. The current source CS2 shown in FIG. 18B is configured such that the back gate of the transistor Tr2 is electrically connected to a wiring VTHL. By electrically connecting the wiring VTHL to an external circuit or the like, the current source CS2 can apply a predetermined potential to the wiring VTHL via the external circuit or the like, thereby applying the predetermined potential to the back gate of the transistor Tr2. This allows the threshold voltage of the transistor Tr2 to be varied. In particular, increasing the threshold voltage of the transistor Tr2 can reduce the off-state current of the transistor Tr2.

[0285] For example, the current source CS1 has a configuration in which the back gate of transistor Tr1 is electrically connected to the second terminal of transistor Tr1, but a configuration in which a capacitor is used to maintain a voltage between the back gate of transistor Tr2 and the second terminal of transistor Tr2 is also possible. Such a configuration example is shown in FIG. 18C. The current source CS3 shown in FIG. 18C includes, in addition to transistors Tr1 and Tr2, a transistor Tr3 and a capacitor C6. The current source CS3 differs from the current source CS1 in that the second terminal of transistor Tr1 is electrically connected to the back gate of transistor Tr1 via the capacitor C6 and the back gate of transistor Tr1 is electrically connected to the first terminal of transistor Tr3. The current source CS3 also has a configuration in which the second terminal of transistor Tr3 is electrically connected to the wiring VTL and the gate of transistor Tr3 is electrically connected to the wiring VWL. The current source CS3 can apply a high-level potential to the wiring VWL to turn on transistor Tr3, thereby establishing electrical continuity between the wiring VTL and the back gate of transistor Tr1. At this time, a predetermined potential can be input to the back gate of transistor Tr1 from line VTL. Then, by applying a low-level potential to line VWL to turn off transistor Tr3, the capacitor C6 can maintain the voltage between the second terminal of transistor Tr1 and the back gate of transistor Tr1. In other words, by determining the voltage applied to the back gate of transistor Tr1 from line VTL, the threshold voltage of transistor Tr1 can be varied, and the threshold voltage of transistor Tr1 can be fixed by transistor Tr3 and capacitor C6.

[0286] Furthermore, for example, a circuit applicable to the current source CS included in the circuit WCS of Fig. 17A may be the current source CS4 shown in Fig. 18D. The current source CS4 is configured such that the back gate of the transistor Tr2 in the current source CS3 of Fig. 18C is electrically connected to the line VTHL instead of the second terminal of the transistor Tr2. In other words, the current source CS4, like the current source CS2 of Fig. 18B, can vary the threshold voltage of the transistor Tr2 depending on the potential provided by the line VTHL.

[0287] In the current source CS4, when a large current flows between the first and second terminals of the transistor Tr1, it is necessary to increase the on-current of the transistor Tr2 in order to pass that current from the terminal T1 to the outside of the current source CS4. In this case, the current source CS4 applies a high-level potential to the line VTHL to lower the threshold voltage of the transistor Tr2 and increase the on-current of the transistor Tr2, thereby allowing the large current flowing between the first and second terminals of the transistor Tr1 to flow from the terminal T1 to the outside of the current source CS4.

[0288] 17A, the circuit WCS can output a current corresponding to the K-bit first data by applying the current sources CS1 to CS4 shown in FIGS. 18A to 18D to the current source CS included in the circuit WCS. The amount of the current can be, for example, a current flowing between the first terminal and the second terminal within a range in which the transistor 34 operates in the subthreshold region.

[0289] 17A may be replaced by the circuit WCS shown in FIG. 17B. The circuit WCS in FIG. 17B has a configuration in which the current source CS shown in FIG. 18A is connected to each of the wirings DW_1 to DW_K. When the channel width of the transistor Tr1_1 is w_1, the channel width of the transistor Tr1_2 is w_2, and the channel width of the transistor Tr1_K is w_K, the ratio of the channel widths is w_1:w_2:w_K=1:2:2. K-1Since the current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width, the circuit WCS shown in FIG. 17B can output a current corresponding to the K-bit first data, similar to the circuit WCS in FIG. 17A.

[0290] Note that the transistors Tr1 (including transistors Tr1_1 to Tr2_K), Tr2 (including transistors Tr2_1 to Tr2_K), and Tr3 can be, for example, transistors applicable to the transistors included in the cell array CA. In particular, OS transistors are preferably used as the transistors Tr1 (including transistors Tr1_1 to Tr2_K), Tr2 (including transistors Tr2_1 to Tr2_K), and Tr3.

[0291] Next, a specific example of the circuit XCS will be described.

[0292] 17C is a block diagram showing an example of a circuit XCS. In addition, in order to show electrical connection between the circuit WCS and peripheral circuits, a wiring XCL is also shown in FIG. 17C. The wiring XCL is any one of the wirings XCL_1 to XCL_m included in the arithmetic unit MAC1 in FIG. 16.

[0293] The circuit XCS shown in FIG. 17C includes, as an example, a switch SWX. A first terminal of the switch SWX is electrically connected to the wiring XCL and a plurality of current sources CS, and a second terminal of the switch SWX is electrically connected to the wiring VINIL2. The wiring VINIL2 functions as a wiring that applies an initialization potential to the wiring XCL, and the initialization potential can be a ground potential (GND), a low-level potential, a high-level potential, or the like. The initialization potential applied by the wiring VINIL2 may be equal to the potential applied by the wiring VINIL1. Note that the switch SWX is turned on only when the initialization potential is applied to the wiring XCL, and is turned off otherwise.

[0294] The switch SWX may be, for example, a switch applicable to the switch SWW.

[0295] The circuit configuration of the circuit XCS in FIG. 17C can be made almost the same as that of the circuit WCS in FIG. 17A. Specifically, the circuit XCS has a function of outputting reference data as a current and a function of outputting L bits (2 L and a function of outputting second data of a value (L is an integer of 1 or more) as a current. In this case, the circuit XCS has a function of outputting second data of a value (L is an integer of 1 or more) as a current. L The circuit XCS has one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and two current sources CS that output information corresponding to the value of the Lth bit as a current. L-1 There are individual ones.

[0296] Incidentally, the reference data output as a current by the circuit XCS can be, for example, information in which the value of the first bit is "1" and the values ​​of the second and subsequent bits are "0".

[0297] In FIG. 17C, the terminal T2 of one current source CS is electrically connected to the wiring DX_1, and the terminals T2 of two current sources CS are electrically connected to the wiring DX_2. L-1 Each of the terminals T2 of the current sources CS is electrically connected to the wiring DX_K.

[0298] The multiple current sources CS in the circuit XCS are each set to the same constant current I Xut from the terminal T1. The wirings DX_1 to DX_K are electrically connected to the current source CS and the Xut That is, the circuit XCS has a function of causing a current corresponding to L-bit information transmitted from the wirings DX_1 to DX_K to flow through the wiring XCL.

[0299] In addition, if an error occurs due to variations in the electrical characteristics of the transistors included in each current source CS of the circuit XCS, the constant current I output from each of the terminals T1 of the multiple current sources CS will Xut The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the constant current I output from the terminal T1 of each of the multiple current sources CS included in the circuit XCS is Xut The following explanation will be given assuming that there is no error.

[0300] 18A to 18D can be used as the current source CS of the circuit XCS, similar to the current source CS of the circuit WCS. In this case, the wiring DW shown in FIGS. 18A to 18D can be replaced with the wiring DX. This allows the circuit XCS to pass a current in the subthreshold current range to the wiring XCL as reference data or L-bit second data.

[0301] Furthermore, the circuit XCS in Fig. 17C can have the same circuit configuration as the circuit WCS shown in Fig. 17B. In this case, the circuit WCS shown in Fig. 17B can be replaced with the circuit XCS, the wiring DW_1 with the wiring DX_1, the wiring DW_2 with the wiring DX_2, the wiring DW_K with the wiring DX_K, the switch SWW with the switch SWX, and the wiring VINIL1 with the wiring VINIL2.

[0302] <<Conversion Circuits ITRZ_1 to ITRZ_n>> Here, a specific example of a circuit that can be applied to the conversion circuits ITRZ_1 to ITRZ_n included in the arithmetic unit MAC1 in FIG. 16 will be described.

[0303] The conversion circuit ITRZ1 shown in Fig. 19A is an example of a circuit that can be applied to the conversion circuits ITRZ_1 to ITRZ_n in Fig. 16. Note that Fig. 19A also illustrates a circuit SWS2, wiring WCL, wiring SWL2, and a transistor F4 in order to show electrical connection between the conversion circuit ITRZ1 and peripheral circuits. The wiring WCL is any one of the wirings WCL_1 to WCL_n included in the arithmetic device MAC1 in Fig. 16, and the transistor F4 is any one of the transistors F4_1 to F4_n included in the arithmetic device MAC1 in Fig. 16.

[0304] The conversion circuit ITRZ1 in FIG. 19A is electrically connected to the wiring WCL via a transistor F4. The conversion circuit ITRZ1 is also electrically connected to the wiring OL. The conversion circuit ITRZ1 has a function of converting the current flowing from the conversion circuit ITRZ1 to the wiring WCL or the current flowing from the wiring WCL to the conversion circuit ITRZ1 into an analog voltage and outputting the analog voltage to the wiring OL. In other words, the conversion circuit ITRZ1 has a current-voltage conversion circuit.

[0305] The conversion circuit ITRZ1 in FIG. 19A includes, for example, a resistor R5 and an operational amplifier OP1.

[0306] The inverting input terminal of the operational amplifier OP1 is electrically connected to the first terminal of the resistor R5 and the second terminal of the transistor F4. The non-inverting input terminal of the operational amplifier OP1 is electrically connected to the wiring VRL. The output terminal of the operational amplifier OP1 is electrically connected to the second terminal of the resistor R5 and the wiring OL.

[0307] The wiring VRL functions as a wiring that applies a constant potential, which may be, for example, a ground potential (GND), a low-level potential, or the like.

[0308] By configuring the conversion circuit ITRZ1 as shown in Figure 19A, the current flowing from the wiring WCL to the conversion circuit ITRZ1 via transistor F4, or the current flowing from the conversion circuit ITRZ1 to the wiring WCL via transistor F4, can be converted into an analog voltage and output to the wiring OL.

[0309] In particular, by setting the constant potential provided by the wiring VRL to the ground potential (GND), the inverting input terminal of the operational amplifier OP1 becomes a virtual ground, and the analog voltage output to the wiring OL can be a voltage based on the ground potential (GND).

[0310] Furthermore, while the conversion circuit ITRZ1 in FIG. 19A is configured to output an analog voltage, the circuit configuration applicable to the conversion circuits ITRZ_1 to ITRZ_n in FIG. 16 is not limited to this. For example, the conversion circuit ITRZ1 may be configured to include an analog-to-digital conversion circuit ADC, as shown in FIG. 19B. Specifically, the conversion circuit ITRZ2 in FIG. 19B is configured such that the input terminal of the analog-to-digital conversion circuit ADC is electrically connected to the output terminal of the operational amplifier OP1 and the second terminal of the resistor R5, and the output terminal of the analog-to-digital conversion circuit ADC is electrically connected to the wiring OL. With this configuration, the conversion circuit ITRZ2 in FIG. 19B can output a digital signal to the wiring OL.

[0311] Also, in the conversion circuit ITRZ2, when the digital signal output to the wiring OL is 1-bit (binary), the conversion circuit ITRZ2 may be replaced with the conversion circuit ITRZ3 shown in FIG. 19C. The conversion circuit ITRZ3 in FIG. 19C has a configuration in which a comparator CMP1 is provided in the conversion circuit ITRZ1 in FIG. 19A. Specifically, in the conversion circuit ITRZ3, the first input terminal of the comparator CMP1 is electrically connected to the output terminal of the operational amplifier OP1 and the second terminal of the resistor R5, the second input terminal of the comparator CMP1 is electrically connected to the wiring VRL2, and the output terminal of the comparator CMP1 is electrically connected to the wiring OL. The wiring VRL2 functions as a wiring that gives a potential for comparing with the potential of the first terminal of the comparator CMP1. With such a configuration, the conversion circuit ITRZ3 in FIG. 19C can output a low-level potential or a high-level potential (binary digital signal) to the wiring OL according to the magnitude of the voltage converted from the current flowing between the source and drain of the transistor F4 by the current-voltage conversion circuit and the voltage given by the wiring VRL2.

[0312] Also, the conversion circuits ITRZ_1 to ITRZ_n applicable to the arithmetic unit MAC1 in FIG. 16 are not limited to the conversion circuits ITRZ1 to ITRZ3 shown in FIGS. 19A to 19C, respectively. For example, when using the arithmetic unit MAC1 for the arithmetic of a hierarchical neural network, it is preferable for the conversion circuits ITRZ1 to ITRZ3 to have a function-based arithmetic unit. Also, as the function-based arithmetic unit, an arithmetic unit such as a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function can be used.

[0313] <Operation Example of Arithmetic Unit> Next, an operation example of the arithmetic unit MAC1 will be described.

[0314] 20 shows a timing chart of an example of the operation of the arithmetic unit MAC1. The timing chart of FIG. 20 shows fluctuations in the potentials of the wiring SWL1, wiring SWL2, wiring WSL_i (i is an integer of 1 to m-1), wiring WSL_i+1, wiring XCL_i, wiring XCL_i+1, node NN_i,j (j is an integer of 1 to n-1), node NN_i+1,j, node NNref_i, and node NNref_i+1 between time T51 and time T63 and in the vicinity thereof. Furthermore, the timing chart of FIG. 20 also shows fluctuations in the potentials of the wiring SWL1, wiring SWL2, wiring WSL_i (i is an integer of 1 to m-1), wiring WSL_i+1, wiring XCL_i, wiring XCL_i+1, node NN_i,j (j is an integer of 1 to n-1), node NN_i+1,j, node NNref_i, and node NNref_i+1, flowing between the first terminal and the second terminal of the transistor 34 included in the arithmetic cell 31_i,j. 34 _i,j and the current I flowing between the first terminal and the second terminal of the transistor 24 included in the reference cell 21_i. 24 _i and the current I flowing between the first terminal and the second terminal of the transistor 34 included in the operation cell 31_i+1,j 34 _i+1,j and the current I flowing between the first terminal and the second terminal of the transistor 24 included in the reference cell 21_i+1. 24 The respective variations of _i+1 and _i+1 are also shown.

[0315] It is to be noted that the circuit WCS of the arithmetic unit MAC1 is the circuit WCS of FIG. 17A, and the circuit XCS of the arithmetic unit MAC1 is the circuit XCS of FIG. 17C.

[0316] In this operation example, the source potentials of transistors 24 and 34 are set to ground potential GND. Also, before time T51, the potentials of nodes NN_i,j, NN_i+1,j, NNref_i, and NNref_i+1 are set to ground potential GND as an initial setting. Specifically, for example, by setting the initialization potential of wiring VINIL1 in FIG. 17A to ground potential GND and turning on switch SWW, transistor F3, and the transistors 32 included in operation cells 31_i,j and 31_i+1,j, the potentials of nodes NN_i,j and NN_i+1,j can be set to ground potential GND. Furthermore, for example, by setting the initialization potential of wiring VINIL2 in Figure 17C to the ground potential GND and turning on switch SWX and the transistors 22 included in operation cells 31_i,j and 31_i+1,j, the potentials of nodes NNref_i,j and NNref_i+1,j can be set to the ground potential GND.

[0317] <<From time T51 to time T52>> Between time T51 and time T52, a high-level potential (denoted as "High" in FIG. 20) is applied to the wiring SWL1, and a low-level potential (denoted as "Low" in FIG. 20) is applied to the wiring SWL2. As a result, a high-level potential is applied to the gates of the transistors F3_1 to F3_n, turning on the transistors F3_1 to F3_n, and a low-level potential is applied to the gates of the transistors F4_1 to F4_n, turning off the transistors F4_1 to F4_n.

[0318] Also, between time T51 and time T52, low-level potentials are applied to wiring WSL_i and wiring WSL_i+1. As a result, low-level potentials are applied to the gates of transistors 32 included in arithmetic cells 31_i,1 to 31_i,n in the i-th row of cell array CA and the gates of transistors 22 included in reference cell 21_i, and transistors 32 and transistors 22 are turned off. Also, low-level potentials are applied to the gates of transistors 32 included in arithmetic cells 31_i+1,1 to 31_i+1,n in the (i+1)-th row of cell array CA and the gates of transistors 22 included in reference cell 21_i+1, and transistors 32 and transistors 22 are turned off.

[0319] Also, between time T51 and time T52, ground potential GND is applied to wiring XCL_i and wiring XCL_i+1. Specifically, for example, when the wiring XCL shown in FIG. 17C is each of wiring XCL_i and wiring XCL_i+1, by setting the initialization potential of wiring VINIL2 to ground potential GND and turning on switch SWX, the potentials of wiring XCL_i and wiring XCL_i+1 can be set to ground potential GND.

[0320] Also, between time T51 and time T52, when the wiring WCL shown in FIG. 17A is each of wiring WCL_1 to wiring WCL_K, first data is not input to wiring DW_1 to wiring DW_K. Also, when the wiring XCL shown in FIG. 17C is each of wiring XCL_1 to wiring XCL_K, second data is not input to wiring DX_1 to wiring DX_K. Here, in circuit WCS of FIG. 17A, it is assumed that low-level potentials are input to each of wiring DW_1 to wiring DW_K, and in circuit XCS of FIG. 17C, it is assumed that low-level potentials are input to each of wiring DX_1 to wiring DX_K.

[0321] Furthermore, between time T51 and time T52, no current flows through the wiring WCL_j, the wiring XCL_i, and the wiring XCL_i+1. 34 _i,j,I 24 _i, I 34 _i+1,j,I 24 _i+1 becomes 0.

[0322] <<From time T52 to time T53>> Between time T52 and time T53, a high-level potential is applied to the wiring WSL_i. As a result, a high-level potential is applied to the gates of the transistors 32 included in the calculation cells 31_i,1 to 31_i,n in the i-th row of the cell array CA and the gates of the transistors 22 included in the reference cell 21_i, so that the transistors 32 and 22 are turned on. Also, between time T52 and time T53, a low-level potential is applied to the wirings WSL_1 to WSL_m except for the wiring WSL_i. Therefore, the transistors 32 included in the calculation cells 31_1,1 to 31_m,n other than the i-th row of the cell array CA and the transistors 22 included in the reference cells 21_1 to 21_m other than the i-th row are turned off.

[0323] Furthermore, the ground potential GND has been continuously applied to the wirings XCL_1 to XCL_m since before time T52.

[0324] <<From time T53 to time T54>> Between time T53 and time T54, a current I is supplied as first data from the circuit WCS to the cell array CA via the transistor F3_j. 0_ Specifically, when the wiring WCL shown in FIG. 17A is the wiring WCL_j, a signal corresponding to the first data is input to each of the wirings DW_1 to DW_K, and a current I flows from the circuit WCS to the second terminal of the transistor F3_j. 0_ i,j flows. In other words, the value of the K-bit signal input as the first data is α_i,j (α_i,j is 0 or more, 2 K-1 or less), then I0_i,j=α_i,j×I Wut (In the figure, "x" is shown as "*").

[0325] Note that when α_i,j is 0, I0_i,j=0, so strictly speaking, no current flows from the circuit WCS to the cell array CA via the transistor F3_j, but in this specification, it may be stated that "a current of I0_i,j=0 flows."

[0326] Between time T53 and time T54, there is a conductive state between the first terminal of the transistor 32 included in the calculation cell 31_i,j in the i-th row of the cell array CA and the wiring WCL_j, and there is a non-conductive state between the first terminal of the transistor 32 included in the calculation cells 31_1,j to 31_m,j other than the i-th row of the cell array CA and the wiring WCL_j, so that a current I0_i,j flows from the wiring WCL_j to the calculation cell 31_i,j.

[0327] Meanwhile, the transistor 32 included in the operation cell 31_i,j is turned on. In the transistor 34, the gate-source voltage is V g _i,j-GND, and the current flowing between the first terminal and the second terminal of the transistor 34 is set to the current I0_i,j.

[0328] In addition, between time T53 and time T54, the circuit XCS supplies the wire XCL_i with a current I ref0 Specifically, when the wiring XCL in FIG. 17C is the wiring XCL_i, a high-level potential is input to the wiring DX_1 and a low-level potential is input to each of the wirings DX_2 to DX_K, and a current I flows from the circuit XCS to the wiring XCL_i. ref0 In other words, I ref0 =I Xut This becomes:

[0329] Between time T53 and time T54, a state of conduction is established between the first terminal of the transistor 22 included in the reference cell 21_i and the wiring XCL_i, so that a current I ref0 is playing.

[0330] As in the operation cell 31_i,j, the transistor 22 included in the reference cell 21_i is turned on. In the transistor 24, the gate-source voltage V gm _i-GND, and the current flowing between the first terminal and the second terminal of the transistor 24 is the current I ref0 is set.

[0331] <<From time T54 to time T55>> Between time T54 and time T55, a low-level potential is applied to the wiring WSL_i, which applies a low-level potential to the gates of the transistors 32 included in the calculation cells 31_i,1 to 31_i,n in the i-th row of the cell array CA and the gate of the transistor 22 included in the reference cell 21_i, turning off the transistors 32 and 22.

[0332] When the transistor 32 included in the processing cell 31_i,j is turned off, the capacitor 35 receives a potential V g _i,jV gm In addition, when the transistor 32 included in the reference cell 21_i is turned off, the capacitor 25 holds 0, which is the difference between the potential of the gate of the transistor 24 (node ​​NNref_i) and the potential of the wiring XCL_i.

[0333] <<From time T55 to time T56>> 17C is the wire XCL_i, the potential of the wire XCL_i can be set to the ground potential GND by setting the initialization potential of the wire VINIL2 to the ground potential GND and turning on the switch SWX.

[0334] Therefore, the potentials of nodes NN_i,1 to NN_i,n change due to capacitive coupling by the capacitor 35 included in each of the calculation cells 31_i,1 to 31_i,n in the i-th row, and the potential of node NNref_i changes due to capacitive coupling by the capacitor 25 included in the reference cell 21_i.

[0335] The change in potential of the nodes NN_i,1 to NN_i,n is calculated by multiplying the change in potential of the wiring XCL_i by a capacitance coupling coefficient determined by the configuration of each of the processing cells 31_i,1 to 31_i,n included in the cell array CA. The capacitance coupling coefficient is calculated based on the capacitance of the capacitor 35, the gate capacitance of the transistor 34, the parasitic capacitance, etc. In each of the processing cells 31_i,1 to 31_i,n, when the capacitance coupling coefficient of the capacitor 35 is p, the potential of the node NN_i,j of the processing cell 31_i,j is calculated by multiplying the potential at the time between time T54 and time T55 by p(V gm _i-GND) decreases.

[0336] Similarly, when the potential of the wiring XCL_i changes, the potential of the node NNref_i also changes due to the capacitive coupling of the capacitor 25 included in the reference cell 21_i. When the capacitive coupling coefficient of the capacitor 25 is p, the same as the capacitor 35, the potential of the node NNref_i of the reference cell 21_i changes from the potential between time T54 and time T55 to p(V gm 20, p=1 is set as an example. Therefore, the potential of the node NNref_i between time T55 and time T56 becomes GND.

[0337] As a result, the potential of the node NN_i,j of the processing cell 31_i,j drops, turning off the transistor 34. Similarly, the potential of the node NNref_i of the reference cell 21_i drops, turning off the transistor 24. Therefore, between time T55 and time T56, 34 _i,j,I 24 Each of _i will be 0.

[0338] <<From time T56 to time T57>> Between time T56 and time T57, a high-level potential is applied to the wiring WSL_i+1. As a result, a high-level potential is applied to the gates of the transistors 32 included in the processing cells 31_i+1,1 to 31_i+1,n in the (i+1)th row of the cell array CA and the gates of the transistors 22 included in the reference cell 21_i+1, turning on the transistors 32 and 22. Between time T56 and time T57, a low-level potential is applied to the wirings WSL_1 to WSL_m except for the wiring WSL_i+1. As a result, the transistors 32 included in the processing cells 31_1,1 to 31_m,n in the (i+1)th row of the cell array CA and the transistors 22 included in the reference cells 21_1 to 21_m in the (i+1)th row of the cell array CA are turned off.

[0339] Furthermore, the ground potential GND has been continuously applied to the wirings XCL_1 to XCL_m since before time T56.

[0340] <<From time T57 to time T58>> Between time T57 and time T58, a current I0_i+1,j flows as the first data from the circuit WCS to the cell array CA via the transistor F3_j. Specifically, when the wiring WCL shown in FIG. 17A is wiring WCL_j+1, a signal corresponding to the first data is input to each of the wirings DW_1 to DW_K, and a current I0_i+1,j flows from the circuit WCS to the second terminal of the transistor F3_j. That is, the value of the K-bit signal input as the first data is changed to α_i+1,j (α_i+1,j is 0 to 2). K -1 or less integer.) Then, I0_i+1,j=α_i+1,j×I Wut (In the figure, "x" is shown as "*").

[0341] Note that when α_i+1,j is 0, I0_i+1,j=0, so strictly speaking, no current flows from the circuit WCS to the cell array CA via transistor F3_j. However, in this specification, etc., it may be stated that "a current of I0_i+1,j=0 flows," as in the case of I0_i,j=0.

[0342] At this time, there is a conductive state between the first terminal of the transistor 32 included in the calculation cell 31_i+1,j in the i+1th row of the cell array CA and the wiring WCL_j, and there is a non-conductive state between the first terminal of the transistor 32 included in the calculation cells 31_1,j to 31_m,j other than the i+1th row of the cell array CA and the wiring WCL_j, so that a current I0_i+1,j flows from the wiring WCL_j to the calculation cell 31_i+1,j.

[0343] Now, suppose that the transistor 32 included in the operation cell 31_i+1,j is in an on state. In the transistor 34, the gate-source voltage is V g _i+1,j-GND, and the current flowing between the first terminal and the second terminal of the transistor 34 is set to current I0_i+1,j.

[0344] In addition, between time T57 and time T58, the circuit XCS supplies the current Iref0 Specifically, similarly to the period from time T53 to time T54, when the wiring XCL shown in FIG. 17C is the wiring XCL_i+1, a high-level potential is input to the wiring DX_1 and a low-level potential is input to each of the wirings DX_2 to DX_K, and a current I flows from the circuit XCS to the wiring XCL_i+1. ref0 =I Xut is playing.

[0345] Between time T57 and time T58, a state of conduction is established between the first terminal of the transistor 22 included in the reference cell 21_i+1 and the wiring XCL_i+1, so that a current I ref0 is playing.

[0346] As in the operation cell 31_i+1,j, the transistor 22 included in the reference cell 21_i+1 is in an on state. In the transistor 24, the gate-source voltage is V gm _i+1-GND, and the current flowing between the first terminal and the second terminal of the transistor 24 is the current I ref0 is set.

[0347] <<From time T58 to time T59>> Between time T58 and time T59, a low-level potential is applied to the wiring WSL_i+1, which applies a low-level potential to the gates of the transistors 32 included in the calculation cells 31_i+1,1 to 31_i+1,n in the (i+1)-th row of the cell array CA and the gate of the transistor 22 included in the reference cell 21_i+1, turning off the transistors 32 and 22.

[0348] When the transistor 32 included in the processing cell 31_i+1,j is turned off, the capacitor 35 is charged with a potential difference V g _i+1,jV gm_i+1 is held. Also, by turning off the transistor 32 included in the reference cell 21_i+1, the capacitor 25 holds 0, which is the difference between the potential of the gate (node ​​NNref_i+1) of the transistor 24 and the potential of the wiring XCL_i+1. Note that the voltage held by the capacitor 25 is a voltage (here, for example, V ds In this case, the potential of the node NNref_i+1 is V ds This can be thought of as the sum of the potentials.

[0349] <<From time T59 to time T60>> 17C is the wiring XCL_i+1, the potential for initialization of the wiring VINIL2 can be set to the ground potential GND by turning on the switch SWX.

[0350] Therefore, the potentials of nodes NN_i,1 to NN_i+1,n change due to capacitive coupling by capacitor 35 contained in each of the calculation cells 31_i+1,1 to 31_i+1,n in the i+1th row, and the potential of node NNref_i+1 changes due to capacitive coupling by capacitor 25 contained in reference cell 21_i+1.

[0351] The change in potential of the nodes NN_i+1,1 through NN_i+1,n is calculated by multiplying the change in potential of the wiring XCL_i+1 by a capacitive coupling coefficient determined by the configuration of each of the processing cells 31_i+1,1 through 31_i+1,n included in the cell array CA. The capacitive coupling coefficient is calculated based on the capacitance of the capacitor 35, the gate capacitance of the transistor 34, parasitic capacitance, etc. In each of the processing cells 31_i+1,1 through 31_i+1,n, the capacitive coupling coefficient due to the capacitor 35 is set to p, which is the same as the capacitive coupling coefficient due to the capacitor 35 in each of the processing cells 31_i,1 through 31_i,n, the potential of the node NN_i+1,j of the processing cell 31_i+1,j is calculated by multiplying the change in potential of the wiring XCL_i+1 by p(V gm _i+1-GND) decreases.

[0352] Similarly, when the potential of the wiring XCL_i+1 changes, the potential of the node NNref_i+1 also changes due to the capacitive coupling of the capacitor 25 included in the reference cell 21_i+1. When the capacitive coupling coefficient of the capacitor 25 is p, the same as the capacitor 35, the potential of the node NNref_i+1 of the reference cell 21_i+1 changes from the potential between time T58 and time T59 to p(V gm 20, p=1 is used as an example. Therefore, the potential of the node NNref_i+1 between time T60 and time T61 becomes GND.

[0353] As a result, the potential of the node NN_i+1,j of the processing cell 31_i+1,j drops, turning off the transistor 34. Similarly, the potential of the node NNref_i+1 of the reference cell 21_i+1 drops, turning off the transistor 24. Therefore, between time T59 and time T60, I 34 _i+1,j,I 24 Each of _i+1 will be 0.

[0354] <<From time T60 to time T61>> Between time T60 and time T61, a low-level potential is applied to the wiring SWL1, so that the low-level potential is applied to the gates of the transistors F3_1 to F3_n, turning off the transistors F3_1 to F3_n.

[0355] <<From time T61 to time T62>> A high-level potential is applied to the wiring SWL2 from time T61 to time T62, so that a high-level potential is applied to the gates of the transistors F4_1 to F4_n, turning on the transistors F4_1 to F4_n.

[0356] <<From time T62 to time T63>> Between time T62 and time T63, the circuit XCS supplies the current I ref0 x_i times x_iI ref0 Specifically, for example, when the wiring XCL shown in FIG. 17C is the wiring XCL_i, a high-level potential or a low-level potential is input to each of the wirings DX_1 to DX_K according to the value of x_i, and a current of x_iI flows from the circuit XCS to the wiring XCL_i. ref0 =x_iI Xut In this operation example, x_i corresponds to the value of the second data. At this time, the potential of the wiring XCL_i varies from 0 to V gm _i+ΔV_i.

[0357] When the potential of the wiring XCL_i changes, the potentials of the nodes NN_i,1 to NN_i,n also change due to capacitive coupling by the capacitors 35 included in each of the processing cells 31_i,1 to 31_i,n in the i-th row of the cell array CA. Therefore, the potential of the node NN_i,j of the processing cell 31_i,j is V g _i,j+pΔV_i.

[0358] Similarly, when the potential of the wiring XCL_i changes, the potential of the node NNref_i also changes due to capacitive coupling by the capacitor 25 included in the reference cell 21_i. Therefore, the potential of the node NNref_i of the reference cell 21_i changes as follows: V gm _i+pΔV_i.

[0359] Therefore, the current flowing between the first terminal and the second terminal of the transistor 34 included in the calculation cell 31_i,j is proportional to the product of the first data w_i,j and the second data x_i, as described in the first embodiment.

[0360] In addition, between time T62 and time T63, the current I ref0 x_i+1 times x_i+1I ref0 Specifically, for example, when the wiring XCL shown in FIG. 17C is the wiring XCL_i+1, a high-level potential or a low-level potential is input to each of the wirings DX_1 to DX_K according to the value of x_i+1, and a current x_i+1I flows from the circuit XCS to the wiring XCL_i+1. ref0 =x_i+1I Xut In this operation example, x_i+1 corresponds to the value of the second data. At this time, the potential of the wiring XCL_i+1 changes from 0 to V gm _i+1+ΔV_i+1.

[0361] When the potential of the wiring XCL_i+1 changes, the potentials of the nodes NN_i+1,1 to NN_i+1,n also change due to capacitive coupling by the capacitors 35 included in each of the processing cells 31_i+1,1 to 31_i+1,n in the i+1th row of the cell array CA. Therefore, the potential of the node NN_i+1,j of the processing cell 31_i+1,j is V g _i+1,j+pΔV_i+1.

[0362] Similarly, when the potential of the wiring XCL_i+1 changes, the potential of the node NNref_i+1 also changes due to capacitive coupling by the capacitor 25 included in the reference cell 21_i+1. Therefore, the potential of the node NNref_i+1 of the reference cell 21_i+1 changes as follows: V gm _i+1+pΔV_i+1.

[0363] Therefore, as explained in the first embodiment, the current flowing between the first terminal and the second terminal of the transistor 34 included in the calculation cell 31_i+1,j is proportional to the product of the first data w_i+1,j and the second data x_i+1.

[0364] Therefore, the current output from the conversion circuit ITRZ_j is proportional to the sum of the products of the weighting coefficients w_i,j and w_i+1,j, which are the first data, and the neuron signal values ​​x_i and x_i+1, which are the second data.

[0365] Therefore, even in the case of the arithmetic unit MAC1 having three or more rows and two or more columns of cell arrays CA, it is possible to perform the product-sum operation as described above. In this case, the arithmetic unit MAC1 selects one of the multiple columns as a current I ref0 , and xI ref0 By using a cell that holds a multiply-and-accumulate signal, it is possible to simultaneously perform multiply-and-accumulate operations for the remaining number of columns among the multiple columns. In other words, by increasing the number of columns in the memory cell array, it is possible to provide a semiconductor device that realizes high-speed multiply-and-accumulate operations. As a result, it is possible to provide a computing device with excellent computing performance per unit power.

[0366] Although the transistors included in the arithmetic unit MAC1 are OS transistors or Si transistors in this embodiment, one embodiment of the present invention is not limited thereto. The transistors included in the arithmetic unit MAC1 may be, for example, transistors containing Ge or the like in a channel formation region, transistors containing a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe in a channel formation region, transistors containing carbon nanotubes in a channel formation region, or transistors containing an organic semiconductor in a channel formation region.

[0367] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0368] (Embodiment 3) In this embodiment, a hierarchical artificial neural network (hereinafter referred to as a neural network) will be described. Note that the operation of the hierarchical neural network can be performed by using the semiconductor device and the operation device described in the above embodiment.

[0369] In neural networks, the strength of synapses can be changed by providing existing information to the neural network. This process of providing existing information to the neural network and determining the strength of connections is sometimes called "learning."

[0370] Furthermore, by providing some information to a neural network that has undergone "learning" (with connection strengths determined), new information can be output based on the connection strengths. In this way, in a neural network, the process of outputting new information based on the provided information and connection strengths is sometimes called "inference" or "cognition." The signals input from neurons in the previous layer to neurons in the next layer correspond to the connection strengths of the synapses connecting those neurons (hereinafter referred to as weighting coefficients), which correspond to the weighting data described in the above embodiment.

[0371] Neural network models include, for example, Hopfield and hierarchical types. In particular, neural networks with multi-layer structures are sometimes called "deep neural networks" (DNNs), and machine learning using deep neural networks is sometimes called "deep learning."

[0372] <Hierarchical neural network> As an example, a hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer, for a total of three or more layers. The hierarchical neural network 100 shown in FIG. 21A shows an example, and the neural network 100 has a first layer through an Rth layer (where R can be an integer equal to or greater than four). In particular, the first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to intermediate layers. Note that FIG. 21A illustrates the (k-1)th layer and the kth layer (where k is an integer equal to or greater than three and equal to or less than R-1) as intermediate layers, and does not illustrate the other intermediate layers.

[0373] Each layer of the neural network 100 has one or more neurons. In FIG. 21A, the first layer is made up of neurons N1 (1) Neuron N p (1) (where p is an integer equal to or greater than 1), and the (k-1)th layer has neurons N1 (k-1) Neuron N m (k-1) (where m is an integer greater than or equal to 1), and the kth layer has neurons N1 (k) Neuron N n (k) (where n is an integer greater than or equal to 1), and the Rth layer has neurons N1 (R) Neuron N q (R) (where q is an integer equal to or greater than 1).

[0374] In addition, in Figure 21A, neuron N1 (1) , neuron Np (1) , neuron N1 (k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , neuron N1 (R) , neuron N q (R) In addition, the (k-1)th layer neuron N i (k-1) (where i is an integer between 1 and m), and the kth layer neuron N j (k) (where j is an integer between 1 and n) are also shown, and other neurons are omitted from the illustration.

[0375] Next, we will explain the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals input and output at each neuron. j (k) Focus on.

[0376] Figure 21B shows the k-th layer neuron N j (k) and neuron N j (k) and the signal input to neuron N j (k) 10 shows the signal output from the

[0377] Specifically, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) The output signal z1 (k-1) ~z m (k-1) But neuron N j (k) The output is directed to neuron N j (k) is z1 (k-1) ~z m (k-1) Depending on z j (k)Generate z j (k) is output as an output signal to each neuron in the (k+1)th layer (not shown).

[0378] The degree of signal transmission for a signal input from a neuron in the previous layer to a neuron in the next layer is determined by the connection strength (hereinafter referred to as a weighting coefficient) of the synapse connecting those neurons. In the neural network 100, the signal output from a neuron in the previous layer is multiplied by the corresponding weighting coefficient before being input to a neuron in the next layer. If i is an integer between 1 and m, then the (k-1)th layer neuron N i (k-1) and the k-th layer neuron N j (k) The weight coefficient of the synapse between i (k-1) j (k) Then, the k-th layer neuron N j (k) The signal input to can be expressed by equation (17).

[0379]

number

[0380] That is, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) From each of these, the k-th layer neuron N j (k) When a signal is transmitted to the (k-1) ~z m (k-1) The weighting coefficients (w1 (k-1) j (k) Or even w m (k-1) j (k) ) is multiplied by the k-th layer neuron N j (k) has w1 (k-1) j (k)z1 (k-1) Or even w m (k-1) j (k) z m (k-1) is input. At this time, the k-th layer neuron N j (k) The sum of the signals input to j (k) is expressed as equation (18).

[0381]

number

[0382] Also, the weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k) and the neuron signal z1 (k-1) ~z m (k-1) A bias may be applied to the result of the sum of products of and. When the bias is b, equation (18) can be rewritten as the following equation (19).

[0383]

number

[0384] Neuron N j (k) u j (k) Depending on j (k) where neuron N j (k) Output signal z from j (k) is defined by the following equation (20).

[0385]

number

[0386] The function f(u j (k) ) is an activation function in a hierarchical neural network, and can be a step function, a linear ramp function, a sigmoid function, etc. The activation function can be the same for all neurons or different for each layer. In addition, the activation functions of neurons in each layer can be the same or different for each layer.

[0387] The signals, weight coefficients w, or biases b output by neurons in each layer may be analog or digital values. Digital values ​​may be, for example, binary or ternary. Values ​​with even larger bit counts may also be used. For analog values, activation functions such as linear ramp functions and sigmoid functions may be used. For binary digital values, a step function that outputs either -1 or 1, or 0 or 1 may be used. Furthermore, signals output by neurons in each layer may be ternary or more. In this case, a ternary activation function may be used, such as a step function that outputs either -1, 0, or 1, or a step function that outputs either 0, 1, or 2. Furthermore, an activation function that outputs five values, such as a step function that outputs either -2, -1, 0, 1, or 2, may be used. By using digital values ​​for at least one of the signals output by neurons in each layer, the weighting coefficient w, or the bias b, it is possible to reduce the circuit size, reduce power consumption, increase the calculation speed, etc. Furthermore, by using analog values ​​for at least one of the signals output by neurons in each layer, the weighting coefficient w, or the bias b, it is possible to improve the accuracy of calculations.

[0388] When an input signal is input to the first layer (input layer), neural network 100 generates an output signal in each layer, from the first layer (input layer) to the last layer (output layer), based on the signal input from the previous layer, using equations (17), (18) (or (19)), and (20), and outputs the output signal to the next layer. The signal output from the last layer (output layer) corresponds to the result of calculation by neural network 100.

[0389] When the calculation device MAC1 described in the second embodiment is applied as the hidden layer, the weight coefficient w s[k-1] (k-1) s_K (k) (where s[k-1] is an integer between 1 and m, and s_K is an integer between 1 and n) is used as the first data, and a current corresponding to the first data is stored in each cell of the same column in sequence, and the neuron N in the (k-1) layer s[k-1] (k-1) Output signal z from s[k-1] (k-1) is used as the second data, and a current corresponding to the second data is passed from the circuit XCS to the wiring XCL of each row, thereby generating a current I S In addition, by using the value of the sum of products to calculate the value of the activation function, the value of the activation function is used as a signal to activate the neuron N in the kth layer. s_K (k) The output signal z s_K (k) It can be said that:

[0390] In addition, when the arithmetic unit MAC1 described in the second embodiment is applied to the output layer, the weighting coefficient w s[R-1] (R-1) s[R] (R) (s[R-1] is an integer equal to or greater than 1, and s[R] is an integer equal to or greater than 1 and equal to or less than q) is used as the first data, and a current corresponding to the first data is stored in each cell of the same column in sequence, and the neuron N in the (R-1) layer s[R-1] (R-1) Output signal z from s[R-1] (R-1)is used as the second data, and a current corresponding to the second data is passed from the circuit XCS to the wiring XCL of each row, thereby generating a current I S In addition, by using the value of the sum of products to calculate the value of the activation function, the value of the activation function is used as a signal to activate the neuron N in the Rth layer. s[R] (R) The output signal z s[R] (R) It can be said that:

[0391] The input layer described in this embodiment may function as a buffer circuit that outputs an input signal to the second layer.

[0392] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0393] (Fourth embodiment) In this embodiment, a structural example of the semiconductor device described in the above embodiment and a structural example of a transistor that can be applied to the semiconductor device described in the above embodiment will be described.

[0394] <Configuration Example 1 of Semiconductor Device> 22A shows, as an example, the semiconductor device described in the above embodiment, which includes a transistor 500 and a capacitor 600. Fig. 22B shows a cross-sectional view of the transistor 500 in the channel length direction, and Fig. 22C shows a cross-sectional view of the transistor 500 in the channel width direction.

[0395] The transistor 500 can be an OS transistor. The transistor 500 can be applied to, for example, the transistor 22 or the transistor 32 described in the above embodiment. The transistor 500 may be a Si transistor, and the silicon used can be, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon, or the like.

[0396] The transistor 500 is provided above an insulator 512 that is provided above a substrate (not shown), for example. The capacitor 600 is provided above the transistor 500, for example. The capacitor 600 can be applied to the capacitor 25 described in the above embodiment, or the like.

[0397] An insulator 514 and an insulator 516 are stacked in this order over the insulator 512. Any of the insulator 512, the insulator 514, and the insulator 516 is preferably made of a substance that has a barrier property against oxygen and hydrogen.

[0398] For example, the insulator 514 is preferably a film having a barrier property that prevents hydrogen and impurities from diffusing from a region where a substrate is provided to a region where the transistor 500 is provided.

[0399] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, diffusion of hydrogen into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, by using a film that suppresses hydrogen diffusion as the insulator 514, it is possible to suppress the deterioration of the characteristics of a semiconductor element, such as the transistor 500. Here, the film that suppresses hydrogen diffusion is specifically a film that releases a small amount of hydrogen.

[0400] As a film having a barrier property against hydrogen, for example, the insulator 514 is preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0401] In particular, aluminum oxide has a high blocking effect against both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. It can also suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0402] For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used for the insulators 512 and 516. Furthermore, by using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced.

[0403] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0404] Conductors that constitute the transistor 500 (for example, the conductor 503 shown in FIGS. 22B and 22C) and the like are embedded in the insulators 512, 514, and 516.

[0405] Above the insulator 516 is the transistor 500 .

[0406] As shown in FIGS. 22B and 22C, transistor 500 includes an insulator 516 on insulator 514, conductor 503 (conductor 503a and conductor 503b) disposed so as to be embedded in insulator 514 or insulator 516, insulator 522 on insulator 516 and on conductor 503, insulator 524 on insulator 522, oxide 530a on insulator 524, oxide 530b on oxide 530a, conductor 542a on oxide 530b, insulator 571a on conductor 542a, and oxide 571b on conductor 542a. The oxide 530b includes a conductor 542b on the oxide 530b, an insulator 571b on the conductor 542b, an insulator 552 on the oxide 530b, an insulator 550 on the insulator 552, an insulator 554 on the insulator 550, a conductor 560 (conductor 560a and conductor 560b) located on the insulator 554 and overlapping with part of the oxide 530b, and an insulator 544 arranged on the insulator 522, the insulator 524, the oxide 530a, the oxide 530b, the conductor 542a, the conductor 542b, the insulator 571a, and the insulator 571b. 22B and 22C , insulator 552 contacts the upper surface of insulator 522, the side surface of insulator 524, the side surface of oxide 530a, the side surface and upper surface of oxide 530b, the side surface of conductor 542, the side surface of insulator 571, the side surface of insulator 544, the side surface of insulator 580, and the lower surface of insulator 550. Furthermore, the upper surface of conductor 560 is disposed so as to be at approximately the same height as the upper surfaces of insulators 554, 550, 552, and 580. Furthermore, insulator 574 contacts at least a portion of the upper surface of conductor 560, 552, 550, 554, and 580. In this specification and the like, conductor 542a and conductor 542b may be collectively referred to as conductor 542, and insulator 571a and insulator 571b may be collectively referred to as insulator 571. Other elements may be expressed in a similar manner.

[0407] Openings reaching the oxide 530b are provided in the insulator 580 and the insulator 544. The insulator 552, the insulator 550, the insulator 554, and the conductor 560 are disposed in the openings. In addition, the conductor 560, the insulator 552, the insulator 550, and the insulator 554 are provided between the insulator 571a and the conductor 542a and between the insulator 571b and the conductor 542b in the channel length direction of the transistor 500. The insulator 554 has a region in contact with the side surface of the conductor 560 and a region in contact with the bottom surface of the conductor 560.

[0408] The oxide 530 preferably includes an oxide 530a disposed on the insulator 524 and an oxide 530b disposed on the oxide 530a. By providing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 530a to the oxide 530b.

[0409] Note that although the transistor 500 has a structure in which the oxide 530 has two layers, the oxide 530a and the oxide 530b, the present invention is not limited to this. For example, the transistor 500 can have a single layer of the oxide 530b or a stacked structure of three or more layers. Alternatively, each of the oxide 530a and the oxide 530b can have a stacked structure.

[0410] The conductor 560 functions as a gate electrode, and the conductor 503 functions as a backgate electrode. Note that the conductor 503 may function as a gate electrode, and the conductor 560 may function as a backgate electrode. The insulators 552, 550, and 554 function as gate insulators for the conductor 560, and the insulators 522 and 524 function as gate insulators for the conductor 503. Note that the gate insulators may also be referred to as gate insulating layers or gate insulating films. The conductor 542a functions as either a source or a drain, and the conductor 542b functions as the other. At least a part of a region of the oxide 530 that overlaps with the conductor 560 functions as a channel formation region.

[0411] FIG. 23A shows an enlarged view of the vicinity of the channel formation region in FIG. 22B. When oxygen is supplied to the oxide 530b, a channel formation region is formed in the region between the conductor 542a and the conductor 542b. Therefore, as shown in FIG. 23A, the oxide 530b includes a region 530bc that functions as the channel formation region of the transistor 500, and regions 530ba and 530bb that are provided on either side of the region 530bc and function as source and drain regions. At least a portion of the region 530bc overlaps with the conductor 560. In other words, the region 530bc is located in the region between the conductor 542a and the conductor 542b. The region 530ba overlaps with the conductor 542a, and the region 530bb overlaps with the conductor 542b.

[0412] The region 530bc, which functions as a channel formation region, has a smaller oxygen vacancy (in this specification, oxygen vacancy in a metal oxide is referred to as V) than the regions 530ba and 530bb. O The region 530bc is a high-resistance region with a low carrier concentration due to its low oxygen vacancy or low impurity concentration. Therefore, the region 530bc can be said to be i-type (intrinsic) or substantially i-type.

[0413] A transistor using a metal oxide has impurities or oxygen vacancies (V O ) may cause fluctuations in electrical characteristics and reduce reliability. O ) hydrogen near the oxygen vacancy (V O ) with hydrogen (hereafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible.

[0414] The regions 530ba and 530bb that function as source and drain regions have oxygen vacancies (V O ) or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, resulting in an increased carrier concentration and low resistance. That is, compared to region 530bc, region 530ba and region 530bb are n-type regions with a higher carrier concentration and lower resistance.

[0415] Here, the carrier concentration of the region 530bc that functions as a channel forming region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 530bc that functions as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm-3 It can be said that:

[0416] A region having a carrier concentration equal to or lower than that of regions 530ba and 530bb and equal to or higher than that of region 530bc may be formed between region 530bc and regions 530ba or 530bb. That is, this region functions as a junction region between region 530bc and regions 530ba or 530bb. The junction region may have a hydrogen concentration equal to or lower than that of regions 530ba and 530bb and equal to or higher than that of region 530bc. The junction region may also have oxygen vacancies equal to or lower than those of regions 530ba and 530bb and equal to or higher than those of region 530bc.

[0417] 23A shows an example in which the regions 530ba, 530bb, and 530bc are formed in the oxide 530b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in the oxide 530b but also in the oxide 530a.

[0418] Furthermore, it may be difficult to clearly detect the boundaries between the regions in the oxide 530. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than gradually varying from region to region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in the region closer to the channel formation region.

[0419] In the transistor 500, the oxide 530 including the channel formation region (the oxide 530a and the oxide 530b) is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0420] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0421] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 530. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 530.

[0422] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 530b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0423] In this way, by disposing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities and oxygen from the structure formed below the oxide 530a into the oxide 530b.

[0424] Furthermore, since the oxide 530a and the oxide 530b have a common element other than oxygen (as a main component), the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. Because the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced, the effect of interface scattering on carrier conduction is reduced, and a high on-current can be obtained.

[0425] The oxide 530b preferably has crystallinity, and in particular, it is preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 530b.

[0426] CAAC-OS has a highly crystalline and dense structure and is free of impurities and defects (e.g., oxygen vacancies (V O In particular, the CAAC-OS can be made to have a dense structure with higher crystallinity by heat-treating the formed metal oxide at a temperature (for example, 400°C or higher and 600°C or lower) at which the metal oxide does not polycrystallize. In this way, the density of the CAAC-OS can be increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0427] On the other hand, since it is difficult to identify clear grain boundaries in CAAC-OS, it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. As a result, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0428] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen near the oxygen vacancies may be introduced into the oxygen vacancies (hereinafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in an oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in an oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0429] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed to supply oxygen from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, this may cause a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 500. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies across the substrate surface, the characteristics of the semiconductor device having the transistor will vary.

[0430] Therefore, in the oxide semiconductor, the region 530bc that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 530ba and 530bb that function as source and drain regions preferably have a high carrier concentration and are n-type. O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the regions 530ba and 530bb.

[0431] Therefore, in this embodiment, in a state where the conductors 542a and 542b are provided on the oxide 530b, microwave treatment is performed in an atmosphere containing oxygen to remove oxygen vacancies in the region 530bc and V O The microwave treatment here refers to a treatment using a device with a power source that generates high-density plasma using microwaves, for example.

[0432] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated. At this time, microwaves or high frequency waves such as RF can also be irradiated onto the region 530bc. The V of the region 530bc can be activated by the action of the plasma, microwaves, etc. O H is split off, hydrogen H is removed from the region 530bc, and oxygen vacancy V Ocan be compensated with oxygen. O H→H+V O This reaction occurs, and the hydrogen concentration in the region 530bc can be reduced. O H can be reduced to lower the carrier concentration.

[0433] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc. are shielded by the conductors 542a and 542b and do not reach the regions 530ba and 530bb. Furthermore, the effects of oxygen plasma can be reduced by the insulators 571 and 580 that cover the oxide 530b and the conductor 542. As a result, during microwave processing, V O Since there is no reduction in H and no excessive supply of oxygen, it is possible to prevent a decrease in the carrier concentration.

[0434] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating film that becomes the insulator 552 or after forming the insulating film that becomes the insulator 550. By performing microwave treatment in an oxygen-containing atmosphere through the insulator 552 or the insulator 550 in this manner, oxygen can be efficiently injected into the region 530bc. Furthermore, by arranging the insulator 552 so as to be in contact with the side surface of the conductor 542 and the surface of the region 530bc, injection of more oxygen than necessary into the region 530bc can be suppressed, thereby suppressing oxidation of the side surface of the conductor 542. Furthermore, oxidation of the side surface of the conductor 542 can be suppressed during formation of the insulating film that becomes the insulator 550.

[0435] The oxygen implanted into the region 530bc can be in various forms, such as oxygen atoms, oxygen molecules, or oxygen radicals (atoms, molecules, or ions with an unpaired electron, also known as O radicals). The oxygen implanted into the region 530bc preferably takes one or more of the above forms, and oxygen radicals are particularly preferred. This can improve the film quality of the insulators 552 and 550, thereby improving the reliability of the transistor 500.

[0436] In this way, oxygen vacancies and V are selectively formed in the oxide semiconductor region 530bc. O By removing H, the region 530bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 530ba and 530bb, which function as source and drain regions, can be prevented, thereby maintaining n-type electrical characteristics. This can suppress fluctuations in the electrical characteristics of the transistor 500 and reduce variations in the electrical characteristics of the transistor 500 within the substrate surface.

[0437] By adopting the above-described configuration, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device with good electrical characteristics.

[0438] 22C , in a cross-sectional view of the transistor 500 in the channel width direction, a curved surface may be formed between the side surface of the oxide 530b and the top surface of the oxide 530b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0439] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 530b in the region overlapping with the conductor 542, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape can improve the coverage of the oxide 530b with the insulators 552, 550, and 554, and the conductor 560.

[0440] The oxide 530 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to the metal element that is the main component is preferably greater than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 530b. Furthermore, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Furthermore, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0441] The oxide 530b is preferably a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), and have a highly crystalline and dense structure. This can prevent the source or drain electrode from extracting oxygen from the oxide 530b. This reduces the extraction of oxygen from the oxide 530b even during heat treatment, making the transistor 500 stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0442] Here, the conduction band minimum changes gradually at the junction between the oxides 530a and 530b. In other words, the conduction band minimum at the junction between the oxides 530a and 530b changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxides 530a and 530b.

[0443] Specifically, when the oxide 530a and the oxide 530b contain a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-M-Zn oxide, the oxide 530a may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0444] Specifically, oxide 530a may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. Oxide 530b may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, or an atomic ratio of In:M:Zn=4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as element M.

[0445] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0446] 22B and other figures, providing an insulator 552 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 530 can cause indium in the oxide 530 to be unevenly distributed at and near the interface between the oxide 530 and the insulator 552. This results in an atomic ratio near the surface of the oxide 530 that is close to that of indium oxide or In-Zn oxide. The increased atomic ratio of indium near the surface of the oxide 530, particularly the oxide 530b, can improve the field-effect mobility of the transistor 500.

[0447] The oxide 530a and the oxide 530b have the above-described structure, which can reduce the defect state density at the interface between the oxide 530a and the oxide 530b. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can achieve a large on-state current and high frequency characteristics.

[0448] At least one of the insulators 512, 514, 544, 571, 574, 576, and 581 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 500 into the transistor 500. Therefore, at least one of the insulators 512, 514, 544, 571, 574, 576, and 581 is preferably made of an insulating material that suppresses diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively, it is preferably made of an insulating material that suppresses diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., through which the above oxygen is less likely to permeate).

[0449] In this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0450] For the insulators 512, 514, 544, 571, 574, 576, and 581, it is preferable to use an insulator that has the function of suppressing diffusion of oxygen and impurities such as water and hydrogen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon nitride oxide, or the like can be used. For example, silicon nitride or the like, which has a high hydrogen barrier property, is preferably used for the insulators 512, 544, and 576. Furthermore, for example, it is preferable to use aluminum oxide or magnesium oxide, which has a high function of capturing and fixing hydrogen, for the insulators 514, 571, 574, and 581. This can suppress diffusion of impurities such as water and hydrogen from the substrate side to the transistor 500 side through the insulators 512 and 514. Alternatively, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film or the like disposed outside the insulator 581 toward the transistor 500. Alternatively, oxygen contained in the insulator 524 or the like can be prevented from diffusing toward the substrate through the insulators 512 and 514. Alternatively, oxygen contained in the insulator 580 or the like can be prevented from diffusing upward from the transistor 500 through the insulator 574. In this way, the transistor 500 is preferably surrounded by the insulators 512, 514, 571, 544, 574, 576, and 581, which have the function of preventing the diffusion of impurities such as water and hydrogen and oxygen.

[0451] Here, it is preferable to use an oxide having an amorphous structure as the insulators 512, 514, 544, 571, 574, 576, and 581. For example, AlO x (x is any number greater than 0), or MgO y It is preferable to use a metal oxide such as y (where y is any number greater than 0). In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, hydrogen contained in the transistor 500 or hydrogen present around the transistor 500 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 500. By using a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, a highly reliable transistor 500 and semiconductor device can be manufactured with excellent characteristics.

[0452] Furthermore, the insulators 512, 514, 544, 571, 574, 576, and 581 preferably have an amorphous structure, but may have a polycrystalline structure in part. The insulators 512, 514, 544, 571, 574, 576, and 581 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0453] The insulators 512, 514, 544, 571, 574, 576, and 581 can be formed by, for example, a sputtering method. Sputtering does not require the use of hydrogen-containing molecules in a film formation gas, and therefore can reduce the hydrogen concentrations of the insulators 512, 514, 544, 571, 574, 576, and 581. Note that the film formation method is not limited to sputtering, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like may also be used as appropriate.

[0454] It may also be desirable to reduce the resistivity of insulators 512, 544, and 576. For example, it may be desirable to reduce the resistivity of insulators 512, 544, and 576 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulators 512, 544, and 576 may be able to reduce charge-up of the conductors 503, 542, 560, etc. in a process using plasma or the like in a semiconductor device manufacturing process. The resistivity of the insulators 512, 544, and 576 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0455] The insulators 516, 574, 580, and 581 preferably have a lower dielectric constant than the insulator 514. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having vacancies, or the like can be used as the insulators 516, 580, and 581 as appropriate.

[0456] For example, the insulator 581 is preferably an insulator that functions as an interlayer film, a planarizing film, or the like.

[0457] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Here, the conductor 503 is preferably provided by being embedded in an opening formed in the insulator 516. In addition, a part of the conductor 503 may be embedded in the insulator 514.

[0458] The conductor 503 includes a conductor 503a and a conductor 503b. The conductor 503a is provided in contact with the bottom surface and sidewall of the opening. The conductor 503b is provided so as to be embedded in a recess formed in the conductor 503a. Here, the height of the top of the conductor 503b is approximately the same as the height of the top of the conductor 503a and the height of the top of the insulator 516.

[0459] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0460] By using a conductive material that can reduce hydrogen diffusion for the conductor 503a, it is possible to prevent impurities such as hydrogen contained in the conductor 503b from diffusing into the oxide 530 via the insulator 524 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductor 503a, it is possible to prevent the conductor 503b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 503a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 503a may be made of titanium nitride.

[0461] The conductor 503b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0462] The electrical resistivity of the conductor 503 is designed taking into account the potential applied to the conductor 503, and the film thickness of the conductor 503 is set to match this electrical resistivity. The film thickness of the insulator 516 is approximately the same as that of the conductor 503. Here, it is preferable to make the film thicknesses of the conductor 503 and the insulator 516 as thin as possible within the range permitted by the design of the conductor 503. By making the film thickness of the insulator 516 thin, the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, thereby reducing the diffusion of the impurities into the oxide 530.

[0463] Note that the conductor 503 is preferably larger than the area of ​​the oxide 530 that does not overlap with the conductors 542a and 542b when viewed from above. In particular, as shown in FIG. 22C , the conductor 503 preferably extends to an area outside the channel width direction ends of the oxides 530a and 530b. That is, outside the side surfaces of the oxide 530 in the channel width direction, the conductor 503 and the conductor 560 preferably overlap with each other via an insulator. With this structure, the channel formation region of the oxide 530 can be electrically surrounded by the electric field of the conductor 560 functioning as a gate electrode and the electric field of the conductor 503 functioning as a backgate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gates is referred to as a surrounded channel (S-channel) structure.

[0464] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. By adopting the S-channel structure, the transistor can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0465] 22C, the conductor 503 is extended to function as a wiring. However, the present invention is not limited to this, and a conductor functioning as a wiring may be provided below the conductor 503. Furthermore, it is not necessary to provide one conductor 503 for each transistor. For example, the conductor 503 may be shared by multiple transistors.

[0466] Note that although the conductor 503 in the transistor 500 has a stacked structure of the conductor 503a and the conductor 503b, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0467] The insulator 522 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 522 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 522 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 524.

[0468] The insulator 522 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulator. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 to the substrate and the diffusion of impurities such as hydrogen from the periphery of the transistor 500 to the oxide 530. Therefore, the insulator 522 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 500 and the generation of oxygen vacancies in the oxide 530. Furthermore, the conductor 503 can be prevented from reacting with oxygen contained in the insulator 524 or the oxide 530.

[0469] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 522 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0470] The insulator 522 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide. As transistors become smaller and more highly integrated, thinning of the gate insulator can lead to problems such as leakage current. Using a high-k material as the insulator functioning as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness. Alternatively, the insulator 522 may be made of a material with a high dielectric constant, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST).

[0471] The insulator 524 in contact with the oxide 530 may be formed using, for example, silicon oxide, silicon oxynitride, or the like as appropriate.

[0472] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 600° C., more preferably 350° C. to 550° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0473] By subjecting the oxide 530 to oxygen addition treatment, oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, O Furthermore, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be removed as H2O (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0474] The insulators 522 and 524 may each have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. The insulator 524 may be formed in an island shape overlapping the oxide 530a. In this case, the insulator 544 is configured to contact the side surface of the insulator 524 and the top surface of the insulator 522.

[0475] The conductor 542a and the conductor 542b are provided in contact with the top surface of the oxide 530b. The conductor 542a and the conductor 542b function as a source electrode and a drain electrode of the transistor 500, respectively.

[0476] As the conductor 542 (conductor 542a and conductor 542b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when they absorb oxygen.

[0477] Note that hydrogen contained in the oxide 530b and the like may diffuse into the conductor 542a or the conductor 542b. In particular, by using a nitride containing tantalum for the conductors 542a and 542b, hydrogen contained in the oxide 530b and the like is likely to diffuse into the conductor 542a or the conductor 542b, and the diffused hydrogen may bond with nitrogen contained in the conductor 542a or the conductor 542b. In other words, hydrogen contained in the oxide 530b and the like may be absorbed by the conductor 542a or the conductor 542b.

[0478] Furthermore, it is preferable that no curved surface be formed between the side surface of the conductor 542 and the top surface of the conductor 542. The conductor 542 without such a curved surface can increase the cross-sectional area of ​​the conductor 542 in the cross section in the channel width direction. This can increase the conductivity of the conductor 542 and the on-state current of the transistor 500.

[0479] The insulator 571a is provided in contact with the top surface of the conductor 542a, and the insulator 571b is provided in contact with the top surface of the conductor 542b. The insulator 571 preferably functions as a barrier insulating film against oxygen. Therefore, the insulator 571 preferably has a function of suppressing oxygen diffusion. For example, the insulator 571 preferably has a function of suppressing oxygen diffusion more than the insulator 580. The insulator 571 may be, for example, a nitride containing silicon, such as silicon nitride. The insulator 571 preferably has a function of capturing impurities such as hydrogen. In this case, the insulator 571 may be an insulator such as a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 571 is preferable because hydrogen can be more effectively captured or fixed. This enables the manufacture of a highly reliable transistor 500 and a semiconductor device with favorable characteristics.

[0480] The insulator 544 is provided to cover the insulator 524, the oxide 530a, the oxide 530b, the conductor 542, and the insulator 571. The insulator 544 preferably has a function of capturing and fixing hydrogen. In this case, the insulator 544 preferably includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. Alternatively, for example, the insulator 544 may be a stacked film of aluminum oxide and silicon nitride on the aluminum oxide.

[0481] By providing the insulator 571 and the insulator 544 as described above, the conductor 542 can be surrounded by an insulator having a barrier property against oxygen. That is, oxygen contained in the insulator 524 and the insulator 580 can be prevented from diffusing into the conductor 542. This can prevent the conductor 542 from being directly oxidized by the oxygen contained in the insulator 524 and the insulator 580, which increases the resistivity and reduces the on-state current.

[0482] The insulator 552 functions as part of the gate insulator. The insulator 552 is preferably a barrier insulating film against oxygen. Any of the insulators that can be used for the insulator 574 described above can be used as the insulator 552. The insulator 552 can be an insulator containing one or both of an oxide of aluminum and hafnium. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 552. In this case, the insulator 552 contains at least oxygen and aluminum.

[0483] As shown in FIG. 22C , the insulator 552 is provided in contact with the top surface and side surfaces of the oxide 530b, the side surfaces of the oxide 530a, the side surfaces of the insulator 524, and the top surface of the insulator 522. That is, the regions of the oxide 530a, the oxide 530b, and the insulator 524 that overlap with the conductor 560 are covered with the insulator 552 in the cross section in the channel width direction. This allows the insulator 552, which has oxygen barrier properties, to block oxygen from being released from the oxides 530a and 530b during heat treatment or the like. This reduces the formation of oxygen vacancies (Vo) in the oxides 530a and 530b. This reduces the oxygen vacancies (Vo) and V formed in the region 530bc. O H can be reduced. Therefore, the electrical characteristics of the transistor 500 can be improved, and the reliability can be improved.

[0484] Conversely, even if the insulator 580, the insulator 550, or the like contains excessive amounts of oxygen, the oxygen can be prevented from being excessively supplied to the oxide 530a and the oxide 530b. Therefore, the region 530bc can prevent the regions 530ba and 530bb from being excessively oxidized, which would cause a decrease in the on-state current or the field-effect mobility of the transistor 500.

[0485] 22B , the insulator 552 is provided in contact with the side surfaces of the conductor 542, the insulator 544, the insulator 571, and the insulator 580. This reduces the oxidation of the side surface of the conductor 542 and the formation of an oxide film on the side surface. This reduces the on-state current or field-effect mobility of the transistor 500.

[0486] The insulator 552, together with the insulator 554, the insulator 550, and the conductor 560, needs to be provided in an opening formed in the insulator 580 or the like. To miniaturize the transistor 500, the insulator 552 preferably has a small thickness. The thickness of the insulator 552 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 1.0 nm or less, 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower and upper limits can be combined. In this case, the insulator 552 only needs to have at least a region with the above-described thickness. The thickness of the insulator 552 is preferably thinner than the thickness of the insulator 550. In this case, the insulator 552 only needs to have at least a region with a thickness thinner than the insulator 550.

[0487] To form the insulator 552 into a thin film as described above, it is preferable to use the ALD method. The ALD method includes a thermal ALD method in which a precursor and a reactant react using only thermal energy, and a plasma-enhanced ALD method in which a plasma-excited reactant is used. The PEALD method may be preferable because it uses plasma, allowing film formation at a lower temperature.

[0488] The ALD method utilizes the self-regulating property of atoms and can deposit atoms one layer at a time, which has the following advantages: it is possible to form an extremely thin film, it is possible to form a film on a structure with a high aspect ratio, it is possible to form a film with few defects such as pinholes, it is possible to form a film with excellent coverage, it is possible to form a film at a low temperature, etc. Therefore, the insulator 552 can be formed with good coverage on the side surface of an opening formed in the insulator 580 or the like, with a thin film thickness as described above.

[0489] Some precursors used in the ALD method contain carbon and other impurities. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0490] The insulator 550 functions as part of the gate insulator. The insulator 550 is preferably disposed in contact with the upper surface of the insulator 552. The insulator 550 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulator 550 is an insulator containing at least oxygen and silicon.

[0491] Like the insulator 524, the insulator 550 preferably has a reduced concentration of impurities such as water and hydrogen. The thickness of the insulator 550 is preferably 1 nm or more, or 0.5 nm or more, and preferably 15 nm or less, or 20 nm or less. Note that the above-mentioned lower and upper limits can be combined. In this case, the insulator 550 only needs to have a region with the above-mentioned thickness in at least a portion thereof.

[0492] 22B and 22C show a configuration in which insulator 550 is a single layer, but the present invention is not limited to this and may have a laminated structure of two or more layers. For example, as shown in Fig. 23B, insulator 550 may have a two-layer laminated structure of insulator 550a and insulator 550b on insulator 550a.

[0493] As shown in FIG. 23B , when the insulator 550 has a two-layer stacked structure, the lower insulator 550a is preferably formed using an insulator that easily transmits oxygen, and the upper insulator 550b is preferably formed using an insulator that suppresses oxygen diffusion. This structure can suppress the diffusion of oxygen contained in the insulator 550a into the conductor 560. That is, it can suppress a decrease in the amount of oxygen supplied to the oxide 530. It can also suppress oxidation of the conductor 560 due to the oxygen contained in the insulator 550a. For example, the insulator 550a may be formed using a material that can be used for the insulator 550 described above, and the insulator 550b may be formed using an insulator containing one or both of aluminum and hafnium oxides. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, hafnium oxide is used as the insulator 550b. In this case, the insulator 550b contains at least oxygen and hafnium. The thickness of the insulator 550b is preferably 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. The above-mentioned lower and upper limits can be combined. In this case, the insulator 550b only needs to have a region with the above-mentioned thickness in at least a portion.

[0494] When silicon oxide, silicon oxynitride, or the like is used for the insulator 550a, the insulator 550b may be an insulating material, such as a high-k material with a high dielectric constant. By forming the gate insulator as a layered structure of the insulators 550a and 550b, a layered structure that is thermally stable and has a high dielectric constant can be achieved. This allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. This allows the dielectric strength of the insulator 550 to be increased.

[0495] The insulator 554 functions as part of the gate insulator. A barrier insulating film against hydrogen is preferably used as the insulator 554. This can prevent impurities such as hydrogen contained in the conductor 560 from diffusing into the insulator 550 and the oxide 530b. The insulator 554 can be any of the insulators that can be used for the insulator 576. For example, silicon nitride formed by a PEALD method can be used as the insulator 554. In this case, the insulator 554 contains at least nitrogen and silicon.

[0496] The insulator 554 may further have a barrier property against oxygen, which can prevent oxygen contained in the insulator 550 from diffusing into the conductor 560.

[0497] The insulator 554, together with the insulator 552, the insulator 550, and the conductor 560, needs to be provided in an opening formed in the insulator 580 or the like. To miniaturize the transistor 500, the insulator 554 preferably has a small thickness. The thickness of the insulator 554 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower and upper limits can be combined. In this case, the insulator 554 only needs to have at least a region with the above-described thickness. The thickness of the insulator 554 is preferably thinner than the thickness of the insulator 550. In this case, the insulator 554 only needs to have at least a region with a thickness thinner than the insulator 550.

[0498] The conductor 560 functions as the gate electrode of the transistor 500. The conductor 560 preferably includes a conductor 560a and a conductor 560b disposed on the conductor 560a. For example, the conductor 560a is preferably disposed so as to surround the bottom and side surfaces of the conductor 560b. As shown in FIGS. 22B and 22C, the height of the top of the conductor 560 roughly coincides with the height of the top of the insulator 550. Note that although the conductor 560 is shown as having a two-layer structure of the conductor 560a and the conductor 560b in FIGS. 22B and 22C, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers, other than the two-layer structure.

[0499] The conductor 560a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0500] Furthermore, since the conductor 560a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 560b caused by oxygen contained in the insulator 550. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0501] Furthermore, since the conductor 560 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 560b can be a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 560b can have a layered structure. Specifically, for example, the conductor 560b can have a layered structure of titanium or titanium nitride and the above conductive material.

[0502] Furthermore, in the transistor 500, the conductor 560 is formed in a self-aligned manner so as to fill an opening formed in the insulator 580, etc. By forming the conductor 560 in this manner, the conductor 560 can be reliably placed in the region between the conductor 542a and the conductor 542b without alignment.

[0503] 22C , in the channel width direction of the transistor 500, the height of the bottom surface of the conductor 560 in a region where the conductor 560 does not overlap with the oxide 530b is preferably lower than the height of the bottom surface of the oxide 530b when the bottom surface of the insulator 522 is used as the reference. The conductor 560, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 530b via the insulator 550 or the like, which makes it easier for the electric field of the conductor 560 to act on the entire channel formation region of the oxide 530b. This increases the on-state current of the transistor 500 and improves its frequency characteristics. The difference in height between the bottom surface of conductor 560 and the bottom surface of oxide 530b in the region where oxide 530a and oxide 530b do not overlap with conductor 560, relative to the bottom surface of insulator 522, is preferably 0 nm or more, 3 nm or more, or 5 nm or more, and is preferably 20 nm or less, 50 nm or less, or 100 nm or less. Note that the above-mentioned lower limit and upper limit values ​​can be combined with each other.

[0504] The insulator 580 is provided on the insulator 544, and openings are formed in the regions where the insulator 550 and the conductor 560 are to be provided. The top surface of the insulator 580 may be planarized.

[0505] The insulator 580, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. The insulator 580 is preferably formed using, for example, the same material as the insulator 516. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form a region containing oxygen that is released by heating.

[0506] The insulator 580 preferably has a low concentration of impurities such as water and hydrogen. For example, the insulator 580 may be formed using an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate.

[0507] The insulator 574 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 580 and preferably has a function of capturing impurities such as hydrogen. The insulator 574 also preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 574 may be an insulator made of a metal oxide having an amorphous structure, such as aluminum oxide. In this case, the insulator 574 contains at least oxygen and aluminum. By providing the insulator 574, which is in contact with the insulator 580 and has a function of capturing impurities such as hydrogen, in the region between the insulators 512 and 581, the insulator 574 can capture impurities such as hydrogen contained in the insulator 580 and maintain a constant amount of hydrogen in the region. In particular, using aluminum oxide having an amorphous structure as the insulator 574 is preferable because it may be able to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 500 and semiconductor device with excellent characteristics.

[0508] The insulator 576 functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 580. The insulator 576 is disposed over the insulator 574. The insulator 576 is preferably a nitride containing silicon, such as silicon nitride or silicon nitride oxide. For example, the insulator 576 may be formed using silicon nitride deposited by a sputtering method. A high-density silicon nitride film can be formed by depositing the insulator 576 by a sputtering method. Alternatively, the insulator 576 may be formed by stacking a silicon nitride film deposited by a PEALD method or a CVD method on the silicon nitride film deposited by a sputtering method.

[0509] One of the first and second terminals of the transistor 500 is electrically connected to a conductor 540a functioning as a plug, and the other of the first and second terminals of the transistor 500 is electrically connected to a conductor 540b. Note that in this specification and the like, the conductors 540a and 540b are collectively referred to as conductors 540.

[0510] Conductors that function as plugs or wiring may have multiple structures collectively designated by the same reference numeral. In this specification, the wiring and the plug connected to the wiring may be an integrated unit. That is, there are cases where a portion of the conductor functions as the wiring, and cases where a portion of the conductor functions as the plug.

[0511] The materials for each plug and wiring can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a laminated layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the plug and wiring from a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce the wiring resistance.

[0512] For example, conductor 540a is provided in a region overlapping with conductor 542a. Specifically, in the region overlapping with conductor 542a, openings are formed in insulators 571, 544, 580, 574, 576, and 581 shown in FIG. 22B and insulators 582 and 586 shown in FIG. 22A, and conductor 540a is provided inside the openings. For example, conductor 540b is provided in a region overlapping with conductor 542b. Specifically, in the region overlapping with conductor 542b, openings are formed in insulators 571, 544, 580, 574, 576, and 581 shown in Fig. 22B, and insulators 582 and 586 shown in Fig. 22A, and conductor 540b is provided inside the openings. Note that insulators 582 and 586 will be described later.

[0513] 22B, an insulator 541a may be provided as an insulator having a barrier property against impurities between the conductor 540a and a side surface of the opening in a region overlapping with the conductor 542a. Similarly, an insulator 541b may be provided as an insulator having a barrier property against impurities between the conductor 540b and a side surface of the opening in a region overlapping with the conductor 542b. Note that in this specification and the like, the insulators 541a and 541b are collectively referred to as the insulator 541.

[0514] The conductors 540a and 540b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 540a and 540b may have a layered structure.

[0515] Furthermore, when the conductor 540 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the insulators 574, 576, 581, 580, 544, and the first conductor disposed near the insulator 571. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 576 from being mixed into the oxide 530 through the conductors 540a and 540b.

[0516] The insulators 541a and 541b may be a barrier insulating film that can be used for the insulator 544 or the like. For example, the insulators 541a and 541b may be made of an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulators 541a and 541b are provided in contact with the insulators 574, 576, and 571, and thus can prevent impurities such as water and hydrogen contained in the insulator 580 or the like from being mixed into the oxide 530 through the conductors 540a and 540b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, oxygen contained in the insulator 580 can be prevented from being absorbed by the conductors 540a and 540b.

[0517] When insulators 541a and 541b are formed into a layered structure as shown in FIG. 22B, it is preferable that the first insulator in contact with the inner wall of an opening such as insulator 580 and the second insulator inside it be made of a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0518] For example, aluminum oxide formed by the ALD method can be used as the first insulator, and silicon nitride formed by the PEALD method can be used as the second insulator. With this structure, oxidation of the conductor 540 can be suppressed and hydrogen contamination of the conductor 540 can be reduced.

[0519] Although the transistor 500 has a structure in which the first insulator of the insulator 541 and the second conductor of the insulator 541 are stacked, the present invention is not limited to this. For example, the insulator 541 may be provided as a single layer or a stacked structure of three or more layers. Furthermore, the transistor 500 has a structure in which the first conductor of the conductor 540 and the second conductor of the conductor 540 are stacked, but the present invention is not limited to this. For example, the conductor 540 may be provided as a single layer or a stacked structure of three or more layers.

[0520] 22A, conductors 610 and 612, which function as wiring and are in contact with the upper portions of conductors 540a and 540b, may be disposed. Conductors 610 and 612 are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors may also have a layered structure. Specifically, for example, the conductors may be a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductors may be formed so as to be embedded in openings provided in an insulator.

[0521] 22A to 22C. The structure of the transistor included in the semiconductor device of one embodiment of the present invention may be changed depending on the situation.

[0522] 22A to 22C may have the structure shown in FIG. 24. The transistor in FIG. 24 differs from the transistor 500 in FIG. 22A to 22C in that it includes an oxide 543a and an oxide 543b. In this specification, the oxide 543a and the oxide 543b are collectively referred to as the oxide 543. The cross-sectional structure of the transistor in FIG. 24 in the channel width direction can be similar to that of the cross-section of the transistor 500 in FIG. 22C.

[0523] The oxide 543a is provided between the oxide 530b and the conductor 542a, and the oxide 543b is provided between the oxide 530b and the conductor 542b. Here, the oxide 543a is preferably in contact with the upper surface of the oxide 530b and the lower surface of the conductor 542a. The oxide 543b is preferably in contact with the upper surface of the oxide 530b and the lower surface of the conductor 542b.

[0524] The oxide 543 preferably has a function of suppressing oxygen permeation. Placing the oxide 543, which has a function of suppressing oxygen permeation, between the conductor 542 functioning as a source or drain electrode and the oxide 530b is preferable because the electrical resistance between the conductor 542 and the oxide 530b can be reduced. Such a structure can improve the electrical characteristics, field-effect mobility, and reliability of the transistor 500 in some cases.

[0525] Alternatively, a metal oxide containing element M may be used as oxide 543. In particular, element M may be aluminum, gallium, yttrium, or tin. Preferably, oxide 543 has a higher concentration of element M than oxide 530b. Alternatively, oxide 543 may be gallium oxide. Alternatively, oxide 543 may be a metal oxide such as In-M-Zn oxide. Specifically, the atomic ratio of element M to In in the metal oxide used for oxide 530b is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, the film thickness of oxide 543 is preferably 0.5 nm or more or 1 nm or more, and is preferably 2 nm or less, 3 nm or less, or 5 nm or less. The above-mentioned lower and upper limits may be combined. Preferably, oxide 543 is crystalline. When oxide 543 is crystalline, oxygen release from oxide 530 can be effectively suppressed. For example, if the oxide 543 has a crystalline structure such as a hexagonal crystal structure, the release of oxygen from the oxide 530 may be suppressed.

[0526] An insulator 582 is provided on the insulator 581, and an insulator 586 is provided on the insulator 582.

[0527] The insulator 582 is preferably made of a substance that has a barrier property against oxygen and hydrogen. Therefore, the insulator 582 can be made of a material similar to that of the insulator 514. For example, the insulator 582 is preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0528] The insulator 586 can be made of a material similar to that of the insulator 512. The use of a material with a relatively low dielectric constant for these insulators can reduce parasitic capacitance between wirings. For example, the insulator 586 can be made of a silicon oxide film, a silicon oxynitride film, or the like.

[0529] Next, a description will be given of a capacitor 600 and its peripheral wiring or plugs included in the semiconductor device shown in Fig. 22A. Note that the capacitor 600, wiring, and / or plugs are provided above the transistor 500 shown in Fig. 22A.

[0530] The capacitor 600 includes, for example, a conductor 610 , a conductor 620 , and an insulator 630 .

[0531] A conductor 610 is provided over one of the conductors 540a and 540b, the conductor 546, and the insulator 586. The conductor 610 functions as one of a pair of electrodes of a capacitor 600.

[0532] A conductor 612 is provided over the other of the conductor 540a and the conductor 540b and over the insulator 586. The conductor 612 functions as a plug, a wiring, a terminal, or the like that electrically connects the transistor 500 to a circuit element, a wiring, or the like arranged above it.

[0533] The conductor 612 and the conductor 610 may be formed at the same time.

[0534] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with silicon oxide added can also be used.

[0535] 22A, the conductor 612 and the conductor 610 are shown as single-layer structures, but are not limited to this configuration and may be a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0536] An insulator 630 is provided on the insulator 586 and the conductor 610. The insulator 630 functions as a dielectric sandwiched between the pair of electrodes of the capacitor 600.

[0537] The insulator 630 can be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, zirconium oxide, or the like. The insulator 630 can be formed as a stacked layer or a single layer using any of the above-mentioned materials.

[0538] Furthermore, for example, a laminated structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material may be used for the insulator 630. With this configuration, the capacitor 600 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the insulator with high dielectric strength improves the dielectric strength, thereby suppressing electrostatic breakdown of the capacitor 600.

[0539] Examples of high-dielectric-constant (high-k) materials (materials with a high relative dielectric constant) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0540] Alternatively, the insulator 630 may be a single layer or a multilayer insulator containing a high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO), or (Ba,Sr)TiO (BST). Alternatively, the insulator 630 may be a compound containing hafnium and zirconium. As semiconductor devices become smaller and more highly integrated, thinning of the gate insulator and dielectrics used in capacitors can cause problems such as leakage current in transistors and capacitors. Using a high-k material for the insulators that function as the gate insulator and dielectrics used in capacitors can reduce the gate potential during transistor operation and ensure the capacitance of capacitors while maintaining the physical film thickness.

[0541] The conductor 620 is provided to overlap with the conductor 610 with the insulator 630 placed therebetween. The conductor 610 functions as one of a pair of electrodes of the capacitor 600.

[0542] The conductor 620 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and tungsten is particularly preferable. When the conductor 620 is formed simultaneously with other structures such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) can be used. For example, the conductor 620 can be made of a material that can be used for the conductor 610. The conductor 620 may have a laminated structure of two or more layers instead of a single layer structure.

[0543] An insulator 640 is provided over the conductor 620 and the insulator 630. The insulator 640 is preferably a film having a barrier property that prevents diffusion of hydrogen, impurities, and the like into a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 514 can be used for the insulator 640.

[0544] An insulator 650 is provided over the insulator 640. The insulator 650 can be provided using a material similar to that of the insulator 512. The insulator 650 may also function as a planarizing film that covers the uneven shape below it. Therefore, the insulator 650 can be made of, for example, a material that can be used for the insulator 514.

[0545] 22A is a planar type, the shape of the capacitive element is not limited to this. The capacitor 600 may be, for example, a cylindrical type instead of a planar type.

[0546] 22A , an insulator 411, an insulator 412, an insulator 413, and an insulator 414 are provided in this order above an insulator 650. The insulators 411, 412, and 413 are provided with a conductor 416 functioning as a plug or a wiring. For example, the conductor 416 can be provided in a region overlapping with a conductor 660, which will be described later.

[0547] Furthermore, openings are provided in the insulators 630, 640, and 650 in regions overlapping with the conductor 612, and the conductor 660 is provided to fill the openings. The conductor 660 functions as a plug or wiring electrically connected to the conductor 416 included in the above-described wiring layer.

[0548] The insulators 411 and 414 are preferably made of an insulator that has barrier properties against impurities such as water and hydrogen, similar to the insulator 514. Therefore, the insulators 411 and 414 can be made of, for example, a material that can be used for the insulator 514.

[0549] For the insulators 412 and 413, similarly to the insulator 512, it is preferable to use an insulator with a relatively low dielectric constant in order to reduce parasitic capacitance between wirings.

[0550] <Transistor configuration example> Next, a configuration will be described in which a dielectric that may have ferroelectricity is provided in and around a transistor 500 that includes a metal oxide in a channel formation region.

[0551] FIG. 25A shows an example of a transistor configuration in which a dielectric that may have ferroelectric properties is provided in the configuration of transistor 500 of FIGS. 22A, 22B, etc.

[0552] 25A has a configuration in which the insulator 522 functioning as a gate insulator for the conductor 503 is replaced with an insulator 520. As one example, the insulator 520 can be a dielectric that may have ferroelectricity.

[0553] Materials that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO X(X is a real number greater than 0), materials in which element J1 (here, element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to hafnium oxide, and materials in which element J2 (here, element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to zirconium oxide. Furthermore, materials that may have ferroelectricity include PbTiO X Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used. Furthermore, the material capable of exhibiting ferroelectricity may be, for example, a mixture or compound selected from the materials listed above. Alternatively, the material capable of exhibiting ferroelectricity may be a laminated structure made of multiple materials selected from the materials listed above. Incidentally, hafnium oxide, zirconium oxide, HfZrO X , and materials in which the element J1 is added to hafnium oxide, etc., may have crystal structures (characteristics) that can change not only depending on the film formation conditions but also on various processes, etc., and therefore in this specification, etc., the term "ferroelectric" does not refer only to materials that exhibit ferroelectricity, but rather refers to materials that can have ferroelectricity.

[0554] Among these, hafnium oxide or a material containing hafnium oxide and zirconium oxide is preferred as a material capable of exhibiting ferroelectricity, since it can be processed into a thin film of only a few nanometers and still retain ferroelectricity. Here, the film thickness of the insulator 520 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less. By using a thin ferroelectric layer, a ferroelectric capacitor can be combined with a miniaturized transistor 500 to form a semiconductor device.

[0555] Although insulator 520 is illustrated as a single layer in FIG. 25A, insulator 520 may be an insulating film of two or more layers including a dielectric material that may have ferroelectricity. A specific example of such a transistor is shown in FIG. 25B. In FIG. 25B, insulator 520 includes insulator 520a and insulator 520b, for example. Insulator 520a is provided on the top surface of insulator 516 and conductor 503, and insulator 520b is provided on the top surface of insulator 520a.

[0556] For example, a dielectric material that may have ferroelectricity may be used as the insulator 520a. For example, silicon oxide may be used as the insulator 520b. Alternatively, for example, silicon oxide may be used as the insulator 520a and a dielectric material that may have ferroelectricity may be used as the insulator 520b.

[0557] As shown in Figure 25B, by using two layers of insulator 520, with one layer being a dielectric that may have ferroelectricity and the other layer being silicon oxide, it is possible to suppress current leakage between conductor 503, which functions as a gate electrode, and oxide 530.

[0558] 25C shows an example of a transistor configuration in which the insulator 520 has three layers. In Fig. 25C, the insulator 520 includes, for example, an insulator 520a, an insulator 520b, and an insulator 520c. The insulator 520c is provided on the top surface of the insulator 516 and the conductor 503, the insulator 520a is provided on the top surface of the insulator 520c, and the insulator 520b is provided on the top surface of the insulator 520a.

[0559] The insulator 520a may be made of, for example, a dielectric material that may have ferroelectricity, and the insulators 520b and 520c may be made of, for example, silicon oxide.

[0560] The structures of the transistors illustrated in FIGS. 25A to 25C can be applied to, for example, the transistor 22 and the transistor 32 illustrated in FIG. 1B, which are described in the above embodiment.

[0561] By applying the structure described in this embodiment to a semiconductor device including a transistor including an oxide semiconductor, fluctuations in electrical characteristics of the transistor can be suppressed and reliability can be improved.

[0562] Furthermore, in a semiconductor device using a transistor having an oxide semiconductor, the area of ​​a circuit constituting the semiconductor device can be reduced by achieving a stacked structure, miniaturization, high integration, and the like. In particular, by using a ferroelectric capacitor as a capacitor included in a semiconductor device, the electrostatic capacitance of the capacitor can be increased, thereby enabling miniaturization of the capacitor. As a result, the area of ​​a circuit including the capacitor can be reduced. Furthermore, as described in this embodiment, stacking transistors and capacitors can increase the circuit scale while suppressing an increase in the circuit area of ​​the semiconductor device.

[0563] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0564] (Embodiment 5) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0565] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. In addition to these, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0566] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 26A. Fig. 26A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0567] As shown in Figure 26A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). The "Crystalline" classification excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0568] The structure within the bold frame in Figure 26A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "Amorphous" and "Crystal."

[0569] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 26B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." In Figure 26B, the horizontal axis represents 2θ [deg.], and the vertical axis represents intensity [au]. The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 26B may be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 26B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 26B is 500 nm.

[0570] As shown in Figure 26B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. As shown in Figure 26B, the peak near 2θ = 31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0571] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 26C. Figure 26C shows a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 26C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0572] As shown in FIG. 26C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0573] <<Structure of oxide semiconductor>> Note that oxide semiconductors may be classified differently from those shown in FIG. 26A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0574] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0575] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0576] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0577] In addition, in an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. Furthermore, the In layer may contain element M. Furthermore, the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0578] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0579] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0580] When the crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. The distortion may also have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries can be identified even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0581] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the transistor's on-state current and field-effect mobility. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in transistor semiconductor layers. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0582] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the decrease in electron mobility due to grain boundaries is unlikely to occur in CAAC-OS. Furthermore, since the crystallinity of oxide semiconductors can be reduced by impurities or defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, CAAC-OS is stable even under high temperatures (so-called thermal budgets) during the manufacturing process. Therefore, using CAAC-OS for OS transistors allows for greater flexibility in the manufacturing process.

[0583] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of these microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD system, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when electron diffraction (also known as selected-area electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0584] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0585] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0586] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0587] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0588] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0589] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0590] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0591] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0592] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0593] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0594] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0595] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0596] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than 1×10, more preferably 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0597] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0598] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0599] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0600] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0601] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0602] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0603] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0604] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0605] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0606] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0607] (Embodiment 6) In this embodiment mode, a configuration of an integrated circuit including each component included in the semiconductor device and the arithmetic device MAC1 described in the above embodiment mode will be described with reference to FIG.

[0608] FIG. 27 shows an example of a semiconductor chip 391 incorporating an integrated circuit 390. The semiconductor chip 391 shown in FIG. 27 has leads 392 and an integrated circuit 390. The integrated circuit 390 has various circuits, including the semiconductor device described in the above embodiment and the arithmetic unit MAC1, provided on a single die. The integrated circuit 390 has a stacked structure and is broadly divided into a layer having Si transistors (Si transistor layer 393), a wiring layer 394, and a layer having OS transistors (OS transistor layer 395). The OS transistor layer 395 can be stacked on the Si transistor layer 393, which facilitates miniaturization of the semiconductor chip 391.

[0609] 27, a QFP (Quad Flat Package) is applied to the package of the semiconductor chip 391, but the form of the package is not limited to this. Other configuration examples include an insertion mounting type DIP (Dual In-line Package) and PGA (Pin Grid Array), a surface mounting type SOP (Small Outline Package), SSOP (Shrink Small Outline Package), TSOP (Thin-Small Outline Package), LCC (Leaded Chip Carrier), QFN (Quad Flat Non-leaded package), BGA (Ball Grid Array), FBGA (Fine pitch Ball Grid Array), a contact mounting type DTP (Dual Tape carrier Package), QTP (Quad Tape-carrier Package), etc., and the like can be used as appropriate.

[0610] The semiconductor device having Si transistors and the arithmetic unit MAC1 can all be formed in the Si transistor layer 393, the wiring layer 394, and the OS transistor layer 395. That is, the elements constituting the semiconductor device can be formed in the same manufacturing process. Therefore, the semiconductor chip shown in FIG. 27 does not need to increase the manufacturing process even if the number of constituent elements increases, and the semiconductor device can be incorporated at low cost.

[0611] According to the above-described embodiment of the present invention, a novel semiconductor device and electronic device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device and electronic device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device and electronic device in which heat generation can be suppressed can be provided.

[0612] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0613] (Embodiment 7) In this embodiment, electronic devices, mobile objects, and computing systems to which the integrated circuit 390 described in the above embodiment (or a semiconductor chip 391 incorporating the integrated circuit 390) can be applied will be described with reference to Figures 28 to 31.

[0614] Fig. 28A shows an external view of an automobile as an example of a moving body. Fig. 28B is a simplified diagram of data exchange within the automobile. The automobile 590 has a plurality of cameras 591 and the like. The automobile 590 also has various sensors (not shown) such as infrared radar, millimeter-wave radar, and laser radar.

[0615] The above-described integrated circuit 390 can be used for a camera 591 or the like in an automobile 590. The automobile 590 processes a plurality of images acquired by a camera 591 in a plurality of imaging directions 592 using the integrated circuit 390 described in the above embodiment, and analyzes the plurality of images collectively using a host controller 594 or the like via a bus 593 or the like, thereby determining the surrounding traffic conditions, such as the presence or absence of guardrails or pedestrians, and performing autonomous driving. The automobile 590 can also be used in systems that provide road guidance, hazard prediction, and the like.

[0616] The integrated circuit 390 performs arithmetic processing such as neural network on the obtained image data, thereby enabling processing such as increasing the image resolution, reducing image noise, facial recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0617] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies may include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc., and a system using artificial intelligence can be provided to these moving bodies by applying a computer according to one embodiment of the present invention.

[0618] Fig. 29A is an external view showing an example of a portable electronic device. Fig. 29B is a simplified diagram showing data exchange within the portable electronic device. Portable electronic device 595 has printed circuit board 596, speaker 597, camera 598, microphone 599, etc.

[0619] In portable electronic device 595, the integrated circuit 390 can be provided on printed circuit board 596. Portable electronic device 595 can improve user convenience by processing and analyzing a plurality of pieces of data obtained by speaker 597, camera 598, microphone 599, etc. using integrated circuit 390 described in the above embodiment.

[0620] In the integrated circuit 390, the obtained image data is subjected to arithmetic processing using a neural network or the like, thereby making it possible to perform processes such as increasing the image resolution, reducing image noise, face recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0621] A portable game console 1100 shown in FIG. 30A includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, operation keys 1107, and the like. The housings 1101, 1102, and 1103 are detachable. By attaching the connection unit 1105 provided on the housing 1101 to the housing 1108, a video image displayed on the display unit 1104 can be output to another video device. On the other hand, by attaching the housings 1102 and 1103 to the housing 1109, the housings 1102 and 1103 are integrated and function as an operation unit. The integrated circuit 390 described in the above embodiment can be incorporated into a chip or the like provided on a substrate of the housing 1102 or 1103.

[0622] 30B shows a stick-type electronic device 1120 that is USB-connected. The electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a board 1124. The board 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are attached to the board 1124. The integrated circuit 390 shown in the previous embodiment can be incorporated into the controller chip 1126 of the board 1124, etc.

[0623] 30C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106 and a control circuit 2110. For example, the control circuit 2110 can incorporate the integrated circuit 390 shown in the previous embodiment.

[0624] The integrated circuit 390 described in the above embodiment can also be used in a server that communicates with the electronic device, instead of being built into the electronic device. In this case, the electronic device and the server form a computing system. Figure 31 shows an example of the configuration of a system 3000.

[0625] The system 3000 is configured by an electronic device 3001 and a server 3002. Communication between the electronic device 3001 and the server 3002 can be performed via an internet line 3003.

[0626] Server 3002 has a plurality of racks 3004. A plurality of circuit boards 3005 are provided in the racks, and integrated circuits 390 described in the above embodiment can be mounted on the circuit boards 3005. This forms a neural network in server 3002. Server 3002 can perform neural network calculations using data input from electronic device 3001 via internet line 3003. The results of calculations by server 3002 can be transmitted to electronic device 3001 via internet line 3003 as necessary. This reduces the calculation load on electronic device 3001.

[0627] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0628] (Notes regarding the present specification) The above-described embodiment and each configuration in the embodiment will be described below with additional notes.

[0629] The configurations shown in each embodiment can be combined as appropriate with configurations shown in other embodiments or examples to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0630] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with another content (or even part of the content) described in that embodiment, and / or with the content (or even part of the content) described in one or more other embodiments.

[0631] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0632] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0633] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0634] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0635] Furthermore, the positional relationships of components shown in the drawings are relative. Therefore, when describing components with reference to the drawings, terms such as "above" and "below" indicating the positional relationships may be used for convenience. The positional relationships of components are not limited to the content described in this specification, and can be rephrased appropriately depending on the situation.

[0636] In this specification and the like, when describing the connection relationship of a transistor, the term "one of the source or drain" (or first electrode or first terminal) is used, and the other of the source and drain is referred to as "the other of the source or drain" (or second electrode or second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0637] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0638] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0639] Furthermore, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0640] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0641] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, a statement that "electrical conduction of positively charged bodies is occurring" can be rephrased as "electrical conduction of negatively charged bodies is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move, and is expressed as a positive current. In other words, the direction in which negatively charged carriers move is opposite to the direction of current, and is expressed as a negative current. Therefore, in this specification, etc., unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0642] In this specification, "A and B are connected" means that A and B are electrically connected. Here, "A and B are electrically connected" means a connection in which an electrical signal can be transmitted between A and B when an object (such as a switch, transistor element, or diode, or a circuit including such an object and wiring) is present between A and B. Note that "A and B are electrically connected" also includes a case in which A and B are directly connected. Here, "A and B are directly connected" means a connection in which an electrical signal can be transmitted between A and B via wiring (or electrodes) or the like, without passing through the object. In other words, a direct connection means a connection that can be regarded as the same circuit diagram when expressed as an equivalent circuit.

[0643] In this specification, a switch refers to a device that has the function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has the function of selecting and switching a path for a current to flow.

[0644] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0645] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0646] In this specification and the like, the terms "film" and "layer" can be interchanged depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer." [Explanation of symbols]

[0647] 10A1: semiconductor device, 10A2: semiconductor device, 10A3: semiconductor device, 10B1: semiconductor device, 10B2: semiconductor device, 10B3: semiconductor device, 10C1: semiconductor device, 10C2: semiconductor device, 10C3: semiconductor device, 10D1: semiconductor device, 10D2: semiconductor device, 10D3: semiconductor device, 20: reference cell unit, 21: reference cell, 22: transistor, 23: transistor, 24: transistor, 25: capacitance, 30: calculation cell unit, 31: calculation cell, 32: transistor, 33: transistor, 34: transistor, 35: capacitance, 100: neural network network, 390: integrated circuit, 391: semiconductor chip, 392: lead, 393: Si transistor layer, 394: wiring layer, 395: OS transistor layer, 411: insulator, 412: insulator, 413: insulator, 414: insulator, 416: conductor, 500: transistor, 503: conductor, 503a: conductor, 503b: conductor, 512: insulator, 514: insulator, 516: insulator, 520: insulator, 520a: insulator, 520b: insulator, 520c: insulator, 522: insulator, 524: insulator, 530: oxide, 530a: oxide, 530b: oxide, 5 30ba: area, 530bb: area, 530bc: area, 540: conductor, 540a: conductor, 540b: conductor, 541: insulator, 541a: insulator, 541b: insulator, 542: conductor, 542a: conductor, 542b: conductor, 543: oxide, 543a: oxide, 543b: oxide, 544: insulator, 546: conductor, 550: insulator, 550a: insulator, 550b: insulator, 552: insulator, 554: insulator, 560: conductor, 560a: conductor, 560b: conductor, 571: insulator, 571a: insulator, 571b: insulator, 574: insulator, 5 76: insulator, 580: insulator, 581: insulator, 582: insulator, 586: insulator, 590: automobile, 591: camera, 592: imaging direction, 593: bus, 594: host controller, 595: portable electronic device, 596: printed wiring board, 597: speaker, 598: camera, 599: microphone, 600: capacitor, 610: conductor, 612: conductor, 620: conductor, 630: insulator, 640: insulator, 650: insulator, 660: conductor, 1100: portable game console, 1101: housing, 1102: housing, 1103: housing, 1104: display unit,1105: Connection part, 1107: Operation key, 1108: Housing, 1109: Housing, 1120: Electronic device, 1121: Housing, 1122: Cap, 1123: USB connector, 1124: Board, 1125: Memory chip, 1126: Controller chip, 1130: Robot, 2101: Sensor, 2106: Sensor, 2110: Control circuit, 3000: System, 3001: Electronic device, 3002: Server, 3003: Internet line, 3004: Rack, 3005: Board,

Claims

[Claim 1] a first transistor, a second transistor, and a capacitor; the first transistor and the second transistor each have a first gate and a second gate; a gate insulating layer for the second gate of the first transistor having ferroelectric properties; one of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor; one of a source and a drain of the first transistor is electrically connected to a first wiring; the other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor; the other of the source and the drain of the first transistor is electrically connected to a second gate of the second transistor; a first gate of the first transistor electrically connected to a second wiring; the other of the source and the drain of the second transistor is electrically connected to the first gate of the second transistor; the other electrode of the capacitor is electrically connected to the first wiring; a first gate of the second transistor and the other of the source and the drain of the second transistor are supplied with a constant potential;

Images