Layered hybrid quantum architecture for quantum computing applications

Abstract

To provide a quantum system and a method of controlling interactions between qubits in a quantum processor.SOLUTION: A quantum system includes a qubit array 100 comprising a plurality of qubits. A bus resonator is coupled between at least one pair of qubits in the qubit array. A Josephson junction (JJ) switch is coupled between the at least one qubit pair of qubits.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates generally to superconducting devices, and more particularly to the integration of control logic in quantum arrays. [Background technology]

[0002] A superconducting quantum computer is a quantum computer implemented using superconducting electronic circuits. Quantum computing studies the application of quantum phenomena to information processing and communication. Various models of quantum computing exist, the most well-known of which include the concepts of qubits and quantum gates. A qubit is a generalization of a bit that has two possible states, but can be in a quantum superposition of both states. A quantum gate is a generalization of a logic gate, but a quantum gate describes the transformation that one or more qubits undergo, given an initial state, after applying a gate to the qubits.

[0003] Today, the challenge in scaling quantum processors containing multiple qubits is controlling the interactions between qubits. Coupling between superconducting qubits, such as microwave crosstalk, can be mitigated by detuning their center frequencies. Instead of changing the inter-qubit coupling constant, the effective coupling can be reduced by making the qubit energies non-degenerate. However, as superconducting qubits are scaled to larger systems, the spectrum of qubit transition frequencies becomes increasingly dense, making it more difficult to suppress residual coupling. Furthermore, realigning the center frequencies of qubits is not only difficult but can also lead to state leakage. Summary of the Invention

[0004] According to an exemplary embodiment, a quantum system includes a qubit array having a plurality of qubits, a bus resonator coupled between at least one pair of qubits in the qubit array, and a switch coupled between at least one pair of qubits in the qubit array.

[0005] In one embodiment, the switch is integrated with a coupled resonator having Josephson junctions (JJs).

[0006] In one embodiment, the switch includes a gate, the gate coupled to an electronic system, the electronic system being tunable by a voltage on the gate.

[0007] In one embodiment, the electronic system is configured to vary the inductance based on the voltage on the gate.

[0008] In one embodiment, the gate is configured to adjust the switch between (i) a low inductance state having a first critical current and (ii) a high inductance state having a second critical current, the second critical current being lower than the first critical current.

[0009] In one embodiment, the switch has a first state that supports supercurrent flow and a second state that is high resistance and supports no supercurrent flow.

[0010] In one embodiment, the voltage on the gate acts to change the inductance of the JJ.

[0011] In one embodiment, the switch includes two or more superconductors separated by an electronic system.

[0012] In one embodiment, the electronic system comprises graphene.

[0013] In one embodiment, the switch is a voltage-controlled superconducting current switch.

[0014] In one embodiment, for at least one qubit of the qubit array, a switch is coupled between the at least one qubit and a readout resonator of the qubit array.

[0015] In one embodiment, the combination of qubit pairs and switches between the qubits and readout resonators is configured to multiplex individual qubits in the array such that each qubit is individually controlled and independent of the qubit frequency.

[0016] In one embodiment, the qubit array is part of a plurality of qubit arrays in a first layer, each of which is separated by one or more switches.

[0017] In one embodiment, there is an asymmetry in the qubit array between at least two of the multiple layers.

[0018] In one embodiment, the quantum system includes multiple layers, each layer having at least one qubit array separated from an adjacent layer by one or more switches.

[0019] In one embodiment, two or more qubits in a qubit array have substantially similar qubit frequencies.

[0020] In one embodiment, multiple layers are laminated together by bump bonding.

[0021] In one embodiment, at least one qubit of the qubit array is blocked by at least one switch.

[0022] According to one embodiment, a method for controlling a quantum system includes providing a qubit array having a plurality of qubits, wherein a bus resonator is coupled between each pair of qubits in the qubit array, and wherein at least one of (i) a Josephson junction (JJ) switch separates at least one qubit pair in the qubit array, or (ii) a second JJ switch separates at least one qubit in the qubit array from a readout resonator.

[0023] In one embodiment, the inductance of the electronic system of the gate of the JJ switch is changed by applying a voltage to the gate of the JJ switch.

[0024] In one embodiment, two or more superconductors are separated by the electronic system of a JJ switch.

[0025] In one embodiment, individual qubits are multiplexed by multiple switches, including a JJ switch and a second JJ switch in the array, such that each qubit is individually controlled and independent of qubit frequency.

[0026] In one embodiment, the qubit array is stacked in multiple layers, with each qubit in the multiple layers individually controlled by multiple switches, independent of the qubit frequency.

[0027] According to one embodiment, a qubit system includes a qubit array comprising a plurality of qubits. A bus resonator is coupled between each pair of adjacent qubits in the qubit array. At least one of: (i) a switch is coupled between each pair of qubits in the qubit array, or (ii) for at least one qubit in the qubit array, a switch is coupled between the at least one qubit and a readout resonator of the qubit array.

[0028] In one embodiment, the switches are integrated with coupled resonators having Josephson junctions (JJs). Each switch includes a gate, the gate coupled to an electronic system, the electronic system tunable by a voltage on the gate. The electronic system is configured to vary the inductance of the JJ based on the voltage on the gate.

[0029] In one embodiment, the combination of qubit pairs and switches between the qubits and readout resonators is configured to multiplex individual qubits in the array such that each qubit is individually controlled and independent of the qubit frequency.

[0030] These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

[0031] The drawings are of exemplary embodiments. The drawings do not describe all embodiments. Other embodiments may be used in addition or instead. Details that may be obvious or unnecessary may be omitted to save space or for more efficient description. Some embodiments may be practiced with additional components or steps, or without all of the components or steps described, or both. The same numerals appearing in different drawings refer to the same or similar components or steps. [Brief explanation of the drawings]

[0032] [Figure 1] FIG. 1 illustrates an example of a qubit array architecture. [Figure 2] FIG. 10 illustrates an example architecture of a qubit array having isolation between qubits and corresponding readout resonators, consistent with an example embodiment. [Figure 3] FIG. 10 illustrates an example architecture of a qubit array having isolation between different types of components, consistent with example embodiments. [Figure 4]FIG. 1 illustrates an example of a three-dimensional multiplexing architecture, consistent with an exemplary embodiment. [Figure 5] FIG. 1 illustrates a three-dimensional multiplexing architecture without symmetry between different layers. [Figure 6] FIG. 7 illustrates an example switch that may be used to implement the switches of FIGS. 2-6, consistent with an example embodiment. [Figure 7] FIG. 1B is a top view of a switch that can be used to provide isolation between two qubits and / or isolation between a qubit and a readout resonator, consistent with an example embodiment. [Figure 8] 1 is a cross-sectional side view of a semiconductor structure that may be used as a Josephson junction switch, consistent with an illustrative embodiment. [Figure 9] 1 is a cross-sectional side view of a quantum well heterostructure used as a JJ switch, consistent with an example embodiment. [Figure 10] 1 is a cross-sectional side view of a Josephson junction switch having an epitaxial superconductor structure on a barrier, consistent with an example embodiment. [Figure 11] 1 is a cross-sectional side view of a Josephson junction switch in which a superconductor structure is built directly on a semiconductor substrate, consistent with an illustrative embodiment. [Figure 12] FIG. 1 provides a cross-sectional side view of a Josephson junction switch having a graphene layer deposited on an insulating substrate between two superconductor structures. DETAILED DESCRIPTION OF THE INVENTION

[0033] Overview In the following detailed description, numerous specific details are set forth by way of example to provide a thorough understanding of the relevant teachings. However, it will be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, or circuits, or combinations thereof, have been described relatively broadly and without detailed description in order to avoid unnecessarily obscuring aspects of the present teachings.

[0034] The present disclosure relates generally to superconducting devices, and more specifically to the integration of control logic within and between quantum arrays. Electromagnetic energy associated with a qubit can be stored in so-called Josephson junctions (JJs) and in the capacitive and inductive elements used to form the qubit. In one example, to read out the state of a qubit, a microwave signal is applied to a microwave readout cavity coupled to the qubit at a cavity frequency, sometimes referred to herein as the qubit frequency. The transmitted (or reflected) microwave signal passes through multiple thermal isolation stages and low-noise amplifiers used to block or reduce noise and improve the signal-to-noise ratio. The amplitude and / or phase of the returned / output microwave signal conveys information about the state of the qubit, such as whether the qubit has dephased to its ground state or to an excited state. The microwave signal conveying quantum information about the qubit's state is typically weak (e.g., on the order of a few microwave photons). To measure this weak signal, low-noise quantum-limited amplifiers (QLAs), such as Josephson amplifiers or traveling-wave parametric amplifiers (TWPAs), can be used as preamplifiers (i.e., first stage amplifiers) at the output of the quantum system to boost the quantum signal while adding a minimum amount of noise dictated by quantum mechanics to improve the signal-to-noise ratio of the output chain. In addition to Josephson amplifiers, certain Josephson microwave components using Josephson amplifiers or Josephson mixers, such as Josephson circulators, Josephson isolators, and Josephson mixers, can be used in scalable quantum processors.

[0035] The ability to incorporate more qubits is crucial to realizing the potential of quantum computers. Improving the computational power and reliability of quantum computers requires improvements in two key areas. First, the number of qubits themselves. The more qubits a quantum processor has, the more states it can manipulate and store. Second, low error rates are required, which are related to accurately manipulating the qubit states and executing a sequence of operations that provides a consistent result, rather than simply unreliable data. Therefore, to improve the fault tolerance of quantum computers, logical qubits should be stored using a large number of physical qubits. Delocalizing local information in this way makes quantum computers less susceptible to local errors, improving the ability to measure eigenbasis qubits, similar to parity checks in classical computers, and enabling the evolution of more fault-tolerant qubits.

[0036] Quantum error-correcting codes, in principle, enable reliable large-scale quantum computing. Codes such as surface codes are currently favored because they can be implemented with two-dimensional arrays of qubits, each constrained to interact only with neighboring qubits. This constraint means that each logical qubit is encoded into a patch of physical qubits, and the diameter of the patch must increase as error-correction capabilities increase. In this case, hundreds or even thousands of physical qubits may be used for each logical qubit. In one embodiment, the proposed architecture relaxes this constraint, allowing a small number of physically separated qubits to interact. In such systems, described by graphs of small, constant degree, interactions, a family of more efficient quantum error-correcting codes can be implemented. For example, quantum expander codes can encode many logical qubits into the same code block of a high-rate code, resulting in overhead that asymptotically approaches a small constant.

[0037] Reference is now made to FIG. 1 , which illustrates an example of a qubit array architecture. For example, qubit array 100 may be based on a surface code architecture in which qubits, represented by circles in FIG. 1 , are arranged on a planar two-dimensional (2D) grid, sometimes referred to herein as a lattice. By way of example and not limitation, the qubit array is a lattice of nine qubits arranged as a 3×3, although it will be understood that other sizes and configurations are supported by the teachings herein. Each of qubits 102(1) through 102(9) communicates using a coplanar waveguide (CPW) resonator (sometimes referred to herein as a bus resonator), represented by solid lines in FIG. 1 . Each pair of qubits (e.g., 116) is coupled via capacitive coupling. These bus resonators may be used to entangle two or more qubits, such as qubit pair 116.

[0038] The states of the qubits are measured using resonant readout lines, sometimes referred to herein as readout resonators, represented by dashed lines in Figure 1. In one embodiment, the readout resonators are CPWs. These readout resonators are used to determine the states of the corresponding qubits.

[0039] As previously mentioned, to maintain the signal integrity of each qubit, it would be beneficial for each qubit 102(1) through 102(9) in the lattice to have a different qubit frequency. For example, qubit 102(1) could have a qubit frequency of 5 GHz, qubit 102(2) could have a qubit frequency of 5.5 GHz, qubit 102(3) could have a qubit frequency of 5.7 GHz, and so on. In this way, the unentangled state of each individual qubit can be easily achieved, and frequency collisions between qubits, such as qubit 116, can be avoided. Without different qubit frequencies, microwave crosstalk between two qubits (e.g., qubit pair 116) could experience frequency collisions and degrade the performance of the quantum computer. However, today's manufacturing processes may not be able to achieve sufficient control of the qubit frequency of each individual qubit 102(1) through 102(9) in qubit array 100.

[0040] Thus, the teachings herein enable tuning of qubits in a qubit array to have substantially similar qubit frequencies while providing isolation between the qubits, thereby reducing sensitivity to semiconductor process capabilities in controlling qubit frequency. Because the qubits in the array are decoupled from each other, frequency collisions can be avoided and microwave crosstalk can be significantly reduced. The teachings herein allow the qubits in the array to remain entangled despite having substantially similar qubit frequencies. Furthermore, qubit coherence times are improved.

[0041] Exemplary Hybrid Quantum Architecture FIG. 2 is an exemplary architecture 200 of a qubit array with isolation between qubits and corresponding readout resonators, consistent with an exemplary embodiment. Architecture 200 has similar features to those described with respect to the architecture of FIG. 1 and, therefore, will not be repeated here for brevity. By way of example only and not by way of limitation, qubit array 202(1) through 202(9) of FIG. 2 is a lattice comprising nine interconnected qubits. Each of the qubits is coupled by a bus resonator, represented by a solid line. In contrast to FIG. 1, architecture 200 of FIG. 2 includes switches (e.g., 208(1) through 208(8)) located between the corresponding qubits (e.g., 202(1) through 202(9)), and readout lines, sometimes referred to herein as readout resonators, represented by dashed lines.

[0042] For example, to access qubit 202(1), switch 208(1) may be activated by an appropriate signal (e.g., a predetermined voltage), while the remaining switches 208(2) through 208(8) are not activated. In this manner, a single readout line may be used to access all qubits in the array through their respective switches, thereby mitigating microwave crosstalk even if the frequencies of one or more qubits in the qubit array are substantially similar. In one embodiment, there is a readout resonator (not shown) for central qubit 202(5), which may be accessed, for example, with bump bonding techniques. Thus, some readout resonators, such as the central qubit 202(5) readout resonator, may be on substantially separate layers.

[0043] Reference is now made to FIG. 3 , which is an exemplary architecture 300 of a qubit array having isolation between different types of components, consistent with illustrative embodiments. Architecture 300 has similar features to those described in the context of FIGS. 1 and 2 and, therefore, will not be repeated here for brevity. Architecture 300 includes switches between pairs of qubits, represented in FIG. 3 as hollow boxes 302(1) through 302(12). For example, qubits 202(1) and 202(2) are separated by switch 302(1). Although architecture 300 is depicted with JJ switches (i.e., solid black boxes) between the readout resonator and the qubits, in various embodiments, JJ switches 302(1) through 302(12) can also be found in architectures without JJ switches between the readout resonator and qubits 202(1) through 202(9). In some embodiments, the switches between qubits (302(1) through 302(12)) and / or the switches between qubits (i.e., represented as solid black boxes in FIG. 3 ) and the readout resonator are Josephson junctions (JJs). The combinations of switches in architecture 300 provide multiplexing of corresponding qubits 202(1) through 202(9). For example, input / output (I / O) lines can be split and distributed among many I / O lines to create a tree structure. The switches can open and close access to various lines, enabling or disabling control of the qubits. Thus, due to multiplexing, a combination of switches can be used to excite a particular qubit without interference from neighboring qubits, even if the qubits have substantially similar frequencies.

[0044] The teachings herein are not limited to two-dimensional configurations. Indeed, the quantum architectures described herein are also applicable to multi-layer architectures. In this regard, FIG. 4 illustrates an exemplary three-dimensional (3D) multiplexing architecture 400 consistent with exemplary embodiments. In the example of FIG. 4, there is symmetry not only within each array in a layer, but also between layers. For example, each layer may include multiple qubit arrays, such as 401(1) through 401(3) in layer 1 of FIG. 4. Each qubit array may include (e.g., JJ) switches between readout resonators, qubits, or both. Each of these qubit arrays 401(1) through 401(3) is aligned and equidistant from one another. Layers 2 and 3 of FIG. 4 include substantially similar, symmetric layers stacked on top of one another. In some embodiments, there may be separate patches for each qubit array, or all qubit arrays may be coupled by switches for full multiplexing (not shown). The teachings herein enable symmetric 3D qubit arrays to be realized with multiplexed readout, protecting each qubit from external noise as well as between qubits, even when at least some of the qubits have substantially similar qubit frequencies.

[0045] It should be noted that in various embodiments, there need not be symmetry within or between layers. In this regard, FIG. 5 illustrates a 3D multiplexing architecture 500 in which there is no symmetry between different layers. For example, as shown between layer 1 and layer 2 in FIG. 5, each layer may have a unique arrangement and / or a different number of qubit arrays. Layer 1 has two qubit arrays 501(1) and 501(2), while layer 2 has three qubit arrays 502(1), 502(2), and 502(3). Furthermore, there need not even be symmetry between qubit arrays on a common layer, as shown by qubit arrays 503(1) through 503(3) in layer 3 in FIG. 5. Furthermore, although each qubit array 501(1) through 503(3) is shown as having a common lattice (e.g., 3 × 3), the lattice may differ between or even within layers. Thus, the teachings herein support asymmetric multi-layer qubit architectures not only between layers but also within each layer. In one embodiment, multiple layer qubit arrays are stacked by bump bonding methods.

[0046] Architectures 200 through 500 provide increased coherence times (e.g., quantum state survival) even when the qubit frequencies of one or more qubits are substantially similar. Furthermore, the multiplexing architecture with strategically placed switches described herein can block qubits with unwanted transition frequencies, thereby avoiding crosstalk arising therefrom. In one example, malfunctioning or simply undesirable qubits can be blocked by a combination of switches described herein.

[0047] Example Switch FIG. 6 illustrates an exemplary switch that can be used to implement the switches of FIGS. 2 through 5 consistent with exemplary embodiments. For example, in FIG. 2, switch 600 can be used to implement switches 208(1) through 208(8). According to another example, in FIG. 3, switch 600 can be used to implement switches 302(1) through 302(12). Switch 600 of FIG. 6 is in the form of a gate-voltage-controlled switch integrated with a coupled resonator. Switch 600 includes a gate 606 that overlaps two superconductor structures 608 and 610. When an appropriate voltage is applied to gate 606, a gate-tunable electronic system 604 creates a path between the two superconductor structures 608 and 610. In one embodiment, switch 600 is a Josephson junction (JJ) and includes two or more superconductors (e.g., 608 and 610) coupled by a weak link provided by gate-tunable electronic system 604. In various configurations, the weak link in the gate-tunable electronic system 604 can comprise a short section of non-superconducting metal (SNS) or a physical constriction (SSS) that weakens the superconductivity at the contact point. In one embodiment, the switch 600 has a tunable Josephson inductance, thereby providing a tunable JJ.

[0048] Reference is now made to FIG. 7 , which illustrates a top view of a switch 700 with additional details consistent with an exemplary embodiment. In the example of FIG. 7 , switch 700 includes a gate 710 overlying two superconductor structures 712 and 714. Switch 700 can be a JJ substantially surrounded by a ground plane 702. Structure 704 illustrates a top view of a portion of a coplanar waveguide bus. The coplanar waveguide comprises a ground plane and a center conductor. The portion of the waveguide illustrated in FIG. 7 comprises a JJ switch. In the example of FIG. 7 , the gate-tunable electronic system, outlined by the dotted line 704, forms a “T” shape, intended to use a portion of the electronic system as a connection to ground. In various embodiments, the notch in the ground plane is not strictly necessary, and other shapes can be used. The notch indicates the portion of the electronic system that forms a contact with ground. Each superconducting structure 712 and 714 leads to a corresponding qubit.

[0049] Thus, a portion of the gate-tunable electronic system 704 (e.g., semiconductor, graphene, etc.) in the gate portion 710 interrupts the superconducting resonator circuit at a critical point to form a switch. In various embodiments, the critical point may include between pairs of qubits, between the qubit and the readout resonator, or both. For example, a voltage applied to the (e.g., metallic) gate 710 tunes the JJ switch to switch between a low-inductance state with a high critical current (≈1-10 μA) and a high-inductance state with a low critical current (≈10 nA).

[0050] The switches described herein achieve fast switching times through tunable strong ZZ coupling. By way of example and not limitation, with a switch resistance of approximately 1 KΩ and a capacitance of 1 pF, a switching time of 1 ns can be achieved.

[0051] In one embodiment, the switches described herein are voltage-controlled superconducting current switches. In contrast, flux-controlled switches rely on current. The use of current can lead to increased crosstalk on the qubit chip, increased heat load on the cryostat, and / or require significantly increased overhead in terms of the structures (such as wire coils) needed to generate the magnetic flux. The use of voltage-controlled superconducting current switches avoids these problems associated with flux-based approaches.

[0052] In conjunction with the foregoing description of key switch locations and top-down views of switches, it may be useful to provide a general discussion of cross sections of example switches. To that end, FIGS. 8 through 12 provide different cross-sectional side views of various example switches that may be used to implement the JJ switches described herein. More specifically, FIG. 8 is a cross-sectional side view of a semiconductor structure that may be used as a JJ switch, consistent with example embodiments. Semiconductor structure 800 includes an insulating substrate 802. Deposited on insulating substrate 802 is a semiconductor 820 separating two superconductors. In one embodiment, semiconductor 820, sometimes referred to herein as an electron system, is indium arsenide (InAs).

[0053] FIG. 9 is a cross-sectional side view of a quantum well heterostructure used as a JJ switch, consistent with an illustrative embodiment. In one embodiment, semiconductor structure 900 includes a quantum well 920 constructed of InAs and barriers 910, 930 constructed of InGaAs. Barrier 910 separates two superconductor structures deposited on quantum well 920. The use of quantum well 920 can achieve high mobility, thereby allowing many electrons to be transported between the superconductor elements. In other embodiments, other semiconductors can be used. For example, the semiconductor structure can be constructed from a layer 920 of germanium (Ge) sandwiched between barriers 910, 930 comprising silicon germanium (SiGe).

[0054] 10 is a cross-sectional side view of a JJ switch having an epitaxial superconductor structure 1040 on a barrier 1010, consistent with an example embodiment. There is a first barrier layer 1030. A quantum well 1020 is constructed on top of the barrier layer 1010. There are two epitaxial superconductor segments 1040 separated by an insulator 1050.

[0055] In one embodiment, the quantum well 1020 of the semiconductor structure 1000 is constructed of InAs and the barriers 1030, 1030 are constructed of InGaAs. There is a barrier 910 separating the two superconductor structures deposited on top of the quantum well 920. For example, the semiconductor quantum well layer 1020 may be constructed of germanium (Ge) and the barriers 1010, 1030 include silicon germanium (SiGe).

[0056] Reference is now made to FIG. 11 , which is a cross-sectional side view of a JJ switch 1100 in which a superconductor structure 1110 is built directly on a semiconductor substrate 1130, consistent with an exemplary embodiment. For example, such a JJ switch 1100 may be implemented to simplify semiconductor processes and reduce costs in fabricating the switch. In one embodiment, a graphene layer may be used to further improve the performance of the JJ switch. In this regard, FIG. 12 provides a cross-sectional side view of a JJ switch having a graphene layer 1210 between two superconductor structures 1220 deposited on an insulating substrate 1230.

[0057] conclusion The description of various embodiments of the present teachings has been presented for purposes of illustration and is not intended to be exhaustive or to limit the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best describe the principles of the embodiments, practical applications or technical improvements found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0058] While the foregoing describes what is considered to be the best mode and / or other examples, it will be understood that various modifications may be made thereto, that the subject matter disclosed herein may be embodied in various forms and examples, and that the present teachings may be applied to numerous applications, only a few of which are described herein. It is intended by the following claims to claim any and all applications, modifications, and variations that fall within the true scope of the present teachings.

[0059] The components, steps, features, objects, benefits, and advantages described herein are merely exemplary. Neither they nor the discussion associated therewith are intended to limit the scope of protection. While various advantages have been described herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise specified, all dimensions, numbers, ratings, positions, sizes, and other specifications described herein, including the claims that follow, are approximate and not precise. They are intended to have a reasonable range consistent with the function to which they relate and practice in the technical field to which they pertain.

[0060] Numerous other embodiments are contemplated, including embodiments with fewer, additional, or different or combinations of components, steps, features, objects, benefits, and advantages, as well as embodiments with different arrangements and / or orderings of components and / or steps.

[0061] While the foregoing has been described in connection with exemplary embodiments, it should be understood that the term "exemplary" is meant merely as an example, not as best or optimal. Except as noted immediately above, nothing described or illustrated is intended to, and should be construed as, dedicating to the public any element, step, feature, object, benefit, advantage, or equivalent, whether claimed or not.

[0062] Terms and phrases used herein shall be understood to have the ordinary meanings ascribed to them in relation to their respective fields of study and research, unless otherwise specified herein. Relative terms such as "first," "second," and the like are used solely to distinguish one entity or act from another and do not necessarily require or imply an actual relationship or sequence between such entities or acts. The terms "comprise," "comprising," or other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or device having a list of elements does not include only those elements, but may include other elements not expressly listed or elements inherent in the process, method, article, or device. The use of an element preceded by "a" or "an" does not, without further constraints, exclude the presence of additional identical elements in a process, method, article, or device that includes that element.

[0063] The Abstract of the Disclosure is provided to enable the reader to quickly grasp the nature of the technical disclosure. It is submitted with the understanding that it will not be used to limit the interpretation or meaning of the claims. In addition, in the foregoing Detailed Description, various features may be found grouped together in various embodiments for the purpose of facilitating disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Accordingly, the following claims stand on their own as separately claimed subject matter and are incorporated into the Detailed Description. The present disclosure also discloses the following inventions: <Appendix 1> A quantum system comprising: a qubit array including a plurality of qubits; a bus resonator coupled between at least one pair of qubits in the qubit array; a switch coupled between the at least one pair of qubits; A quantum system comprising: <Appendix 2> the switch comprises coupled resonators having Josephson junctions (JJs); 2. The quantum system of claim 1, wherein the switch is integrated with the bus resonator. <Appendix 3> 3. The quantum system of any one of claims 1 to 2, wherein the switch comprises a gate coupled to an electronic system, the electronic system being tunable by a voltage on the gate. <Appendix 4> 4. The quantum system of claim 3, wherein the electronic system is configured to change inductance based on a voltage on the gate. <Appendix 5> 5. The quantum system of any one of claims 3-4, wherein the gate is configured to adjust the switch between (i) a low-inductance state having a first critical current and (ii) a high-inductance state having a second critical current, the second critical current being lower than the first critical current. <Appendix 6> the switch has a first state that supports a superconducting current; 6. The quantum system of any one of claims 1 to 5, wherein the first switch has a second state that is high resistance and supports no supercurrent. <Appendix 7> 7. The quantum system of any one of claims 3 to 6, wherein the voltage on the gate acts to change the inductance of the JJ. <Appendix 8> 8. The quantum system of any one of claims 3 to 7, wherein the switch comprises two or more superconductors separated by the electronic system. <Appendix 9> 9. The quantum system of any one of claims 3 to 8, wherein the electronic system comprises graphene. <Appendix 10> 10. A quantum system according to any one of claims 1 to 9, wherein the switch is a voltage-controlled superconducting current switch. <Appendix 11> 11. The quantum system of any one of claims 1 to 10, further comprising, for at least one qubit of the qubit array, a switch coupled between the at least one qubit and a readout resonator of the qubit array. <Appendix 12> 12. The quantum system of claim 11, wherein the combination of qubit pairs and switches between qubits and readout resonators is configured to multiplex individual qubits in the array such that each qubit is individually controlled and independent of qubit frequency. <Appendix 13> the qubit array is part of a plurality of qubit arrays in a first layer; 13. The quantum system of any one of claims 1 to 12, wherein the plurality of qubit arrays in the first layer are each separated by one or more switches. <Appendix 14> 14. The quantum system of any one of claims 1 to 13, wherein there is an asymmetry in the quantum bit array between at least two of the plurality of layers. <Appendix 15> 15. The quantum system of any one of claims 1 to 14, wherein the quantum system comprises multiple layers, each layer comprising at least one qubit array separated from an adjacent layer by one or more switches. <Appendix 16> 16. The quantum system of any one of claims 1 to 15, wherein two or more qubits in the qubit array have substantially similar qubit frequencies. <Appendix 17> 17. The quantum system of any one of claims 1 to 16, wherein the multiple layers are stacked together by bump bonding. <Appendix 18> 1. A method of controlling a quantum system, said method comprising: providing a qubit array having a plurality of qubits; coupling a bus resonator between each pair of qubits in the qubit array; and isolating at least one qubit pair of the qubit array by a Josephson junction (JJ) switch; or isolating at least one qubit of the qubit array from a readout resonator with a second JJ switch. with at least one of A method comprising: <Appendix 19> 19. The method of claim 18, further comprising changing the inductance of an electronic system of a gate of the JJ switch by applying a voltage to the gate. <Appendix 20> 20. The method of any one of claims 18-19, further comprising separating two or more superconductors by the electronic system of the JJ switch. <Appendix 21> 21. The method of any one of claims 18-20, further comprising multiplexing individual qubits with a plurality of switches, including the JJ switch and the second JJ switch in the array, such that each qubit is individually controlled and independent of qubit frequency. <Appendix 22> stacking multiple qubit arrays on multiple layers; controlling each qubit in the plurality of layers individually and independently of the qubit frequency by a plurality of switches; 22. The method of any one of claims 18 to 21, further comprising: <Appendix 23> A quantum system comprising: a qubit array comprising a plurality of qubits; a bus resonator coupled between each pair of adjacent qubits in the qubit array; a switch coupled between each pair of qubits in the qubit array; or for at least one qubit of the qubit array, a switch between the at least one qubit and a readout resonator of the qubit array; with at least one of A quantum system comprising: <Appendix 24> the switch is integrated with a coupled resonator having a Josephson junction (JJ); each switch having a gate coupled to an electronic system, the electronic system being adjustable by a voltage on the gate; 24. The quantum system of claim 23, wherein the electronic system is configured to vary the inductance of the JJ based on a voltage on the gate. <Appendix 25> 25. The quantum system of any one of claims 23-24, wherein a combination of qubit pairs and switches between qubits and readout resonators are configured to multiplex individual qubits in the array such that each qubit is individually controlled and independent of qubit frequency.

Claims

1. 1. A method of controlling a quantum system, said method comprising: providing a qubit array having a plurality of qubits; coupling a bus resonator between each pair of qubits of the qubit array; isolating at least one pair of qubits in the qubit array with a first Josephson junction (JJ) switch; or and isolating at least one qubit of the qubit array from a readout resonator with a second JJ switch. and at least one of applying a voltage to a gate of the first JJ switch or the second JJ switch to change the inductance of an electronic system provided below the gate; A method comprising:

2. The method of claim 1 , further comprising separating two or more superconductors by the electronic system.

3. 3. The method of claim 1, further comprising multiplexing individual qubits with a plurality of switches, including the first JJ switch and the second JJ switch, in the qubit array such that each qubit is individually controlled and independent of qubit frequency.

4. stacking a plurality of qubit arrays on a plurality of layers; controlling each qubit in the plurality of layers individually and independently of the qubit frequency by a plurality of switches; The method of any one of claims 1 to 3, further comprising:

5. A quantum system comprising: a qubit array comprising a plurality of qubits; a bus resonator coupled between each pair of adjacent qubits in the qubit array; a first switch integrated with the bus resonator; or for at least one qubit of the qubit array, a second switch between the at least one qubit and a readout resonator of the qubit array. wherein the at least one of the first JJ switch or the second JJ switch comprises a gate and an electronic system provided below the gate, the electronic system being configured to change an inductance by applying a voltage to the gate. A quantum system comprising:

6. 6. The quantum system of claim 5, wherein the electronic system is tunable by a voltage on the gate.

7. 7. The quantum system of claim 6, wherein the combination of the first switch and the second switch is configured to multiplex individual qubits in the qubit array such that each qubit is individually controlled and independent of qubit frequency.

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