Semiconductor package including semiconductor chip including rear surface structure

Abstract

To provide a semiconductor package including a semiconductor chip including a rear surface structure, in which the generation of voids in an adhesive layer between conductor chips is prevented and the collapse of a bump structure at the lamination of the semiconductor chips is prevented.SOLUTION: A semiconductor package 10 includes a first semiconductor chip 100A, a second semiconductor chip 100B, and a plurality of bump structures 140 between the first semiconductor chip and the second semiconductor chip, and an adhesive layer 180. The first semiconductor chip includes a substrate 110 having a front surface and a rear surface, a rear surface protection layer 155 on the rear surface, a plurality of rear surface pads 160 on the rear surface protection layer, and a rear surface structure 170 between two rear surface pads among the rear surface pads. The second semiconductor chip includes first and second pad regions, and a test pad region between the first pad region and the second pad region. The first pad region includes a plurality of first front surface pads, and the second pad region includes a plurality of second front surface pads. The test pad region includes a test pad.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor package that includes a semiconductor chip that includes a backside structure. [Background technology]

[0002] As demands for higher performance, higher speed, and / or more functionality of semiconductor devices increase, the integration level of semiconductor devices is also increasing. In order to manufacture semiconductor devices with fine patterns that meet the trend toward higher integration of semiconductor devices, it is necessary to realize patterns with fine widths or fine separation distances. In addition, there is a demand for higher integration of semiconductor devices mounted in semiconductor packages. Summary of the Invention [Problem to be solved by the invention]

[0003] One of the technical problems to be solved by the technical concept of the present invention is to provide a semiconductor package including a semiconductor chip having a structure on its rear surface. [Means for solving the problem]

[0004] A semiconductor package according to an exemplary embodiment may include: a first semiconductor chip including a substrate having opposing front and rear surfaces, a rear protective layer on the rear surface, a plurality of rear pads on the rear protective layer, and at least one rear structure between the rear pads; a second semiconductor chip disposed on the first semiconductor chip and including a first pad area, a second pad area, and a test pad area between the first pad area and the second pad area; a plurality of bump structures disposed between the first semiconductor chip and the second semiconductor chip and connected to the rear pads of the first semiconductor chip; and an adhesive layer surrounding the bump structures between the first semiconductor chip and the second semiconductor chip. The first pad area may include a plurality of first front pads, the second pad area may include a plurality of second front pads, and the test pad area may include a test pad. The first front pads may be spaced apart at a first pitch, and a minimum distance between the first front pads and the second front pads may be greater than the first pitch. At least a portion of the at least one rear structure may vertically overlap the test pad.

[0005] A semiconductor package according to an exemplary embodiment may include: a first semiconductor chip including a substrate having opposing front and rear surfaces, a rear protective layer disposed on the rear surface of the substrate, a plurality of rear pads on the rear protective layer, and at least one rear structure between the rear pads; a second semiconductor chip disposed on the first semiconductor chip and including a plurality of front pads electrically connected to the rear pads and a test pad between the front pads; a plurality of bump structures disposed between the rear pads of the first semiconductor chip and the front pads of the second semiconductor chip; and an adhesive layer surrounding the bump structures between the first and second semiconductor chips. The bump structures may include a first bump structure, a second bump structure, and a third bump structure spaced apart from each other in a first horizontal direction. The center of the first bump structure and the center of the second bump structure may be spaced apart by a first distance along the first horizontal direction, and the center of the second bump structure may be spaced apart by a second distance along the first horizontal direction from the center of the third bump structure, the second distance being greater than the first distance. The test pad may be disposed between the second bump structure and the third bump structure. At least a portion of the at least one rear structure may vertically overlap the test pad.

[0006] A semiconductor package according to an exemplary embodiment may include a plurality of vertically stacked semiconductor chips, a plurality of bump structures electrically connecting the semiconductor chips between the plurality of semiconductor chips, a plurality of adhesive layers surrounding the bump structures between the plurality of semiconductor chips, and an encapsulant covering the plurality of semiconductor chips and the plurality of adhesive layers. The plurality of semiconductor chips may include a first semiconductor chip including a substrate having front and rear surfaces facing each other, a rear protective layer on the rear surface, a plurality of rear pads on the rear protective layer, and at least one rear structure between the plurality of rear pads; and a second semiconductor chip disposed on the first semiconductor chip and including a first pad area, a second pad area, and a test pad area between the first pad area and the second pad area. The first pad area may include a plurality of first front pads, the second pad area may include a plurality of second front pads, and the test pad area may include a test pad. The plurality of first front pads may be spaced apart at a first pitch, and a minimum distance between the plurality of first front pads and the plurality of second front pads may be greater than the first pitch. At least a portion of the at least one rear structure may vertically overlap the test pad. [Effects of the Invention]

[0007] According to an embodiment of the technical concept of the present invention, in a structure in which semiconductor chips are stacked, a rear structure is disposed on the top surface of the semiconductor chip, which can prevent voids from occurring in an adhesive layer between the semiconductor chips and can prevent the bump structure from collapsing when the semiconductor chips are stacked.

[0008] The various yet significant advantages and effects of the present invention are not limited to the above, but can be more easily understood in the course of describing specific embodiments of the present invention. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a side cross-sectional view of a semiconductor package according to an exemplary embodiment. [Figure 2] FIG. 2 is a plan view of the semiconductor chip shown in FIG. [Figure 3] FIG. 3 is a partially enlarged view of the semiconductor chip shown in FIG. 2. [Figure 4] FIG. 2 is a plan view of the semiconductor chip shown in FIG. [Figure 5] 4 is a vertical cross-sectional view of the semiconductor chip shown in FIG. 3 taken along line II'. [Figure 6] 1 is a plan view of a semiconductor chip according to an exemplary embodiment; [Figure 7] 1 is a plan view of a semiconductor chip according to an exemplary embodiment; [Figure 8] 1 is a plan view of a semiconductor chip according to an exemplary embodiment; [Figure 9] 1 is a plan view of a semiconductor chip according to an exemplary embodiment; [Figure 10] 1 is a side cross-sectional view of a semiconductor package according to an exemplary embodiment. [Figure 11] 1 is a side cross-sectional view of a semiconductor package according to an exemplary embodiment. [Figure 12] 1 is a side cross-sectional view of a semiconductor package according to an exemplary embodiment. [Figure 13a] 1A to 1C are cross-sectional views illustrating major steps of a method for manufacturing a semiconductor package according to an exemplary embodiment. [Figure 13b] 1A to 1C are cross-sectional views illustrating major steps of a method for manufacturing a semiconductor package according to an exemplary embodiment. [Figure 13c] 1A to 1C are cross-sectional views illustrating major steps of a method for manufacturing a semiconductor package according to an exemplary embodiment. [Figure 13d] 1A to 1C are cross-sectional views illustrating major steps of a method for manufacturing a semiconductor package according to an exemplary embodiment. [Figure 13e] 1A to 1C are cross-sectional views illustrating major steps of a method for manufacturing a semiconductor package according to an exemplary embodiment. [Figure 13f] 1A to 1C are cross-sectional views illustrating major steps of a method for manufacturing a semiconductor package according to an exemplary embodiment. [Figure 14] 1 is a side cross-sectional view of a semiconductor package according to an exemplary embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[0011] FIG. 1 is a side cross-sectional view of a semiconductor package according to an exemplary embodiment.

[0012] Referring to FIG. 1, a semiconductor package 10 according to an embodiment of the present disclosure may include a first semiconductor chip 100A, a chip structure CS, an adhesive layer 180, an encapsulant 190, and connection terminals 192.

[0013] The chip structure CS may be disposed on the first semiconductor chip 100A. The chip structure CS may include multiple semiconductor chips, for example, a second semiconductor chip 100B, a third semiconductor chip 100C, a fourth semiconductor chip 100D, and a fifth semiconductor chip 100E. The first to fifth semiconductor chips 100A, 100B, 100C, 100D, and 100E may have similar structures. In FIG. 1, the second semiconductor chip 100B, the third semiconductor chip 100C, the fourth semiconductor chip 100D, and the fifth semiconductor chip 100E are illustrated as having the same width in the horizontal direction (e.g., the X direction), and the horizontal width of the first semiconductor chip 100A is larger than the horizontal width of the second semiconductor chip 100B, but this is not limiting. In one embodiment, the horizontal width of first semiconductor chip 100A may be the same as the horizontal widths of second semiconductor chip 100B, third semiconductor chip 100C, fourth semiconductor chip 100D, and fifth semiconductor chip 100E.

[0014] In embodiments, the chip structure CS may include more or fewer semiconductor chips than those shown in the drawings. For example, the chip structure CS may include three or fewer semiconductor chips or five or more semiconductor chips. In embodiments, a heat dissipation structure may be disposed on top of the chip structure CS. The heat dissipation structure (not shown) may include a material with excellent thermal conductivity, such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), iron (Fe), graphite, graphene, etc.

[0015] In one embodiment, the first semiconductor chip 100A may be a buffer chip or a control chip including a plurality of logic elements and / or memory elements. The first semiconductor chip 100A transmits signals from the second to fifth semiconductor chips 100B, 100C, 100D, and 100E stacked thereon to the outside, and can also transmit signals and power from the outside to the second to fifth semiconductor chips 100B, 100C, 100D, and 100E. The second to fifth semiconductor chips 100B, 100C, 100D, and 100E may be memory chips including volatile memory elements such as DRAM and SRAM, or non-volatile memory elements such as PRAM, MRAM, FeRAM, or RRAM. The semiconductor package 10 of this embodiment may be used in high-bandwidth memory (HBM) products or electronic data processing (EDP) products.

[0016] The semiconductor package 10 may further include bump structures 140 (e.g., chip connection terminals or bump terminals) disposed between the semiconductor chips 100A, 100B, 100C, 100D, and 100E. The bump structures 140 and the through vias 150 may electrically connect the semiconductor chips 100A, 100B, 100C, 100D, and 100E to each other.

[0017] The adhesive layer 180 may be disposed between the semiconductor chips 100A, 100B, 100C, 100D, and 100E and may surround the bump structures 140. Portions of the adhesive layer 180 may protrude horizontally from the side surfaces of the semiconductor chips 100A, 100B, 100C, 100D, and 100E.

[0018] The encapsulant 190 is disposed on the first semiconductor chip 100A and can encapsulate at least a portion of each of the second to fifth semiconductor chips 100B, 100C, 100D, and 100E. The encapsulant 190 can be formed to expose the top surface of the fifth semiconductor chip 100E. In one embodiment, the encapsulant 190 can be formed to cover the top surface of the fifth semiconductor chip 100E. The encapsulant 190 can include a resin such as epoxy or polyimide. For example, the resin can include bisphenol-group epoxy resin, polycyclic aromatic epoxy resin, o-cresol novolac epoxy resin, biphenyl-group epoxy resin, or naphthalene-group epoxy resin.

[0019] The connection terminals 192 may be disposed on the lower surface of the substrate 110 of the first semiconductor chip 100A. The connection terminals 192 may be electrically connected to the circuit layer 120 of the substrate 110 of the first semiconductor chip 100A. The connection terminals 192 may be electrically connected to an external device such as a main board. The connection terminals 192 may include a conductive material and may have the form of a ball, pin, or lead. For example, the connection terminals 192 may be external connection terminals such as solder balls for connecting the semiconductor package 10 to an external element.

[0020] FIG. 2 is a plan view of the semiconductor chip shown in FIG. 1. For example, FIG. 2 may be a plan view of the front surface FS of the second semiconductor chip 100B viewed from below. FIG. 3 is an enlarged view of a portion of the semiconductor chip shown in FIG. 2. For example, FIG. 3 may correspond to region A shown in FIG. 2. FIG. 4 is a plan view of the semiconductor chip shown in FIG. 1. For example, FIG. 4 may be a plan view of the rear surface BS of the first semiconductor chip 100A viewed from above. For convenience of explanation, the positions of the test pads 135 of the second semiconductor chip 100B are indicated by dotted lines in FIG. 4. FIG. 5 is a vertical cross-sectional view of the semiconductor chip shown in FIG. 3 taken along line I-I'.

[0021] 2 to 5, each of the semiconductor chips 100A, 100B, 100C, 100D, and 100E may include a substrate 110, a circuit layer 120, front pads 130, test pads 135, through vias 150, a rear protective layer 155, rear pads 160, and a rear structure 170. In an embodiment, the through vias 150, the rear protective layer 155, the rear pads 160, and the rear structure 170 may be omitted from the semiconductor chip at the top of the chip structure CS, for example, the fifth semiconductor chip 100E. The first pad region PR may include a first front pad among the front pads 130, and the second pad region PR may include a second front pad among the front pads 130. The test pads 135 may be included in the test region TR.

[0022] The substrate 110 may be a semiconductor wafer substrate having a front surface FS and a back surface BS facing each other. For example, the substrate 110 may be a semiconductor wafer including a semiconductor element such as silicon or germanium, or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The front surface FS may be an active surface having an active region doped with impurities, and the back surface BS may be an inactive surface disposed opposite the front surface FS.

[0023] The circuit layer 120 is disposed on the front surface FS of the substrate 110 and may include a wiring structure 125 connected to the active region and an interlayer insulating layer 121 surrounding the wiring structure 125. The interlayer insulating layer 121 may include flowable oxide (FOX), tonen silazane (TOSZ), undoped silica glass (USG), borosilica glass (BSG), phosphosilica glass (PSG), borophosphosilica glass (BPSG), plasma enhanced tetra ethyl orthosilicate (PETEOS), fluoride silicate glass (FSG), high density plasma (HDP) oxide, plasma enhanced oxide (PEOX), flowable chemical vapor deposition (FCVD) oxide, or a combination thereof. At least a portion of the interlayer insulating layer 121 surrounding the wiring structure 125 may be composed of a low dielectric layer. The interlayer insulating layer 121 may be formed using chemical vapor deposition (CVD), a flowable-CVD process, or a spin-coating process. The wiring structure 125 may be formed as a multilayer structure including wiring patterns and vias made of, for example, aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or a combination thereof. A barrier film (not shown) including titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) may be disposed between the wiring structure 125 and the interlayer insulating layer 121. Discrete elements 115 constituting an integrated circuit may be disposed on the front surface FS of the substrate 110. In this case, the wiring structure 125 may be electrically connected to the discrete elements 115 by interconnects 113 (e.g., contact plugs). The discrete elements 115 may include various active and / or passive elements such as FETs such as planar FETs and FinFETs, memory elements such as flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, FeRAM, and RRAM, logic elements such as AND, OR, and NOT, system LSIs, CIS, and MEMS.

[0024] The front pads 130 and the test pads 135 may be arranged on the front surface FS of the substrate 110. As shown in Figures 2 and 3, each of the semiconductor chips 100A, 100B, 100C, 100D, and 100E may include a pad region PR, a pad region SR, and a test pad region TR. The pad region SR may extend along the X direction, and the four pad regions PR may be spaced apart from each other in the X and Y directions. However, the arrangement of the pad regions PR, the pad regions SR, and the test pad region TR is merely an example and is not limiting.

[0025] Front pads 130 may be arranged in the pad regions PR and SR. For example, front pads 130 used to transmit power supply voltages and ground voltages may be arranged in the pad region PR. Front pads 130 that can provide paths for transmitting / receiving data signals may be arranged in the pad region SR. The front pads 130 may be electrically connected to the wiring structure 125 of the circuit layer 120. In one embodiment, at least one of the front pads 130 arranged in the pad region PR may be a dummy pad that is not electrically connected to the wiring structure 125. The front pads 130 are illustrated as being circular in a plan view, but are not limited thereto. In an embodiment, the front pads 130 may have a shape such as an oval or a rectangle.

[0026] The test pad area TR may be disposed in a central portion of the front surface FS of the substrate 110. For example, the test pad area TR may be disposed between pad areas PR spaced apart from each other in the X direction, or may extend in the Y direction. For example, in the exemplary embodiment shown in FIG. 5 , the test pad area TR may be disposed between a first pad area PR on one side in the X direction and a second pad area PR on the opposite side in the X direction. The first pad area PR includes a plurality of first front surface pads 130 within the X and Y coordinates of the first pad area PR, the second pad area PR includes a plurality of second front surface pads 130 within the X and Y coordinates of the second pad area PR, and the test pad area TR includes a test pad 135 within the X and Y coordinates of the test pad area TR.

[0027] Test pads 135 may be arranged in the test pad region TR along the Y direction. The test pads 135 may be used for defect testing of the semiconductor chips 100A, 100B, 100C, 100D, and 100E and may be electrically connected to the wiring structures 125 of the circuit layer 120. The test pads 135 are shown as rectangular in plan view, but are not limited thereto. In an embodiment, the test pads 135 may have a circular, oval, or other shape. In one embodiment, the horizontal width of the test pads 135 may be greater than the horizontal width of the front pads 130. As shown in FIG. 5, the test pads 135 may be arranged at the same vertical level as the front pads 130.

[0028] The front pads 130 may be spaced apart from one another at a first pitch P1. For example, the pads of the first front pads 130 arranged in the first pad region PR may be spaced apart from one another at a first pitch P1. Here, the pitch may refer to the horizontal distance between the centers of the front pads 130. The minimum distance between the front pads 130 arranged in different pad regions PR may be greater than the first pitch P1. For example, as shown in FIGS. 3 and 5, the distance D between the front pads 130 adjacent to the test pad 135 may be greater than the first pitch P1. In one embodiment, the minimum distance between the first front pads 130 and the second front pads 130 in the second pad region PR may be greater than the first pitch P1.

[0029] The front pad 130 and the test pad 135 may include a conductive material such as aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or a combination thereof. A barrier film (not shown) including titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) may be disposed on at least one surface of the front pad 130 and the test pad 135.

[0030] 5, each of the semiconductor chips 100A, 100B, 100C, 100D, and 100E may further include a front protection layer PL covering the front pads 130 and the test pads 135. The front protection layer PL may cover the circuit layer 120 and partially expose the front pads 130 and the test pads 135.

[0031] The through vias 150 may extend vertically from the front surface FS to the back surface BS of the substrate 110 and may be electrically connected to at least one of the back surface pads 160. The through vias 150 may be electrically connected to wiring structures 125 of the circuit layer 120, such as signal wiring, power wiring, and ground wiring. In one embodiment, the back surface structures 170 may be separated from the through vias 150. For example, the back surface structures 170 may not vertically overlap the through vias 150 or may not be electrically connected to the through vias 150. In some embodiments, some of the through vias 150 may vertically overlap the back surface structures 170.

[0032] The through via 150 may include a via plug 152 and a barrier layer 151 surrounding the side surface of the via plug 152. The via plug 152 may include, for example, tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu) and may be formed by a plating process, a PVD process, or a CVD process. The barrier layer 151 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) and may be formed by a plating process, a PVD process, or a CVD process.

[0033] Each of the semiconductor chips 100A, 100B, 100C, 100D, and 100E may further include a side insulating film 153 extending along a side surface of a portion of the through via 150. The side insulating film 153 may electrically isolate the via plug 152 from the substrate 110. The side insulating film 153 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride (e.g., HARP (High Aspect Ratio Process) oxide), and may be formed by a PVD process or a CVD process.

[0034] The rear protective layer 155 is disposed on the rear surface BS of the substrate 110 and may include an insulating material. The rear protective layer 155 may include, for example, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride. In an embodiment, the rear protective layer 155 may include multiple protective layers. For example, the rear protective layer 155 may include a first protective layer 156 and a second protective layer 157 that include different materials. The first protective layer 156 may include silicon oxide, and the second protective layer 157 may include, but is not limited to, silicon nitride. In some embodiments, the rear protective layer 155 may be a single layer made of silicon oxide. The rear protective layer 155 may protect the rear surface BS of the substrate 110 and electrically insulate the rear pad 160 from the substrate 110. The through via 150 may penetrate the rear protective layer 155. For example, the top surface of the rear protective layer 155 may be coplanar with the top surface of the through via 150.

[0035] The rear pads 160 and the rear structure 170 may be disposed on the rear surface BS of the substrate 110. For example, the rear pads 160 and the rear structure 170 may be disposed on the upper surface of the rear protective layer 155. The rear pads 160 may be disposed in pad regions PR and pad regions SR. The rear pads 160 may be electrically connected to the corresponding front pads 130 by the bump structures 140. For example, the rear pads 160 may vertically overlap the corresponding front pads 130. For example, the rear pads 160 may be arranged at the same pitch as the front pads 130. For example, the rear pads 160 and the front pads 130 may be arranged at a first pitch P1. The rear pads 160 may be electrically connected to the corresponding through vias 150. For example, the rear pads 160 may contact the corresponding through vias 150 and vertically overlap the corresponding through vias 150.

[0036] In one embodiment, each rear pad among the plurality of rear pads 160 may be electrically connected to the circuit layer 120, and each rear structure 170 may not be electrically connected to the circuit layer 120. The rear structures 170 may be dummy pads or dummy patterns that are not electrically connected to other circuit elements (e.g., each rear structure may be electrically floating), or may not be electrically connected to any active circuit elements, and the rear pads 160 may be connection pads that are electrically connected to additional circuit elements such as active circuit elements. For example, each rear structure 170 may be a conductive pattern.

[0037] The rear pad 160 may include a seed layer 161 and a metal layer 162 on the seed layer 161. The seed layer 161 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The metal layer 162 may include at least one of aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), and tungsten (W). For example, the metal layer 162 may include copper (Cu).

[0038] The rear surface structures 170 may be disposed in the test pad region TR. The rear surface structures 170 may be disposed in the Y direction within the test pad region TR. For example, the rear surface structures 170 may vertically overlap the corresponding test pads 135. As an example of "vertically overlapping," as shown in FIG. 5 , the X and Y coordinates of the test pads 135 (or portions thereof) overlap with the X and Y coordinates of the rear surface structures 170 (or portions thereof). In one embodiment, some of the rear surface structures 170 may be disposed in the pad region PR, but are not limited thereto.

[0039] In one embodiment, the horizontal width of the rear surface structure 170 may be smaller than the horizontal width of the test pads 135. For example, the rear surface structures 170 may be arranged to form two columns, and when viewed in a cross-sectional view, one test pad 135 may vertically overlap two rear surface structures 170. For example, the horizontal width of the rear surface structure 170 may be greater than about 0.3 times and less than about 0.5 times the horizontal width of the test pads 135. In one embodiment, the rear surface structures 170 may be arranged at the same pitch as the rear surface pads 160. For example, the rear surface structure 170 may include a first rear surface structure and may further include a second rear surface structure spaced apart from the first rear surface structure by a second pitch P2, which may be the same as the first pitch P1. In one embodiment, the second pitch P2 may be smaller than the first pitch P1.

[0040] The rear structure 170 may include a seed layer 171 and a metal layer 172 on the seed layer 171. The seed layer 171 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The metal layer 172 may include at least one of aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), and tungsten (W). For example, the metal layer 172 may include copper (Cu). In one embodiment, the rear structure 170 may include the same material as the rear pad 160. For example, the seed layer 171 and the metal layer 172 may include the same material as the seed layer 161 and the metal layer 162, respectively.

[0041] In one embodiment, the rear structure 170 may be formed in the same process as the rear pad 160. The size of the rear structure 170 may be the same as the size of the rear pad 160. For example, the horizontal width of the rear structure 170 may be the same as the horizontal width of the rear pad 160. In one embodiment, the thickness of the rear structure 170 may be the same as the thickness of the rear pad 160.

[0042] Although the rear pad 160 and rear structure 170 are shown as being circular in plan view, they are not limited thereto. In embodiments, the rear pad 160 and rear structure 170 may have shapes such as oval, square, etc., but do not all have to have the same shape.

[0043] The semiconductor package 10 may further include bump structures 140 disposed between the plurality of semiconductor chips 100A, 100B, 100C, 100D, and 100E. The bump structures 140 may contact the corresponding front pads 130 and rear pads 160, respectively, and may be electrically connected to the corresponding front pads 130 and rear pads 160. The bump structures 140 may be disposed at the same pitch as the rear pads 160. For example, the rear structures 170 may be spaced apart from each other at a first pitch P1. The bump structures 140 may be bump terminals or chip connection terminals that electrically and physically connect two adjacent semiconductor chips among the plurality of semiconductor chips 100A, 100B, 100C, 100D, and 100E.

[0044] In an embodiment of the present disclosure, the test pad 135 and the rear structure 170 may not contact the bump structure 140 and may not be electrically connected to the bump structure 140. For example, the first and second centers of adjacent first and second bump structures 140 may be spaced apart by a first pitch P1, and the bump structures 140 arranged in different pad regions PR across the test pad 135 may be spaced apart by a distance D greater than the first pitch P1. In one embodiment, D is the distance between the second center of the second bump structure 140 and the third center of the third bump structure 140, and the test pad 135 is located between the second bump structure 140 and the third bump structure 140.

[0045] The bump structure 140 may include a first portion 141 and a second portion 142 below the first portion 141. The first portion 141 may contact the corresponding front pad 130. The first portion 141 may have a cylindrical or polygonal cylindrical shape, such as a square or octagonal prism, and may include, for example, nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), gold (Au), or a combination thereof. The second portion 142 may have a spherical or ball shape and may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and / or an alloy thereof. The alloys may include, for example, Sn—Pb, Sn—Ag, Sn—Au, Sn—Cu, Sn—Bi, Sn—Zn, Sn—Ag—Cu, Sn—Ag—Bi, Sn—Ag—Zn, Sn—Cu—Bi, Sn—Cu—Zn, Sn—Bi—Zn, and the like.

[0046] The adhesive layer 180 may be disposed between the semiconductor chips 100A, 100B, 100C, 100D, and 100E and may surround the bump structure 140. The upper surface of the rear structure 170 and the lower surface of the test pad 135 may be in contact with the adhesive layer 180. As shown in FIG. 5 , the adhesive layer 180 may have a first thickness T1 between the first semiconductor chip 100A and the second semiconductor chip 100B and a second thickness T2 smaller than the first thickness T1. For example, the adhesive layer 180 may include a first portion having the first thickness T1 between the rear protective layer 155 and the front protective layer PL and a second portion having the second thickness T2 between the rear structure 170 and the test pad 135.

[0047] The adhesive layer 180 may be, but is not limited to, a non-conductive film (NCF) or a molded underfill (MUF), and may include at least one of an epoxy resin, silica (SiO2), and an acrylic copolymer, or a combination thereof.

[0048] 6 to 9 are plan views of semiconductor chips according to exemplary embodiments.

[0049] 6, the first semiconductor chip 100A of the semiconductor package 10a may include rear surface structures 170 disposed on the rear surface BS. In one embodiment, the rear surface structures 170 may be arranged in three columns. For example, the horizontal width of the rear surface structures 170 may be greater than about 0.2 times and less than about 0.3 times the horizontal width of the test pads 135. In one embodiment, the rear surface structures 170 may be arranged at a different pitch from the rear surface pads 160. For example, the rear surface structures 170 may be spaced apart from each other by a third pitch P3, which may be smaller than the first pitch P1.

[0050] 7, the first semiconductor chip 100A of the semiconductor package 10b may include a rear surface structure 170 disposed on the rear surface BS. In one embodiment, the rear surface structures 170 may be arranged in a column, and one test pad 135 may vertically overlap one rear surface structure 170. In one embodiment, the horizontal width of the rear surface structure 170 may be smaller than the horizontal width of the test pad 135.

[0051] 8, the first semiconductor chip 100A of the semiconductor package 10c may include a rear structure 170 disposed on the rear surface BS. In one embodiment, the rear structures 170 may be disposed in a column, and one test pad 135 may vertically overlap one rear structure 170. In one embodiment, the horizontal width of the rear structure 170 may be greater than the horizontal width of the test pad 135. In one embodiment, the horizontal width of the rear structure 170 may be the same as the horizontal width of the test pad 135. In the embodiments of FIGS. 7 and 8, the horizontal width of the rear structure 170 may be about 0.8 to about 1.2 times the horizontal width of the test pad 135.

[0052] 9, the first semiconductor chip 100A of the semiconductor package 10d may include a rear surface structure 170 disposed on the rear surface BS. In one embodiment, the rear surface structure 170 may extend along the Y direction and vertically overlap the plurality of test pads 135. The horizontal width of the rear surface structure 170 is illustrated as being smaller than the horizontal width of the test pads 135, but is not limited thereto. In some embodiments, the horizontal width of the rear surface structure 170 may be larger than or the same as the horizontal width of the test pads 135.

[0053] 10-12 are vertical cross-sectional views of semiconductor packages according to exemplary embodiments.

[0054] 10, the first semiconductor chip 100A of the semiconductor package 10e may include a rear structure 170 disposed on the rear surface BS. In one embodiment, the size of the rear structure 170 may be larger than the size of the rear pads 160. For example, the thickness of the rear structure 170 may be larger than the thickness of the rear pads 160. For example, the thickness of the seed layer 171 of the rear structure 170 may be the same as the thickness of the seed layer 161 of the rear pads 160, but the thickness of the metal layer 172 of the rear structure 170 may be larger than the thickness of the metal layer 162 of the rear pads 160. In one embodiment, the thickness of the rear structure 170 may be about 0.5 to about 0.75 times the thickness of the adhesive layer 180. Here, the thickness of the adhesive layer 180 may refer to the vertical distance between the rear protective layer 155 of the first semiconductor chip 100A and the front protective layer PL of the second semiconductor chip 100B.

[0055] 11, the first semiconductor chip 100A of the semiconductor package 10f may include a rear structure 170 disposed on the rear surface BS. In one embodiment, one rear structure 170 may be disposed in the test pad region TR when viewed in a cross-sectional view. For example, the rear structures 170 may be disposed as shown in FIGS. 7 to 9. The horizontal width of the rear structure 170 may be approximately 0.8 to 1.2 times the horizontal width of the test pad 135.

[0056] 12, the first semiconductor chip 100A of the semiconductor package 10g may include a rear surface structure 170 disposed on the rear surface BS. In one embodiment, three rear surfaces 170 may be disposed in the test pad region TR when viewed in cross section. For example, the rear surfaces 170 may be disposed as shown in FIG. 6. The horizontal width of the rear surface structures 170 may be smaller than the horizontal width of the rear surface pads 160.

[0057] 13a to 13f are cross-sectional views illustrating major steps of a method for manufacturing a semiconductor package according to an exemplary embodiment.

[0058] 13a, a preliminary substrate 110' may be provided having a front surface FS and a back surface BS. A circuit layer 120 and through vias 150 may be formed on the front surface FS of the preliminary substrate 110'. The through vias 150 may be formed before the circuit layer 120 is formed or after the circuit layer 120 is formed. The through vias 150 extend vertically from the front surface FS and may not pass completely through the preliminary substrate 110'.

[0059] 13b, a bump structure 140 may be formed on the front surface FS of the preliminary substrate 110′. The bump structure 140 may be connected to the front surface pads 130 described with reference to FIG. 5. The bump structure 140 may be electrically connected to the circuit layer 120 via the front surface pads 130.

[0060] 13c, the rear surface BS of the preliminary substrate 110′ may be partially etched to form a rear protective layer 155. For example, after partially removing the rear surface BS to expose the through vias 150, a protective material may be deposited to cover the rear surface BS and the through vias 150, and a planarization process may be performed to form the rear protective layer 155.

[0061] 13d, a seed material layer CL may be formed on the rear protective layer 155, and a mask M may be formed on the seed material layer CL. The seed material layer CL may completely cover the rear protective layer 155, and the mask M may be patterned to partially expose the seed material layer CL.

[0062] 13e, the rear pads 160 and the rear structure 170 may be formed on the rear protective layer 155. For example, the metal layers 162, 172 of the rear pads 160 and the rear structure 170 may be formed by performing a plating process using the seed material layer CL as a seed layer. Thereafter, the mask M may be removed, and the seed material layer CL covering the rear protective layer 155 may be partially removed to form the seed layers 161, 171 of the rear pads 160 and the rear structure 170. In one embodiment, the rear structure 170 may be formed in a separate process from the rear pads 160.

[0063] Thereafter, the preliminary substrate 110' may be sawed along scribe lines (not shown) to form the substrate 110, and the upper semiconductor chip 101 may be manufactured.

[0064] 13f, an upper semiconductor chip 101 may be mounted (stacked) on a lower semiconductor chip 102. The lower semiconductor chip 102 may have the same or similar structure as the upper semiconductor chip 101. For example, the upper semiconductor chip 101 and the lower semiconductor chip 102 may each correspond to one of the semiconductor chips 100A, 100B, 100C, 100D, and 100E shown in FIGS.

[0065] In one embodiment, the upper semiconductor chip 101 may be mounted on the lower semiconductor chip 102 by a thermocompression bonding process. For example, an adhesive layer AL covering the bump structures 140 may be formed on the front surface FS of the upper semiconductor chip 101. Then, the bump structures 140 may be bonded to the rear surface pads 160 of the lower semiconductor chip 102. The adhesive layer AL may correspond to the adhesive layer 180 described above. As shown in FIG. 1, during the thermocompression bonding process, the adhesive layer AL may move to the edge of the upper semiconductor chip 101, and a portion of the adhesive layer 180 may protrude from the side of the semiconductor chip.

[0066] As described with reference to FIG. 5, the front pads 130 and the bump structures 140 may not be disposed in the test pad region TR. Therefore, as shown in FIG. 13f, the distance between the first bump structure 140a and the second bump structure 140b may be greater than the pitch of the bump structures 140. In this case, the lower surface of the adhesive layer AL between the first bump structure 140a and the second bump structure 140b may be concave, and the adhesive layer AL may be formed relatively thin. Therefore, when the upper semiconductor chip 101 is mounted on the lower semiconductor chip 102 by a thermocompression bonding process, the adhesive layer AL may move to the center of the upper semiconductor chip 101 to fill the space between the first bump structure 140a and the second bump structure 140b, which may cause the bump structure 140 to collapse.

[0067] However, in the embodiment of the present disclosure, the lower semiconductor chip 102 may include a rear structure 170 on its upper surface that vertically overlaps the test pads 135 of the upper semiconductor chip 101. Therefore, during the thermocompression bonding process, it is possible to prevent or reduce the movement of the adhesive material layer AL toward between the first bump structure 140a and the second bump structure 140b, thereby preventing or reducing collapse of the bump structure 140. In addition, it is possible to prevent voids from occurring in the adhesive layer 180.

[0068] FIG. 14 is a vertical cross-sectional view of a semiconductor package according to an exemplary embodiment.

[0069] 14, a semiconductor package 1000 according to an embodiment may include a package substrate 600, an interposer substrate 700, and at least one package structure PKG. The semiconductor package 1000 may further include a logic chip or a processor chip 800 disposed adjacent to the package structure PKG on the interposer substrate 700. The package structure PKG may have the same or similar features as the semiconductor packages 10, 10a, 10b, 10c, 10d, 10e, 10f, and 10g described with reference to FIGS.

[0070] The package substrate 600 is a support substrate on which the interposer substrate 700, the logic chip 800, and the package structure PKG are mounted, and may be a semiconductor package substrate, such as a printed circuit board (PCB), a ceramic substrate, a glass substrate, or a tape wiring substrate. The package substrate 600 may include lower pads 612, upper pads 611, and a wiring circuit 613 electrically connecting the lower pads 612 and the upper pads 611. The body of the package substrate 600 may include different materials depending on the type of substrate. For example, if the package substrate 600 is a printed circuit board, the body may be a copper clad laminate, or a copper clad laminate having a wiring layer laminated on its cross section or both sides. The lower pads 612 and the upper pads 611 and the wiring circuit 613 may form an electrical path connecting the lower and upper surfaces of the package substrate 600. External connection bumps 620 connected to the lower pads 612 may be disposed on the lower surface of the package substrate 600. The external connection bumps 620 may include, for example, solder balls.

[0071] The interposer substrate 700 may include a substrate 701, a lower protective layer 703, a lower pad 705, an interconnect structure 710, a conductive bump 720, and a through via 730. The package structure PKG and the processor chip 800 may be stacked on the package substrate 600 via the interposer substrate 700. The interposer substrate 700 may electrically connect the package structure PKG and the processor chip 800 to each other.

[0072] The substrate 710 may be formed of, for example, any one of a silicon, organic, plastic, and glass substrate. If the substrate 701 is a silicon substrate, the interposer substrate 700 may be referred to as a silicon interposer. If, unlike the one shown in the drawing, the substrate 701 is an organic substrate, the interposer substrate 700 may be referred to as a panel interposer.

[0073] A lower protective layer 703 may be disposed on the lower surface of the substrate 701, and lower pads 705 may be disposed on the lower protective layer 703. The lower pads 705 may be connected to through vias 730. The package structure PKG and the processor chip 800 may be electrically connected to the package substrate 600 via conductive bumps 720 disposed on the lower pads 705.

[0074] The interconnect structure 710 is disposed on the upper surface of the substrate 701 and may include an interlayer insulating layer 711 and a single-layer or multi-layer wiring structure 712. When the interconnect structure 710 is composed of a multi-layer wiring structure, wiring patterns on different layers may be connected to each other through contact vias. Upper pads 704 connected to the wiring structure 712 may be disposed on the interconnect structure 710. The package structure PKG and the processor chip 800 may be connected to the upper pads 704 through connection bumps 139.

[0075] The through vias 730 may extend from the top surface to the bottom surface of the substrate 701, penetrating the substrate 701. Furthermore, the through vias 730 may extend into the interconnect structure 710 and electrically connect with the wiring of the interconnect structure 710. If the substrate 701 is silicon, the through vias 730 may be referred to as TSVs. Depending on the embodiment, the interposer substrate 700 may include only interconnect structures therein, and may not include through vias.

[0076] The interposer 700 may be used to convert or transmit input electrical signals between the package substrate 600 and the package structure PKG or the processor chip 800. Therefore, the interposer substrate 700 may not include elements such as active or passive elements. In an embodiment, the interconnect structure 710 may be disposed below the through via 730.

[0077] The conductive bumps 720 may be disposed on the lower surface of the interposer substrate 700 and electrically connected to the wiring of the interconnect structure 710. The interposer substrate 700 may be mounted on the package substrate 600 via the conductive bumps 720. The conductive bumps 720 may be connected to the lower pads 705 via the wiring of the interconnect structure 710 and through vias 730. For example, some of the lower pads 705 used for power or ground may be integrated and connected to the conductive bumps 720, allowing the number of lower pads 705 to be greater than the number of conductive bumps 720.

[0078] The logic chip or processor chip 800 may include, for example, a central processor (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), a cryptographic processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application specific integrated circuit (ASIC), etc.

[0079] The present invention is not limited by the above-described embodiments and the accompanying drawings, but is limited by the scope of the appended claims. Therefore, various substitutions, modifications, and changes may be made by those skilled in the art without departing from the technical spirit of the present invention as defined in the claims, and these also fall within the scope of the present invention. [Explanation of symbols]

[0080] 10 Semiconductor Package CS Chip Structure 110 Board FS front BS rear PR pad area SR pad area TR test pad area 130 Front pad 135 Test pad PL Front protection layer 140 Bump structure 150 Through via 155 Rear protective layer 160 Rear pad 170 Rear structure 180 Adhesive layer 190 Sealant

Claims

1. a first semiconductor chip including a substrate having a front surface and a rear surface opposite to each other, a rear protective layer on the rear surface, a plurality of rear pads on the rear protective layer, and a rear structure between two rear pads of the plurality of rear pads; a second semiconductor chip disposed on the first semiconductor chip, the second semiconductor chip including a first pad area, a second pad area, and a test pad area between the first pad area and the second pad area; a plurality of bump structures disposed between the first semiconductor chip and the second semiconductor chip and connected to the plurality of rear surface pads of the first semiconductor chip; an adhesive layer surrounding the plurality of bump structures between the first semiconductor chip and the second semiconductor chip; Including, the first pad area includes a plurality of first front pads, the second pad area includes a plurality of second front pads, and the test pad area includes a test pad; the plurality of first front pads are spaced apart at a first pitch; a minimum distance between the first plurality of front pads and the second plurality of front pads is greater than the first pitch; At least a portion of the rear structure vertically overlaps the test pad.

2. Each of the first front pads of the plurality of first front pads is connected to a corresponding one of the bump structures of the plurality of bump structures; The semiconductor package of claim 1 , wherein each of the second front pads is connected to a corresponding one of the bump structures.

3. the rear structure is not electrically connected to any bump structure; The semiconductor package of claim 1 , wherein the test pad is not electrically connected to any bump structure.

4. The semiconductor package according to claim 1 , wherein a lower surface of the test pad is in contact with the adhesive layer.

5. The semiconductor package of claim 1 , wherein a top surface of the rear structure contacts the adhesive layer.

6. The semiconductor package of claim 1 , wherein the test pad is not electrically connected to the rear structure.

7. the first semiconductor chip further includes a circuit layer on the front side; At least one rear pad among the plurality of rear pads is electrically connected to the circuit layer; The semiconductor package of claim 1 , wherein the rear structure is not electrically connected to the circuit layer.

8. The semiconductor package of claim 1 , wherein the thickness of the rear structure is the same as the thickness of each of the plurality of rear pads.

9. The semiconductor package of claim 1 , wherein the rear structure includes a seed layer in contact with the rear protective layer, and a metal layer on the seed layer.

10. The semiconductor package of claim 1 , wherein the horizontal width of the rear structure is the same as the horizontal width of each of the plurality of rear pads.

11. the rear structure is a first rear structure, The vehicle further includes a second rear structure spaced apart from the first rear structure by a second pitch, The semiconductor package of claim 1 , wherein the second pitch is the same as the first pitch.

12. The semiconductor package of claim 1 , wherein the thickness of the rear structure is greater than the thickness of each of the plurality of rear pads.

13. 13. The semiconductor package of claim 12, wherein the thickness of the rear structure is about 0.5 to about 0.75 times the thickness of the adhesive layer.

14. the rear structure is a first rear structure, The vehicle further includes a second rear structure spaced apart from the first rear structure by a second pitch, The semiconductor package of claim 1 , wherein the second pitch is smaller than the first pitch.

15. 2. The semiconductor package of claim 1, wherein the horizontal width of the rear structure is about 0.8 to about 1.2 times the horizontal width of the test pad.

16. The semiconductor package of claim 1 , wherein the rear structure comprises the same material as the plurality of rear pads.

17. a first semiconductor chip including a substrate having a front surface and a rear surface opposite to each other, a rear protective layer disposed on the rear surface of the substrate, a plurality of rear pads on the rear protective layer, and a rear structure between two rear pads of the plurality of rear pads; a second semiconductor chip disposed on the first semiconductor chip, the second semiconductor chip including a plurality of front surface pads electrically connected to the plurality of rear surface pads, and a test pad between the plurality of front surface pads; a plurality of bump structures disposed between the plurality of rear surface pads of the first semiconductor chip and the plurality of front surface pads of the second semiconductor chip; an adhesive layer surrounding the plurality of bump structures between the first semiconductor chip and the second semiconductor chip; Including, The plurality of bump structures include a first bump structure, a second bump structure, and a third bump structure spaced apart from each other in a first horizontal direction, a first center of the first bump structure and a second center of the second bump structure are spaced apart by a first distance along the first horizontal direction, and the second center of the second bump structure is spaced apart by a second distance, the second distance being greater than the first distance, along the first horizontal direction from a third center of the third bump structure; the test pad is disposed between the second bump structure and the third bump structure; At least a portion of the rear structure vertically overlaps the test pad.

18. the second semiconductor chip further includes a front protection layer covering the plurality of front pads and the test pad; the adhesive layer includes a first portion between the rear protective layer and the front protective layer and a second portion between the rear structure and the test pad; 18. The semiconductor package of claim 17, wherein a first thickness of the first portion of the adhesive layer is greater than a second thickness of the second portion of the adhesive layer.

19. the first semiconductor chip further includes a plurality of through vias extending from the front surface to the rear surface; the plurality of rear surface pads vertically overlap the plurality of through vias; The semiconductor package of claim 17 , wherein the rear structure is spaced apart from the plurality of through vias.

20. a plurality of vertically stacked semiconductor chips; a plurality of bump structures for electrically connecting the plurality of semiconductor chips between the plurality of semiconductor chips; a plurality of adhesive layers surrounding the plurality of bump structures between the plurality of semiconductor chips; a sealing material that covers the semiconductor chips and the adhesive layers; Including, The plurality of semiconductor chips include: a first semiconductor chip including a substrate having a front surface and a rear surface opposite to each other, a rear protective layer on the rear surface, a plurality of rear pads on the rear protective layer, and a rear structure between two rear pads of the plurality of rear pads; a second semiconductor chip disposed on the first semiconductor chip, the second semiconductor chip including a first pad area, a second pad area, and a test pad area between the first pad area and the second pad area; Including, the first pad area includes a plurality of first front pads, the second pad area includes a plurality of second front pads, and the test pad area includes a test pad; the plurality of first front pads are spaced apart at a first pitch; a minimum distance between the first plurality of front pads and the second plurality of front pads is greater than the first pitch; At least a portion of the rear structure vertically overlaps the test pad.

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