Semiconductor module and electronic circuit

Abstract

To provide a highly reliable semiconductor capable of suppressing ringing generated in gate voltage and current of a semiconductor chip configuring a bridge circuit.SOLUTION: At a side of a semiconductor module 1, a power supply terminal 51 and a ground terminal 52 are arranged between first and third gate control terminals GT1, GT3, so that the power supply terminal 51 and the ground terminal 52 are arranged in parallel. At the other side, first and second middle point terminals 61, 62 are arranged between second and fourth gate control terminals GT2, GT4, so that the first and second midpoint terminals 61, 62 are arranged in parallel. Second gate control wiring 132 and fourth gate control wiring 134 are arranged not to exist a point in parallel and adjacent to penetration current paths AA, BB from the power supply terminal 51 to the ground terminal 52, when the electronic module 1 is seen in plain view.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module and an electronic circuit. [Background technology]

[0002] A bridge circuit using semiconductor chips as switching elements is known (see, for example, Patent Document 1). FIG. 9 is a diagram showing the configuration of a semiconductor module 900 described in Patent Document 1. In the semiconductor module 900, first to fourth semiconductor chips Q1 to Q4 are mounted on corresponding wiring patterns 911 to 914, respectively. Also, first to fourth gate control terminals GT1 to GT4 are connected to the gate electrodes G of the first to fourth semiconductor chips Q1 to Q4 via first to fourth gate control wires 921 to 924, respectively. Also, first to fourth sensing terminals ST1 to ST4 are connected to the source electrodes S of the first to fourth semiconductor chips Q1 to Q4 via first to fourth sensing wires 931 to 934, respectively.

[0003] In such a bridge circuit, the first to fourth semiconductor chips Q1 to Q4 alternately repeat an operation in which the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are both turned on and an operation in which the third semiconductor chip Q3 and the second semiconductor chip Q2 are both turned on, in response to gate control signals applied from the corresponding first to fourth gate control terminals GT1 to GT4 via the first to fourth gate control wirings 921 to 924.

[0004] When the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are both turned on, the third semiconductor chip Q3 and the second semiconductor chip Q2 are both turned off. On the other hand, when the third semiconductor chip Q3 and the second semiconductor chip Q2 are both turned on, the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are both turned off.

[0005] 9, when the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are both turned on, the current path of the main current is, as shown by solid line A in Fig. 9, from the power supply terminal (positive power supply terminal) 951 through the first semiconductor chip Q1, from the first midpoint terminal 961 through a load (not shown), and then from the second midpoint terminal 962 through the fourth semiconductor chip Q4 to the ground terminal (negative power supply terminal) 952. Note that the "main current" refers to the current that flows from the power supply terminal 951 to the ground terminal 952, and in the following explanation, it may also be simply referred to as "current."

[0006] 9, the current path when the third semiconductor chip Q3 and the second semiconductor chip Q2 are both turned on is a path that runs from the power supply terminal 951 through the third semiconductor chip Q3, from the second midpoint terminal 962 through a load (not shown), and then from the first midpoint terminal 961 through the second semiconductor chip Q2 to the earth terminal 952. Note that the current path indicated by the solid line A may be referred to as current path A, and the current path indicated by the dashed line B may be referred to as current path B. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] International Publication No. 2020 / 241239 Summary of the Invention [Problem to be solved by the invention]

[0008] In a bridge circuit such as the semiconductor module 900 described above, loss and ringing can occur due to parasitic inductance within the circuit. In particular, when wide bandgap semiconductors are used, their high slew rate and high operating frequency make loss and ringing more likely to occur due to parasitic inductance within the circuit. Ringing can occur not only in the drain (collector) voltage and current and source (emitter) voltage and current of the semiconductor chip, but also in the gate voltage and current.

[0009] The semiconductor module 900 operates as described above, but when the semiconductor chips that make up the bridge circuit repeatedly turn on and off, if ringing occurs in the gate voltage and current (falling edge of the gate voltage and current) when the semiconductor chips change from on to off, the semiconductor chips that should be turned off may mistakenly turn on, which could damage the switching elements.

[0010] Therefore, the present invention has been made to solve the above problems, and aims to provide a highly reliable semiconductor module and electronic circuit that can suppress ringing that occurs in the gate voltage and current of the semiconductor chips that make up the bridge circuit. [Means for solving the problem]

[0011] a first midpoint terminal to which the second electrode of the first semiconductor chip and the first electrode of the second semiconductor chip are connected; a second midpoint terminal to which the second electrode of the third semiconductor chip and the first electrode of the fourth semiconductor chip are connected; a first gate control terminal connected to the gate electrode of the first semiconductor chip via a first gate control wiring, a second gate control terminal connected to the gate electrode of the second semiconductor chip via a second gate control wiring, a third gate control terminal connected to the gate electrode of the third semiconductor chip via a third gate control wiring, and a fourth gate control terminal connected to the gate electrode of the fourth semiconductor chip via a fourth gate control wiring, and the first semiconductor chip is configured to function as a high side and a low side, and a second switching circuit having the third semiconductor chip on its high side and the fourth semiconductor chip on its low side, the power supply terminal, the earth terminal, the first gate control terminal, and the third gate control terminal being arranged on one side of the semiconductor module such that the power supply terminal and the earth terminal are between the first gate control terminal and the third gate control terminal and are parallel to each other; and the first midpoint terminal, the second midpoint terminal, the second gate control terminal, and the fourth gate control terminal being arranged on the other side of the semiconductor module such that the first midpoint terminal and the second midpoint terminal are between the second gate control terminal and the fourth gate control terminal and are parallel to each other; and when the semiconductor module is viewed from above, the second gate control wiring and the fourth gate control wiring are arranged so that there are no locations adjacent to or parallel to a through current path from the power supply terminal to the earth terminal.

[0012] The electronic circuit of the present invention includes first to fourth semiconductor chips each having a first electrode, a second electrode, and a gate electrode; a power supply terminal to which the first electrode of the first semiconductor chip and the first electrode of the third semiconductor chip are connected; a ground terminal to which the second electrode of the second semiconductor chip and the second electrode of the fourth semiconductor chip are connected; a first midpoint terminal to which the second electrode of the first semiconductor chip and the first electrode of the second semiconductor chip are connected; a second midpoint terminal to which the second electrode of the third semiconductor chip and the first electrode of the fourth semiconductor chip are connected; a first gate control terminal connected to the gate electrode of the first semiconductor chip via a first gate control wiring; a third gate control terminal connected to the gate electrode of the third semiconductor chip via a third gate control wiring, and a fourth gate control terminal connected to the gate electrode of the fourth semiconductor chip via a fourth gate control wiring, and a bridge circuit is configured in which a first switching circuit having the first semiconductor chip as a high side and the second semiconductor chip as a low side and a second switching circuit having the third semiconductor chip as a high side and the fourth semiconductor chip as a low side are connected in parallel, and the electronic circuit is characterized in that, when the electronic circuit is viewed in a plane, the second gate control wiring and the fourth gate control wiring are arranged so that there are no locations adjacent to or parallel to the through current path from the power supply terminal to the earth terminal. [Effects of the Invention]

[0013] In a bridge circuit using semiconductor chips as switching elements, a through-current path from a power supply terminal to a ground terminal may be formed for a very short time when each semiconductor chip is switched on and off. For example, in a semiconductor module 900, both the first semiconductor chip Q1 and the second semiconductor chip Q2 may be conductive. In this case, as shown by the dashed-dotted line AA in FIG. 9 , a through-current path is formed from the power supply terminal 951 through the first semiconductor chip Q1, then through the second semiconductor chip Q2, and to the ground terminal 952. Also, in the semiconductor module 900, both the third semiconductor chip Q3 and the fourth semiconductor chip Q4 may be conductive. In this case, as shown by the dashed-dotted line BB in FIG. 9 , a through-current path is formed from the power supply terminal 951 through the third semiconductor chip Q3, then through the fourth semiconductor chip Q4, and to the ground terminal 952. The through-current path shown by the dashed-dotted line AA may be referred to as the through-current path AA, and the through-current path shown by the dashed-dotted line BB may be referred to as the through-current path BB.

[0014] In the semiconductor module 900, when the semiconductor module 900 is viewed from above, the second gate control wiring 922 is arranged so that there is a portion where it is adjacent to and parallel to the through current path AA (particularly near the area indicated by the symbol AA1). Also, the fourth gate control wiring 924 is arranged so that there is a portion where it is adjacent to and parallel to the through current path BB (particularly near the area indicated by the symbol BB1). Through diligent research by the inventors of the present invention, it has been found that when the second gate control wiring and the fourth gate control wiring are arranged as described above, ringing is likely to occur in the gate voltage and current of the second semiconductor chip and the fourth semiconductor chip (see examples of the embodiment described later).

[0015] On the other hand, in the semiconductor module and electronic circuit of the present invention, when the semiconductor module or electronic circuit is viewed in plan, the second gate control wiring and the fourth gate control wiring are arranged so that there are no locations adjacent to or parallel to the through-current path from the power supply terminal to the ground terminal. Therefore, with the semiconductor module and electronic circuit of the present invention, the second semiconductor chip and the fourth semiconductor chip are less susceptible to the influence of the through-current path, and ringing that occurs in the gate voltage and current when the second semiconductor chip and the fourth semiconductor chip are turned off can be suppressed. This makes the semiconductor module and electronic circuit of the present invention highly reliable, capable of suppressing ringing that occurs in the gate voltage and current of the semiconductor chips that make up the bridge circuit. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a plan view of the internal configuration of a semiconductor module 1 according to an embodiment. [Figure 2] 2 is an enlarged view showing a main part of the semiconductor module 1 shown in FIG. [Figure 3] 2 is an equivalent circuit diagram of a bridge circuit 100 in the semiconductor module 1 according to the embodiment. [Figure 4] This is a diagram in which a current path is added to FIG. [Figure 5] 4 is a graph shown to explain the occurrence of ringing in the semiconductor module 1 according to the embodiment. [Figure 6] 4 is a graph shown to explain the occurrence of ringing in the semiconductor module 1 according to the embodiment. [Figure 7] 4 is a graph shown to explain the occurrence of ringing in the semiconductor module 1 according to the embodiment. [Figure 8] 10 is a plan view of the internal configuration of a semiconductor module 2 according to a modified example. FIG. [Figure 9] 1 is a diagram showing the configuration of a semiconductor module 900 described in Patent Document 1. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0017] The semiconductor module and electronic circuit of the present invention will be described below based on the embodiments shown in the drawings. The embodiments described below do not limit the invention according to the claims. Furthermore, not all of the elements and combinations thereof described in the embodiments are necessarily essential to the solution of the present invention.

[0018] [Embodiment] FIG. 1 is a plan view of the internal configuration of a semiconductor module 1 according to the embodiment. Fig. 2 is an enlarged view of a main part of the semiconductor module 1 shown in Fig. 1. Fig. 2 is an enlarged view of the main part of the semiconductor module 1 shown in Fig. 1, mainly including the first to fourth wiring patterns 10 to 40 and the semiconductor chips Q1 to Q4 mounted on the first to fourth wiring patterns 10 to 40. In order to avoid complicating the drawing, some of the reference numerals that should be assigned to the components are omitted in Fig. 1, but these reference numerals are shown in Fig. 2. The internal configuration of a semiconductor module 1 according to the embodiment will be described below with reference to Figs. 1 and 2.

[0019] The semiconductor module 1 according to the embodiment includes first to fourth semiconductor chips Q1 to Q4, first to fourth wiring patterns 10 to 40, a power supply terminal (positive power supply terminal) 51, a ground terminal (negative power supply terminal) 52, a first midpoint terminal 61, and a second midpoint terminal 62. In the following description, when the first to fourth semiconductor chips Q1 to Q4 are collectively described, they may be referred to as "semiconductor chips Q1 to Q4" without the terms "first" and "second." Furthermore, when the first to fourth wiring patterns 10 to 40 are collectively described, they may be referred to as "wiring patterns 10 to 40" without the terms "first" and "second." The first to fourth wiring patterns 10 to 40 are the first wiring pattern 10, the second wiring pattern 20, the third wiring pattern 30, and the fourth wiring pattern 40.

[0020] Of the wiring patterns 10 to 40, the second wiring pattern 20 is a wiring pattern on which no semiconductor chips are mounted, and will be described in detail later. The first wiring pattern 10 has a first semiconductor chip Q1 and a third semiconductor chip Q3 mounted thereon, the third wiring pattern 30 has a second semiconductor chip Q2 mounted thereon, and the fourth wiring pattern 40 has a fourth semiconductor chip Q4 mounted thereon.

[0021] The semiconductor module 1 according to the embodiment includes a bridge circuit 100 (see the equivalent circuit in FIG. 3) in which a first switching circuit SW1 (see the equivalent circuit in FIG. 3, which will be described later) having a first semiconductor chip Q1 of the semiconductor chips Q1 to Q4 as its high side and a second semiconductor chip Q2 as its low side is connected in parallel with a second switching circuit SW2 (see the equivalent circuit in FIG. 3) having a third semiconductor chip Q3 as its high side and a fourth semiconductor chip Q4 as its low side. In this bridge circuit 100, an operation in which both the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are turned on and an operation in which both the third semiconductor chip Q3 and the second semiconductor chip Q2 are turned on are alternately repeated.

[0022] 1 and 2, the power supply terminal 51, the earth terminal 52, the first neutral terminal 61, and the second neutral terminal 62 will be described. The power supply terminal 51 and the earth terminal 52 are terminals that supply power to the bridge circuit, and when viewed as a current flow, the power supply terminal 51 is the current input side and the earth terminal 52 is the current output side.

[0023] In the semiconductor module 1 according to the embodiment, the power supply terminal 51 includes two power supply terminals 511 and 512, which may be referred to as the "first power supply terminal 511" and the "second power supply terminal 512." The first power supply terminal 511 and the second power supply terminal 512 are formed by dividing one power supply terminal into two, and the same voltage is applied to the first power supply terminal 511 and the second power supply terminal 512. The first power supply terminal 511 is located near the first semiconductor chip Q1, and the second power supply terminal 512 is located near the third semiconductor chip Q3. The first power supply terminal 511 and the second power supply terminal 512 are located on either side of the ground terminal 52, sandwiching the ground terminal 52 therebetween.

[0024] On the other hand, the first midpoint terminal 61 and the second midpoint terminal 62 are terminals to which a load (not shown) is connected. The first midpoint terminal 61 is connected to the third wiring pattern 30, and the second midpoint terminal 62 is connected to the fourth wiring pattern 40. The first midpoint terminal 61 and the second midpoint terminal 62 are arranged adjacent to each other. When the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are both turned on, the direction of the current flowing between the first midpoint terminal 61 and the second midpoint terminal 62 is reversed from when the third semiconductor chip Q3 and the second semiconductor chip Q2 are both turned on.

[0025] In the semiconductor module 1 according to the embodiment, the semiconductor chips Q1 to Q4 are assumed to be MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and to have a rectangular shape in a plan view. The semiconductor module 1 according to the embodiment will be described assuming that vertical MOSFETs are used. In the semiconductor module 1 according to the embodiment, the wiring patterns 10 to 40 are formed on a DCB (Direct Copper Bonding) substrate 70, which is a ceramic substrate in which a metal (copper) is directly bonded to a base made of ceramic (alumina, aluminum nitride, silicon nitride, etc.). Hereinafter, the DCB substrate 70 may also be simply referred to as the substrate 70.

[0026] Each of the semiconductor chips Q1 to Q4 has a first electrode (hereinafter referred to as a drain electrode D), a second electrode (hereinafter referred to as a source electrode S), and a gate electrode G. Here, since the semiconductor chips Q1 to Q4 are illustrated as being vertical MOSFETs, the semiconductor chips Q1 to Q4 are arranged so that the drain electrode D is on the surface of the semiconductor chips Q1 to Q4 facing the wiring patterns 10 to 40 (the back surface of the semiconductor chips Q1 to Q4).

[0027] Therefore, the drain electrode D cannot be seen in the drawings, and therefore the reference symbol D indicating the drain electrode is not shown. However, in the specification, for example, the drain electrode D of the first semiconductor chip Q1 will be described with the reference symbol D. This also applies to the other semiconductor chips Q2 to Q4. Furthermore, the gate electrode G is provided on the surface of the semiconductor chips Q1 to Q4 on the source electrode S side.

[0028] Next, the wiring patterns 10 to 40 will be described. In the first wiring pattern 10, a recess 12 that has a recessed shape when the first wiring pattern 10 is viewed from above is formed in a predetermined range of one side 11 (referred to as the first side 11) of the multiple sides of the first wiring pattern 10. Here, in the semiconductor module 1, the side that is located on the upper side in the illustrations of FIGS. 1 and 2 is referred to as the first side 11.

[0029] Note that the "recess 12" is not a recess recessed in the thickness direction of the substrate 70, but rather a recess recessed downward along the y-axis on the plane of the substrate 70 when the first wiring pattern 10 is viewed in a plan view.

[0030] Furthermore, the first wiring pattern 10 has a first semiconductor chip Q1 and a third semiconductor chip Q3 mounted thereon, and a first power supply terminal 511 and a second power supply terminal 512 connected thereto as power supply terminals 51. As described above, the first power supply terminal 511 is disposed close to the first semiconductor chip Q1, and the second power supply terminal 512 is disposed close to the third semiconductor chip Q3. The first semiconductor chip Q1 and the third semiconductor chip Q3 are disposed parallel to each other with the recess 12 sandwiched therebetween (with the recess 12 between them). The position at which the recess 12 is formed is assumed to be approximately the center of the first wiring pattern 10 in the left-right direction along the x-axis shown in the drawing.

[0031] As described above, in the semiconductor module 1 according to the embodiment, the power supply terminal 51, which is the positive-side power supply terminal, has two power supply terminals: a first power supply terminal 511 and a second power supply terminal 512. The first power supply terminal 511 is located near the first semiconductor chip Q1 on the high side. The second power supply terminal 512 is located near the third semiconductor chip Q3 on the other high side. Therefore, when the first semiconductor chip Q1 and the third semiconductor chip Q3 are turned on, a shorter current path can be formed, which contributes to reducing the parasitic inductance of the bridge circuit.

[0032] Next, the second wiring pattern 20 will be described. The second wiring pattern 20 is surrounded on three sides by the recessed portion 12 of the first wiring pattern 10, and is disposed so that a portion of the second wiring pattern 20 protrudes outward (upward along the y-axis in the figure) from the opening of the recessed portion 12. At least the portion of the second wiring pattern 20 protruding from the recessed portion 12 has a tapered protrusion 23 having a first oblique side 21 and a second oblique side 22. Note that, hereinafter, the "tapered protrusion 23" may be referred to simply as the "protrusion 23" without the term "tapered." A ground terminal 52 is connected to the second wiring pattern 20. Note that the ground terminal 52 is connected to the second wiring pattern 20 so as to straddle the first wiring pattern 10 without contacting it.

[0033] In the semiconductor module 1 according to the embodiment, the second wiring pattern 20 has a shape that is symmetrical about a center line C of the second wiring pattern 20 that passes through the vertex P of the protrusion 23. However, the "shape that is symmetrical about a line" is not strictly defined, and includes shapes that are slightly different on one side and the other side of the axis of symmetry (center line C).

[0034] Here, the angle θ (see FIG. 2) formed between the first oblique side 21 and the second oblique side 22 of the protrusion 23 is not particularly limited, but is assumed to be 90 degrees in the semiconductor module 1 according to the embodiment. Therefore, the angle formed between the first oblique side 21 and the center line C and the angle formed between the second oblique side 22 and the center line C are both 45 degrees.

[0035] Next, the third wiring pattern 30 and the fourth wiring pattern 40 will be described. The third wiring pattern 30 and the fourth wiring pattern 40 are arranged along the first wiring pattern 10. To explain in more detail, the third wiring pattern 30 and the fourth wiring pattern 40 are arranged along the first side 11 of the first wiring pattern 10 from one end, i.e., the left end 11a shown in the drawing (see FIG. 2), to the other end, i.e., the right end 11b shown in the drawing (see FIG. 2). Here, as shown in FIGS. 1 and 2, the third wiring pattern 30 is arranged on the left side of the first side 11 of the first wiring pattern 10 in the left-right direction along the x-axis, and the fourth wiring pattern 40 is arranged on the right side of the first side 11 of the first wiring pattern 10 in the left-right direction along the x-axis.

[0036] The third wiring pattern 30 has a second semiconductor chip Q2 mounted thereon and a first midpoint terminal 61 connected thereto. The third wiring pattern 30 has a horizontal portion 30a (see FIG. 2) extending left and right along the x-axis in the figure, and a vertical portion 30b (see FIG. 2) extending up and down along the y-axis. The first midpoint terminal 61 is connected to the vertical portion 30b of the third wiring pattern 30, and extends upward in the figure along the y-axis.

[0037] The third wiring pattern 30 has a hypotenuse 31 (see FIG. 2) formed along the first hypotenuse 21 of the convex portion 23 of the second wiring pattern 20. The hypotenuse 31 faces the first hypotenuse 21 of the second wiring pattern 20 and is parallel to it. The second semiconductor chip Q2 is disposed along the hypotenuse 31 of the third wiring pattern 30.

[0038] On the other hand, a fourth semiconductor chip Q4 is mounted on the fourth wiring pattern 40, and a second midpoint terminal 62 is connected to the fourth wiring pattern 40. The fourth wiring pattern 40 has a horizontal portion 40a (see FIG. 2) extending left and right along the x-axis in the figure, and a vertical portion 40b (see FIG. 2) extending up and down along the y-axis. The second midpoint terminal 62 is connected to the vertical portion 40b of the fourth wiring pattern 40, and extends upward in the figure along the y-axis.

[0039] The fourth wiring pattern 40 has a hypotenuse 41 (see FIG. 2) formed along the second hypotenuse 22 of the convex portion 23 of the second wiring pattern 20. The hypotenuse 41 faces the second hypotenuse 22 of the second wiring pattern 20 and is parallel to the second hypotenuse 22. The fourth semiconductor chip Q4 is disposed along the hypotenuse 41 of the fourth wiring pattern 40.

[0040] In the semiconductor module 1 according to the embodiment, the first wiring pattern 10 has a shape that is symmetrical about an extension axis (not shown) that extends the center line C of the second wiring pattern 20 downward in the figure. The third wiring pattern 30 and the fourth wiring pattern 40 are arranged so as to have shapes that are symmetrical about an extension axis that extends the center line C of the second wiring pattern 20 upward in the figure. However, even in this case, the shape that is symmetrical about an axis is not strictly defined, and includes shapes that are slightly different on one side and the other side of the symmetry axis.

[0041] With the wiring patterns 10 to 40 arranged in this manner, the second wiring pattern 20 is surrounded by the first wiring pattern 10, the third wiring pattern 30, and the fourth wiring pattern 40, and is located near the center of the substrate 70.

[0042] In the semiconductor module 1 according to the embodiment, the semiconductor chips Q1 to Q4 have a rectangular shape in plan view, which may be a square or a rectangle, but will be described here as a rectangle. Of the multiple sides, i.e., the first side and the second side opposite the first side, of the multiple sides of each of the semiconductor chips Q1 to Q4, namely the first side to the fourth side, are short sides, and the third side and the fourth side opposite the third side are long sides. However, the semiconductor chips Q1 to Q4 are rectangular in shape, with the long sides being slightly longer than the short sides.

[0043] 2, in the semiconductor chips Q1 to Q4, the first side, which is one of the short sides of each semiconductor chip, is referred to as the "first short side a1," the second side, which is the other short side, is referred to as the "second short side a2," the third side, which is one of the long sides, is referred to as the "first long side b1," and the fourth side, which is the other long side, is referred to as the "second long side b2." Explaining this using the first semiconductor chip Q1 as an example, the first side, which is one of the short sides of the first semiconductor chip Q1, is referred to as the "first short side a1," the second side, which is the other short side, is referred to as the "second short side a2," the third side, which is one of the long sides, is referred to as the "first long side b1," and the fourth side, which is the other long side, is referred to as the "second long side b2." This is also true for the other semiconductor chips Q2 to Q4 (see FIG. 2).

[0044] 2, the first semiconductor chip Q1 mounted on the first wiring pattern 10 is arranged such that a first short side a1, which is a first side of the first semiconductor chip Q1, is aligned along a first side 11 of the first wiring pattern 10. A source electrode S, which serves as a second electrode of the first semiconductor chip Q1, is connected to the third wiring pattern 30 via a second electrode connecting member 81 (hereinafter referred to as a source connecting member 81) such as an aluminum wire. The source connecting member 81 extends from the side of the first short side a1 of the first semiconductor chip Q1 in a direction perpendicular to the first short side a1 and is connected to the third wiring pattern 30.

[0045] 2, the third semiconductor chip Q3 mounted on the first wiring pattern 10 has a first short side a1, which is a first side of the third semiconductor chip Q3, arranged along the first side 11 of the first wiring pattern 10. A source electrode S, which serves as a second electrode of the third semiconductor chip Q3, is connected to the fourth wiring pattern 40 via a second electrode connecting member 83 (hereinafter referred to as the source connecting member 83) such as an aluminum wire. The source connecting member 83 extends from the side of the first short side a1 of the third semiconductor chip Q3 in a direction perpendicular to the first short side a1 and is connected to the fourth wiring pattern 40. Therefore, in the semiconductor module 1 of the embodiment, the first semiconductor chip Q1 and the third semiconductor chip Q3 are arranged on the first wiring pattern 10 so that the extension direction of the source connection member 81 connected to the first semiconductor chip Q1 is parallel to the extension direction of the source connection member 83 connected to the third semiconductor chip Q3.

[0046] 2, the second semiconductor chip Q2 mounted on the third wiring pattern 30 has a first short side a1, which is a first side of the second semiconductor chip Q2, arranged along a hypotenuse 31 formed on the third wiring pattern 30. A source electrode S, which serves as a second electrode of the second semiconductor chip Q2, is connected to the second wiring pattern 20 via a second electrode connecting member 82 (hereinafter referred to as a source connecting member 82) such as an aluminum wire. The source connecting member 82 extends from the side of the first short side a1 of the second semiconductor chip Q2 in a direction perpendicular to the first short side a1 and is connected to the second wiring pattern 20.

[0047] 2, the fourth semiconductor chip Q4 mounted on the fourth wiring pattern 40 has a first short side a1, which is a first side of the fourth semiconductor chip Q4, arranged along a hypotenuse 41 formed on the fourth wiring pattern 40. A source electrode S, which serves as a second electrode of the fourth semiconductor chip Q4, is connected to the second wiring pattern 20 via a second electrode connecting member 84 (hereinafter referred to as a source connecting member 84) such as an aluminum wire. The source connecting member 84 extends from the side of the first short side a1 of the fourth semiconductor chip Q4 in a direction perpendicular to the first short side a1 and is connected to the second wiring pattern 20.

[0048] Now, looking at the second semiconductor chip Q2 mounted on the third wiring pattern 30 and the fourth semiconductor chip Q4 mounted on the fourth wiring pattern 40, the first short side a1 of the second semiconductor chip Q2 is arranged along the oblique side 31 formed on the third wiring pattern 30, and the first short side a1 of the fourth semiconductor chip Q4 mounted on the fourth wiring pattern 40 is arranged along the oblique side 41 formed on the fourth wiring pattern 40. Therefore, the second semiconductor chip Q2 and the fourth semiconductor chip Q4 are arranged obliquely, not parallel to each other.

[0049] The wiring patterns 10 to 40 have been described above as the wiring patterns formed on the substrate 70, but in addition to the wiring patterns 10 to 40, first to fourth gate control wiring patterns 111 to 114 and first to fourth sensing wiring patterns 121 to 124 are also formed on the substrate 70, as shown in Figures 1 and 2. Then, first to fourth gate control terminals GT1 to GT4 are connected to the first to fourth gate control wiring patterns 111 to 114, as shown in Figure 1, and first to fourth sensing terminals ST1 to ST4 are connected to the first to fourth sensing wiring patterns 121 to 124, as shown in Figure 1.

[0050] The first to fourth gate control wiring patterns 111 to 114 are connected to the gate electrodes G of the semiconductor chips Q1 to Q4 via connecting members such as aluminum wires, respectively. These connecting members are referred to as first to fourth gate control wirings 131 to 134. The first to fourth sensing wiring patterns 121 to 124 are connected to the source electrodes S of the semiconductor chips Q1 to Q4 via connecting members such as aluminum wires, respectively. These connecting members are referred to as first to fourth sensing wirings 141 to 144.

[0051] In the semiconductor module 1, the first sensing terminal ST1 is disposed on one side of the semiconductor module 1, and is between the power supply terminal 51 (the first power supply terminal 511 and the second power supply terminal 512) and the ground terminal 52, and the first gate control terminal GT1. The second sensing terminal ST2 is disposed on the other side of the semiconductor module 1, and is between the first midpoint terminal 61 and the second midpoint terminal 62, and the second gate control terminal GT2. The third sensing terminal ST3 is disposed on one side of the semiconductor module 1, and is between the power supply terminal 51 (the first power supply terminal 511 and the second power supply terminal 512) and the ground terminal 52, and the third gate control terminal GT3. The fourth sensing terminal ST4 is disposed on the other side of the semiconductor module 1, and is between the first midpoint terminal 61 and the second midpoint terminal 62, and the fourth gate control terminal GT4.

[0052] Here, taking the first semiconductor chip Q1 as an example, a first gate control wiring pattern 111 and a first sensing wiring pattern 121 are formed corresponding to the first semiconductor chip Q1. The gate electrode G of the first semiconductor chip Q1 and the first gate control wiring pattern 111 are connected by a first gate control wiring 131. Therefore, the gate electrode G of the first semiconductor chip Q1 is connected to the first gate control terminal GT1 via the first gate control wiring 131. The first gate control wiring 131 is connected to the gate electrode G of the semiconductor chip Q1 from the second short side a2 (see FIG. 2) side of the first semiconductor chip Q1.

[0053] The source electrode S of the first semiconductor chip Q1 and the first sensing wiring pattern 121 are connected by a first sensing wiring 141. Therefore, the source electrode S of the first semiconductor chip Q1 is connected to the first sensing terminal ST1 via the first sensing wiring 141. Like the first gate control wiring 131, the first sensing wiring 141 is also connected to the source electrode S of the first semiconductor chip Q1 from the second short side a2 (see FIG. 2) side of the semiconductor chip Q1.

[0054] Similarly, in the other semiconductor chips (second to fourth semiconductor chips Q2 to Q4), second to fourth gate control wiring patterns 112 to 114 and second to fourth sensing wiring patterns 122 to 124 are formed corresponding to the second to fourth semiconductor chips Q2 to Q4, respectively. The gate electrodes G of the second to fourth semiconductor chips Q2 to Q4 are connected to the second to fourth gate control wiring patterns 112 to 114 by second to fourth gate control wirings 132 to 134. The source electrodes S of the second to fourth semiconductor chips Q2 to Q4 are connected to the second to fourth sensing wiring patterns 122 to 124 by second to fourth sensing wirings 142 to 144.

[0055] Therefore, the gate electrodes G of the semiconductor chips Q2 to Q4 are connected to the second to fourth gate control terminals GT2 to GT4 via the second to fourth gate control wirings 132 to 134, and the source electrodes S of the semiconductor chips Q2 to Q4 are connected to the second to fourth sensing terminals ST2 to ST4 via the second to fourth sensing wirings 142 to 144.

[0056] In the second to fourth semiconductor chips Q2 to Q4, the second to fourth gate control wirings 132 to 134 are connected to the gate electrodes G of the semiconductor chips Q2 to Q4 from the side of the second short sides a2 (see Figure 2) of the second to fourth semiconductor chips Q2 to Q4, and the second to fourth sensing wirings 142 to 144 are connected to the source electrodes S of the semiconductor chips Q2 to Q4 from the side of the second short sides a2 (see Figure 2) of the second to fourth semiconductor chips Q2 to Q4.

[0057] In the semiconductor module 1 of the embodiment configured as described above, as shown in FIG. 1, on one side of the semiconductor module 1 (the side on which the first wiring pattern 10 is arranged), the power supply terminal 51 (first power supply terminal 511 and second power supply terminal 512), the earth terminal 52, the first sensing terminal ST1, the first gate control terminal GT1, the third sensing terminal ST3, and the third gate control terminal GT3 are arranged in parallel and in a straight line.

[0058] Specifically, with the earth terminal 52 at the center, the first power supply terminal 511 is arranged to the left of the earth terminal 52 in the figure, and the second power supply terminal 512 is arranged to the right of the earth terminal 52 in the figure. The first sensing terminal ST1 and the first gate control terminal GT1 are arranged to the left of the first power supply terminal 511 in the figure, in this order, toward the left in the figure. Furthermore, the third sensing terminal ST3 and the third gate control terminal GT3 are arranged to the right of the second power supply terminal 512 in the figure, in this order, toward the right in the figure.

[0059] By arranging the power supply terminal 51 (first power supply terminal 511 and second power supply terminal 512), ground terminal 52, first gate control terminal GT1, first sensing terminal ST1, third gate control terminal GT3, and third sensing terminal ST3 in this manner, the first sensing terminal ST1 is interposed between the first power supply terminal 511 and the first gate control terminal GT1, and the third sensing terminal ST3 is interposed between the second power supply terminal 512 and the third gate control terminal GT3. As a result, the first gate control terminal GT1 and the third gate control terminal GT3 are located away from the power supply terminal 51 and the ground terminal 52, and are therefore less susceptible to the influence of the current flowing through the power supply terminal 51 and the ground terminal 52.

[0060] Furthermore, on the other side of the semiconductor module 1 (the side where the third wiring pattern 30 and the fourth wiring pattern 40 are arranged), as shown in FIG. 1, a first midpoint terminal 61, a second midpoint terminal 62, a second sensing terminal ST2, a second gate control terminal GT2, a fourth sensing terminal ST4, and a fourth gate control terminal GT4 are arranged in parallel and in a straight line.

[0061] Specifically, the first midpoint terminal 61 and the second midpoint terminal 62 are arranged in parallel in the center. The second sensing terminal ST2 and the second gate control terminal GT2 are arranged in this order to the left of the first midpoint terminal 61. The fourth sensing terminal ST4 and the fourth gate control terminal GT4 are arranged in this order to the left of the second midpoint terminal 62.

[0062] By arranging the first midpoint terminal 61, the second midpoint terminal 62, the second sensing terminal ST2, the second gate control terminal GT2, the fourth sensing terminal ST4, and the fourth gate control terminal GT4 in this manner, the second sensing terminal ST2 is interposed between the first midpoint terminal 61 and the first gate control terminal GT1, and the fourth sensing terminal ST4 is interposed between the second midpoint terminal 62 and the fourth gate control terminal GT4. As a result, the second gate control terminal GT2 and the fourth gate control terminal GT4 are located away from the first midpoint terminal 61 and the second midpoint terminal 62, and are therefore less susceptible to the influence of the current flowing through the first midpoint terminal 61 and the second midpoint terminal 62.

[0063] The configuration of the semiconductor module 1 according to the embodiment has been described above. The semiconductor module 1 according to the embodiment configured in this manner is sealed with resin and packaged. In Fig. 1, a frame indicated by reference numeral 150 represents the outer periphery of the package. This also applies to Figs. 4 and 9, which will be described later.

[0064] FIG. 3 is an equivalent circuit diagram of a bridge circuit 100 in a semiconductor module 1 according to an embodiment. Note that in FIG. 3, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals. As described above, the bridge circuit 100 represented by the equivalent circuit shown in FIG. 3 has a configuration in which a first switching circuit SW1, which has a first semiconductor chip Q1 as its high side and a second semiconductor chip Q2 as its low side, and a second switching circuit SW2, which has a third semiconductor chip Q3 as its high side and a fourth semiconductor chip Q4 as its low side, are connected in parallel. Note that in the bridge circuit 100 shown in FIG. 3, the first power supply terminal 511 and the second power supply terminal 512 are collectively referred to as a power supply terminal 51.

[0065] In such a bridge circuit 100, when a predetermined voltage is applied to the gate electrodes G of the first semiconductor chip Q1 and the fourth semiconductor chip Q4, both the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are turned on. Also, when a predetermined voltage is applied to the gate electrodes G of the third semiconductor chip Q3 and the second semiconductor chip Q2, both the third semiconductor chip Q3 and the second semiconductor chip Q2 are turned on.

[0066] Here, when the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are both turned on, the current path is as shown by the solid line A in Figure 3, passing from the power supply terminal 51 through the first semiconductor chip Q1, from the first midpoint terminal 61 through a load not shown, and then from the second midpoint terminal 62 through the fourth semiconductor chip Q4 to the earth terminal 52.

[0067] On the other hand, when the third semiconductor chip Q3 and the second semiconductor chip Q2 are both turned on, the current path is as shown by dashed line B in Figure 3, passing from the power supply terminal 51 through the third semiconductor chip Q3, from the second midpoint terminal 62 through a load not shown, and then from the first midpoint terminal 61 through the second semiconductor chip Q2 to the earth terminal 52.

[0068] Such a current path will be explained in Fig. 4. Fig. 4 is a diagram in which the current path is added to Fig. 1, and the configuration of the semiconductor module 1 is the same as Figs. 1 and 2. However, Fig. 4 mainly shows the reference numerals of the components necessary for explaining the current path. For this reason, some of the reference numerals indicating the components shown in Figs. 1 and 2 have been omitted in Fig. 4.

[0069] 4, the current path indicated by the solid line A (current path A) and the current path indicated by the dashed line B (current path B) each schematically show the shortest current path when a current flows from the power supply terminal 51 (first power supply terminal 511 or second power supply terminal 512) of the semiconductor module 1, and the shortest current paths are referred to as "shortest current path A" and "shortest current path B." Note that "shortest current path A" and "shortest current path B" shown in FIG. 4 are shown only schematically.

[0070] 4, the current path indicated by the dashed dotted line AA (current path AA) and the current path indicated by the dashed two dotted line BB (current path BB) respectively schematically show the current paths when a current (through current) flows from the power supply terminal 51 (first power supply terminal 511 or second power supply terminal 512) of the semiconductor module 1 to the earth terminal 52, and these current paths are referred to as the "through current path AA" and the "through current path BB." Note that the "through current path AA" and the "through current path BB" shown in FIG. 4 are also shown schematically.

[0071] When the semiconductor module 1 is viewed from above, the second gate control wiring 132 and the fourth gate control wiring 134 are arranged so as not to be adjacent to or parallel to the through-current paths AA and BB extending from the power supply terminal 51 (the first power supply terminal 511 or the second power supply terminal 512) to the ground terminal 52. In this specification, "adjacent" with respect to the gate control wiring and the current path means that there are no conductive members or other current paths between the gate control wiring and the current path. Also, in this specification, "parallel" with respect to the gate control wiring and the current path means that the extension direction of the gate control wiring and the direction of the current path are parallel or nearly parallel when the semiconductor module is viewed from above. In this specification, "nearly parallel" with respect to two directions means that the relationship between the directions of the two directions is closer to parallel than perpendicular (the difference between the directions of the two directions is less than 45°). In this case, the current path refers to the path through which the current density is highest when a current flows.

[0072] Furthermore, when the semiconductor module 1 is viewed from above, the first gate control wiring 131 and the third gate control wiring 133 are also arranged so that there are no locations where they are adjacent to and parallel to the through current paths AA and BB.

[0073] Next, the relationship between the second gate control wiring 132 and the fourth gate control wiring 134 and the shortest current paths A and B will be described. When the first semiconductor chip Q1 and the fourth semiconductor chip Q4 are both turned on, the shortest current path A is a path that runs from the first power supply terminal 511, which is closer to the first semiconductor chip Q1, to the first wiring pattern 10 and then to the first semiconductor chip Q1. The current then flows from the drain electrode D (not shown) of the first semiconductor chip Q1 mounted on the first wiring pattern 10, through the source electrode S, via the source connection member 81, through the third wiring pattern 30, and to the first midpoint terminal 61. The current then flows through a load (not shown) from the second midpoint terminal 62 to the fourth wiring pattern 40, from the drain electrode D (not shown) of the fourth semiconductor chip Q4 mounted on the fourth wiring pattern 40, through the source electrode S, via the source connection member 84, through the second wiring pattern 20, and to the ground terminal 52.

[0074] On the other hand, when the third semiconductor chip Q3 and the second semiconductor chip Q2 are both turned on, the shortest current path B of the current is a path that runs from the second power supply terminal 512, which is closer to the third semiconductor chip Q3, through the first wiring pattern 10, and to the third semiconductor chip Q3. The current then flows from the drain electrode D (not shown) of the third semiconductor chip Q3 through the source electrode S, via the source connecting member 83, and through the fourth wiring pattern 40 to the second midpoint terminal 62. After that, the current passes through a load (not shown) and enters the third wiring pattern 30 from the first midpoint terminal 61, and then flows from the drain electrode D (not shown) of the second semiconductor chip Q2 mounted on the third wiring pattern 30 through the source electrode S, from the source connecting member 82, through the second wiring pattern 20, and to the ground terminal 52.

[0075] In the following explanation, of the shortest current path A, the shortest current path from the power supply terminal 51 (first power supply terminal 511) to the first midpoint terminal 61 will be referred to as the first shortest current path A1 (see FIG. 4), and the shortest current path from the second midpoint terminal 62 to the earth terminal 52 will be referred to as the shortest current path A2 (see FIG. 4). Similarly, of the shortest current path B, the shortest current path from the power supply terminal 51 (second power supply terminal 512) to the second midpoint terminal 62 will be referred to as the second shortest current path B1 (see FIG. 4), and the shortest current path from the first midpoint terminal 61 to the earth terminal 52 will be referred to as the shortest current path B2 (see FIG. 4).

[0076] 4, in the semiconductor module 1 according to the embodiment, the second gate control wiring 132 of the second semiconductor chip Q2 is arranged so as to intersect with the first shortest current path A1 on the third wiring pattern 30 when the semiconductor module 1 is viewed in a plan view. Similarly, the fourth gate control wiring 134 of the fourth semiconductor chip Q4 is arranged so as to intersect with the second shortest current path B1 on the fourth wiring pattern 40 when the semiconductor module 1 is viewed in a plan view.

[0077] With this configuration, when the second semiconductor chip Q2 changes from on to off, the second gate control wiring 132 of the second semiconductor chip Q2 is less affected by the current flowing through the first shortest current path A1. This makes it possible to suppress ringing that occurs in the second gate voltage and current when the second semiconductor chip Q2 is turned off. Similarly, when the fourth semiconductor chip Q4 changes from on to off, the fourth gate control wiring 134 of the fourth semiconductor chip Q4 is less affected by the current flowing through the second shortest current path B1. This makes it possible to further suppress ringing that occurs in the gate voltage and current of the fourth semiconductor chip Q4 when the fourth semiconductor chip Q4 is turned off.

[0078] In the section from the power supply terminal 51 (first power supply terminal 511 or second power supply terminal 512) to the first semiconductor chip Q1 and the third semiconductor chip Q3, the shortest current paths A and B and the through current paths AA and BB are substantially the same paths (see FIG. 4). Therefore, with regard to the first gate control wiring 131 and the third gate control wiring 133, it can also be expressed as "the first gate control wiring 131 and the third gate control wiring 133 are arranged so that there are no locations where they are adjacent to and parallel to the shortest current paths A and B."

[0079] Here, a description will be given of the results (example) of measuring (simulating) the ringing that occurs in the semiconductor module 1. Here, the description will be given of the results of measuring the ringing when the second semiconductor chip Q2 is turned off.

[0080] 5 to 7 are graphs shown to explain the occurrence of ringing in the semiconductor module 1 according to the embodiment. FIG. 5(A) is a graph showing the current waveform of the phase current (current passing through the first center point terminal 61 and the second center point terminal 62) in the semiconductor module 1. FIG. 5(B) is a graph showing a portion of FIG. 5(A) (the area indicated by the rectangle E shown with a dashed line) enlarged in the horizontal direction. Note that the area indicated by the rectangle E in FIG. 5(A) includes the waveform when the second semiconductor chip Q2 is turned off. The areas indicated by the rectangle E in FIGS. 5(C), 6(A), 6(C), 7(A), and 7(C), which will be described later, also include the waveform when the second semiconductor chip Q2 is turned off. Fig. 5(C) is a graph showing the Vds waveform (voltage waveform of the drain-source voltage) in the second semiconductor chip Q2 of the semiconductor module 1. Fig. 5(D) is a graph showing a portion of Fig. 5(C) (the area indicated by the dashed rectangle E) enlarged in the horizontal direction.

[0081] Fig. 6(A) is a graph showing the Id waveform (current waveform of the drain current) in the first semiconductor chip Q1 of the semiconductor module 1. Fig. 6(B) is a graph showing a portion of Fig. 6(A) (the area indicated by the dashed rectangle E) enlarged in the horizontal direction. Fig. 6(C) is a graph showing the Id waveform in the second semiconductor chip Q2 of the semiconductor module 1. Fig. 6(D) is a graph showing a portion of Fig. 6(C) (the area indicated by the dashed rectangle E) enlarged in the horizontal direction.

[0082] Fig. 7(A) is a graph showing a Vgs waveform (voltage waveform of the gate-source voltage) in the second semiconductor chip Q2 of the semiconductor module 1. Fig. 7(B) is a graph showing a portion of Fig. 7(A) (the area indicated by the dashed rectangle E) enlarged in the horizontal direction. Fig. 7(C) is a graph showing an Ig waveform (current waveform of the gate current) in the second semiconductor chip Q2 of the semiconductor module 1. Fig. 7(D) is a graph showing a portion of Fig. 7(C) (the area indicated by the dashed rectangle E) enlarged in the horizontal direction.

[0083] First, as shown in Figures 5(A) and 5(B), no ringing was observed in the phase current itself in the semiconductor module 1. On the other hand, as shown in Figures 5(C) and 5(D), ringing was observed in the Vds waveform in the second semiconductor chip Q2 (see the area indicated by the ellipse F1 in Figure 5(D)).

[0084] 6(A) to 6(D), ringing of almost the same waveform occurred at almost the same timing in the Id waveforms of the first semiconductor chip Q1 and the second semiconductor chip Q2 (see the area indicated by the ellipse F2 in FIGS. 6(B) and 6(D)). This indicates that ringing occurred in the current path passing through the first semiconductor chip Q1 and the second semiconductor chip Q2, i.e., the through current path AA (see FIG. 4).

[0085] 7(A) to 7(D), the occurrence of ringing in the Vgs waveform and Ig waveform of the second semiconductor chip Q2 when the second semiconductor chip Q2 is turned off (during the falling edge) was confirmed (see the area indicated by the ellipse F3 in FIGS. 7(B) and 7(D)). Considering the current waveforms of the phase currents described above, the Vds waveform in the second semiconductor chip Q2, and the Id waveforms in the first semiconductor chip Q1 and the second semiconductor chip Q2, it is believed that the ringing in the Vgs waveform and Ig waveform of the second semiconductor chip Q2 is mainly caused by ringing in the through current path AA.

[0086] Although not shown in the figure, the same phenomenon as that of the second semiconductor chip Q2 occurs in the fourth semiconductor chip Q4. That is, ringing occurs in the gate voltage and current of the fourth semiconductor chip Q4, which is mainly caused by ringing in the through current path BB (see FIG. 4).

[0087] As explained above, ringing occurs in the gate voltage and current in the semiconductor module 1 when the second semiconductor chip Q2 and the fourth semiconductor chip Q4 are turned off. However, in the semiconductor module 1, the second gate control wiring 132 and the fourth gate control wiring 134 do not run parallel to the through current paths AA and BB at locations where they are adjacent to each other, and therefore the ringing in the semiconductor module 1 is sufficiently suppressed. Although not shown, the ringing in the semiconductor module 1 is reduced in amplitude to about 50% compared to the corresponding ringing in a semiconductor module (such as the semiconductor module 900 shown in FIG. 9 ) in which the second gate control wiring and the fourth gate control wiring run parallel to the through current paths at locations where they are adjacent to each other. This indicates that the gate current and voltage are significantly affected by the current and voltage in the adjacent and parallel current paths.

[0088] Furthermore, when the semiconductor module 1 is viewed from above, the first gate control wiring 131 and the third gate control wiring 133 are also arranged so that there are no locations where they are adjacent to or parallel to the through current paths AA and BB. Therefore, the same effects as those in the second semiconductor chip Q2 and the fourth semiconductor chip Q4 are obtained in the first semiconductor chip Q1 and the third semiconductor chip Q3. In other words, ringing of the gate voltage and current caused by ringing of the through current paths AA and BB is reduced in the first semiconductor chip Q1 and the third semiconductor chip Q3 as well.

[0089] As described above, in the semiconductor module 1 according to the embodiment, when the semiconductor module 1 is viewed in a plan view, the second gate control wiring 132 and the fourth gate control wiring 134 are arranged so as not to be adjacent to or parallel to the through-current paths AA and BB that extend from the power supply terminal 51 (the first power supply terminal 511 and the second power supply terminal 512) to the ground terminal 52. According to the semiconductor module 1 according to the embodiment, the second semiconductor chip Q2 and the fourth semiconductor chip Q4 are less susceptible to the effects of the through-current paths AA and BB, and ringing that occurs in the gate voltage and current when the second semiconductor chip Q2 and the fourth semiconductor chip Q4 are turned off can be suppressed. This prevents the second semiconductor chip Q2 and the fourth semiconductor chip Q4, which should be turned off, from mistakenly turning on, thereby suppressing damage to the switching elements.

[0090] In this way, the semiconductor module 1 according to the embodiment is a highly reliable semiconductor module that can suppress ringing that occurs in the gate voltage and current of the semiconductor chips that form the bridge circuit.

[0091] Furthermore, in the semiconductor module 1 according to the embodiment, the first gate control wiring 131 and the third gate control wiring 133 are also arranged so that there are no locations adjacent to or parallel to the through current paths AA and BB when the semiconductor module 1 is viewed in a plan view. Therefore, according to the semiconductor module 1 according to the embodiment, the first semiconductor chip Q1 and the third semiconductor chip Q3 are also less susceptible to the influence of the through current paths AA and BB, and ringing that occurs in the gate voltage and current when the first semiconductor chip Q1 and the third semiconductor chip Q3 are turned off can be suppressed.

[0092] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, modifications such as those shown below are also possible.

[0093] (1) In the above-described embodiment, two power supply terminals 51 (first power supply terminal 511 and second power supply terminal 512) and one earth terminal 52 are provided, but conversely, two earth terminals (first earth terminal and second earth terminal) and one power supply terminal 51 may be provided. In other words, the semiconductor module of the present invention may have two earth terminals, a first earth terminal and a second earth terminal, which are disposed on both sides of the power supply terminal, sandwiching the power supply terminal therebetween. Although not shown in the drawings, in this case, the power supply terminal 51 is disposed at the center of the substrate 70 in the left-right direction and connected to the first wiring pattern. Meanwhile, one first earth terminal and one second earth terminal are disposed on both the left and right sides of the power supply terminal 51, and these two earth terminals are connected to the second wiring pattern 20 so as to straddle the first wiring pattern 10.

[0094] (2) In the above-described embodiment, source connection members 81 to 84 made of wires or the like are used as connection members for connecting each source electrode S of semiconductor chips Q1 to Q4 to the wiring pattern to which each source electrode S is connected. However, connectors (connection clips) may also be used as connection members.

[0095] 8 is a plan view of the internal configuration of a semiconductor module 2 according to a modified example. The semiconductor module 2 is an example in which connectors are used as connection members for connecting each source electrode S of the semiconductor chips Q1 to Q4 to a wiring pattern. The semiconductor module 2 in FIG. 8 is illustrated as having a configuration basically similar to that of the semiconductor module 1 according to the embodiment. In the semiconductor module 2 shown in FIG. 8, connectors (connection clips) 91 to 94 are used as connection members (second electrode connection members, source connection members) for connecting each source electrode S of the semiconductor chips Q1 to Q4 to a wiring pattern.

[0096] Specifically, the source electrode S of the first semiconductor chip Q1 is connected to the third wiring pattern 30 by a connector 91, and the source electrode S of the second semiconductor chip Q2 is connected to the second wiring pattern 20 by a connector 92. In addition, the source electrode S of the third semiconductor chip Q3 is connected to the fourth wiring pattern 40 by a connector 93, and the source electrode S of the fourth semiconductor chip Q4 is connected to the second wiring pattern 20 by a connector 94.

[0097] In this way, by using connectors 91 to 94 as second electrode connecting members that connect each source electrode S of semiconductor chips Q1 to Q4 to the corresponding wiring pattern, the connecting members that connect each source electrode S of semiconductor chips Q1 to Q4 to the corresponding wiring pattern can be made to have low impedance, thereby contributing to reducing parasitic inductance.

[0098] 8 illustrates a case where the source electrodes S of the semiconductor chips Q1 to Q4 and the corresponding wiring patterns to which the source electrodes S are connected are all connected by connectors 91 to 94, but the source electrodes S of a specific semiconductor chip among the source electrodes S of the semiconductor chips Q1 to Q4 may be connected to the corresponding wiring patterns using connectors. Although not shown in the drawings, for example, the source electrodes S of the first and third semiconductor chips Q1 and Q3 may be connected to the wiring patterns 30 and 40 using connectors 91 and 93.

[0099] (3) In the above-described embodiment, the first to fourth sensing wirings 141 to 144 of the semiconductor chips Q1 to Q4 may be configured to have lower impedance than the first to fourth gate control wirings 131 to 134 of the semiconductor chips Q1 to Q4. Note that, in order to make the first to fourth sensing wirings 141 to 144 have lower impedance, for example, if the first to fourth sensing wirings 141 to 144 are made of wires, this can be achieved by making the diameter of the wires larger than the diameter of the first to fourth gate control wirings 131 to 134.

[0100] In this case, in particular, by making the second sensing wiring 142 of the second semiconductor chip Q2 and the fourth sensing wiring 144 of the fourth semiconductor chip Q4 have lower impedance than the second gate control wiring 132 and the fourth gate control wiring 134, the second gate control wiring 132 of the second semiconductor chip Q2 and the fourth gate control wiring 134 of the fourth semiconductor chip Q4 become less susceptible to the influence of the current flowing through the first shortest current path A1 or the second shortest current path B1, thereby further enhancing the effect of suppressing ringing that occurs in the gate voltage and current of the semiconductor chips Q2 and Q4.

[0101] In other words, by making the second sensing wiring 142 of the second semiconductor chip Q2 and the fourth sensing wiring 144 of the fourth semiconductor chip Q4 low impedance, the voltage induced on the second gate control wiring 132 and the fourth gate control wiring 134 side is alleviated by the presence of the second and fourth sensing wirings 141, 144, thereby further enhancing the effect of suppressing ringing that occurs in the gate voltage and current of the second and fourth semiconductor chips Q2, Q4.

[0102] (4) The shapes of the first wiring pattern 10 and the third and fourth wiring patterns 30, 40 are not limited to those shown in FIG. 1, but can be appropriately made into the most suitable shapes.

[0103] (5) In the above-described embodiment, vertical MOSFETs are used as the semiconductor chips Q1 to Q4, but the present invention is not limited to vertical MOSFETs and may be horizontal MOSFETs. Furthermore, semiconductor chips other than MOSFETs may be used as the semiconductor chips Q1 to Q4. For example, SiC-MOSFETs, GaNFETs, etc. may be used. Other semiconductor chips, such as IGBTs (Insulated Gate Bipolar Transistors), may also be used. Furthermore, although the semiconductor chips Q1 to Q4 are rectangular in shape in the above-described embodiment, they may also be square in shape.

[0104] (6) In the above-described embodiment, the substrate 70 is a DCB substrate, but is not limited to a DCB substrate. For example, other ceramic substrates such as an AMB (Active Metal Brazing) substrate, or a copper-based or aluminum-based metal-based substrate, etc., can also be used as the substrate 70. Metals other than copper (e.g., aluminum) can also be used as the metal bonded to the ceramic substrate.

[0105] (7) In the above embodiment, the present invention has been described using a semiconductor module as an example, but the present invention is not limited to this. For example, the present invention can also be applied to electronic circuits manufactured using all or part of discrete electronic components. [Explanation of symbols]

[0106] 1, 2... semiconductor module, 10... first wiring pattern, 11... first side of first wiring pattern, 11a... one end (left end) of first side 11 of first wiring pattern 10, 11b... other end (right end) of first side 11 of first wiring pattern 10, 12... recess, 20... second wiring pattern, 21... first oblique side, 22... second oblique side, 23... convex portion (tapered convex portion), 30... third wiring pattern, 30a... horizontal portion of third wiring pattern 30, 30b... vertical portion of third wiring pattern 30, 31... on first oblique side 21 a fourth wiring pattern, 40a a horizontal portion of the fourth wiring pattern, 40b a vertical portion of the fourth wiring pattern, 41 a hypotenuse of the fourth wiring pattern along the second hypotenuse, 51 a power supply terminal (positive power supply terminal), 511 a first power supply terminal, 512 a second power supply terminal, 52 a ground terminal (negative power supply terminal), 61 a first midpoint terminal, 62 a second midpoint terminal, 70 a substrate, 81 to 84 a source connecting member (second electrode connecting member), 91 to 94 a connector (connecting clip), 1 11 to 114...first to fourth gate control wiring patterns, 121 to 124...first to fourth sensing wiring patterns, 131 to 134...first to fourth gate control wirings, 141 to 144...first to fourth sensing wirings, 150...outer periphery of package, C...center line of protrusion 23, A, B...shortest current path, A1...first shortest current path from first power supply terminal 511 to first midpoint terminal 61, A2...shortest current path from second midpoint terminal 62 to earth terminal 52, B1...second shortest current path from second power supply terminal 512 to second midpoint terminal 62, B2 ··· the shortest current path from the first midpoint terminal 61 to the ground terminal 52, Q1··· the first semiconductor chip, Q2··· the second semiconductor chip, Q3··· the third semiconductor chip, Q4··· the fourth semiconductor chip, a1··· the first side (first short side) of the semiconductor chips Q1 to Q4, a2··· the second side (second short side) of the semiconductor chips Q1 to Q4, b1··· the third side (first long side) of the semiconductor chips Q1 to Q4, b2··· the fourth side (second long side) of the semiconductor chips Q1 to Q4, G··· the gate electrode of the semiconductor chips Q1 to Q4, S··· the source electrode (second electrode) of the semiconductor chips Q1 to Q4, AA,BB: through current path, GT1 to GT4: first to fourth gate control terminals, ST1 to ST4: first to fourth sensing terminals,

Claims

1. first to fourth semiconductor chips each having a first electrode, a second electrode, and a gate electrode; a power supply terminal to which the first electrode of the first semiconductor chip and the first electrode of the third semiconductor chip are connected; a ground terminal to which the second electrode of the second semiconductor chip and the second electrode of the fourth semiconductor chip are connected; a first midpoint terminal to which the second electrode of the first semiconductor chip and the first electrode of the second semiconductor chip are connected; a second midpoint terminal to which the second electrode of the third semiconductor chip and the first electrode of the fourth semiconductor chip are connected; a first gate control terminal connected to the gate electrode of the first semiconductor chip via a first gate control wiring, a second gate control terminal connected to the gate electrode of the second semiconductor chip via a second gate control wiring, a third gate control terminal connected to the gate electrode of the third semiconductor chip via a third gate control wiring, and a fourth gate control terminal connected to the gate electrode of the fourth semiconductor chip via a fourth gate control wiring, a semiconductor module including a bridge circuit in which a first switching circuit having the first semiconductor chip as a high side and the second semiconductor chip as a low side and a second switching circuit having the third semiconductor chip as a high side and the fourth semiconductor chip as a low side are connected in parallel, the power supply terminal, the ground terminal, the first gate control terminal, and the third gate control terminal are arranged on one side of the semiconductor module such that the power supply terminal and the ground terminal are between the first gate control terminal and the third gate control terminal, and the power supply terminal and the ground terminal are in parallel; the first midpoint terminal, the second midpoint terminal, the second gate control terminal, and the fourth gate control terminal are arranged on the other side of the semiconductor module such that the first midpoint terminal and the second midpoint terminal are between the second gate control terminal and the fourth gate control terminal, and the first midpoint terminal and the second midpoint terminal are in parallel; A semiconductor module characterized in that, when the semiconductor module is viewed in a plane, the second gate control wiring and the fourth gate control wiring are arranged so that there are no locations adjacent to or parallel to the through current path from the power supply terminal to the earth terminal.

2. A semiconductor module characterized in that, when the semiconductor module is viewed in a plane, the first gate control wiring and the third gate control wiring are also arranged so that there are no locations adjacent to or parallel to the through current path.

3. When the semiconductor module is viewed from above, the second gate control wiring is arranged so as to intersect with a first shortest current path extending from the power supply terminal to the first midpoint terminal; 2. The semiconductor module according to claim 1, wherein the fourth gate control wiring is arranged so as to intersect with a second shortest current path extending from the power supply terminal to the second midpoint terminal.

4. the semiconductor module further includes a first sensing terminal connected to the second electrode of the first semiconductor chip via a first sensing wiring, a second sensing terminal connected to the second electrode of the second semiconductor chip via a second sensing wiring, a third sensing terminal connected to the second electrode of the third semiconductor chip via a third sensing wiring, and a fourth sensing terminal connected to the second electrode of the fourth semiconductor chip via a fourth sensing wiring; the first sensing terminal is disposed on the one side of the semiconductor module and between the power supply terminal, the ground terminal and the first gate control terminal; the second sensing terminal is disposed on the other side of the semiconductor module and between the first midpoint terminal and the second midpoint terminal and the second gate control terminal; the third sensing terminal is disposed on the one side of the semiconductor module and between the power supply terminal and the ground terminal and the third gate control terminal; 2. The semiconductor module according to claim 1, wherein the fourth sensing terminal is disposed on the other side of the semiconductor module and between the first midpoint terminal and the second midpoint terminal and the fourth gate control terminal.

5. 5. The semiconductor module of claim 4, wherein at least the second sensing wiring and the fourth sensing wiring among the first sensing wiring, the second sensing wiring, the third sensing wiring and the fourth sensing wiring have lower impedance than the second gate control wiring and the fourth gate control wiring.

6. the semiconductor module further includes first to fourth wiring patterns; the first wiring pattern is connected to the first power supply terminal and is mounted with the first semiconductor chip and the third semiconductor chip; the second wiring pattern is connected to the ground terminal; the third wiring pattern is connected to the first midpoint terminal and is mounted with the second semiconductor chip; and the fourth wiring pattern is connected to the second midpoint terminal and is mounted with the fourth semiconductor chip; In the first wiring pattern, a recessed portion that has a recessed shape when the first wiring pattern is viewed from above is formed in a predetermined range of one of a plurality of sides of the first wiring pattern, and the first semiconductor chip and the third semiconductor chip are mounted so as to sandwich the recessed portion, the second wiring pattern is surrounded on three sides by the recess of the first wiring pattern, and is disposed so that a portion of the second wiring pattern protrudes outward from an opening of the recess, and a tapered convex portion having a first oblique side and a second oblique side is formed in at least the portion of the second wiring pattern that protrudes from the recess, the third wiring pattern and the fourth wiring pattern are arranged along the first wiring pattern, the third wiring pattern has an oblique side along the first oblique side of the tapered convex portion, and the fourth wiring pattern has an oblique side along the second oblique side of the tapered convex portion, In the first semiconductor chip, the second electrodes of the first semiconductor chip are connected to the third wiring pattern via second electrode connecting members, the second semiconductor chip is disposed along the oblique side formed on the third wiring pattern, and the second electrodes of the second semiconductor chip are connected to the second wiring pattern via second electrode connecting members; In the third semiconductor chip, the second electrodes of the third semiconductor chip are connected to the fourth wiring pattern via second electrode connecting members, the fourth semiconductor chip is disposed along the oblique side formed on the fourth wiring pattern, and the second electrodes of the fourth semiconductor chip are connected to the second wiring pattern via second electrode connecting members; 4. The semiconductor module according to claim 3, wherein, when the semiconductor module is viewed in a plane, the second gate control wiring is arranged so as to intersect with the first shortest current path on the third wiring pattern, and the fourth gate control wiring is arranged so as to intersect with the second shortest current path on the fourth wiring pattern.

7. 7. The semiconductor module according to claim 6, wherein the first semiconductor chip and the third semiconductor chip are arranged on the first wiring pattern so that the extension direction of the second electrode connecting member connected to the first semiconductor chip is parallel to the extension direction of the second electrode connecting member connected to the third semiconductor chip.

8. 7. The semiconductor module according to claim 6, wherein a connector is used as the second electrode connecting member.

9. 2. The semiconductor module according to claim 1, wherein the power supply terminal includes two power supply terminals, a first power supply terminal and a second power supply terminal, and the first power supply terminal and the second power supply terminal are arranged on either side of the earth terminal, sandwiching the earth terminal therebetween.

10. 2. The semiconductor module according to claim 1, wherein the earth terminal comprises two earth terminals, a first earth terminal and a second earth terminal, and the first earth terminal and the second earth terminal are arranged on either side of the power supply terminal, sandwiching the power supply terminal therebetween.

11. first to fourth semiconductor chips each having a first electrode, a second electrode, and a gate electrode; a power supply terminal to which the first electrode of the first semiconductor chip and the first electrode of the third semiconductor chip are connected; a ground terminal to which the second electrode of the second semiconductor chip and the second electrode of the fourth semiconductor chip are connected; a first midpoint terminal to which the second electrode of the first semiconductor chip and the first electrode of the second semiconductor chip are connected; a second midpoint terminal to which the second electrode of the third semiconductor chip and the first electrode of the fourth semiconductor chip are connected; a first gate control terminal connected to the gate electrode of the first semiconductor chip via a first gate control wiring, a second gate control terminal connected to the gate electrode of the second semiconductor chip via a second gate control wiring, a third gate control terminal connected to the gate electrode of the third semiconductor chip via a third gate control wiring, and a fourth gate control terminal connected to the gate electrode of the fourth semiconductor chip via a fourth gate control wiring, an electronic circuit including a bridge circuit in which a first switching circuit having the first semiconductor chip as a high side and the second semiconductor chip as a low side and a second switching circuit having the third semiconductor chip as a high side and the fourth semiconductor chip as a low side are connected in parallel; When the electronic circuit is viewed in a plan view, the second gate control wiring and the fourth gate control wiring are arranged so that there are no locations where they are adjacent to or parallel to a through current path from the power supply terminal to the earth terminal.

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