Semiconductor integrated optical device

Abstract

To provide a semiconductor integrated optical device with high reliability.SOLUTION: A semiconductor integrated optical device includes: a first-conductivity type semiconductor layer; a first core layer placed on the first conductivity type semiconductor layer and a second core layer placed on the first-conductivity type semiconductor layer; a first protrusion portion of a first conductivity type which extends from the first-conductivity type semiconductor layer in a direction of growth of the first core layer and the second core layer, and which is formed between the first core layer and the second core layer to join the first core layer and the second core layer by a butt joint; a second-conductivity type semiconductor layer placed on the first core layer and the second core layer; and a first electrode placed on the second-conductivity type semiconductor layer so as to cover a portion above the first core layer. The second-conductivity type semiconductor layer has a first high-resistance region locally formed therein, the first high-resistance region being formed above the first protrusion portion.SELECTED DRAWING: Figure 4A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor optical integrated device. [Background technology]

[0002] Semiconductor optical integrated devices are known that integrate multiple optical functional elements. Each of the multiple optical functional elements has a different semiconductor layered structure. One method for integrating and forming different semiconductor layered structures on the same substrate is the butt joint method (hereinafter referred to as the BJ method). A known structure is a BJ where two semiconductor layered structures are connected, in which a sidewall shape control layer is formed between the two semiconductor layered structures by mass transport in a portion of the substrate (Patent Document 1). According to Patent Document 1, forming a sidewall shape control layer suppresses the occurrence of crystal defects in the semiconductor layered structure, resulting in a semiconductor optical integrated device with reduced degradation over time. It is also known that, to electrically insulate the connections between multiple optical functional elements, a high-resistance region is formed between the connections by irradiating them with protons (Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2014-82411 [Patent Document 2] Patent Publication No. 11-121787 Summary of the Invention [Problem to be solved by the invention]

[0004] As transmission speeds in optical communications increase, modulation elements, for example, are required to have high-speed response. Reducing the capacitance of semiconductor optical elements is an effective way to improve high-speed response. At the same time, the prices of semiconductor optical elements are also decreasing. Reducing element size is an effective way to satisfy both requirements. However, reducing element size leads to a decrease in the withstand voltage against electrostatic discharge (ESD), raising concerns about reduced reliability.

[0005] An object of the present invention is to provide a semiconductor optical integrated device with excellent reliability. [Means for solving the problem]

[0006] The semiconductor optical integrated element comprises a first conductivity type semiconductor layer, a first core layer arranged on the first conductivity type semiconductor layer, a second core layer arranged on the first conductivity type semiconductor layer, a first protrusion of first conductivity type extending from the first conductivity type semiconductor layer in the stacking direction of the first core layer and the second core layer and formed between the first core layer and the second core layer to butt-joint the first core layer and the second core layer, a second conductivity type semiconductor layer arranged on the first core layer and the second core layer, and a first electrode arranged on the second conductivity type semiconductor layer so as to cover the upper part of the first core layer, and a first high resistance region is formed locally in the second conductivity type semiconductor layer above the first protrusion. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is an example of a top view of a semiconductor optical integrated device according to a first embodiment. [Figure 2] 2 is a schematic cross-sectional view taken along line II-II of the semiconductor optical integrated device shown in FIG. 1. FIG. [Figure 3] FIG. 2 is a schematic cross-sectional view of the semiconductor optical integrated device shown in FIG. 1 taken along line III-III. [Figure 4A] 3 is an enlarged view of a connection portion between a semiconductor laser portion and a connection waveguide portion in the schematic cross-sectional view shown in FIG. 2. FIG. [Figure 4B]FIG. 4B is a diagram showing the impurity concentrations of the first upper optical confinement layer and the cladding layer of FIG. 4A. [Figure 5] 3 is an enlarged view of a connection portion between a connection waveguide portion and a modulator portion in the schematic cross-sectional view shown in FIG. 2. FIG. [Figure 6] FIG. 2 is a partially enlarged view of a schematic cross-sectional view taken along line II-II according to Modification 1 of the first embodiment. [Figure 7] FIG. 2 is a partially enlarged view of a schematic cross-sectional view taken along line II-II according to Modification 2 of the first embodiment. [Figure 8] FIG. 10 is a schematic cross-sectional view of a semiconductor optical integrated device according to a second embodiment. [Figure 9] 10 is an example of a top view of a semiconductor optical integrated device according to a third embodiment. [Figure 10] 10 is an enlarged view of a schematic cross-sectional view taken along line XX of the semiconductor optical integrated device shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Elements with the same reference numerals in all the drawings have the same or equivalent functions, and their repeated explanation will be omitted. Note that the size of the figures does not necessarily correspond to the magnification.

[0009] [First embodiment] FIG. 1 is a top view of a semiconductor optical integrated device according to a first embodiment. FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a schematic cross-sectional view taken along line III-III in FIG. 1. The semiconductor optical integrated device has three optical functional elements integrated on a substrate 1. The three optical functional elements are a semiconductor laser section 10, a connecting waveguide section 20, and a modulator section 30. Here, the modulator section 30 is an electro-absorption modulator, but is not limited to this. The substrate 1 is a semiconductor substrate of a first conductivity type, i.e., an n-type semiconductor substrate. The semiconductor optical integrated device has a counter electrode 2 on the back surface, a semiconductor laser electrode 3 on the front surface of the semiconductor laser section 10, and a modulator electrode 4 on the front surface of the modulator section 30. The counter electrode 2, the semiconductor laser electrode 3, and the modulator electrode 4 are metal layers. The semiconductor laser electrode 3 is disposed on a second conductivity type semiconductor layer 28 so as to cover the first core layer 11 (described later). The modulator electrode 4 is disposed on the second conductivity type semiconductor layer 28 so as to cover the upper portion of the third core layer 31 (described later). By injecting a current between the semiconductor laser electrode 3 and the counter electrode 2, the semiconductor laser section 10 oscillates continuous light. The oscillated continuous light is input to the connecting waveguide section 20 and propagates to the modulator section 30. A high-frequency electrical signal is applied between the modulator electrode 4 and the counter electrode 2. The continuous light is converted into a high-frequency optical signal in response to the applied voltage, and the signal is emitted from the end face on the modulator section 30 side. An insulating film 7 is formed on the surface of the semiconductor optical integrated device. The counter electrode 2 may be provided individually for each optical functional element. Although not shown, a low-reflection end face coating film is formed on the end face on the modulator section 30 side. A high-reflection end face coating film is formed on the end face on the semiconductor laser section 10 side. However, a low-reflection end face coating film may also be formed on the end face on the semiconductor laser section 10 side.

[0010] The semiconductor optical integrated device includes a first conductivity type semiconductor layer 18. Here, the first conductivity type semiconductor layer 18 is part of the substrate 1. The semiconductor laser section 10 includes a first core layer 11 on the first conductivity type semiconductor layer 18. The connection waveguide section 20 includes a second core layer 21 on the first conductivity type semiconductor layer 18. The modulator section 30 includes a third core layer 31 on the first conductivity type semiconductor layer 18. The first core layer 11 and the second core layer 21 are connected by a butt joint method (hereinafter referred to as BJ method). The BJ connection section has a structure in which the tip of the first core layer 11 and the tip of the second core layer 21 are butt-jointed and connected. The second core layer 21 and the third core layer 31 are connected by the BJ method. A second conductivity type cladding layer 5 and a second conductivity type contact layer 6 are formed on the first core layer 11 and the third core layer 31. A second conductivity type cladding layer 5 is formed on the second core layer 21. Hereinafter, the second conductivity type semiconductor layer disposed on the first core layer 11 will be referred to as the second conductivity type semiconductor layer 28. Here, the cladding layer 5 and the contact layer 6 constitute the second conductivity type semiconductor layer 28. The second conductivity type semiconductor layer 28 may include other layers. Note that although the cladding layer 5 has a structure common to the three optical functional elements and the contact layer 6 has a structure common to the two optical functional elements, they may also have separate structures. Here, the second conductivity type is p-type. Note that the first conductivity type may be p-type and the second conductivity type may be n-type.

[0011] As shown in FIG. 3, the semiconductor optical integrated device is a buried-type semiconductor optical integrated device in which both sides of a mesa structure are buried with semiconductor layers. The first core layer 11, cladding layer 5, and contact layer 6 form a mesa structure, and both sides of the mesa structure are covered with semiconductor buried layers 8. Here, the semiconductor buried layer 8 is a semi-insulating semiconductor layer or a laminated structure of a p-type semiconductor layer and an n-type semiconductor layer. The structure in FIG. 3 is substantially the same in the modulator section 30. The structure in FIG. 3 is also substantially the same in the connection waveguide section 20, except that the contact layer 6 and semiconductor laser electrode 3 are not provided and an insulating film 7 is placed on top of the mesa structure. Furthermore, each core layer may be a ridge type that does not have a mesa structure.

[0012] Fig. 4A shows an enlarged view of the connection portion between the semiconductor laser portion 10 and the connection waveguide portion 20. Fig. 4B is a diagram schematically showing the impurity densities of the first upper optical confinement layer 15 and the cladding layer 5 in the region immediately above the first protrusion 9. The first core layer 11 of the semiconductor laser portion 10 and the second core layer 21 of the connection waveguide portion 20 are BJ-connected.

[0013] The first core layer 11 includes a first lower-type optical confinement layer (hereinafter referred to as the first lower SCH layer) 13, an active layer 14, and a first upper SCH layer 15. The first lower SCH layer 13 has the same conductivity type as the first conductivity-type semiconductor layer 18. Here, it is an n-type layer. The active layer 14 is a multiple quantum well layer (hereinafter referred to as an MQW layer), an i-type semiconductor layer that does not intentionally contain impurities. The first upper SCH layer 15 has the same conductivity type as the second conductivity-type semiconductor layer 28, and is a p-type semiconductor layer here. Although not shown, a diffraction grating layer is included between the first upper SCH layer 15 and the cladding layer 5. The diffraction grating layer may be located between the substrate 1 and the first lower SCH layer 13. The semiconductor laser section 10 is configured to oscillate light in the 1.3 μm band or the 1.55 μm band. The semiconductor layers shown here are merely examples, and other layers may be included. Furthermore, the first lower SCH layer 13 and the first upper SCH layer 15 may be made of an i-type semiconductor that does not intentionally contain impurities.

[0014] The second core layer 21 includes a second lower SCH layer 23, a waveguide layer 24, and a second upper SCH layer 25. The second lower SCH layer 23 has the same conductivity type as the first conductivity type semiconductor layer 18. In this example, it is an n-type layer. The waveguide layer 24 is a bulk semiconductor layer and is an i-type semiconductor layer that does not intentionally contain impurities. The second upper SCH layer 25 has the same conductivity type as the second conductivity type semiconductor layer 28 and is a p-type semiconductor layer in this example. Note that the semiconductor layers shown here are merely examples, and other layers may be included. Furthermore, the second lower SCH layer 23 and the second upper SCH layer 25 may be i-type semiconductors that do not intentionally contain impurities. The second conductivity type semiconductor layer 28 is also disposed on the second core layer 21.

[0015] A first conductive type first protrusion 9 is included at least partially between the first core layer 11 and the second core layer 21. The first protrusion 9 extends from the first conductive type semiconductor layer 18 in the stacking direction of the first core layer 11 and the second core layer 21 and is formed between the first core layer 11 and the second core layer 21 to butt-joint the first core layer 11 and the second core layer 21. Specifically, the first protrusion 9 can reduce a decrease in optical coupling efficiency at the BJ connection. The first protrusion 9 is formed integrally with the first conductive type semiconductor layer 18 and has a shape that is inclined toward the semiconductor laser section 10. The first conductive type semiconductor layer 18 is part of the substrate 1 in this embodiment. Therefore, the first protrusion 9 is the same n-type semiconductor layer as the substrate 1 and is made of the same material. In this embodiment, the substrate 1 and the first protrusion 9 are n-type InP layers. A buffer layer of the same conductivity type as the substrate 1 may be formed between the substrate 1 and the first core layer 11 and the second core layer 21. In this case, the buffer layer serves as the first conductive type semiconductor layer 18. The first protrusion 9 is a recrystallized region formed by a mass transport phenomenon in part of the first conductive type semiconductor layer 18 during or before the growth of the second core layer 21, along the sidewall of the first core layer 11. The first protrusion 9 may be formed in the entire region where the first core layer 11 and the second core layer 21 contact each other. Near the first BJ connection portion 40, the second core layer 21 has an overall inclined shape along the first protrusion 9. In this embodiment, the first core layer 11 is formed first, followed by the formation of the second core layer 21, so that the first protrusion 9 is formed so as to be inclined toward the semiconductor laser portion 10. If the second core layer 21 were formed first, the first protrusion 9 would be inclined toward the connection waveguide portion 20. Although the top surface of the first core layer 11 (top surface of the first upper SCH layer 15) and the top surface of the second core layer 21 (top surface of the second upper SCH layer 25) are shown as being flush with each other in the drawing, there may be a difference in level. Also, the second core layer 21 may protrude toward the cladding layer 5 near the first BJ connection portion 40 so as to exceed the height of the flat end portion of the second upper SCH 25.

[0016] When viewed in the stacking direction of the semiconductor layers (hereinafter, first direction D1), the tip T of the first protrusion 9 is formed to a position beyond the active layer 14. In other words, the tip T reaches partway through the first upper SCH layer 15. In this specification, the region where the first protrusion 9 exists in a planar view is defined as the first BJ connection portion 40. As shown in FIG. 4A , the end of the first BJ connection portion 40 on the connection waveguide portion 20 side is the position where the first protrusion 9 begins to bulge from the first conductivity type semiconductor layer 18. On the other hand, on the semiconductor laser portion 10 side, the first protrusion 9 is not at the position where it begins to bulge from the first conductivity type semiconductor layer 18, but is at the position where it protrudes furthest toward the first core layer 11 in the direction in which the mesa structure extends (hereinafter, second direction D2).

[0017] The semiconductor optical integrated device includes a first high-resistance region 50 locally formed on the first protrusion 9. Specifically, the first high-resistance region 50 is formed on the first BJ connection portion 40. The first high-resistance region 50 is formed by implanting impurity ions into the cladding layer 5 of a second conductivity type (here, p-type). Here, hydrogen ions (protons) are implanted. Other materials include He and Si. P-type carriers in the region implanted with the impurity ions are inactivated, making this region more resistive than the region not implanted. The impurity ions are implanted from the surface side of the semiconductor multilayer (here, the contact layer 6) after the semiconductor multilayer is grown. Therefore, the interface of the region implanted with the impurity ions is not as clear as the interface of the semiconductor layer during crystal growth, and the first high-resistance region 50 is formed with a distribution. Here, the distribution refers to the distribution of resistivity. The resistivity distribution is proportional to the density (volume density) of the implanted impurity ions (here, protons). Therefore, the resistivity distribution can be roughly interpreted as the distribution of impurity ion density. Although the impurity ions are implanted as ions, they do not necessarily remain in an ionic state after being implanted into the semiconductor layer. Hereinafter, the impurity ions implanted into the semiconductor layer will be simply referred to as impurities. Furthermore, resistivity and impurity density are generally proportional, but when impurity ions are implanted at a concentration significantly higher than the carrier concentration of the semiconductor layer, the proportionality is not necessarily high (resistivity change becomes sluggish). Specifically, in the region directly above the first protrusion 9, the impurities contained in the first upper optical confinement layer 15 and the cladding layer 5 are distributed as shown in FIG. 4B. The dashed line in FIG. 4B indicates the threshold at which the semiconductor layer becomes inactive. The region where the impurity density exceeds the threshold exhibits high resistivity. As shown in FIG. 4B, in this embodiment, the center of the distribution of the first high-resistance region 50 in the first direction D1 is located below the center of the cladding layer 5 (the first protrusion 9 side, the lower side in FIG. 4B). Furthermore, in the second direction D2, the first high-resistance region 50 is centered around the tip T. Here, the center of distribution refers to the point where the impurity density is highest. In other words, in the first direction D1, the impurity density is higher in the region below the center of the cladding layer 5 than in the region above the center.In other words, the resistivity of the first high-resistance region 50 is higher in the region below the center of the cladding layer 5 than in the region above the center. In addition, in the second direction D2, the impurity density is highest near the tip T and decreases with increasing distance from the tip T. In the second direction D2, the density does not necessarily need to be highest above the tip T; it is sufficient that the density of the entire first BJ connection portion 40 is higher than that of other regions. In this embodiment, the first high-resistance region 50 is arranged not only in the first BJ connection portion 40 but also in the semiconductor laser portion 10 and the connection waveguide portion 20, but this is not limiting. For example, the first high-resistance region 50 may be arranged only in the first BJ connection portion 40, or only in the first BJ connection portion 40 and the semiconductor laser portion 10. However, if the first high-resistance region 50 extends too far toward the semiconductor laser portion 10, which is energized, an insufficient electric field may be applied to the region of the semiconductor laser portion 10 on the first BJ connection portion 40 side, potentially resulting in degradation of optical characteristics. Therefore, it is desirable that the first high resistance region 50 be within a region of 5 μm from the first BJ connection portion 40 .

[0018] To achieve a sufficiently high resistance, the impurity density is preferably equal to or greater than the carrier density of the semiconductor layer in the region to be inactivated. However, if the impurity density is sufficiently greater than the carrier density, the excessively implanted impurities may move within the semiconductor layer during other manufacturing processes and affect the characteristics. For example, the impurity density is preferably 1 to less than 10 times the carrier density.

[0019] The first high-resistance region 50 may also be disposed in the first upper SCH layer 15, the first protrusion 9, and part of the second upper SCH layer 25. However, it is preferable that the first high-resistance region 50 is not disposed in the active layer 14. Because the active layer 14 is a region into which current is injected and light is emitted, the presence of the first high-resistance region 50 may degrade the optical characteristics. Ideally, the first high-resistance region 50 is disposed only in the cladding layer 5. However, as described above, because the first high-resistance region 50 is formed by implanting impurity ions, some of the first high-resistance region 50 may also be implanted into the first core layer 11 and the second core layer 21 due to manufacturing variations. The first high-resistance region 50 has an approximately waterdrop-like shape, as shown in FIG. 4A.

[0020] [effect] The first protrusion 9 is effective in reducing the decrease in optical coupling efficiency at the first BJ connection 40. However, when we conducted electrostatic discharge (ESD) resistance tests on the semiconductor laser unit 10 using the structure described in Patent Document 1, we found that while the general specifications were met, applying a voltage exceeding the standard first resulted in crystal degradation near the first BJ connection 40. We speculate that this is due to the following mechanism: A voltage applied to the semiconductor laser electrode 3 is transmitted to the cladding layer 5 via the second-conductivity contact layer 6. This voltage is applied toward the first-conductivity-type semiconductor layer 18 (substrate 1). However, because the first protrusion 9 (particularly the tip T), which is an n-type semiconductor layer, is close to the cladding layer 5, which is a p-type layer, the voltage concentrates near the tip T. As a result, we speculate that ESD-induced crystal degradation occurs near the first protrusion 9, i.e., near the first BJ connection 40. Furthermore, it is presumed that one of the reasons why the crystal quality near the first BJ connection part 40 is poorer than that of areas distant from the first BJ connection part 40 is that the area near the first BJ connection part 40 is prone to deterioration. On the other hand, in this embodiment, the first high-resistance region 50 is arranged in the cladding layer 5 above the first protrusion part 9. This makes it possible to reduce the concentration of the electric field on the first protrusion part 9, suppressing crystal deterioration near the first BJ connection part 40 and realizing a semiconductor optical integrated device with excellent reliability.

[0021] To fully achieve the above effect, it is effective for the high-resistance region, i.e., the region into which impurities are implanted, to be located above and close to the first protrusion 9. Furthermore, in the first direction D1, the impurity density is higher below the center of the cladding layer 5, i.e., closer to the first protrusion 9. This inactivates p-type carriers in the region near the first protrusion 9, increasing the resistance, thereby sufficiently reducing voltage concentration. In other words, the resistivity directly above the first protrusion 9 is higher than in other regions, suppressing voltage concentration on the first protrusion 9. If the impurity density were higher near the top of the cladding layer 5, the voltage applied to the semiconductor laser electrode 3 would not be strong at the top of the cladding layer 5, but would spread within the cladding layer 5 toward the tip T, potentially causing voltage concentration at the tip T. Therefore, as shown in FIG. 4A, it is preferable that the impurity density be higher below the center of the cladding layer 5, as shown in FIG. 4A.

[0022] 5 shows an enlarged view of the vicinity of the connection portion between the connecting waveguide section 20 and the modulator section 30. The second core layer 21 of the connecting waveguide section 20 and the third core layer 31 of the modulator section 30 are BJ-connected.

[0023] The third core layer 31 includes a third lower SCH layer 33, an absorption layer 34, and a third upper SCH layer 35. The third lower SCH layer 33 has the same conductivity type as the first conductivity type semiconductor layer 18. Here, it is an n-type layer. The absorption layer 34 is an MQW layer, an i-type semiconductor layer that does not intentionally contain impurities. The third upper SCH layer 35 has the same conductivity type as the second conductivity type semiconductor layer 28. Here, it is a p-type semiconductor layer. The second conductivity type semiconductor layer 28 is also disposed on the third core layer 31. The modulator section 30 is an optical functional element that converts light oscillated by the semiconductor laser section 10 into a high-frequency optical signal. Note that the semiconductor layers shown here are merely examples, and other layers may be included. Furthermore, the third lower SCH layer 33 and the third upper SCH layer 35 may be i-type semiconductors that do not intentionally contain impurities.

[0024] A second protrusion 19 is included in a portion between the second core layer 21 and the third core layer 31. The second protrusion 19 extends from the first conductivity type semiconductor layer 18 in the stacking direction of the third core layer 31 and is formed between the second core layer 21 and the third core layer 31 to butt-joint the second core layer 21 and the third core layer 31. Specifically, the second protrusion 19 is formed integrally with the first conductivity type semiconductor layer 18 and has a shape that is inclined toward the modulator section 30. The first conductivity type semiconductor layer 18 is the substrate 1 in this embodiment. Therefore, the second protrusion 19 has the same first conductivity type (n-type semiconductor layer) as the substrate 1 and is made of the same material. In this embodiment, the second protrusion 19 is an n-type InP layer. Near the second BJ connection portion 42, the second core layer 21 has an overall inclined shape that follows the second protrusion 19. In this embodiment, the second core layer 21 is formed after the third core layer 31, so the second protrusion 19 is formed so as to be inclined toward the modulator section 30. If the second core layer 21 were formed first, the second protrusion 19 would be inclined toward the connecting waveguide section 20. Note that although the top surface of the second core layer 21 (top surface of the second upper SCH layer 25) and the top surface of the third core layer 31 (top surface of the third upper SCH layer 35) are shown as being flush with each other, a step may be present. In addition, the second core layer 21 may protrude toward the cladding layer 5 near the second BJ connection section 42 so as to exceed the height of the flat end of the third upper SCH 35.

[0025] When viewed in the first direction D1, the tip T2 of the second protrusion 19 is formed to a position beyond the absorption layer 34. The tip T2 reaches partway into the third upper SCH layer 35. In this specification, as in FIG. 4A , the region where the second protrusion 19 protrudes from the first conductivity-type semiconductor layer 18 (substrate 1) is defined as the second BJ connection portion 42. As shown in FIG. 5 , the end of the second BJ connection portion 42 on the connection waveguide section 20 side is the position where the second protrusion 19 begins to bulge from the first conductivity-type semiconductor layer 18. On the other hand, on the modulator section 30 side, the end is not the position where the second protrusion 19 begins to bulge from the first conductivity-type semiconductor layer 18, but the position where it protrudes furthest toward the third core layer 31 in the second direction D2.

[0026] Similar to the first BJ connection portion 40, the second BJ connection portion 42 also has a second high-resistance region 52 formed locally on the second protrusion 19. The second high-resistance region 52 has the same characteristics as the first high-resistance region 50. Therefore, in an ESD withstand voltage test in which a voltage is applied between the modulator electrode 4 and the counter electrode 2, voltage concentration on the second protrusion 19 is reduced, the ESD withstand voltage of the second BJ connection portion 42 region is improved, and a highly reliable semiconductor optical integrated device can be realized.

[0027] Note that the interface between the first high-resistance region 50 and the first high-resistance region 50 is not clear because the region is formed by implanting impurity ions. Figures 4A, 5, and subsequent figures merely show the interface between the first high-resistance region 50 and the first high-resistance region 50 for the sake of explanation.

[0028] [Variation 1] FIG. 6 is a schematic cross-sectional view of the vicinity of the first BJ connection portion 40 along line II-II according to Modification 1 of the semiconductor optical integrated device of the first embodiment. In this modification, in the first direction D1, the first high-resistance region 50 starts from a region close to the upper surface of the cladding layer 5 and is formed in a region not reaching the first core layer 11 or the second core layer 21. However, as shown in FIG. 6, the shape of the first high-resistance region 50 is roughly waterdrop-shaped, with the lower side wider than the upper side. Ideally, the first high-resistance region 50 does not reach the active layer 14, but it is preferable that it be positioned so as to contact the tip T. However, because the first high-resistance region 50 is formed by implanting impurity ions (protons), there is variation in the positional accuracy in the first direction D1. If the first high-resistance region 50 is formed so as not to reliably reach the active layer 14, the impurity ions may not reach the lower surface of the cladding layer 5. However, in the first direction D1, the impurity density in the cladding layer 5 is lower below the center of the cladding layer 5 (toward the first protrusion 9) than above. As a result, the concentration of voltage at the tip T is reduced, and a semiconductor optical integrated element with excellent ESD resistance (excellent reliability) is realized.

[0029] [Variation 2] 7 is a schematic cross-sectional view of the vicinity of the first BJ connection portion 40 along line II-II according to Modification 2 of the semiconductor optical integrated device of the first embodiment. In this modification, the first high resistance region 50 is not located in the connection waveguide portion 20 in the second direction D2. The first high resistance region 50 is located only in the first BJ connection portion 40 and the semiconductor laser portion 10. Therefore, the area in which the first high resistance region 50 is located is smaller than in the first embodiment. It goes without saying that the above-mentioned effects can also be obtained in this embodiment.

[0030] In the first embodiment, Modification 1, and Modification 2, the contact layer 6 and the semiconductor laser electrode 3 overlap with the first BJ connection portion 40 in the second direction D2. Therefore, a voltage applied to the semiconductor laser electrode 3 is likely to be applied to the first protrusion 9. If the contact layer 6 and the semiconductor laser electrode 3 are arranged so as not to overlap with the first BJ connection portion 40 (first protrusion 9), the voltage applied to the first protrusion 9 is reduced. However, because the voltage spreads inside the cladding layer 5, even if the contact layer 6 and the semiconductor laser electrode 3 do not overlap with the first BJ connection portion 40, the voltage tends to concentrate on the first protrusion 9. Of course, if the tips of the contact layer 6 and the semiconductor laser electrode 3 are spaced farther from the first BJ connection portion 40 to the extent that the voltage does not spread to the first protrusion 9, crystal degradation originating from the first BJ connection portion 40 can be reduced. However, this structure creates a region in the active layer 14 where no voltage is applied, which may affect the optical characteristics. Therefore, from the viewpoint of optical characteristics, it is preferable that the contact layer 6 and the semiconductor laser electrode 3 overlap a portion of the first BJ connection portion 40. With such a structure, the present invention improves ESD resistance and realizes a highly reliable semiconductor optical integrated device. Even if the contact layer 6 and the semiconductor laser electrode 3 do not overlap the first BJ connection portion 40, the effects of the present invention can be achieved as long as their tips are close to the first BJ connection portion 40. For example, the effects of the present invention can be achieved as long as the distance between the first BJ connection portion 40 and the tips of the contact layer 6 and the semiconductor laser electrode 3 in the second direction D2 is 5 μm or less. It goes without saying that the above explanation also applies to the second BJ connection portion 42, which is the connection point between the modulator portion 30 and the connection waveguide portion 20.

[0031] [Second embodiment] 8 is a schematic cross-sectional view taken along the mesa structure of a semiconductor optical integrated device according to the second embodiment. The difference from the first embodiment is that a third high-resistance region 254 for the purpose of electrical insulation is disposed in the connection waveguide portion 20. The first high-resistance region 50 and the second high-resistance region 52 disposed in the first BJ connection portion 40 and the second BJ connection portion 42 are the same as those in the first embodiment.

[0032] Different electrical signals are input to the semiconductor laser section 10 and the modulator section 30. However, the semiconductor laser section 10 and the modulator section 30 may be electrically connected via the cladding layer 5. Therefore, the electrical signals input to the semiconductor laser section 10 and the modulator section 30 may affect each other. Increasing the electrical insulation between the semiconductor laser section 10 and the modulator section 30 improves the characteristics of the semiconductor optical integrated device. In this embodiment, a third high-resistance region 254 is disposed in the cladding layer 5 of the connecting waveguide section 20. The third high-resistance region 254 is formed by implanting impurity ions (protons in this case), similar to the first high-resistance region 50 and the second high-resistance region 52. However, the impurity density distribution of the third high-resistance region 254 differs from that of the first high-resistance region 50 and the second high-resistance region 52 in the first direction D1. In the first direction D1, the impurity density distribution in the third high-resistance region 254 is higher above the center of the cladding layer 5 (closer to the insulating film 7) than below (closer to the second core layer 21). In other words, the resistivity of the third high-resistance region 254 is higher above the center of the cladding layer 5 than below. The voltage applied to the semiconductor laser electrode 3 and the modulator electrode 4 is higher at the upper side of the cladding layer 5. Therefore, crosstalk between two electrical signals is more likely to occur at the upper side of the cladding layer 5. By increasing the impurity density in the third high-resistance region 254 at the upper side of the cladding layer 5, crosstalk between electrical signals can be reduced and electrical insulation between the semiconductor laser section 10 and the modulator section 30 can be improved. The impurities contained in the first high-resistance region 50, the second high-resistance region 52, and the third high-resistance region 254 may be the same material or different materials. It is preferable that the impurities contained in the first high-resistance region 50 and the second high-resistance region 52 are the same material.

[0033] The third high-resistance region 254 may extend to the first BJ connection portions 40 and 42. In the second embodiment, the first high-resistance region 50 and the second high-resistance region 52 are separated from the third high-resistance region 254 in the first BJ connection portions 40 and 42. However, they may be continuous. If the second high-resistance region 52 is disposed in a region extending to the second core layer 21, a large number of impurity ions will be implanted into the cladding layer 5. These impurities may migrate during the manufacturing process. If they migrate (diffuse) to the waveguide layer 24, the active layer 14, and the absorption layer 34, they may degrade the reliability and characteristics of these layers. Therefore, it is preferable to dispose the impurities (high-resistance regions) within a range that achieves their purpose. In the second embodiment, it is preferable to dispose the first high-resistance region 50 and the second high-resistance region 52 so that the impurity density is higher on the lower side of the cladding layer 5, and the impurity density of the third high-resistance region 254 is higher on the upper side of the cladding layer 5.

[0034] [Third embodiment] Fig. 9 is a top view of a semiconductor optical integrated device according to the third embodiment. Fig. 10 is a schematic cross-sectional view taken along line XX in Fig. 9. The semiconductor optical integrated device of this embodiment has a semiconductor laser section 10 and an optical amplifier section 70 integrated on a substrate 1. In other words, it is a semiconductor optical integrated device in which two optical functional elements are integrated. The semiconductor laser section 10 has the same structure as in the first embodiment.

[0035] The optical amplifier section 70 has the function of amplifying the light emitted by the semiconductor laser section 10. The optical amplifier section 70 includes a second core layer 21B. The second core layer 21B includes a second lower SCH layer 23B, an optical amplifier layer 24B, and a second upper SCH layer 25B. The second lower SCH layer 23B is of a first conductivity type, and the second upper SCH layer 25B is of a second conductivity type. The optical amplifier layer 24B is an MQW layer. The optical amplifier section 70 includes an optical amplifier electrode 74. The semiconductor layers shown here are merely examples, and the optical amplifier section 70 may include other layers. The second lower SCH layer 23B and the second upper SCH layer 25B may be i-type semiconductors that do not intentionally contain impurities.

[0036] A first conductivity type buffer layer 360 is disposed between the substrate 1 and the first and second core layers 11 and 21B. The first conductivity type buffer layer 360 has the same conductivity type as the substrate 1, and in this case also serves as the first conductivity type semiconductor layer 318.

[0037] The first core layer 11 and the second core layer 21B are BJ-connected by a first BJ connection portion 40B including a first protrusion 9B. The first protrusion 9B is a recrystallized region in which a part of the first conductivity-type semiconductor layer 18 is formed along the sidewall of the first core layer 11 by the mass transport phenomenon, similar to the first protrusion 9 of the first embodiment.

[0038] A first high-resistance region 50B is formed in the cladding layer 5 above the first protrusion 9B. The first high-resistance region 50B serves both to reduce electric field concentration in the first protrusion 9B and to provide electrical insulation between the semiconductor laser section 10 and the optical amplifier section 70. Therefore, the impurity density distribution in the first high-resistance region 50B is higher below the cladding layer 5 in the first direction D1 than above, but the impurity density above the cladding layer 5 exceeds the threshold for inactivating the semiconductor layer. In the first direction D1, if the impurity that inactivates carriers in the cladding layer 5 is located above the first protrusion 9B and below the center of the cladding layer 5 (on the first protrusion 9B side), the electric field concentration in the first protrusion 9B can be reduced. Preferably, some of the impurity reaches the semiconductor layers below the cladding layer 5, such as the first upper SCH layer 15, the second upper SCH layer 25B, and the first protrusion 9B, to enhance the effect. However, it is preferable that no impurities are placed in the active layer 14 and the light amplification layer 24B.

[0039] In the above embodiment, the substrate is described as a conductive substrate, but this is not limiting. An insulating (including semi-insulating) substrate may also be used. When an insulating substrate is used, a first conductive type semiconductor layer (e.g., a buffer layer) is disposed between the substrate and the core layer, and the protrusions have the same conductivity type. In addition, the counter electrode is disposed on the surface on which each core layer is formed, rather than on the back side of the substrate.

[0040] The present invention provides a semiconductor optical integrated device in which multiple optical functional elements are integrated on a single substrate via butt-joint connection, achieving excellent reliability. This is achieved by providing a protrusion between the core layers of two optical functional elements and disposing a high-resistance region on top of the protrusion. The protrusion is a first-conductivity-type semiconductor layer. A second-conductivity-type semiconductor layer is disposed on top of the core layer and the protrusion, and the high-resistance region is disposed within the second-conductivity-type semiconductor layer. The high-resistance region is formed by implanting impurity ions. The impurity ions inactivate carriers in the second-conductivity-type semiconductor layer, increasing the resistivity of the implanted region. This forms the high-resistance region. The density of the impurity disposed in the second-conductivity-type semiconductor layer is higher near the core layer than farther from the core layer in the stacking direction of the semiconductor layers. The impurity may be hydrogen, helium, Si, or the like. [Explanation of symbols]

[0041] 1 board 2 Counter electrode 3. Semiconductor laser electrodes 4. Modulator Electrode 5 Cladding layer 6 Contact layer 7. Insulating film 8 Buried Layer 9, 9B 1st protrusion 19 Second protrusion 10 Semiconductor laser section 11 First core layer 13 First lower optical confinement layer 14 Active layer 15 First upper optical confinement layer 18 First conductivity type semiconductor layer 20 Connection waveguide section 21, 21B Second core layer 23, 23B Second lower optical confinement layer 24 Waveguide layer 24B Optical amplification layer 25, 25B Second upper optical confinement layer 28 Second conductivity type semiconductor layer 30 Modulator section 31 Third Core Layer 33 Third lower optical confinement layer 34 Absorbing layer 35 Third upper optical confinement layer 40, 40B 1st BJ connection part 42 Second BJ connection part 50, 50B 1st high resistance region 52 2nd high resistance region 254 3rd high resistance region 70 Optical amplifier 74 Optical amplifier electrode 360 buffer layer D1 1st direction D2 2nd direction T, T2 tip

Claims

1. a first conductivity type semiconductor layer; a first core layer disposed on the first conductivity type semiconductor layer; a second core layer disposed on the first conductive type semiconductor layer; a first conductive type first protrusion extending from the first conductive type semiconductor layer in a stacking direction of the first core layer and the second core layer, and formed between the first core layer and the second core layer to butt-joint the first core layer and the second core layer; a second conductivity type semiconductor layer disposed on the first core layer and the second core layer; a first electrode disposed on the second conductive type semiconductor layer so as to cover the first core layer from above; Equipped with a first high resistance region is formed locally in the second conductive type semiconductor layer on the first protrusion; Semiconductor optical integrated device.

2. 2. The semiconductor optical integrated device according to claim 1, The first high-resistance region is formed by disposing a first impurity in the second conductivity type semiconductor layer.

3. 3. The semiconductor optical integrated device according to claim 2, the second conductive type semiconductor layer includes a second conductive type clad layer in contact with the first core layer, The semiconductor optical device, wherein the first high resistance region is disposed in at least the cladding layer.

4. 4. The semiconductor optical integrated device according to claim 3, a density of the first impurity in the first high resistance region is higher on the side of the first protrusion than on the side of the first electrode when viewed from the center of the cladding layer in the stacking direction;

5. 4. The semiconductor optical integrated device according to claim 3, a resistivity of the first high-resistivity region on the first protrusion side is higher than that on the first electrode side when viewed from the center of the cladding layer in the stacking direction;

6. 4. The semiconductor optical integrated device according to claim 3, The first high resistance region is disposed in a part of the first protruding portion.

7. 3. The semiconductor optical integrated device according to claim 2, In a plan view, the density of the first impurity in the first high resistance region decreases with increasing distance from the first protruding portion.

8. 3. The semiconductor optical integrated device according to claim 2, the first protrusion has a tip closest to the second conductivity type semiconductor layer, a first impurity concentration in the first high resistance region being highest above the tip portion;

9. 3. The semiconductor optical integrated device according to claim 2, the first core layer is formed by stacking a first lower optical confinement layer, an active layer, and a first upper optical confinement layer in this order from the first conductivity type semiconductor layer side; The first high resistance region is disposed in a part of the first upper optical confinement layer.

10. 3. The semiconductor optical integrated device according to claim 2, the second core layer is formed by laminating a second lower optical confinement layer, a waveguide layer, and a second upper optical confinement layer in this order from the first conductivity type semiconductor layer side; The first high resistance region is disposed in a part of the second upper optical confinement layer.

11. 3. The semiconductor optical integrated device according to claim 2, The semiconductor optical integrated device, wherein the first impurity is hydrogen, helium, or silicon.

12. 3. The semiconductor optical integrated device according to claim 2, a third core layer disposed on the first conductive type semiconductor layer and on the opposite side of the core layer from the first core layer; a second protrusion of the first conductivity type extending from the first conductivity type semiconductor layer toward the stacking direction of the third core layer, and formed between the second core layer and the third core layer to butt-joint the second core layer and the third core layer; a second electrode disposed so as to cover the third core layer; Furthermore, the second conductive type semiconductor layer is also disposed on the third core layer, the second electrode is disposed on the second conductivity type semiconductor layer, a second high-resistivity region formed locally in the second conductive type semiconductor layer on the second protrusion;

13. 13. The semiconductor optical integrated device according to claim 12, The second high-resistance region is formed by disposing a second impurity in the second conductivity type semiconductor layer.

14. 13. The semiconductor optical integrated device according to claim 12, a third high-resistance region is disposed in the second conductivity type semiconductor layer on the second core layer;

15. 15. The semiconductor optical integrated device according to claim 14, The semiconductor optical integrated device, wherein the third high-resistance region is formed by disposing a third impurity in the second conductivity type semiconductor layer.

16. 16. The semiconductor optical integrated device according to claim 15, a density of the impurity in the third high resistance region is lower on the second core layer side than on the opposite side to the second core layer side when viewed from the center of the cladding layer in the stacking direction;

17. 2. The semiconductor optical integrated device according to claim 1, The first protrusion is formed integrally with the first conductive type semiconductor layer.

18. 18. The semiconductor optical integrated device according to claim 17, The first protrusion is formed of the same material as the first conductivity type semiconductor layer.

19. 14. The semiconductor optical integrated device according to claim 13, The semiconductor optical integrated device, wherein the first impurity and the second impurity are made of the same material.

20. 16. The semiconductor optical integrated device according to claim 15, The semiconductor optical integrated device, wherein the first impurity and the third impurity are the same material.

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