Chip processing system

Abstract

To provide a technique for improving workability of an operation of transferring a chip from a carrier to a device substrate.SOLUTION: A chip bonding device bonds a chip having a second device electrically connected to a first device to a device substrate having a plurality of first devices on a main surface thereof. The chip bonding device includes a first carrier holding part, a substrate holding part, a pickup part, and a mount part. The first carrier holding part holds a chip carrier having a plurality of adsorption parts for electrostatically adsorbing the chip on a surface thereof. The substrate holding part holds the device substrate. The pickup part separates the chip from the chip carrier held by the first carrier holding part. The mount part mounts the chip separated from the chip carrier by the pickup part on the device substrate held by the substrate holding part.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to a chip laminating apparatus, a chip processing system, and a chip processing method. [Background technology]

[0002] The substrate carrier described in Patent Document 1 includes a doped semiconductor substrate, multiple electrostatic field generating circuits for generating electrostatic fields, and a charging interface. Each electrostatic field generating circuit has a positive pole, a negative pole, and a bias pole. The charging interface charges or discharges each electrostatic field generating circuit, thereby turning the electrostatic field on or off.

[0003] The substrate carrier described in Patent Document 2 includes an electrical insulating layer and an electrode portion embedded in the electrical insulating layer. A portion of the electrode portion is exposed on the back surface of the substrate carrier and functions as a connection terminal connected to each switch of the voltage control unit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 9,984,913 [Patent Document 2] Japanese Patent Publication No. 2009-99674 Summary of the Invention [Problem to be solved by the invention]

[0005] One aspect of the present disclosure provides a technique for improving the workability of transferring a chip from a carrier to a device substrate. [Means for solving the problem]

[0006] A chip bonding apparatus according to one embodiment of the present disclosure bonds a chip having a second device electrically connected to a first device to a device substrate having a plurality of first devices on a main surface. The chip bonding apparatus includes a first carrier holding unit, a substrate holding unit, a pickup unit, and a mount unit. The first carrier holding unit holds a chip carrier having a plurality of suction units on its surface that electrostatically attract the chip. The substrate holding unit holds the device substrate. The pickup unit separates the chip from the chip carrier held by the first carrier holding unit. The mount unit mounts the chip separated from the chip carrier by the pickup unit onto the device substrate held by the substrate holding unit. [Effects of the Invention]

[0007] According to one aspect of the present disclosure, the workability of transferring chips from a carrier to a device substrate can be improved. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing an example of the second chip processing system. [Figure 2] Figure 2(A) is a cross-sectional view showing an example of a chip attached to a frame via tape, Figure 2(B) is a cross-sectional view showing an example of a chip carrier, and Figure 2(C) is a cross-sectional view showing an example of a chip electrostatically adsorbed to a chip carrier. [Figure 3] FIG. 3 is a plan view showing an example of the suction portions and recesses on the surface of the carrier substrate. [Figure 4] FIG. 4 is a plan view showing a modified example of the suction portion and the recessed portion on the surface of the carrier substrate. [Figure 5] FIG. 5 is a cross-sectional view showing an example of a chip arraying device. [Figure 6] FIG. 6 is a plan view showing an example of the first chip processing system. [Figure 7]Figure 7(A) is a cross-sectional view showing an example of a device substrate, Figure 7(B) is a cross-sectional view showing an example of a chip after the protective film has been removed, and Figure 7(C) is a cross-sectional view showing an example of a substrate with a chip. [Figure 8] FIG. 8 is a cross-sectional view showing an example of a tip cleaning device. [Figure 9] FIG. 9 is a cross-sectional view showing an example of a chip bonding apparatus. [Figure 10] FIG. 10 is a cross-sectional view showing an example of a gas supply pipe. [Figure 11] Figure 11(A) is a cross-sectional view showing an example of the operation of the first contact position adjustment unit, Figure 11(B) is a cross-sectional view showing an example of the operation following Figure 11(A), and Figure 11(C) is a cross-sectional view showing an example of the operation following Figure 11(B). [Figure 12] FIG. 12 is a cross-sectional view showing a modified example of the chip bonding apparatus. [Figure 13] FIG. 13 is a cross-sectional view showing a modified example of the chip carrier. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In each drawing, the same or corresponding components are denoted by the same reference numerals, and their description may be omitted. In this specification, the X-axis, Y-axis, and Z-axis directions are perpendicular to each other. The X-axis and Y-axis directions are horizontal directions, and the Z-axis direction is vertical.

[0010] 1 to 5, an example of the second chip processing system 201 will be described. As shown in FIGS. 2(A) to 2(C), the second chip processing system 201 transfers chips CP attached to a frame FR via a tape TP from the tape TP to a chip carrier 10. This rearranges the chips CP.

[0011] The processing by the second chip processing system 201 is performed before the processing by the first chip processing system 101, which will be described later. The first chip processing system 101 mounts the chip CP on the device substrate W. As a result, the first device Wb on the device substrate W and the second device CPb on the chip CP are electrically connected (see FIG. 7(C)).

[0012] Although the first chip processing system 101 and the second chip processing system 201 are provided separately in this embodiment, they may also be provided as an integrated system. For example, the chip array device 230 of the second chip processing system 201 may be incorporated into the first chip processing system 101.

[0013] 2A are carried into the second chip processing system 201. The chips CP are adhered to a tape TP, and the outer periphery of the tape TP is attached to a frame FR. The chips CP are arranged in an opening of the frame FR. The chips CP are obtained by dicing a substrate, that is, by dividing the substrate into individual pieces.

[0014] The chip CP has a base substrate CPa and a second device CPb formed on the base substrate CPa. The base substrate CPa is, for example, a silicon wafer, a compound semiconductor wafer, or a glass substrate. The second device CPb includes a semiconductor element, a circuit, or a terminal. The second device CPb is disposed on the opposite side of the base substrate CPa from the tape TP.

[0015] The second devices CPb are covered with a protective film PF before the substrate is diced. The protective film PF protects the second devices CPb, for example, when the substrate is diced. The protective film PF is singulated together with the substrate. The protective film PF is not particularly limited, but is preferably water-soluble. After dicing, the water-soluble protective film PF can be removed by supplying pure water or the like to the water-soluble protective film PF.

[0016] The chip carrier 10 shown in FIG. 2B is carried into the second chip processing system 201. The chip carrier 10 electrostatically attracts and transports a plurality of chips CP. The plurality of chips CP are transported together with the chip carrier 10. The chip carrier 10 includes a carrier substrate 20, a plurality of electrodes 30, and a plurality of operation terminals 40.

[0017] The carrier substrate 20 has a front surface 21 and a back surface 22 facing opposite to the front surface 21. The front surface 21 of the carrier substrate 20 has a plurality of adsorption portions 21a that come into contact with the chips CP and electrostatically adsorb the chips CP. The carrier substrate 20 insulates the plurality of electrodes 30 and maintains the charge supplied to each electrode 30.

[0018] The carrier substrate 20 may be provided with a capacitor (not shown). The capacitor stores an electric charge to be supplied to each electrode 30. The electric charge may be either a positive charge or a negative charge. The capacitor may also recover an electric charge discharged from each electrode 30. The capacitor is electrically connected to each electrode 30 via, for example, an operation terminal 40.

[0019] Charge may be supplied to each electrode 30 from outside the carrier substrate 20. Charge may also be discharged from each electrode 30 to outside the carrier substrate 20.

[0020] The plurality of electrodes 30 are provided on the carrier substrate 20, and generate an electrostatic attraction force for each attraction portion 21a to electrostatically attract the chip CP. An electrode 30 is provided for each attraction portion 21a. The electrodes 30 may be either monopolar or bipolar. The electrodes 30 are exposed on the surface 21 of the carrier substrate 20, but may not be exposed and may be embedded inside the carrier substrate 20.

[0021] The operation terminal 40 is provided on the carrier substrate 20, connected to the second attraction force control unit 239 (see FIG. 5) or the first attraction force control unit 139 (see FIGS. 9, 10, 11, and 12), and receives control from the second attraction force control unit 239 or the first attraction force control unit 139. Hereinafter, the first attraction force control unit 139 and the second attraction force control unit 239 may be collectively referred to as the attraction force control units 139 and 239.

[0022] The attraction force control units 139 and 239 control the attraction force by controlling the charge accumulated in the electrode 30. For example, the attraction force control units 139 and 239 control the generation or disappearance of the attraction force by controlling the supply or discharge of charge to or from the electrode 30. The attraction force is a Coulomb force or a Johnson-Rahbek force.

[0023] An attractive force is generated by the accumulation of electric charge on the electrode 30. After that, even after the connection between the operation terminal 40 and the second attractive force control unit 239 is released, the operation terminal 40 maintains the state in which electric charge is accumulated on the electrode 30, and maintains the state in which an attractive force is generated. Therefore, multiple chips CP can be transported together with the chip carrier 10.

[0024] The attraction force disappears when the charge is discharged from the electrode 30. Thereafter, it becomes possible to separate the chip CP from the chip carrier 10. Because the generation and disappearance of the attraction force are controlled by supplying and discharging the charge, the workability of transferring the chip CP can be improved compared to when an adhesive is applied and removed.

[0025] The operation terminal 40 is exposed on the rear surface 22 of the carrier substrate 20 and is connected to the suction force control units 139, 239 by wire. The operation terminal 40 and the suction force control units 139, 239 may be connected wirelessly. The operation terminal 40 may also be exposed on the front surface 21 or side surface of the carrier substrate 20.

[0026] The operation terminal 40 is provided for each suction portion 21a. Note that one operation terminal 40 may be provided in common to a plurality of suction portions 21a. It is sufficient that the suction force control units 139, 239 can control the suction force for each suction portion 21a individually.

[0027] Meanwhile, the surface 21 of the carrier substrate 20 has recesses 21b on the periphery of each of the multiple suction portions 21a that are recessed deeper than the suction portions 21a. As a result, as will be described in detail later, the side holding head 133a inserted into the recesses 21b can hold the side surface CPe of the chip CP over the entire vertical direction, as shown in FIG. 9. This allows the side surface CPe of the chip CP to be stably held, preventing the chip CP from falling. Note that in addition to the side surface CPe of the chip CP, the lower surface (second surface CPd) of the chip CP may also be supported.

[0028] The chip carrier 10 may have a through-hole 50 in the suction portion 21a that penetrates the carrier substrate 20 from the front surface 21 to the back surface 22. As a result, as will be described in detail later, as shown in Fig. 9 or 11, a push pin 136 can be inserted into the through-hole 50 and the push pin 136 can be used to push the chip CP, thereby assisting in the separation of the chip CP. Alternatively, as shown in Fig. 10, gas can be supplied from a gas supply pipe 137 to the through-hole 50, and the pressure of the gas can be used to push the chip CP, thereby assisting in the separation of the chip CP.

[0029] The electrode 30 may be arranged so as to surround the through-hole 50. One electrode 30 may be arranged in a ring shape around the through-hole 50, or multiple electrodes 30 may be arranged at intervals around the through-hole 50. The number of electrodes 30 may be three or more. By arranging the electrodes 30 so as to surround the through-hole 50, the chip CP can be electrostatically attracted stably to the attraction portion 21a.

[0030] 3, the recesses 21b may be formed in a net shape, and the adsorption portions 21a may be arranged in islands in the net of the recesses 21b. This makes it easier to discharge the cleaning liquid from the recesses 21b when supplying the cleaning liquid to the chip CP for the purpose of removing the protective film PF, as will be described in detail later, as shown in FIG.

[0031] The recesses 21b extend to the periphery of the surface 21 of the carrier substrate 20 so that the cleaning liquid can be easily discharged out of the carrier substrate 20. The depth of the recesses 21b is uniform overall, but may become deeper from the center toward the periphery of the surface 21 of the carrier substrate 20. In the latter case, the cleaning liquid can be discharged by utilizing gravity.

[0032] The suction portion 21a may be smaller than the chip CP. Compared to when the suction portion 21a is the same size as the chip CP, the positioning precision of the chip CP can be relaxed when rearranging multiple chips CP on the chip carrier 10. If the suction portion 21a is smaller than the chip CP, even if the chip CP is slightly misaligned, the chip CP will protrude from the suction portion 21a. Therefore, the side surface CPe of the chip CP can be held over the entire vertical direction.

[0033] The recess 21b may be formed along the entire periphery of the suction portion 21a as shown in Fig. 3, or may be formed along only a part of the periphery of the suction portion 21a as shown in Fig. 4. Even in the latter case, the side holding head 133a inserted into the recess 21b can hold the side surface CPe of the chip CP along the entire vertical direction, and can stably hold the side surface CPe of the chip CP.

[0034] 1, the second chip processing system 201 includes, for example, a second loading / unloading station 210, a second processing station 220, and a second control device 290. The second loading / unloading station 210 and the second processing station 220 are arranged in this order from the negative side of the X-axis to the positive side of the X-axis.

[0035] The second carry-in / out station 210 includes a mounting table 211. Cassettes C1 to C4 are mounted on the mounting table 211. Cassette C1 accommodates a chip carrier 10. Cassette C2 accommodates a chip carrier 10 with a plurality of chips CP electrostatically attracted thereto. Cassette C3 accommodates a plurality of chips CP attached to a frame FR via a tape TP. Cassette C4 accommodates a used frame FR. A used frame FR is a frame FR that remains after a plurality of chips CP have been peeled off from the tape TP. Chips CP may remain in the used frame FR.

[0036] The second transfer station 210 includes a third transfer region 212, a third carrier transfer arm 213, and a frame transfer arm 214. The third transfer region 212 is adjacent to the mounting table 211. The third carrier transfer arm 213 holds and transfers the chip carrier 10 in the third transfer region 212. The frame transfer arm 214 holds and transfers the frame FR in the third transfer region 212. The third carrier transfer arm 213 and the frame transfer arm 214 are each capable of movement in the horizontal direction (both the X-axis and Y-axis directions) and vertical direction, and of rotation about a vertical axis.

[0037] The second transfer station 210 has a drive unit (not shown) that moves or rotates the third carrier transfer arm 213 and the frame transfer arm 214. The third carrier transfer arm 213 and the frame transfer arm 214 may be mounted on the same Y-axis slider and moved simultaneously in the Y-axis direction, or may be mounted on different Y-axis sliders and moved independently in the Y-axis direction. When the third carrier transfer arm 213 and the frame transfer arm 214 are mounted on the same Y-axis slider, they may be stacked in the Z-axis direction. When the third carrier transfer arm 213 and the frame transfer arm 214 are mounted on different Y-axis sliders, the multiple Y-axis sliders are arranged with a shift in the Z-axis direction.

[0038] The third carrier transport arm 213 takes out the chip carrier 10 from the cassette C1 and transports it to the chip arrangement device 230. The third carrier transport arm 213 also takes out the chip carrier 10 with multiple chips CP electrostatically adsorbed thereto from the chip arrangement device 230 and stores it in a cassette C2. The third carrier transport arm 213 that takes out the chip carrier 10 from the cassette C1 and the third carrier transport arm 213 that stores the chip carrier 10 in the cassette C2 may be provided separately.

[0039] The frame transport arm 214 takes out a plurality of chips CP together with the frame FR from the cassette C3 and transports them to the chip arrangement device 230. The frame transport arm 214 also takes out a used frame FR from the chip arrangement device 230 and stores it in a cassette C4. The frame transport arm 214 that takes out the frame FR from the cassette C3 and the frame transport arm 214 that stores the frame FR in the cassette C4 may be provided separately.

[0040] The second processing station 220 includes a chip arrangement device 230. The chip arrangement device 230 is adjacent to the third transfer region 212. The chip arrangement device 230 rearranges the chips CP by transferring the chips CP attached to the frame FR via the tape TP from the tape TP to the chip carrier 10. As shown in FIG. 5 , the chip arrangement device 230 includes, for example, a second carrier holding unit 231, a frame holding unit 232, and a chip transport unit 233.

[0041] The second carrier holding part 231 holds the chip carrier 10. For example, the second carrier holding part 231 holds the carrier substrate 20 horizontally from below with the surface 21 of the carrier substrate 20 facing upward. The second carrier holding part 231 is capable of movement in the horizontal direction (both the X-axis direction and the Y-axis direction, or only the X-axis direction) and rotation around a vertical axis.

[0042] The frame holding part 232 holds the frame FR with multiple chips CP attached to the frame FR via tapes TP. The frame holding part 232 holds the frame FR horizontally, for example, from below. The frame holding part 232 is capable of movement in the horizontal direction (both the X-axis and Y-axis directions, or only the X-axis direction) and rotation around a vertical axis.

[0043] The chip transfer unit 233 transfers the chip CP from the tape TP provided at the opening of the frame FR held by the frame holding unit 232 to the chip carrier 10 held by the second carrier holding unit 231. The chip transfer unit 233 has a collet 233a that holds the chip CP and a collet movement mechanism 233b (see FIG. 1) that moves the collet 233a. The collet 233a vacuum-sucks the chip CP. The collet 233a can move horizontally (in both the X-axis and Y-axis directions) and vertically, and can rotate about a vertical axis.

[0044] The collet 233a holds the chip CP from the side opposite to the tape TP. The chip CP has a first surface CPc and a second surface CPd that faces the opposite direction from the first surface CPc and contacts the tape TP. A protective film PF is formed on the first surface CPc in advance, and the collet 233a holds the chip CP via the protective film PF. This prevents contact between the chip CP and the collet 233a and prevents contact scratches from occurring on the chip CP. This is particularly effective when the first surface CPc of the chip CP includes a second device CPb.

[0045] With the collet 233a holding the chip CP from above, the collet moving mechanism 233b moves the collet 233a upward, thereby peeling the chip CP from the tape TP. Thereafter, the collet moving mechanism 233b moves the collet 233a horizontally and then downward, thereby placing the chip CP on the chip carrier 10.

[0046] The chip CP is placed on the chip carrier 10 without being turned upside down. The second surface CPd of the chip CP comes into contact with the suction portion 21a on the surface 21 of the carrier substrate 20. The suction portion 21a may be smaller than the second surface CPd of the chip CP, and the second surface CPd of the chip CP may protrude from the suction portion 21a.

[0047] The chip arrangement device 230 may have a push pin 236. The push pin 236 pushes up the chip CP from below via the tape TP. The collet 233a adsorbs the chip CP pushed up by the push pin 236. By pushing up the chip CP to be separated more than the surrounding chips CP, contact between the surrounding chips CP and the collet 233a can be suppressed.

[0048] Although not shown, the chip array device 230 may have an expanding section. The expanding section radially expands the tape TP to increase the distance between adjacent chips CP. This prevents the adjacent chips CP from rubbing against each other.

[0049] The second carrier holding unit 231 is provided with, for example, a second contact terminal 238 and a second attraction force control unit 239. The second contact terminal 238 comes into contact with an operation terminal 40 of the chip carrier 10. A plurality of second contact terminals 238 are provided corresponding to the plurality of operation terminals 40. The second attraction force control unit 239 is connected to the operation terminal 40 of the chip carrier 10 via the second contact terminal 238 provided on the second carrier holding unit 231. The operation terminal 40 receives a control signal transmitted from the second attraction force control unit 239. The second attraction force control unit 239 may be provided outside the second carrier holding unit 231 or may be part of the second control device 290.

[0050] The second attraction force control unit 239 controls the attraction force while connected to the operation terminal 40 of the chip carrier 10. The second attraction force control unit 239 controls the charge accumulated in the electrode 30. The second attraction force control unit 239 controls the supply of charge to the electrode 30, thereby controlling the generation of an attraction force. The timing of supplying charge to the electrode 30 may be different for each attraction unit 21a, or may be the same for multiple attraction units 21a.

[0051] Even if the connection between the operation terminal 40 and the second suction force control unit 239 is released after the chip arrangement device 230 transfers the chip CP from the tape TP to the chip carrier 10, the operation terminal 40 maintains a state in which electric charge is accumulated in the electrode 30, and maintains a state in which an attractive force is generated. Therefore, a plurality of chips CP can be transported together with the chip carrier 10.

[0052] The second control device 290 is, for example, a computer, and includes a CPU (Central Processing Unit) 291 and a storage medium 292 such as a memory. The storage medium 292 stores programs that control various processes executed in the second chip processing system 201. The second control device 290 controls the operation of the second chip processing system 201 by having the CPU 291 execute the programs stored in the storage medium 292. A unit control unit that controls the operation of each unit constituting the second chip processing system 201 may be provided, and a system control unit that controls multiple unit control units may be provided. The unit control units and the system control unit may form the second control device 290.

[0053] Next, a description will be given of an example of a chip processing method using the second chip processing system 201. The following chip processing method is carried out under the control of the second control device 290.

[0054] First, the third carrier transport arm 213 of the second carry-in / out station 210 takes out the chip carrier 10 from the cassette C1 and transports it to the chip arrangement device 230. Once the second carrier holding part 231 of the chip arrangement device 230 holds the chip carrier 10, the third carrier transport arm 213 retreats from the chip arrangement device 230.

[0055] Furthermore, the frame transport arm 214 of the second carry-in / out station 210 takes out the frame FR together with the plurality of chips CP from the cassette C3 and transports them to the chip arrangement device 230. Once the frame holding section 232 of the chip arrangement device 230 holds the frame FR, the frame transport arm 214 retreats from the chip arrangement device 230.

[0056] Next, the chip alignment device 230 transfers the chips CP attached to the frame FR via the tape TP from the tape TP to the chip carrier 10, and rearranges the chips CP. The chip carrier 10 electrostatically attracts the plurality of chips CP.

[0057] Next, the third carrier transport arm 213 takes out the chip carrier 10 with the plurality of chips CP electrostatically adsorbed thereto from the chip arrangement device 230 and stores it in a cassette C2. Thereafter, the plurality of chips CP, while still electrostatically adsorbed to the chip carrier 10, are provided to the first chip processing system 101.

[0058] Furthermore, the frame transport arm 214 removes the used frame FR from the chip arrayer 230 and stores it in the cassette C4. The frame FR is reused.

[0059] 6 to 10, an example of the first chip processing system 101 will be described. As shown in FIGS. 7(A) to 7(C), the first chip processing system 101 separates chips CP from the chip carrier 10 and mounts the separated chips CP on a device substrate W, thereby manufacturing a chip-equipped substrate CW.

[0060] A device substrate W shown in FIG. 7(A) is loaded into the first chip processing system 101. The device substrate W has a base substrate Wa and a plurality of first devices Wb formed on the base substrate Wa. The base substrate Wa is, for example, a silicon wafer, a compound semiconductor wafer, or a glass substrate. The first devices Wb include semiconductor elements, circuits, terminals, or the like. A plurality of first devices Wb are formed on the main surface We of the device substrate W.

[0061] Although the chip carrier 10 shown in Fig. 7B may be loaded into the first chip processing system 101, in this embodiment, the chip carrier 10 shown in Fig. 2B is loaded. The chip carrier 10 electrostatically adsorbs a plurality of chips CP. The chip CP has second devices CPb electrically connected to first devices Wb on a first surface CPc.

[0062] The first surface CPc of the chip CP does not have to be covered with the protective film PF as shown in Fig. 7(B) when it is carried in, but in this embodiment it is covered with the protective film PF as shown in Fig. 2(B). The protective film PF can protect the first surface CPc of the chip CP until just before the chip CP is mounted, and can suppress the adhesion of particles and the occurrence of scratches.

[0063] 6, the first chip processing system 101 includes, for example, a first loading / unloading station 110, a first processing station 120, and a first control device 190. The first loading / unloading station 110 and the first processing station 120 are arranged in this order from the negative side of the X-axis to the positive side of the X-axis.

[0064] The first carry-in / out station 110 includes a mounting table 111. Cassettes C5 to C8 are mounted on the mounting table 111. Cassette C5 accommodates chip carriers 10 before the chips CP are separated. Cassette C6 accommodates chip carriers 10 after the chips CP have been separated. Cassette C7 accommodates device substrates W before the chips CP are mounted. Cassette C8 accommodates device substrates W after the chips CP have been mounted.

[0065] The first transfer station 110 includes a second transfer region 112, a second carrier transfer arm 113, and a second substrate transfer arm 114. The second transfer region 112 is adjacent to the mounting table 111. The second carrier transfer arm 113 holds and transfers a chip carrier 10 in the second transfer region 112. The second substrate transfer arm 114 holds and transfers a device substrate W in the second transfer region 112. The second carrier transfer arm 113 and the second substrate transfer arm 114 are each capable of movement in the horizontal direction (both in the X-axis and Y-axis directions) and vertical direction, and of rotation about a vertical axis.

[0066] The first transfer station 110 has a drive unit (not shown) that moves or rotates the second carrier transfer arm 113 and the second substrate transfer arm 114. The second carrier transfer arm 113 and the second substrate transfer arm 114 may be mounted on the same Y-axis slider and moved simultaneously in the Y-axis direction, or may be mounted on different Y-axis sliders and moved independently in the Y-axis direction. When the second carrier transfer arm 113 and the second substrate transfer arm 114 are mounted on the same Y-axis slider, they are stacked in the Z-axis direction. When the second carrier transfer arm 113 and the second substrate transfer arm 114 are mounted on different Y-axis sliders, the multiple Y-axis sliders are arranged offset in the Z-axis direction.

[0067] The second carrier transport arm 113 takes out the chip carrier 10 from the cassette C5 before the chips CP are separated, and transports it to the transition device 115. The second carrier transport arm 113 also takes out the chip carrier 10 from the transition device 115 after the chips CP have been separated, and stores it in the cassette C6. The second carrier transport arm 113 that takes out the chip carrier 10 from the cassette C5 and the second carrier transport arm 113 that stores the chip carrier 10 in the cassette C6 may be provided separately.

[0068] The second substrate transport arm 114 takes out the device substrate W before the chip CP is mounted thereon from the cassette C7 and transports it to the transition device 116. The second substrate transport arm 114 also takes out the device substrate W after the chip CP has been mounted thereon from the transition device 116 and stores it in the cassette C8. The second substrate transport arm 114 that takes out the device substrate W from the cassette C7 and the second substrate transport arm 114 that stores the device substrate W in the cassette C8 may be provided separately.

[0069] The first loading / unloading station 110 includes transition apparatuses 115, 116. The transition apparatuses 115, 116 are disposed between and adjacent to the second transfer region 112 of the first loading / unloading station 110 and the first transfer region 122 of the first processing station 120. The transition apparatuses 115, 116 may be stacked vertically to reduce the footprint of the first loading / unloading station 110.

[0070] The chip carrier 10 before the chip CP is separated is placed on the transition device 115. The chip carrier 10 after the chip CP is separated may also be placed on the transition device 115. Separate transition devices 115 may be provided before and after the chip CP is separated, or multiple transition devices 115 may be provided for each.

[0071] The device substrate W before the chip CP is mounted is placed on the transition device 116. The device substrate W after the chip CP is mounted may also be placed on the transition device 116. Separate transition devices 116 may be provided before and after the chip CP is mounted, or multiple transition devices 116 may be provided for each.

[0072] The first processing station 120 includes a first transfer region 122, a first carrier transfer arm 123, and a first substrate transfer arm 124. The first transfer region 122 extends in the X-axis direction. The first carrier transfer arm 123 holds and transfers chip carriers 10 in the first transfer region 122. The first substrate transfer arm 124 holds and transfers device substrates W in the first transfer region 122. The first carrier transfer arm 123 and the first substrate transfer arm 124 are each capable of movement in the horizontal direction (both in the X-axis and Y-axis directions) and vertical direction, and of rotation about a vertical axis.

[0073] The first processing station 120 has a drive unit (not shown) that moves or rotates the first carrier transport arm 123 and the first substrate transport arm 124. The first carrier transport arm 123 and the first substrate transport arm 124 may be mounted on the same X-axis slider and moved simultaneously in the X-axis direction, or may be mounted on different X-axis sliders and moved independently in the X-axis direction. When the first carrier transport arm 123 and the first substrate transport arm 124 are mounted on the same X-axis slider, they are stacked in the Z-axis direction. When the first carrier transport arm 123 and the first substrate transport arm 124 are mounted on different X-axis sliders, the multiple X-axis sliders are arranged offset in the Z-axis direction.

[0074] The first carrier transport arm 123 takes out the chip carrier 10 before the chips CP are separated from it from the transition device 115, and transports it to the chip bonding device 130 via the chip cleaning device 125. The first carrier transport arm 123 also takes out the chip carrier 10 after the chips CP have been separated from it from the chip bonding device 130, and transports it to the transition device 115. The first carrier transport arm 123 that transports the chip carrier 10 before the chips CP are separated from it and the first carrier transport arm 123 that transports the chip carrier 10 after the chips CP have been separated may be provided separately.

[0075] The first substrate transport arm 124 takes out the device substrate W before the chip CP is mounted thereon from the transition apparatus 116, and transports it to the chip bonding apparatus 130 via the surface modification apparatus 126 and the substrate cleaning apparatus 127. The first substrate transport arm 124 also takes out the device substrate W after the chip CP has been mounted thereon from the chip bonding apparatus 130, and transports it to the transition apparatus 116. The first substrate transport arm 124 that transports the device substrate W before the chip CP is mounted thereon and the first substrate transport arm 124 that transports the device substrate W after the chip CP has been mounted thereon may be provided separately.

[0076] The first processing station 120 includes a chip cleaning device 125, a surface modification device 126, a substrate cleaning device 127, and a chip bonding device 130. The chip cleaning device 125, the surface modification device 126, the substrate cleaning device 127, and the chip bonding device 130 are adjacent to the first transfer region 122 and are disposed on the positive Y-axis side or the negative Y-axis side of the first transfer region 122.

[0077] The chip cleaning device 125 cleans a plurality of chips CP electrostatically attracted to the chip carrier 10. After cleaning the chips CP, the chips CP are bonded to the device substrate W, thereby preventing foreign matter from getting caught. The chip cleaning device 125 may remove the protective film PF by supplying a cleaning liquid to the chips CP. If the protective film PF is water-soluble, pure water such as DIW (deionized water) is supplied as the cleaning liquid.

[0078] As shown in FIG. 8, the chip cleaning device 125 includes, for example, a carrier holding unit 141, a rotation drive unit 142, a nozzle 143, and a cup 144. The carrier holding unit 141 holds the carrier substrate 20 horizontally from below with the surface 21 of the carrier substrate 20 facing upward. The rotation drive unit 142 rotates the carrier substrate 20 together with the carrier holding unit 141. The nozzle 143 supplies cleaning liquid to the multiple chips CP. The nozzle 143 may move in a direction perpendicular to the rotation center line of the carrier holding unit 141. The cup 144 collects the cleaning liquid. The cleaning liquid collected in the cup 144 is discharged from the inside to the outside of the cup 144 by a drainage unit (not shown).

[0079] According to this embodiment, as shown in Fig. 3, the recesses 21b are formed in a net shape, and the adsorption portions 21a are arranged in island shapes in the mesh of the recesses 21b. This makes it easy to discharge the cleaning liquid from the recesses 21b when supplying the cleaning liquid to the chips CP. The recesses 21b extend to the periphery of the surface 21 of the carrier substrate 20 so that the cleaning liquid can be easily discharged outside the carrier substrate 20. The depth of the recesses 21b is uniform overall, but may become deeper from the center toward the periphery of the surface 21 of the carrier substrate 20. In the latter case, the cleaning liquid can be discharged by utilizing gravity.

[0080] The tip cleaning device 125 may have a cleaning head (not shown). The cleaning head is a brush or sponge, etc., and scrubs and cleans the plurality of tips CP. The cleaning head may apply ultrasonic waves to the liquid film formed between the plurality of tips CP. The liquid film is formed by supplying cleaning liquid from the nozzle 143.

[0081] The surface modification apparatus 126 performs plasma processing on the main surface Wc of the device substrate W. In the surface modification apparatus 126, oxygen gas, which is a processing gas, is excited to form plasma and ionized under reduced pressure, for example. The oxygen ions are irradiated onto the main surface Wc of the device substrate W, thereby modifying the main surface Wc. The processing gas is not limited to oxygen gas, and may be, for example, nitrogen gas. The surface modification apparatus 126 may also perform plasma processing on the first surfaces CPc of the chips CP on the chip carrier 10. If the diameter of the chip carrier 10 is the same as the diameter of the device substrate W, the chips CP and the device substrate W can be modified in the same surface modification apparatus 126. When the chips CP are plasma processed on the chip carrier 10, the surface modification apparatus 126 can be kept small in size compared to when the chips CP are plasma processed on the frame FR, and the manufacturing cost of the first chip processing system 101 can also be reduced. The surface modification device 126 for modifying the device substrate W and the surface modification device 126 for modifying the chip CP may be provided separately, in which case throughput can be improved.

[0082] The substrate cleaning apparatus 127 cleans the main surface Wc of the device substrate W. For example, the substrate cleaning apparatus 127 supplies pure water (e.g., deionized water) onto the device substrate W while rotating the device substrate W held on a spin chuck. The pure water spreads over the entire main surface Wc by centrifugal force, cleaning the main surface Wc. The pure water imparts OH groups to the previously modified main surface Wc. The device substrate W and the chips CP can be bonded together using hydrogen bonds between the OH groups. The substrate cleaning apparatus 127 may clean the first surfaces CPc of the chips CP on the chip carrier 10, or may impart OH groups to the first surfaces CPc of the chips CP. If the diameter of the chip carrier 10 is the same as the diameter of the device substrate W, the chips CP and the device substrate W can be cleaned in the same substrate cleaning apparatus 127. Cleaning the chips CP on the chip carrier 10 can prevent the substrate cleaning apparatus 127 from becoming too large, compared to cleaning the chips CP on the frame FR, and the manufacturing cost of the first chip processing system 101 can also be reduced. Note that the substrate cleaning apparatus 127 for cleaning the device substrate W and the substrate cleaning apparatus 127 for cleaning the chip CP may be provided separately, in which case throughput can be improved. The chip cleaning apparatus 125 may be used to clean the chip CP instead of the substrate cleaning apparatus 127. When modifying or cleaning the chip CP on the frame FR, the modification or cleaning deteriorates the tape TP, so the tape TP must be reattached to reuse the frame FR. In contrast, when modifying or cleaning the chip CP on the chip carrier 10, the modification or cleaning does not deteriorate the chip carrier 10, so the chip carrier 10 can be reused as is.

[0083] The chip bonding apparatus 130 bonds the chip CP to the device substrate W. Specifically, the chip bonding apparatus 130 separates the chip CP from the chip carrier 10 and mounts the separated chip CP on the device substrate W. A first device Wb on the device substrate W and a second device CPb on the chip CP are electrically connected. As shown in FIG. 9 , the chip bonding apparatus 130 includes, for example, a first carrier holding unit 131, a substrate holding unit 132, a pickup unit 133, and a mount unit 134.

[0084] The first carrier holding part 131 holds the chip carrier 10. For example, the first carrier holding part 131 holds the carrier substrate 20 horizontally from below with the surface 21 of the carrier substrate 20 facing upward. The first carrier holding part 131 is capable of movement in the horizontal direction (both in the X-axis direction and the Y-axis direction) and rotation around a vertical axis.

[0085] The chip carrier 10 electrostatically attracts the chip CP. When the chip CP is electrostatically attracted, the attraction force can be eliminated by discharging the electric charge. Unlike when the chip CP is fixed with an adhesive, there is no need to remove the adhesive. Therefore, the workability of transferring the chip CP from the chip carrier 10 to the device substrate W can be improved.

[0086] The substrate holding unit 132 holds the device substrate W. For example, the substrate holding unit 132 holds the device substrate W horizontally from below with the main surface Wc of the device substrate W facing upward. The substrate holding unit 132 is capable of movement in the horizontal direction (both in the X-axis direction and the Y-axis direction) and rotation around a vertical axis.

[0087] The pickup unit 133 separates the chip CP from the chip carrier 10 held by the first carrier holding unit 131. The pickup unit 133 has a side holding head 133a that holds the side surface CPe of the chip CP, and a first head moving mechanism 133b (see FIG. 6) that moves the side surface holding head 133a. The side surface holding head 133a can move horizontally (in both the X-axis and Y-axis directions) and vertically, and can rotate around a vertical axis. The side surface holding head 133a may support the underside (second surface CPd) of the chip CP in addition to the side surface CPe of the chip CP.

[0088] The side surface holding head 133a holds the side surface CPe of the chip CP. For example, the side surface holding head 133a has a pair of openable and closable claws, and holds the chip CP by sandwiching it between the pair of claws. The side surface holding head 133a may vacuum-suck the side surface CPe of the chip CP.

[0089] The side holding head 133a does not hold the first surface CPc of the chip CP, but forms a gap between the first surface CPc and the side holding head 133a, which makes it possible to prevent particles from adhering to the first surface CPc and to prevent scratches from occurring on the first surface CPc even when the protective film PF is removed and the first surface CPc is exposed.

[0090] The side holding head 133a is inserted into a recess 21b formed in the surface 21 of the carrier substrate 20. At this time, the pair of claws is opened so as not to touch the chip CP. After that, the pair of claws close to sandwich and hold the chip CP.

[0091] The side surface holding head 133a is inserted into the recess 21b to hold the side surface CPe of the chip CP over the entire vertical direction, thereby stably holding the side surface CPe of the chip CP and preventing the chip CP from falling.

[0092] Thereafter, the first head moving mechanism 133b moves the side surface holding head 133a upward. The side surface holding head 133a is extracted from the recess 21b of the carrier substrate 20. As a result, the chip CP is separated from the chip carrier 10.

[0093] Thereafter, the chip CP is transferred from the side holding head 133a to the suction head 134a. The suction head 134a suction-holds the second surface CPd of the chip CP. After being separated from the chip carrier 10, the chip CP is turned upside down and brought into contact with the device substrate W.

[0094] The mount unit 134 mounts the chip CP, which has been separated from the chip carrier 10 by the pickup unit 133, onto the device substrate W held by the substrate holding unit 132. The mount unit 134 has a suction head 134a that suction-holds the second surface CPd of the chip CP, and a second head moving mechanism 134b (see FIG. 6) that moves the suction head 134a.

[0095] The suction head 134a is capable of moving horizontally (in both the X-axis and Y-axis directions) and vertically, and of rotating about a horizontal axis (i.e., upside down). The suction head 134a picks up the chip CP from above and moves downward in that state to mount the chip CP on the main surface Wc of the device substrate W.

[0096] In this embodiment, the suction head 134a of the mount unit 134 directly receives the chip CP from the side holding head 133a of the pickup unit 133, but the chip CP may be received via a transport unit (not shown). The transport unit transports the chip CP from the pickup unit 133 to the mount unit 134. The transport unit may turn the chip CP upside down.

[0097] The chip bonding device 130 may have a push pin 136. The push pin 136 is inserted into the through hole 50 of the chip carrier 10 and pushes the chip CP, thereby assisting in separation of the chip CP. A communication hole 131a that communicates with the through hole 50 of the chip carrier 10 is formed in the first carrier holding part 131. The push pin 136 waits in the communication hole 131a and is inserted from the communication hole 131a into the through hole 50 to push the chip CP. When the push pin 136 pushes the chip CP, a pair of claws that constitute the side holding head 133a waits beside the chip CP. After the push pin 136 pushes the chip CP, the pair of claws close to hold the chip CP in place.

[0098] 10, the chip bonding apparatus 130 may have a gas supply pipe 137 instead of the push pin 136. The gas supply pipe 137 supplies gas to the through hole 50 of the chip carrier 10 and pushes the chip CP with the gas pressure, thereby assisting in separation of the chip CP. A communication hole 131a that communicates with the through hole 50 of the chip carrier 10 is formed in the first carrier holding part 131. The gas supply pipe 137 supplies gas to the through hole 50 via the communication hole 131a.

[0099] The gas supply pipe 137 has a plurality of individual pipes 137a that individually supply gas to the plurality of through holes 50. An on-off valve 137b is provided midway through each of the plurality of individual pipes 137a. When the plurality of chips CP are individually separated, the separation of each chip CP can be assisted by individually controlling the plurality of on-off valves 137b.

[0100] The first carrier holding unit 131 is provided with, for example, a first contact terminal 138 and a first attraction force control unit 139. The first contact terminal 138 comes into contact with an operation terminal 40 of the chip carrier 10. A plurality of first contact terminals 138 are provided corresponding to the plurality of operation terminals 40. The first attraction force control unit 139 is connected to the operation terminal 40 of the chip carrier 10 via the first contact terminal 138 provided on the first carrier holding unit 131. The operation terminal 40 receives a control signal transmitted from the first attraction force control unit 139. The first attraction force control unit 139 may be provided outside the first carrier holding unit 131 or may be part of the first control device 190.

[0101] The first attraction force control unit 139 controls the attraction force while connected to the operation terminal 40 of the chip carrier 10. The first attraction force control unit 139 controls the charge accumulated in the electrode 30. The first attraction force control unit 139 controls the discharge of the charge from the electrode 30, thereby eliminating the attraction force.

[0102] The first attraction force control unit 139 performs control to eliminate the attraction force for the chip CP to be separated from the chip carrier 10, while maintaining the attraction force for the remaining chip CP. The timing of supplying electric charge to the electrode 30 differs for each attraction unit 21a. As a result, when one chip CP is separated from the chip carrier 10, the remaining chip CP can be electrostatically attracted to the chip carrier 10, and the remaining chip CP can be prevented from falling due to contact with the side holding head 133a.

[0103] 11, the chip bonding device 130 may include a first contact position adjustment unit 135 that moves the chip carrier 10 relatively to the first carrier holding unit 131, thereby bringing multiple operation terminals 40 into contact with one first contact terminal 138 in sequence. This can accommodate multiple chip carriers 10 with different pitches of the operation terminals 40. The first contact position adjustment unit 135 moves the chip carrier 10, but it may also move the first carrier holding unit 131. Note that a push pin 136 is inserted into the through hole 50 of the chip carrier 10, but a gas supply pipe 137 may supply gas.

[0104] Although not shown, the chip arraying device 230 may include a second contact position adjustment unit that moves the chip carrier 10 relatively to the second carrier holding unit 231, thereby bringing the operation terminals 40 into contact with one second contact terminal 238 in sequence. The second contact position adjustment unit moves the chip carrier 10, but may also move the second carrier holding unit 231.

[0105] The first control device 190 (see FIG. 6) is, for example, a computer, and includes a CPU (Central Processing Unit) 191 and a storage medium 192 such as a memory. The storage medium 192 stores programs that control various processes executed in the first chip processing system 101. The first control device 190 controls the operation of the first chip processing system 101 by having the CPU 191 execute the programs stored in the storage medium 192. A unit control unit that controls the operation of each unit constituting the first chip processing system 101 may be provided, and a system control unit that controls multiple unit control units may be provided. The unit control units and the system control unit may form the first control device 190.

[0106] Next, a description will be given of an example of a chip processing method using the first chip processing system 101. The following chip processing method is carried out under the control of the first control device 190.

[0107] First, the second carrier transport arm 113 of the first load / unload station 110 removes the chip carrier 10 from the cassette C5 before the chips CP are separated and transports it to the transition device 115. Next, the first carrier transport arm 123 of the first processing station 120 removes the chip carrier 10 from the transition device 115 before the chips CP are separated and transports it to the chip cleaning device 125. Next, the chip cleaning device 125 cleans the multiple chips CP to remove the protective film PF. Thereafter, the first carrier transport arm 123 removes the chip carrier 10 from the chip cleaning device 125 before the chips CP are separated and transports it to the chip bonding device 130. Along the way, the first carrier transport arm 123 may transport the chip CP together with the chip carrier 10 to the surface modification device 126 and the substrate cleaning device 127. OH groups can be added to the bonding surfaces of the chips CP, and the chips CP and the device substrate W can be firmly bonded by hydrogen bonding between the OH groups.

[0108] In parallel with the above process, the following process is performed. First, the second substrate transport arm 114 of the first carry-in / out station 110 takes out the device substrate W, on which the chips CP have not yet been mounted, from the cassette C7 and transports it to the transition device 116. Next, the first substrate transport arm 124 of the first processing station 120 takes out the device substrate W, on which the chips CP have not yet been mounted, from the transition device 116 and transports it to the surface modification device 126. Next, the surface modification device 126 plasma-treats the main surface Wc of the device substrate W. Thereafter, the first substrate transport arm 124 takes out the device substrate W from the surface modification device 126 and transports it to the substrate cleaning device 127. Next, the substrate cleaning device 127 cleans the main surface Wc of the device substrate W. Thereafter, the first substrate transport arm 124 takes out the device substrate W from the substrate cleaning device 127 and transports it to the chip bonding device 130.

[0109] Next, the chip bonding device 130 separates the chip CP from the chip carrier 10 and mounts the separated chip CP on the device substrate W, thereby manufacturing the chip-attached substrate CW shown in Fig. 7(C). The first device Wb of the device substrate W and the second device CPb of the chip CP are electrically connected to each other.

[0110] Thereafter, the first substrate transport arm 124 takes out the device substrate W after the chip CP has been mounted from the chip bonding apparatus 130 and transports it to the transition apparatus 116. Next, the second substrate transport arm 114 of the first carry-in / out station 110 takes out the device substrate W after the chip CP has been mounted from the transition apparatus 116 and stores it in the cassette C8.

[0111] Furthermore, the first carrier transport arm 123 takes out the chip carrier 10 from which the chip CP has been separated, from the chip bonding device 130, and transports it to the transition device 115. Next, the second carrier transport arm 113 of the first carry-in / out station 110 takes out the device substrate W from which the chip CP has been separated, from the transition device 115, and stores it in a cassette C6.

[0112] Next, a modified example of the chip bonding apparatus 130 will be described with reference to FIG. 12. Differences will be mainly described below. As shown in FIG. 12, the chip bonding apparatus 130 may bond multiple chips CP, CP2 having different functions to a device substrate W. Two chips CP, CP2 are electrically connected to one first device Wb. The two chips CP, CP2 are different devices, i.e., have different electrical circuits. The device substrate W has multiple first devices Wb, and two chips CP, CP2 are electrically connected to each of the multiple first devices Wb. Note that the number of chips electrically connected to one first device Wb may be three or more. Three or more chips electrically connected to one first device Wb may have different electrical circuits.

[0113] The chip bonding device 130 includes, for example, a first carrier holding unit 131, a substrate holding unit 132, a pickup unit 133, and a mount unit 134. The first carrier holding unit 131 holds a chip carrier 10. The chip carrier 10 electrostatically attracts and transports multiple chips CP, CP2 having different functions. The multiple chips CP, CP2 are transported together with the chip carrier 10.

[0114] As shown in FIG. 13, the carrier substrate 20 has a front surface 21 and a back surface 22 facing opposite to the front surface 21. The front surface 21 of the carrier substrate 20 has a plurality of suction portions 21a. The suction portions 21a that electrostatically suction the chip CP and the suction portions 21a that electrostatically suction the chip CP2 may have different dimensions or shapes. The suction portions 21a that electrostatically suction the chip CP2 are formed smaller than the chip CP2. When arranging a plurality of chips CP2 on the chip carrier 10, the positioning accuracy of the chip CP2 can be relaxed.

[0115] The surface 21 of the carrier substrate 20 has recesses 21b around the periphery of each of the multiple suction portions 21a that are recessed deeper than the suction portions 21a. As a result, as shown in FIG. 12, the side holding head 133a inserted into the recesses 21b can hold the side surface CP2e of the chip CP2 over the entire vertical direction. This allows the side surface CP2e of the chip CP2 to be stably held, preventing the chip CP2 from falling. Note that in addition to the side surface CP2e of the chip CP2, the lower surface (second surface CP2d) of the chip CP2 may also be supported.

[0116] As shown in FIG. 12, the pickup unit 133 has a side holding head 133a. The side holding head 133a that holds the side surface CP2e of the chip CP2 and the side holding head 133a that holds the side surface CPe of the chip CP may have different dimensions or shapes and may be provided separately. Multiple side holding heads 133a may be attached to a single rotating holder and rotate together with the rotating holder. Multiple side holding heads 133a may be provided, and control may be performed to switch the side holding head 133a to be used depending on the dimensions or shape of the chips CP and CP2.

[0117] The chip bonding device 130 sequentially separates a plurality of chips CP having the same function from the chip carrier 10 one by one and bonds them to the device substrate W. Thereafter, the chip bonding device 130 sequentially separates a plurality of chips CP2 having the same function one by one from the chip carrier 10 and bonds them to the device substrate W. When switching the side holding head 133a to be used depending on the dimensions or shapes of the chips CP and CP2, the number of switching operations can be reduced.

[0118] Although not shown, the pickup unit 133 may have a suction head that holds the first surfaces CPc and CP2c of the chips CP and CP2 in a non-contact manner. The suction head suctions the first surfaces CPc and CP2c of the chips CP and CP2 while leaving a gap between the suction head and the chips CP and CP2. The suction head may be, for example, an ultrasonic or Bernoulli type. The ultrasonic type utilizes the squeeze effect caused by ultrasonic vibrations, while the Bernoulli type utilizes the Bernoulli effect. The ultrasonic type can suppress horizontal deviation more effectively than the Bernoulli type.

[0119] The mount unit 134 mounts the chips CP and CP2, which have been separated from the chip carrier 10 by the pickup unit 133, onto the device substrate W held by the substrate holder 132. The mount unit 134 has a suction head 134a. The suction head 134a suctions and holds the second surface CP2d of the chip CP2. The suction head 134a suctioning and holding the second surface CP2d of the chip CP2 and the suction head 134a holding the second surface CPd of the chip CP may have different dimensions or shapes, and may be provided separately. Multiple suction heads 134a may be attached to a single rotating holder and rotate together with the rotating holder. Multiple suction heads 134a may be provided, and control may be performed to switch the suction head 134a to be used depending on the dimensions or shape of the chips CP and CP2.

[0120] The chip bonding device 130 sequentially separates a plurality of chips CP having the same function from the chip carrier 10 one by one and bonds them to the device substrate W. Thereafter, the chip bonding device 130 sequentially separates a plurality of chips CP2 having the same function one by one from the chip carrier 10 and bonds them to the device substrate W. When switching the suction head 134a to be used depending on the dimensions or shapes of the chips CP and CP2, the number of switching operations can be reduced.

[0121] 12, the chips CP and CP2 may be arranged in the same arrangement when they are electrostatically attracted to the chip carrier 10 and when they are attached to the device substrate W. This makes it possible to equalize the time required to separate the chips CP and CP2 from the chip carrier 10 and attach them to the device substrate W (the time required to manufacture the chip-attached substrate CW), thereby enabling consistent quality control of the chip-attached substrate CW.

[0122] As described above, one chip carrier 10 may electrostatically attract and transport multiple chips CP, CP2 with different functions. In this case, the chip arrangement device 230 transfers the multiple chips CP, CP2 with different functions from tapes prepared for each function of the chips CP, CP2 onto one chip carrier 10. The chips CP and CP2 are attached to different frames via different tapes, and are transferred onto one chip carrier 10.

[0123] It should be noted that chip carriers 10 may be prepared according to the functions of the chips CP and CP2. The chip carrier 10 that electrostatically attracts the chip CP and the chip carrier 10 that electrostatically attracts the chip CP2 may be prepared separately and transported in order to the chip bonding apparatus 130. In this case as well, the chip bonding apparatus 130 can bond a plurality of chips CP and CP2 having different functions to the device substrate W.

[0124] The following notes are provided regarding the above embodiment. [Appendix 1] A chip arraying device that arrays a plurality of chips on a chip carrier having a plurality of suction portions on a surface thereof that electrostatically suction the chips, a second carrier holding portion that holds the chip carrier; a frame holder that holds the frame with the plurality of chips attached to the frame via tape; a chip transfer unit that transfers the chip from the tape provided at the opening of the frame held by the frame holding unit to the chip carrier held by the second carrier holding unit; A chip arraying device comprising:

[0125] [Appendix 2] the chip has a first surface and a second surface facing opposite to the first surface and in contact with the tape; a protective film is formed in advance on the first surface of the chip; 2. The chip arrangement device according to claim 1, wherein the chip transport unit has a collet that holds the chip via the protective film, and a collet movement mechanism that moves the collet.

[0126] [Appendix 3] the chip carrier comprises: a carrier substrate having the front surface and a back surface facing opposite to the front surface; a plurality of electrodes provided on the carrier substrate for individually generating, for each of the suction portions, an attraction force for electrostatically attracting the chip; and an operation terminal provided on the carrier substrate and connected to a second attraction force control portion for controlling the attraction force; The chip alignment device according to claim 1 or 2, further comprising the second suction force control unit.

[0127] [Appendix 4] a second contact terminal provided in the second carrier holding portion and in contact with the operation terminal; 4. The chip arrangement device according to claim 3, wherein the second suction force control unit is connected to the operation terminal via the second contact terminal.

[0128] [Appendix 5] A chip arrangement device as described in Appendix 4, comprising a second contact position adjustment unit that moves the chip carrier relative to the second carrier holding unit, thereby sequentially contacting multiple operation terminals with one second contact terminal.

[0129] [Appendix 6] A chip processing method, comprising arranging a plurality of chips on a chip carrier having a plurality of suction portions on a surface thereof for electrostatically suctioning the chips, holding the chip carrier with a second carrier holding portion; holding the frame with a frame holding part in a state in which the plurality of chips are attached to the frame via tape; transferring the chip from the tape provided at the opening of the frame held by the frame holding part to the chip carrier held by the second carrier holding part; A chip processing method comprising:

[0130] Although the embodiments of the chip bonding apparatus, chip processing system, and chip processing method according to the present disclosure have been described above, the present disclosure is not limited to the above embodiments. Various changes, modifications, substitutions, additions, deletions, and combinations are possible within the scope of the claims. These naturally fall within the technical scope of the present disclosure.

[0131] This application claims priority based on Patent Application No. 2022-038103, filed with the Japan Patent Office on March 11, 2022, and the entire contents of Patent Application No. 2022-038103 are incorporated herein by reference. [Explanation of symbols]

[0132] 10 Chip Carriers 21 Surface 21a Adsorption part 130 Chip bonding device 131 First carrier holding part 132 Board holding part 133 Pickup section 134 Mounting section CP Chip CPb Second Device CPc front page CPd Side 2 W device substrate Wb 1st device Wc main surface

Claims

1. 1. A chip bonding apparatus that bonds a chip having a second device electrically connected to a device substrate having a plurality of first devices on a main surface thereof, the chip bonding apparatus comprising: a first carrier holder for holding a chip carrier having a plurality of adsorption portions on its surface for electrostatically adsorbing the chip; a substrate holder for holding the device substrate; a pickup unit that separates the chip from the chip carrier held by the first carrier holding unit; a mount unit that mounts the chip separated from the chip carrier by the pickup unit onto the device substrate held by the substrate holding unit; A chip bonding apparatus comprising:

2. the chip carrier comprises: a carrier substrate having the front surface and a back surface facing opposite to the front surface; a plurality of electrodes provided on the carrier substrate for individually generating, for each of the suction portions, an attraction force for electrostatically attracting the chip; and an operation terminal provided on the carrier substrate and connected to a first attraction force control portion for controlling the attraction force; the surface of the carrier substrate has a recessed portion on a periphery of each of the plurality of suction portions that is recessed deeper than the suction portion; 2. The chip bonding apparatus according to claim 1, wherein the pickup unit has a side holding head that is inserted into the recess and holds a side surface of the chip, and a first head moving mechanism that moves the side holding head.

3. the chip carrier has a through-hole in the suction portion that penetrates the carrier substrate from the front surface to the back surface; The chip bonding apparatus according to claim 2 , further comprising a push pin that is inserted into the through-hole and pushes the chip.

4. the chip carrier has a through-hole in the suction portion that penetrates the carrier substrate from the front surface to the back surface; The chip bonding apparatus according to claim 2 , further comprising a gas supply pipe for supplying gas to the through-hole.

5. the chip bonding apparatus includes the first suction force control unit, A chip bonding apparatus as described in any one of claims 2 to 4, wherein the first suction force control unit controls to eliminate the suction force on the chip that is scheduled to be separated from the chip carrier and to maintain the suction force on the remaining chips.

6. a first contact terminal provided on the first carrier holding portion and contacting the operation terminal of the chip carrier; 5. The chip bonding apparatus according to claim 2, wherein the first suction force control section is connected to the operation terminal via the first contact terminal.

7. The chip bonding apparatus according to claim 6, further comprising a first contact position adjustment unit that moves the chip carrier relative to the first carrier holding unit to sequentially contact the plurality of operation terminals with one of the first contact terminals.

8. a chip bonding apparatus according to any one of claims 1 to 4; a chip cleaning apparatus that removes a protective film that has been formed in advance on the chip that is electrostatically attracted by the chip carrier; a first transport area adjacent to the chip bonding apparatus and the chip cleaning apparatus; and a first carrier transport arm that transports the chip carrier in the first transport area, The first carrier transport arm transports the chip carrier from the chip cleaning device to the chip bonding device.

9. a chip bonding apparatus according to any one of claims 1 to 4, a surface modification apparatus that plasma-treats the main surface of the device substrate, a substrate cleaning apparatus that supplies water to the plasma-treated main surface, a first transfer area adjacent to the chip bonding apparatus, the surface modification apparatus, and the substrate cleaning apparatus, and a first substrate transfer arm that transfers the device substrate in the first transfer area; a chip processing system, wherein the first substrate transport arm transports the device substrate to the surface modification device, the substrate cleaning device, and the chip bonding device in this order;

10. 1. A chip processing method, comprising: bonding a chip having a second device electrically connected to a device substrate having a plurality of first devices on a main surface thereof, the chip including: A chip processing method in which attaching the chip to the device substrate includes holding a chip carrier having a plurality of adsorption portions on its surface that electrostatically adsorb the chip with a first carrier holding portion, holding the device substrate with a substrate holding portion, separating the chip from the chip carrier held by the first carrier holding portion, and mounting the chip separated from the chip carrier on the device substrate held by the substrate holding portion.

11. the chip carrier comprises: a carrier substrate having the front surface and a back surface facing opposite to the front surface; a plurality of electrodes provided on the carrier substrate for individually generating, for each of the suction portions, an attraction force for electrostatically attracting the chip; and an operation terminal provided on the carrier substrate and connected to a first attraction force control portion for controlling the attraction force; the surface of the carrier substrate has a recessed portion on a periphery of each of the plurality of suction portions that is recessed deeper than the suction portion; The chip processing method of claim 10, wherein separating the chip from the chip carrier comprises inserting a side holding head that holds the side of the chip into the recess on the surface of the carrier substrate without touching the chip, holding the side of the chip with the side holding head inserted into the recess, and removing the side holding head from the recess.

12. a through-hole penetrating the carrier substrate from the front surface to the back surface is formed in the suction portion; The chip processing method according to claim 11 , wherein separating the chip from the chip carrier comprises inserting a push pin into the through-hole and pushing the chip with the push pin.

13. a through-hole penetrating the carrier substrate from the front surface to the back surface is formed in the suction portion; The chip processing method according to claim 11 , wherein separating the chip from the chip carrier comprises supplying a gas to the through-hole and pushing the chip with the pressure of the gas.

14. A chip processing method according to any one of claims 11 to 13, wherein separating the chip from the chip carrier includes causing the first suction force control unit to eliminate the suction force on the chip that is scheduled to be separated from the chip carrier, while maintaining the suction force on the remaining chips.

15. A chip processing method according to any one of claims 11 to 13, comprising contacting a first contact terminal provided on the first carrier holding portion with the operation terminal of the chip carrier, thereby connecting the operation terminal with the first suction force control portion via the first contact terminal.

16. 16. The chip processing method according to claim 15, further comprising moving the chip carrier relatively to the first carrier holding portion to sequentially bring the plurality of operation terminals into contact with one of the first contact terminals.

17. A chip processing method according to any one of claims 10 to 13, further comprising removing a protective film pre-formed on the chip electrostatically adsorbed by the chip carrier before bonding the chip to the device substrate.

18. plasma-treating the main surface of the device substrate before bonding the chip to the device substrate; supplying water to the plasma-treated main surface before bonding the chip to the device substrate; The chip processing method according to any one of claims 10 to 13, comprising:

19. arranging a plurality of the chips on the chip carrier before bonding the chips to the device substrate; A chip processing method according to any one of claims 10 to 13, wherein arranging the plurality of chips comprises holding the chip carrier with a second carrier holding portion, holding the frame with a frame holding portion with the plurality of chips attached to the frame via tape, and transferring the chips from the tape provided at an opening of the frame held by the frame holding portion to the chip carrier held by the second carrier holding portion.

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