Module in which fan-out type wafer level packaging unit is wire-bonded to electronic member

Abstract

To provide a module in which a FOWLP unit effectively solving a problem where manufacturing cost is high when each conductive wire is manufactured and environmental protection is disadvantageous in a conventional FOWLP technique of a module is wire-bonded onto an electronic member.SOLUTION: A module in which a FOWLP unit is wire-bonded onto an electronic member includes the FOWLP unit, the electronic member, and at least one first bonding wire and at least two second bonding wires. The FOWLP unit includes a carrier, at least two dies, a first dielectric layer, a second dielectric layer, a plurality of conductive wires, an outside protective layer and a plurality of welding pads. Each of the conductive wires is composed of a metal paste filled into a plurality of first grooves of the first dielectric layer and a plurality of second grooves of the second dielectric layer, and at least the one welding pad is located around a chip region of a second surface of each of the dies and is electrically connected to the outside.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a module, and more particularly to a module in which Fan-Out Wafer Level Packaging (FOWLP) units are wire-bonded to electronic components. [Background technology]

[0002] Packaging technology that is light, thin, short, small, highly efficient and highly reliable is the trend in the development of the semiconductor industry, among which FOWLP is a conventional packaging technology.

[0003] In advanced FOWLP packaging, the redistribution layer (RDL) is the most important element. Each conductive line in the RDL provides electrical expansion and interconnection in the XY plane to multiple pads on the die, allowing for multiple, more dispersed pads around each die, effectively improving the design space and reliability of each conductive line. However, the most important factor in the fabrication of each conductive line in the RDL is how to achieve the electrical expansion and interconnection in the XY plane while maintaining or achieving a certain degree of lightness, thinness, and compactness. However, in conventional RDL technology, where FOWLP packaging technology is applied, conductive lines are formed using chemical plating or electroplating techniques. In addition to relatively high material and production costs, the conventional technology processes do not meet or are unfavorable to environmental protection requirements. Furthermore, when using FOWLP to provide products with higher performance or more functions, at least two dies are usually installed on the FOWLP and integrated via the RDL to form a multi-chip type fan-out wafer-level packaging unit. At this time, the design space requirements for each conductive line of the RDL in the FOWLP increase relatively, and the manufacturing technology for each conductive line of the RDL also becomes relatively important.

[0004] In addition, when FOWLP is used in the manufacture of module products, it is usually integrated into the FOWLP via RDL to form a FOWLP unit, and then the FOWLP unit is combined with electronic components to form a module. At this time, the material and manufacturing costs of the product increase relatively, and the manufacturing technology of each conductive line in the RDL also becomes relatively more important. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2024-80601 Summary of the Invention [Problem to be solved by the invention]

[0006] The objective of the present invention is to provide a module in which the FOWLP unit is wire-bonded onto an electronic component, the FOWLP unit including: a FOWLP unit, an electronic component, at least one first bonding wire and at least two second bonding wires; the FOWLP unit including a carrier, at least two dies, a first dielectric layer, a second dielectric layer, a plurality of conductive lines, an outer protective layer, and a plurality of welding pads, each of the conductive lines being formed by a metal paste filled in a plurality of first grooves in the first dielectric layer and a plurality of second grooves in the second dielectric layer; and at least one welding pad being located around a chip area on a second surface of each of the dies for electrical connection to the outside, thereby effectively solving the problems of the conventional FOWLP technology for modules, which result in high manufacturing costs and are unfriendly to the environment when manufacturing each conductive line. [Means for solving the problem]

[0007] In order to achieve the above object, the present invention provides a module in which a FOWLP unit is wire-bonded to an electronic component, the module including a carrier, at least two dies, a first dielectric layer, a second dielectric layer, a plurality of conductive lines, an outer protective layer, a plurality of welding pads, an electronic component, at least one first bonding wire, and at least two second bonding wires, the carrier having a first surface and an opposite second surface, each of the dies being separated from the same or different wafers, and each The dies are arranged side by side on the second surface of the carrier in parallel and spaced apart relation, each die having a first surface and an opposing second surface, the first surface of each die being fixed on the carrier, the second surface of each die having a plurality of pads, a vertical extent of a chip on the second surface being defined as a chip area, the first dielectric layer being arranged on the second surface of the carrier and the second surface of each of the dies, the first dielectric layer having a plurality of first grooves extending horizontally, the pads of each of the dies being exposed to the outside by each of the first grooves. the second dielectric layer is disposed on the first dielectric layer, the second dielectric layer has a plurality of second grooves extending horizontally, each of the second grooves being connected to each of the first grooves, each of the conductive lines being formed by a metal paste filled in each of the first grooves and each of the second grooves, each of the conductive lines being electrically connected to the pads of each of the dies; the outer protective layer is disposed on the second dielectric layer and has a plurality of openings, at least two of the openings being located around the chip area on the second surface of each of the dies, and each of the conductive lines is The second surface of the electronic component is exposed to the outside through the openings, and the welding pads are metal structures having a certain thickness formed in the openings of the outer protective layer and electrically connected to the conductive lines. The dies can be electrically connected to the outside through the pads, the conductive lines, and the welding pads located around the chip area of ​​the second surface of each die, forming a FOWLP unit. The electronic component has a first surface for mounting the first surface of the carrier, and the first bonding wires are wire bonding.forming first and second solder joints on the weld pads of each of the dies by a wire bonding process, forming electrical connections to each of the dies of the FOWLP unit; each of the second bonding wires forming third solder joints on the weld pads around the chip area by the wire bonding process, and forming fourth solder joints on the first surface of the electronic component, electrically connecting each of the dies of the FOWLP unit and the electronic component; The first bonding wires and the second bonding wires are simultaneously formed by the wire bonding process. The manufacturing method of the module includes step S1 of providing a carrier, the carrier having a first surface and a second surface opposite to the first surface, and arranging a plurality of dies separated from the same wafer or different wafers on the second surface of the carrier in parallel and spaced relation, each of the dies having a second surface opposite to the first surface, the first surface of each of the dies being disposed on the carrier, the second surface of each of the dies having a plurality of pads, Step S2 defines the vertical extent of the chip on the second surface as a chip area; Step S3 arranges a first dielectric layer on the second surface of the carrier and each of the dies; Step S4 forms a plurality of first grooves extending horizontally on the first dielectric layer, allowing each pad of each of the dies to be exposed to the outside from each of the first grooves; Step S5 arranges a second dielectric layer on the first dielectric layer; Step S6 forms a plurality of second grooves extending horizontally on the second dielectric layer, each of the second grooves being capable of communicating with each of the first grooves; Step S7: filling a metal paste to make the thickness of the metal paste higher than the surface of the second dielectric layer; Step S8: polishing the metal paste higher than the surface of the second dielectric layer to make the surface of the metal paste flush with the surface of the second dielectric layer to form a plurality of conductive lines; Step S9: arranging an outer protective layer on the second dielectric layer; and Step S9: forming a plurality of openings in the outer protective layer, forming at least one of the openings around the chip area on the second surface of each of the dies, so that each of the conductive lines can be exposed to the outside through each of the openings. Step S10; forming a welding pad in each of the openings of the outer protective layer, each welding pad being a metal structure with a certain thickness, and each welding pad being electrically connected to each of the conductive wires; Step S11; performing a division process to form a plurality of FOWLP units by division, each FOWLP unit having at least two of the dies; Step S12; providing an electronic component having a first surface, and arranging the first surface of the carrier of the FOWLP unit on the first surface of the electronic component; Step S13;and performing a step S14 of forming a first solder joint and a second solder joint on each of the weld pads of each of the dies of the FOWLP unit using at least one first bonding wire, respectively, and forming third solder joints on each of the weld pads around the chip area of ​​the FOWLP unit using at least two second bonding wires, respectively, and forming fourth solder joints on an electronic component, wherein the dies in the FOWLP units on the electronic component are electrically connected via the first bonding wires, and the dies in the FOWLP units and the electronic component on the electronic component are electrically connected via the second bonding wires, thereby forming a module.

[0008] In one preferred embodiment of the present invention, the electronic component is a printed circuit board.

[0009] In one preferred embodiment of the present invention, the surface of each of said weld pads is flush with the surface of the outer protective layer.

[0010] In a preferred embodiment of the present invention, each of the dies is formed by being separated from the same wafer or from different wafers.

[0011] In a preferred embodiment of the present invention, the horizontal heights of the second faces of the dies on the carrier between each other are the same.

[0012] In a preferred embodiment of the present invention, the carrier comprises a silicon (Si) carrier, a glass carrier, or a ceramic carrier.

[0013] In one preferred embodiment of the present invention, the metal paste comprises silver paste, nanosilver paste, copper paste or nanocopper paste.

[0014] In a preferred embodiment of the present invention, the first surface of each of the dies is further disposed on the carrier using a die attach film (DAF). [Effects of the Invention]

[0015] The module 1 of the present invention has the following advantages compared to conventional module technologies with FOWLP units: (1) Steps S3 to S10 in the manufacturing method of the module 1 of the present invention are all simplified and easy to perform precisely, which is particularly advantageous for reducing the thickness of the packaging unit. Therefore, the process of the present invention is simplified and can not only save costs, but also effectively improve the usage efficiency and reliability of the module 1. (2) The method for forming each of the conductive wires 50 of the FOWLP unit 1a in the module 1 of the present invention can effectively solve the problem that the manufacturing cost of each conductive wire in the conventional FOWLP technology is likely to be high and is unfriendly to the environment, and therefore the material cost and manufacturing cost of the module 1 of the present invention are also relatively reduced. (3) The module 1 of the present invention can provide a module product with higher performance (e.g., each of the dies 20 has the same specifications, performance, or function) or more functions (e.g., each of the dies 20 has different specifications, performance, or function), thereby enhancing the market competitiveness of the module product. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 2 is a side cross-sectional view of the module of the present invention. [Figure 2] FIG. 1 is a side cross-sectional view of a die of the present invention positioned on a carrier. [Figure 3] FIG. 10 is a cross-sectional side view of the first dielectric layer of the present invention disposed on a second planar surface of the carrier and die. [Figure 4] FIG. 2 is a cross-sectional side view of a second dielectric layer of the present invention disposed on a first dielectric layer. [Figure 5] FIG. 2 is a side cross-sectional view of the first and second grooves of the present invention filled with metal paste. [Figure 6]6 is a side cross-sectional view of polishing to a metal paste higher than the surface of the second dielectric layer of FIG. 5; [Figure 7] 1 is a side cross-sectional view of molding a plurality of apertures in the outer protective layer of the present invention. [Figure 8] 1 is a side cross-sectional view of a fan-out type wafer-level packaging unit of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0017] As shown in FIG. 1, the present invention provides a module 1 in which a FOWLP unit is wire-bonded to an electronic component, and the module 1 includes a FOWLP unit 1a, an electronic component 80, at least one first bonding wire 90, and at least two second bonding wires 100.

[0018] As shown in FIG. 8, the FOWLP unit 1a includes a carrier 10, at least two dies 20, a first dielectric layer 30, a second dielectric layer 40, a plurality of conductive lines 50, an outer protective layer 60, and a plurality of welding pads 70.

[0019] 2, the carrier 10 has a first surface 11 and an opposing second surface 12. The carrier 10 may be a silicon (Si) carrier, a glass carrier, or a ceramic carrier, which are advantageous for various product developments and applications, but are not limited to these.

[0020] The dies 20 are separated from the same wafer or different wafers, and are arranged parallel to and spaced apart from each other on the second surface 12 of the carrier 10, as shown in Fig. 2, and each die 20 has a first surface 21 and an opposing second surface 22, the first surface 21 of each die 20 is fixed on the carrier 10, and the second surface 22 of each die has a plurality of pads 23, and the range of the second surface 22 in the chip vertical direction is defined as a chip area 10a. In Fig. 2, each of the pads 23 on each die 20 is described as two pads 23 as an example.

[0021] In addition, in order to explain the structural relationships and related functions of the present invention, in the embodiment shown in Figures 1 to 8, each of the dies 20 on the carrier 10 further includes, but is not limited to, a first die 20a and a second die 20b, i.e., each of the dies 20 is described as having two dies 20 as an example.

[0022] The first dielectric layer 30 is disposed on the second surface 12 of the carrier 10 and the second surface 22 of each of the dies 20 (20a, 20b), and the first dielectric layer 30 has a plurality of first grooves 31 formed to extend horizontally, as shown in Fig. 3. Each of the pads 23 of each of the dies 20 (20a, 20b) is exposed to the outside through each of the first grooves 31.

[0023] The second dielectric layer 40 is disposed on the first dielectric layer 30. The second dielectric layer 40 has a plurality of second grooves 41 formed to extend in the horizontal direction, and each of the second grooves 41 communicates with each of the first grooves 31 as shown in FIG.

[0024] Each of the conductive lines 50 is formed by a metal paste 50a filled in each of the first grooves 31 and each of the second grooves 41. As shown in Fig. 6, each of the conductive lines 50 is electrically connected to each of the pads 23 of each of the dies 20 (20a, 20b). Examples of the metal paste 50a include, but are not limited to, silver paste, nano-silver paste, copper paste, and nano-copper paste.

[0025] The outer protective layer 60 is disposed on the second dielectric layer 40, and has a plurality of openings 61, at least two of which are disposed around the chip region 10a on the second surface 22 of each of the dies 20 (20a, 20b), as shown in Figure 7. Each of the conductive lines 50 is exposed to the outside through each of the openings 61. In Figure 7, the openings 61 of the outer protective layer 60 are described by taking four openings 61 as an example.

[0026] 8, each of the welding pads 70 is a metal structure having a certain thickness formed in each of the openings 61 of the outer protective layer 60, and is electrically connected to each of the conductive lines 50. Each of the dies 20 (20a, 20b) can be electrically connected to the outside through each of the pads 23, each of the conductive lines 50, and each of the welding pads 70 located around the chip area 10a on the second surface 22 of each of the dies 20 (20a, 20b), and the fan-out type wafer-level packaging unit 1a is formed as shown in FIG.

[0027] As shown in FIG. 1, the electronic component 80 has a first surface 81 on which the first surface 11 of the carrier 10 of the FOWLP unit 1a is placed, and the electronic component 80 is a printed circuit board (PCB).

[0028] Each of the first bonding wires 90 is subjected to a wire bonding process to form a first solder joint 91 and a second solder joint 92 on each of the welding pads 70 in each of the dies 20 (20a, 20b), thereby forming an electrical connection to each of the dies 20 (20a, 20b) of the FOWLP unit 1a, as shown in FIG. 1.

[0029] 1, the solder joint on the first die 20a is a first solder joint 91, and the solder joint on the second die 20b is a second solder joint 92. That is, each of the first bonding wires 90 is illustrated as a single wire, and each of the first bonding wires 90 is further wire-bonded to two adjacent weld pads 70 on each of the dies 20 (20a, 20b), completing the electrical connection between the weld pads within the shortest distance between the dies. This not only reduces manufacturing costs but also prevents cross-line conditions within the package. The cross-line condition refers to when a bonding wire between a weld pad and its corresponding weld pad crosses over the space above another weld pad, causing interference between the signals between the weld pads and the bonding wires.

[0030] Each of the second bonding wires 100 is subjected to the wire bonding process to form a third solder joint 101 on each of the welding pads 70 around the chip area 10a, and a fourth solder joint 102 on the first surface 81 of the electronic component 80, so that each of the dies 20 (20a, 20b) of the FOWLP unit 1a is electrically connected to the electronic component 80, as shown in FIG. 1.

[0031] In the embodiment of the present invention shown in FIG. 1, the solder joints on each of the welding pads 70 around the chip area 10a of the first die 20a and the second die 20b are the third solder joints 101, and the solder joints on the first surface 81 of the electronic component 80 around the chip area 10a adjacent to the first die 20a and the second die 20b are the fourth solder joints 102, i.e., the number of second bonding wires 100 is two as an example.

[0032] As shown in FIG. 1, the first bonding wires 90 and the second bonding wires 100 are simultaneously formed by the wire bonding process, which simplifies the manufacturing process.

[0033] The manufacturing method of the module 1 includes the following steps. Step S1: As shown in Fig. 2, a carrier 10 is provided. The carrier 10 has a first surface 11 and an opposing second surface 12, as shown in Fig. 2. 2, a plurality of dies 20 separated from the same wafer or different wafers are arranged in parallel and spaced apart on the second surface 12 of the carrier 10. Each of the dies 20 has a first surface 21 and an opposing second surface 22, the first surface 21 of each of the dies 20 is arranged on the carrier 10, the second surface 22 of each of the dies 20 has a plurality of pads 23, and the range of the second surface 22 of each of the dies 20 in the chip vertical direction is defined as a chip area 10a. Step S3: As shown in FIG. 3, a first dielectric layer 30 is disposed on the carrier 10 and the second surface 22 of each of the dies 20. Step S4: A plurality of first grooves 31 are formed on the first dielectric layer 30, extending horizontally, and the pads 23 of each die 20 are exposed to the outside through each of the first grooves 31, as shown in FIG. 3. Step S5: As shown in FIG. 4, a second dielectric layer 40 is disposed on the first dielectric layer 30. Step S6: A plurality of second grooves 41 are formed on the second dielectric layer 40 to extend horizontally, and each of the second grooves 41 may communicate with each of the first grooves 31, as shown in FIG. Step S7: Fill each of the first grooves 31 and each of the second grooves 41 with a metal paste 50a, so that the thickness of the metal paste 50a is higher than the surface of the second dielectric layer 40, as shown in FIG. Step S8: The metal paste 50a, which is higher than the surface of the second dielectric layer 40, is polished so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40, thereby forming a plurality of conductive lines 50 as shown in FIG. 6. Step S9: As shown in FIG. 7, an outer protective layer 60 is disposed on the second dielectric layer 40. Step S10: Form a plurality of openings 61 in the outer protective layer 60, at least one of which is formed around the chip area 10a on the second surface 22 of each of the dies 20, and expose each conductive line 50 to the outside through each of the openings 61, as shown in FIG. 7. Step S11: As shown in Fig. 8, a welding pad 70 is formed in each of the openings 61 of the outer protective layer 60. Each of the welding pads 70 is a metal structure having a certain thickness, as shown in Fig. 8. Each of the welding pads 70 is electrically connected to each of the conductive wires 50. Step S12: As shown in Figure 8, a division process is performed to form a plurality of the FOWLP units 1a, where each of the FOWLP units 1a has at least two of the dies 20. Step S13: Provide an electronic component 80 having a first surface 81, and place the first surface 11 of the carrier 10 of the FOWLP unit 1a on the first surface of the electronic component 80, as shown in FIG. Step S14: As shown in FIG. 1, a wire bonding process is performed to form first and second solder joints 91 and 92 on the welding pads 70 of the die 20 of the FOWLP unit 1a using at least one first bonding wire 90, and to form third solder joints 101 on the welding pads 70 around the chip region 10a of the FOWLP unit 1a using at least two second bonding wires 100, and to form fourth solder joints 102 on the electronic component 80. The die 20 in the FOWLP unit 1a on the electronic component 80 are electrically connected via the first bonding wires 90. The die 20 in the FOWLP unit 1a on the electronic component 80 are electrically connected to the electronic component 80 via the second bonding wires 100, forming a module 1 as shown in FIG. 1.

[0034] Steps S3 to S10 in the manufacturing process of the module 1 can be considered as key steps for fabricating the redistribution layer (RDL) of the FOWLP unit 1a. Steps S4 to S8 are all easy to precisely implement, making the process relatively simple. While each conductive line 50 in the redistribution layer provides electrical expansion and interconnection in the XY plane, the FOWLP unit 1a can also achieve a certain degree of lightness, thinness, and compactness when it has at least two dies 20.

[0035] 1, the surface of each of the weld pads 70 is flush with the surface of the outer protective layer 60, which facilitates wire bonding on the surface of each of the weld pads 70 and improves product reliability. Furthermore, each of the weld pads 70 can withstand the positive pressure generated during wire bonding or solder joint formation, so that the internal circuitry (such as each of the conductive wires 50) can be passed through or placed below each of the weld pads 70 without being damaged by the positive pressure.

[0036] Referring to FIG. 2, when the dies 20 are formed by dividing the same wafer, the dies 20 have the same specifications, performance, or function.

[0037] Referring to FIG. 2, if each die 20 is formed by dividing it from a different wafer, it is advantageous for various applications of the product, and each die 20 can have different specifications, performance, or functions, for example, the specifications of the first die 20a in FIG. 2 are smaller than the specifications of the second die 20b.

[0038] Referring to FIG. 2, since the horizontal heights of the second surfaces 22 between the dies 20 on each carrier 10 are the same, the first grooves 31 of the first dielectric layer 30 and the second grooves 41 of the second dielectric layer 40 formed by the RDL technique can be smoothly extended and shaped, which helps the structure subsequently stacked on each die 20 maintain better structural flatness and improve product reliability.

[0039] Referring to FIG. 2, the first surface 21 of each of the dies 20 is further disposed on the carrier 10 using a die attach film 110 .

[0040] The module 1 of the present invention has the following advantages compared to conventional module technologies with FOWLP units: (1) Steps S3 to S10 in the manufacturing method of the module 1 of the present invention are all simplified and easy to perform precisely, which is particularly advantageous for reducing the thickness of the packaging unit. Therefore, the process of the present invention is simplified and can not only save costs, but also effectively improve the usage efficiency and reliability of the module 1. (2) The method for forming each of the conductive wires 50 of the FOWLP unit 1a in the module 1 of the present invention can effectively solve the problem that the manufacturing cost of each conductive wire in the conventional FOWLP technology is likely to be high and is unfriendly to the environment, and therefore the material cost and manufacturing cost of the module 1 of the present invention are also relatively reduced. (3) The module 1 of the present invention can provide a module product with higher performance (e.g., each of the dies 20 has the same specifications, performance, or function) or more functions (e.g., each of the dies 20 has different specifications, performance, or function), thereby enhancing the market competitiveness of the module product. [Explanation of symbols]

[0041] 1 module 1a Fan-out type wafer level packaging unit 10. Career 10a Chip Area 11 Page 1 12 Side 2 20 Die 20a First die 20b Second die 21 Page 1 22 Side 2 23 Pad 30 First dielectric layer 31 First groove 40 Second dielectric layer 41 Second groove 50 Conductive wire 50a metal paste 60 Outer protective layer 61 Aperture 70 welding pads 80 Electronic Materials 81 Page 1 90 First bonding wire 91 First solder joint 92 Second solder joint 100 Second bonding wire 101 Third solder joint 102 4th solder joint 110 Die attach film

Claims

1. A module in which a fan-out type wafer level packaging unit is wire-bonded to an electronic component, a carrier, at least two dies, a first dielectric layer, a second dielectric layer, a plurality of conductive lines, an outer protective layer, a plurality of weld pads, an electronic component, at least one first bonding wire, and at least two second bonding wires; the carrier has a first surface and an opposing second surface; each die is separated from the same or a different wafer, each die is arranged side by side on the second surface of the carrier in parallel and spaced relation, each die has a first surface and an opposing second surface, the first surface of each die is fixed on the carrier, the second surface of each die has a plurality of pads, and the vertical extent of a chip on the second surface is defined as a chip area; the first dielectric layer is disposed on the second surface of the carrier and the second surface of each of the dies, the first dielectric layer has a plurality of first grooves extending horizontally, and the pads of each of the dies are exposed to the outside by each of the first grooves; the second dielectric layer is disposed on the first dielectric layer, and the second dielectric layer has a plurality of second grooves formed extending in a horizontal direction, each of the second grooves communicating with each of the first grooves; Each of the conductive lines is formed by a metal paste filled in each of the first grooves and each of the second grooves, and each of the conductive lines is electrically connected to the pad of each of the dies; the outer protective layer is disposed on the second dielectric layer and has a plurality of openings, at least two of the openings being located around the chip area on the second surface of each of the dies, and each of the conductive lines is exposed to the outside through each of the openings; each of the welding pads is a metal structure having a certain thickness formed in each of the openings of the outer protective layer, and is electrically connected to each of the conductive lines; each of the dies can be electrically connected to the outside through each of the pads, each of the conductive lines, and each of the welding pads located around the chip area on the second surface of each of the dies in order, thereby forming a fan-out type wafer level packaging unit; the electronic component has a first surface on which the first surface of the carrier is placed, each of the first bonding wires forms a first solder joint and a second solder joint on each of the weld pads of each of the dies by a wire bonding process, thereby forming an electrical connection to each of the dies of the fan-out wafer-level packaging unit; each of the second bonding wires forms a third solder joint on each of the weld pads around the chip area by the wire bonding process, and forms a fourth solder joint on the first surface of the electronic component, so that each of the dies and the electronic component of the fan-out wafer-level packaging unit are electrically connected; each of the first bonding wires and each of the second bonding wires are formed simultaneously by the wire bonding process; The manufacturing method of the module includes: Step S1: providing a carrier, the carrier having a first surface and an opposing second surface; Step S2: arranging a plurality of dies separated from the same wafer or different wafers on the second surface of the carrier in parallel and spaced relation, each die having a second surface opposite to a first surface, the first surface of each die being disposed on the carrier, the second surface of each die having a plurality of pads, and a chip area in the vertical direction of the second surface of each die being defined as a chip area; Step S3: disposing a first dielectric layer on the second surface of the carrier and on each of the dies; Step S4: forming a plurality of first grooves extending horizontally on the first dielectric layer, so that each pad of each die can be exposed to the outside through each of the first grooves; Step S5 of disposing a second dielectric layer on the first dielectric layer; Step S6: forming a plurality of second grooves extending horizontally on the second dielectric layer, each of the second grooves being capable of communicating with each of the first grooves; Step S7: filling each of the first grooves and each of the second grooves with a metal paste so that the thickness of the metal paste is higher than the surface of the second dielectric layer; Step S8: polishing the metal paste that is higher than the surface of the second dielectric layer to make the surface of the metal paste flush with the surface of the second dielectric layer to form a plurality of conductive lines; Step S9 of disposing an outer protective layer on the second dielectric layer; Step S10: forming a plurality of openings in the outer protective layer, forming at least one of the openings around the chip area on the second surface of each of the dies, and allowing each of the conductive lines to be exposed to the outside through each of the openings; Step S11: forming a welding pad in each of the openings of the outer protective layer, each welding pad being a metal structure having a certain thickness, and each welding pad being electrically connected to each of the conductive wires; Step S12: performing a division process to form a plurality of fan-out wafer level packaging units by division, each of the fan-out wafer level packaging units having at least two of the dies; Step S13: Providing an electronic component having a first surface, and arranging the first surface of the carrier of the fan-out type wafer-level packaging unit on the first surface of the electronic component; and performing a wire bonding process (Wire Bonding) to cause at least one first bonding wire to form a first solder joint and a second solder joint on each of the welding pads of each of the dies of the fan-out wafer-level packaging unit, respectively, and to cause at least two second bonding wires to form third solder joints on each of the welding pads around the chip area of ​​the fan-out wafer-level packaging unit, respectively, and to form a fourth solder joint on an electronic component, wherein each of the dies in the fan-out wafer-level packaging unit on the electronic component are electrically connected via each of the first bonding wires, and each of the dies in the fan-out wafer-level packaging unit on the electronic component and the electronic component are electrically connected via each of the second bonding wires, thereby forming a module.

2. The module of claim 1 , wherein the electronic component is a printed circuit board.

3. The module of claim 1 , wherein a surface of each of said weld pads is flush with a surface of the outer protective layer.

4. The module of claim 1 , wherein each of the dies is formed by being separated from the same wafer or different wafers.

5. 2. The module of claim 1, wherein the horizontal heights of the second faces between the dies on the carrier are the same.

6. The module of claim 1 , wherein the carrier comprises a silicon (Si) carrier, a glass carrier, or a ceramic carrier.

7. 10. The module of claim 1, wherein the metal paste comprises silver paste, nanosilver paste, copper paste, or nanocopper paste.

8. The module of claim 1 , wherein the first surface of each die is further disposed on the carrier using a die attach film.

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