Fan-out type wafer level packaging unit

Abstract

To provide a fan-out type wafer level packaging unit effectively solving a problem where manufacturing cost is high when each conductive wire is manufactured and environmental protection is disadvantageous in a conventional FOWLP technique of a module.SOLUTION: A fan-out type wafer level packaging unit includes a carrier, at least two dies, a first dielectric layer, a second dielectric layer, a plurality of conductive wires, at least two first welding pads, at least one first bonding wire and an outside protective layer. Each of the dies is electrically connected to each other through each of the first bonding wires. Each of the conductive wires is composed of a metal paste filled into each first groove of the first dielectric layer and each second groove of the second dielectric layer. A second welding pad is formed in each opening of the outside protective layer, and each of the dies is electrically connected to the outside by each of the second welding pads located around a chip region of a second surface of each of the dies.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a packaging unit, and more particularly to a fan-out wafer-level packaging unit. [Background technology]

[0002] Packaging technology that is light, thin, short, small, efficient, and reliable is a trend in the development of the semiconductor industry, and among them, Fan-Out Wafer Level Packaging (FOWLP) is a conventional packaging technology.

[0003] The redistribution layer (RDL) is the most important element in advanced packaging, FOWLP. Each conductive line in the RDL provides electrical expansion and interconnection to multiple pads on the die in the XY plane, allowing for more dispersed pads around each die, effectively improving the design space and reliability of each conductive line. However, achieving a certain level of lightness, thinness, and compactness in the RDL is crucial in the fabrication of each conductive line in the RDL. However, in conventional FOWLP packaging, conductive lines are formed using electroless plating or electroplating. This results in relatively high material and production costs, and the traditional process does not meet environmental protection requirements. When using FOWLP to provide products with higher performance or more functions, at least two dies are typically installed in the FOWLP and integrated through an RDL to form a multi-die FOWLP unit. This increases the design space requirements for each conductive line in the RDL of the FOWLP, and the manufacturing technology for each conductive line in the RDL becomes more important. Furthermore, multi-die FOWLP units lack an effective electrical connection method between the at least two dies installed inside, resulting in limited functionality for conventional products. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2024-80601 Summary of the Invention [Problem to be solved by the invention]

[0005] The objective of the present invention is to provide a fan-out wafer-level packaging (FOWLP) unit including a carrier, at least two dies, a first dielectric layer, a second dielectric layer, a plurality of conductive lines, at least two first welding pads, at least one first bonding wire, and an outer protective layer, wherein the dies are electrically connected to each other via the first bonding wires, the conductive lines being formed of metal paste filled in first grooves of the first dielectric layer and second grooves of the second dielectric layer, and second welding pads are formed in openings of the outer protective layer, and the dies can be electrically connected to the outside through the second welding pads located around chip areas on the second surfaces of the dies, thereby effectively solving the problems of conventional module FOWLP technology, such as high manufacturing costs and environmental issues when manufacturing conductive lines. [Means for solving the problem]

[0006] In order to achieve the above object, the present invention provides a FOWLP unit, the FOWLP unit including: a carrier; at least two dies; a first dielectric layer; a second dielectric layer; a plurality of conductive lines; at least two first welding pads; at least one first bonding wire; and an outer protective layer, wherein each of the dies is divided from the same or different wafers, and the dies are arranged side by side on the carrier in parallel and spaced apart relation, each of the dies having a first surface and an opposing second surface, the first surface of each of the dies being fixed on the carrier, the second surface of each of the dies having a plurality of pads, a chip vertical extent of the second surface being defined as a chip area, and the first dielectric layer is formed on the chip. a first dielectric layer disposed on the second surface of the carrier and each of the dies, the first dielectric layer having a plurality of first grooves extending horizontally, the pads of each of the dies being exposed to the outside by each of the first grooves; a second dielectric layer disposed on the first dielectric layer, the second dielectric layer having a plurality of second grooves extending horizontally, each of the second grooves being connected to each of the first grooves; each of the conductive lines being formed by a metal paste filled in each of the first grooves and each of the second grooves; each of the conductive lines being electrically connected to the pads of each of the dies; two of the first welding pads being formed corresponding to each of the two conductive lines in each of the dies; and each of the first bonding wires being formed by wire bonding. forming first and second solder joints on the first welding pads of each die by a bonding process, and forming electrical connections to each die through the first bonding wires; the outer protective layer is disposed on the second dielectric layer and has a plurality of openings, at least two of which are located around the chip area on the second surface of each die; each conductive line is exposed to the outside through each opening to form a second welding pad in each opening; each die can be electrically connected to the outside through each pad and each second welding pad in turn, forming the FOWLP unit; and the dies in the FOWLP unit are electrically connected to each other through the first bonding wires. A manufacturing method for the FOWLP unit includes: providing a carrier (S1).Step S2 includes arranging a plurality of dies separated from the same wafer or different wafers on the carrier in parallel and spaced relation, each die having a first surface and a second surface opposite thereto, the first surface of each die being disposed on the carrier, the second surface of each die having a plurality of pads, and a vertical extent of the chip on the second surface being defined as a chip area; Step S3 includes arranging a first dielectric layer on the second surface of the carrier and each of the dies; and forming a plurality of first grooves extending horizontally on the first dielectric layer, and connecting each pad of each of the dies to each of the first grooves. Step S4: Exposing the first grooves to the outside; Step S5: Arranging a second dielectric layer on the first dielectric layer; Step S6: Forming a plurality of second grooves extending horizontally on the second dielectric layer, each of the second grooves being capable of communicating with each of the first grooves; Step S7: Filling each of the first grooves and each of the second grooves with metal paste to make the thickness of the metal paste higher than the surface of the second dielectric layer; Step S8: Polishing the metal paste that is higher than the surface of the second dielectric layer to make the surface of the metal paste flush with the surface of the second dielectric layer to form a plurality of second grooves. Step S8: forming conductive lines; Step S9: forming first pads on the conductive lines of each die, and two of the first pads are provided corresponding to each conductive line; Step S10: performing a wire bonding process, and using at least one first bonding wire to form a first solder joint and a second solder joint on each of the first welding pads of each die, and each die forms an electrical connection through each of the first bonding wires; Step S11: disposing an outer protective layer on the second dielectric layer, and forming an outer protective layer on the second dielectric layer. The method includes step S11 of covering each of the first welding pads and each of the first bonding wires with a protective layer; step S12 of forming a plurality of openings in the outer protective layer, forming at least one of the openings around the chip area on the second surface of each of the dies, and allowing each of the conductive lines to be exposed to the outside through each of the openings to form a second welding pad in each of the openings; and step S13 of performing a division process to divide one package having at least two of the dies into one unit to form a plurality of FOWLP units.

[0007] In one preferred embodiment of the present invention, the die is electrically connected to each of the first welding pads of each of the other dies via each of the pads, each of the conductive lines, and each of the first bonding wires located on each of the first welding pads around the chip area on the second surface of each of the dies.

[0008] In a preferred embodiment of the present invention, each of the dies is formed by being separated from the same wafer or from different wafers.

[0009] In a preferred embodiment of the present invention, the horizontal heights of the second faces of the dies on the carrier between each other are the same.

[0010] In a preferred embodiment of the present invention, the carrier comprises a silicon (Si) carrier, a glass carrier, or a ceramic carrier.

[0011] In one preferred embodiment of the present invention, the metal paste comprises silver paste, nanosilver paste, copper paste or nanocopper paste.

[0012] In a preferred embodiment of the present invention, the first surface of each of the dies is further disposed on the carrier using a die attach film (DAF).

[0013] In a preferred embodiment of the present invention, each of the openings is further provided with a solder ball, and each of the solder balls can be electrically connected to each of the second welding pads in each of the openings.

[0014] In a preferred embodiment of the present invention, the FOWLP unit is mounted on an electronic component so as to be electrically connected using each of the solder balls. [Effects of the Invention]

[0015] The FOWLP unit 1 of the present invention has the following advantages over conventional FOWLP units. (1) Steps S9 and S12 in the manufacturing method of the FOWLP unit 1 of the present invention are all simplified and easy to perform precisely, which is particularly advantageous for reducing the thickness of the packaging unit. Therefore, the process of the present invention is simplified and can save costs, and the use efficiency and reliability of the FOWLP unit 1 can be effectively improved. (2) The method for forming each of the conductive wires 50 of the present invention can effectively solve the problems that the conventional FOWLP technology tends to increase the manufacturing cost when manufacturing each conductive wire and is unfavorable for environmental protection. (3) Each conductive line in the RDL of the present invention can generate an XY-plane electrical expansion and interconnection effect, while at the same time maintaining or achieving a certain degree of light, thin, short, and small integration effect in the multi-die type FOWLP unit, thereby providing a product with higher performance (e.g., each of the dies 20 has the same specifications, performance, or function) or more functions (e.g., each of the dies 20 has different specifications, performance, or function). (4) Each die 20 of the present invention can be electrically connected to each of the first welding pads 60 of the other die 20 through each of the pads 23, each of the conductive wires 50, and each of the first bonding wires 70 located on each of the first welding pads 60. For example, the first die 20a can be electrically connected to the second die 20b through each of the first bonding wires 70, which can effectively solve the problem of a lack of effective electrical connection between dies in a conventional multi-die type FOWLP unit. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a side cross-sectional view of a FOWLP unit of the present invention mounted on a printed circuit board. [Figure 2] FIG. 2 is a side cross-sectional view of the die of the present application disposed on a carrier. [Figure 3] FIG. 2 is a cross-sectional side view of the first dielectric layer of the present invention disposed on the carrier and the second surface of the die. [Figure 4]FIG. 2 is a cross-sectional side view of a second dielectric layer of the present invention disposed on a first dielectric layer. [Figure 5] FIG. 2 is a side cross-sectional view of the first and second grooves of the present invention filled with metal paste. [Figure 6] 6 is a side cross-sectional view of grinding the metal paste higher than the surface of the second dielectric layer of FIG. 5. [Figure 7] 1 is a side cross-sectional view showing a wire bonding process according to the present invention; [Figure 8] 1 is a side cross-sectional view of molding a plurality of apertures in the outer protective layer of the present invention. [Figure 9] FIG. 2 is a side cross-sectional view of the FOWLP unit of the present invention. [Figure 10] FIG. 10 is a side cross-sectional view of another embodiment of a FOWLP unit of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0017] Referring to FIG. 8 , the present invention provides a FOWLP unit 1, which includes a carrier 10, at least two dies 20, a first dielectric layer 30, a second dielectric layer 40, a plurality of conductive lines 50, at least two first welding pads 60, at least one first bonding wire 70, and an outer protective layer 80.

[0018] The carrier 10 includes a silicon (Si) carrier, a glass carrier, or a ceramic carrier, as shown in FIG.

[0019] The dies 20 are separated from the same or different wafers, and are arranged parallel to and spaced apart from each other on the carrier 10. Each die 20 has a first surface 21 and an opposing second surface 22. The first surface 21 of each die 20 is fixed on the carrier 10. The second surface 22 of each die has a plurality of pads 23. The range of the second surface 22 in the chip vertical direction is defined as a chip area 1a, as shown in Fig. 2. In Fig. 2, the pads 23 of each die 20 are described as two pads 23 as an example.

[0020] In the embodiment shown in Figures 1 to 9, each of the dies 20 on the carrier 10 further includes a first die 20a and a second die 20b, that is, each of the dies 20 is described as having two dies 20 as an example.

[0021] The first dielectric layer 30 is disposed on the carrier 10 and the second surface 22 of each of the dies 20 (20a, 20b), and the first dielectric layer 30 has a plurality of first grooves 31 formed to extend horizontally, as shown in Fig. 3. Each of the pads 23 of each of the dies 20 (20a, 20b) is exposed to the outside through each of the first grooves 31.

[0022] The second dielectric layer 40 is disposed on the first dielectric layer 30. The second dielectric layer 40 has a plurality of second grooves 41 formed to extend in the horizontal direction, and each of the second grooves 41 communicates with each of the first grooves 31 as shown in FIG.

[0023] Each of the conductive lines 50 is formed by a metal paste 50a filled in each of the first grooves 31 and each of the second grooves 32. Each of the conductive lines 50 is electrically connected to each of the pads 23 of each of the dies 20 (20a, 20b), as shown in Fig. 6. Examples of the metal paste 50a include, but are not limited to, silver paste, nano-silver paste, copper paste, and nano-copper paste.

[0024] 7, two of the first welding pads 60 are formed corresponding to the two conductive wires 50 in each die 20 (20a, 20b). Each of the first welding pads 60 is subjected to a positive pressure generated during a wire bonding process or during the formation of a solder joint, and the internal circuitry (such as each of the conductive wires 50) can pass under or be placed under each of the first welding pads 60 without being damaged by the positive pressure.

[0025] Each of the first bonding wires 70 is wire bonded to form a first solder joint 71 and a second solder joint 72 on each of the first welding pads 60 in each of the dies 20 (20a, 20b), thereby forming an electrical connection to each of the dies 20 (20a, 20b) via each of the first bonding wires 70, as shown in FIG. 7.

[0026] In addition, in the embodiment of the present invention shown in FIG. 1, the solder joint on the first die 20a is the first solder joint 71, and the solder joint on the second die 20b is the second solder joint 72, that is, each of the first bonding wires 70 is described as one wire.

[0027] The outer protective layer 80 is disposed on the second dielectric layer 40 and covers the first welding pads 60 and the first bonding wires 70. The outer protective layer 80 has a plurality of openings 81, at least two of which are disposed around the chip area 1a on the second surface 22 of each of the dies 20 (20a, 20b), as shown in FIG. 8 . The conductive lines 50 are exposed to the outside through the openings 81, and second welding pads 51 are formed within the openings 81. The dies 20 (20a, 20b) are electrically connected to the outside through the pads 23, the conductive lines 50, and the second welding pads 51, in order, to form the FOWLP unit 1.

[0028] The dies 20 (20a, 20b) in the FOWLP unit 1 are electrically connected to each other via the first bonding wires 70, as shown in FIG. are.

[0029] The manufacturing method of the FOWLP unit 1 includes the following steps: Step S1: As shown in FIG. 2, a carrier 10 is provided. 2, a plurality of dies 20 separated from the same or different wafers are arranged in parallel and spaced apart on the carrier 10. Each of the dies 20 has a first surface 21 and an opposing second surface 22, the first surface 21 of each of the dies 20 is arranged on the carrier 10, the second surface 22 of each of the dies 20 has a plurality of pads 23, and the range of the second surface 22 in the chip vertical direction is defined as a chip area 1a. Step S3: As shown in FIG. 3, a first dielectric layer 30 is disposed on the carrier 10 and the second surface 22 of each of the dies 20. Step S4: A plurality of first grooves 31 are formed on the first dielectric layer 30, extending horizontally, and the pads 23 of each die 20 are exposed to the outside through each of the first grooves 31, as shown in FIG. 3. Step S5: As shown in FIG. 4, a second dielectric layer 40 is disposed on the first dielectric layer 30. Step S6: A plurality of second grooves 41 are formed on the second dielectric layer 40 to extend horizontally, and each of the second grooves 41 may communicate with each of the first grooves 31, as shown in FIG. Step S7: Fill each of the first grooves 31 and each of the second grooves 41 with a metal paste 50a, so that the thickness of the metal paste 50a is higher than the surface of the second dielectric layer 40, as shown in FIG. Step S8: The metal paste 50a, which is higher than the surface of the second dielectric layer 40, is polished so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40, thereby forming a plurality of conductive lines 50 as shown in FIG. 6. Step S9: Form first welding pads 60 on each of the conductive wires 50 of each of the dies 20, and as shown in FIG. 7, two of the first welding pads 60 are placed on each of the conductive wires 50. Step S10: A wire bonding process is performed, and at least one first bonding wire 70 is bonded to each of the first welding pads 60 in each of the dies 20 to form a first solder joint 71 and a second solder joint 72. As shown in FIG. 7, each of the dies 20 is electrically connected via each of the first bonding wires 70. Step S11: As shown in FIG. 8, an outer protective layer 80 is disposed on the second dielectric layer 40, and the outer protective layer 80 covers the first welding pads 60 and the first bonding wires 70. Step S12: A plurality of openings 81 are formed in the outer protective layer 80, at least one of which is formed around the chip area 1a on the second surface 22 of each of the dies 20, and each conductive wire 50 is exposed to the outside through each opening 81 to form a second welding pad 51 in each opening 81, as shown in FIG. 8. Step S13: As shown in FIG. 8, a division process is performed to divide a package having at least three dies 20 into one unit, thereby forming a plurality of FOWLP units 1.

[0030] The processes of steps S3 to S12 in the manufacturing method of the FOWLP unit 1 can be regarded as key steps for fabricating the RDL of the FOWLP unit 1. Steps S4 to S8 are all easy to precisely implement, making the process relatively simple and allowing each conductive line 50 of the RDL to achieve electrical expansion and interconnection in the XY plane, while at the same time maintaining or achieving a certain degree of lightness, thinness, and compactness when the FOWLP unit 1 has at least two dies 20.

[0031] Referring to FIG. 10, each die 20 can be electrically connected to each of the first welding pads 60 of the other die 20 via each of the pads 23, each of the conductive wires 50, and each of the first bonding wires 70 located on each of the first welding pads 60 in sequence, for example, the first die 20a can be electrically connected to the second die 20b via each of the first bonding wires 70.

[0032] Referring to FIG. 2, when the dies 20 are formed by dividing the same wafer, the dies 20 have the same specifications, performance, or function.

[0033] If each die 20 is formed by dividing it from a different wafer, it is advantageous for various applications of the product, and each die 20 can have different specifications, performance, or functions, for example, the specifications of the first die 20a in Figure 2 are smaller than the specifications of the second die 20b.

[0034] Referring to FIG. 2, since the horizontal height of each of the second surfaces 22 between the dies 20 on each of the carriers 10 is the same, each of the first grooves 31 of the first dielectric layer 30 and each of the second grooves 41 of the second dielectric layer 40 formed by the RDL technique can be smoothly extended and formed, which helps the structure subsequently stacked on each of the dies 20 maintain better structural flatness and improve product reliability.

[0035] Referring to FIG. 2, the first surface 21 of each of the dies 20 is further disposed on the carrier using a die attach film 90 .

[0036] 9, each of the openings 81 is further provided with a solder ball 100, and each of the solder balls 100 can be electrically connected to each of the second welding pads 51 in each of the openings 81. As shown in FIG. 1, the FOWLP unit 1 can be installed on an electronic component 2 so as to be electrically connected using each of the solder balls 100. As shown in FIG. 1, the electronic component 2 is, but is not limited to, a printed circuit board.

[0037] The FOWLP unit 1 of the present invention has the following advantages over conventional FOWLP units. (1) Steps S9 and S12 in the manufacturing method of the FOWLP unit 1 of the present invention are all simplified and easy to perform precisely, which is particularly advantageous for reducing the thickness of the packaging unit. Therefore, the process of the present invention is simplified and can save costs, and the use efficiency and reliability of the FOWLP unit 1 can be effectively improved. (2) The method for forming each of the conductive wires 50 of the present invention can effectively solve the problems that the conventional FOWLP technology tends to increase the manufacturing cost when manufacturing each conductive wire and is unfavorable for environmental protection. (3) Each conductive line in the RDL of the present invention can generate an XY-plane electrical expansion and interconnection effect, while at the same time maintaining or achieving a certain degree of light, thin, short, and small integration effect in the multi-die type FOWLP unit, thereby providing a product with higher performance (e.g., each of the dies 20 has the same specifications, performance, or function) or more functions (e.g., each of the dies 20 has different specifications, performance, or function). (4) Each die 20 of the present invention can be electrically connected to each of the first welding pads 60 of the other die 20 through each of the pads 23, each of the conductive wires 50, and each of the first bonding wires 70 located on each of the first welding pads 60. For example, the first die 20a can be electrically connected to the second die 20b through each of the first bonding wires 70, which can effectively solve the problem of a lack of effective electrical connection between dies in a conventional multi-die type FOWLP unit. [Explanation of symbols]

[0038] 1 Fan-out type wafer level packaging unit 1a Chip area 10. Career 20 Die 20a First die 20b Second die 21 Page 1 22 Side 2 23 Pad 30 First dielectric layer 31 First groove 40 Second dielectric layer 41 Second groove 50 Conductive wire 50a metal paste 51 Second welding pad 60 No. 1 Welding Pad 70 First bonding wire 71 First solder joint 72 Second solder joint 80 Outer protective layer 81 Aperture 90 Die Attach Film 100 solder balls 2. Electronic materials

Claims

1. 1. A fan-out wafer level packaging (FOWLP) unit, comprising: a carrier, at least two dies, a first dielectric layer, a second dielectric layer, a plurality of conductive lines, at least two first weld pads, at least one first bonding wire, and an outer protective layer; the dies are separated from the same wafer or different wafers, the dies are arranged side by side on the carrier in parallel and spaced apart relation, each die has a first surface and an opposing second surface, the first surface of each die is fixed on the carrier, the second surface of each die has a plurality of pads, and the vertical extent of a chip on the second surface is defined as a chip area; the first dielectric layer is disposed on the carrier and the second surface of each of the dies, the first dielectric layer has a plurality of first grooves extending horizontally, and the pads of each of the dies are exposed to the outside by each of the first grooves; the second dielectric layer is disposed on the first dielectric layer, and the second dielectric layer has a plurality of second grooves formed extending in a horizontal direction, each of the second grooves communicating with each of the first grooves; Each of the conductive lines is formed by a metal paste filled in each of the first grooves and each of the second grooves, and each of the conductive lines is electrically connected to the pad of each of the dies; two of the first welding pads are formed corresponding to two of the conductive wires in each of the dies, Each of the first bonding wires forms a first solder joint and a second solder joint on each of the first welding pads of each of the dies through a wire bonding process, thereby forming an electrical connection to each of the dies through each of the first bonding wires; the outer protective layer is disposed on the second dielectric layer and has a plurality of openings, at least two of which are located around the chip area on the second surface of each of the dies, and each of the conductive lines is exposed to the outside by each of the openings to form a second welding pad within each of the openings, and each of the dies can be electrically connected to the outside through each of the pads, each of the conductive lines, and each of the second welding pads located around the chip area on the second surface of each of the dies in order, forming the FOWLP unit; the dies in the FOWLP unit are electrically connected to each other via the first bonding wires; The method for manufacturing the FOWLP unit includes: Step S1: providing a carrier; Step S2: arranging a plurality of dies separated from the same wafer or different wafers on the carrier in parallel and spaced relation, each die having a first surface and an opposing second surface, the first surface of each die being disposed on the carrier, the second surface of each die having a plurality of pads, and a chip area in the vertical direction of the second surface being defined as a chip area; Step S3: disposing a first dielectric layer on the second surface of the carrier and on each of the dies; Step S4: forming a plurality of first grooves extending horizontally on the first dielectric layer, so that each pad of each die can be exposed to the outside through each of the first grooves; Step S5 of disposing a second dielectric layer on the first dielectric layer; Step S6: forming a plurality of second grooves extending horizontally on the second dielectric layer, each of the second grooves being capable of communicating with each of the first grooves; Step S7: filling each of the first grooves and each of the second grooves with a metal paste so that the thickness of the metal paste is higher than the surface of the second dielectric layer; Step S8: polishing the metal paste that is higher than the surface of the second dielectric layer to make the surface of the metal paste flush with the surface of the second dielectric layer to form a plurality of conductive lines; Step S9: forming first pads on the conductive lines of each die, and two first pads are provided corresponding to each conductive line; Step S10: performing a wire bonding process, causing at least one first bonding wire to form a first solder joint and a second solder joint on each of the first welding pads of each of the dies, respectively, and each of the dies forms an electrical connection through each of the first bonding wires; Step S11: disposing an outer protective layer on the second dielectric layer, and causing the outer protective layer to cover each of the first welding pads and each of the first bonding wires; Step S12: forming a plurality of openings in the outer protective layer, forming at least one opening around the chip region on the second surface of each of the dies, allowing each of the conductive lines to be exposed to the outside through each opening, and forming a second welding pad within each opening; Step S13: performing a division process to form a plurality of FOWLP units by division; FOWLP units, including:

2. 2. The FOWLP unit of claim 1, wherein the die is electrically connected to each of the first weld pads of each of the other dies via each of the pads, each of the conductive lines, and each of the first bonding wires located on each of the first weld pads around the chip area on the second surface of each of the dies.

3. The FOWLP unit according to claim 1 , wherein each of the dies is formed by dividing from the same wafer or different wafers.

4. 2. The FOWLP unit of claim 1, wherein the horizontal heights of the second faces between the dies on the carrier are the same.

5. The FOWLP unit of claim 1 , wherein the carrier comprises a silicon carrier, a glass carrier, or a ceramic carrier.

6. 2. The FOWLP unit of claim 1, wherein the metal paste comprises silver paste, nanosilver paste, copper paste, or nanocopper paste.

7. The FOWLP unit of claim 1 , wherein the first surface of each die is further disposed on the carrier using a die attach film.

8. 2. The FOWLP unit according to claim 1, wherein each of the openings is further provided with a solder ball, each of the solder balls being capable of electrically connecting with each of the second weld pads in each of the openings.

9. The FOWLP unit according to claim 8 , wherein the FOWLP unit is installed on an electronic component so as to be electrically connected using each of the solder balls.

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