Semiconductor package

Abstract

To provide a manufacturing method for forming a wiring layer on a large-sized substrate.SOLUTION: In a semiconductor package 1, a rewiring element 31 includes an insulation layer 33 having insulation properties and a first rewiring layer 34 covered with the insulation layer. The first rewiring layer includes a first conductive part 30E located at least in part on a surface of the rewiring element 31 where semiconductor elements overlap. The insulation layer of the rewiring element includes a side face facing an interposer in a direction in which a rewiring layer chip 30 adjoins the interposer 20. The interposer includes a second rewiring layer 24 including a second conductive part 20E located on a surface where semiconductor elements of the interposer overlap. The semiconductor elements are electrically connected to the first conductive part 30E and second conductive part 20E, and include a first semiconductor element 40 and a second semiconductor element 45. A first conductive part of the first rewiring layer of the rewiring element includes first wiring 35 electrically connecting the first semiconductor element and second semiconductor element.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] TECHNICAL FIELD Embodiments of the present disclosure relate to a semiconductor package, a semiconductor package intermediate, a redistribution layer chip, a redistribution layer chip intermediate, a method for manufacturing a semiconductor package, and a method for manufacturing a semiconductor package intermediate. [Background technology]

[0002] Packaging technology that mounts multiple semiconductor elements with different functions, such as CPUs and memories, on a single substrate at high density has been attracting attention. A substrate that electrically connects multiple semiconductor elements is also called an interposer. For example, Patent Documents 1 and 2 disclose semiconductor packages that include an interposer with through electrodes and a semiconductor element mounted on the interposer.

[0003] In recent years, FOWLP (Fan Out Wafer Level Package) has been attracting attention as a technology for achieving even higher density in semiconductor elements. An example of FOWLP is described below. First, a wiring layer is formed on a substrate having the shape of a wafer, such as an 8-inch wafer. Next, semiconductor elements are mounted on the substrate. Next, a mold resin layer that encapsulates the wiring layer and semiconductor elements is formed on the substrate. When connecting the semiconductor elements to another wiring substrate, the structure including the wiring layer, semiconductor elements, and mold resin layer is peeled off from the substrate. With FOWLP, the wiring layer can be formed even in areas outside the semiconductor elements. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6014907 [Patent Document 2] Patent No. 6159820 Summary of the Invention [Problem to be solved by the invention]

[0005] Fan-Out Panel Level Package (FOPLP) is known as a technology that can achieve higher productivity than FOWLP. In FOPLP, a substrate in the shape of a panel larger than a wafer is used. For example, fourth-generation glass, sixth-generation glass, eighth-generation glass, or tenth-generation glass is used as the substrate. However, forming a wiring layer on a large substrate may require the introduction of a new large-scale exposure tool. As a result, the equipment cost may increase.

[0006] An embodiment of the present disclosure aims to provide a semiconductor package, a semiconductor package intermediate, a redistribution layer chip, a redistribution layer chip intermediate, a method for manufacturing a semiconductor package, and a method for manufacturing a semiconductor package intermediate that can effectively solve such problems. [Means for solving the problem]

[0007] An embodiment of the present disclosure relates to the following [1] to

[21] . [1] A semiconductor package, an interposer; a redistribution layer chip adjacent to the interposer; a semiconductor element overlying the interposer and the redistribution layer chip; the redistribution layer chip includes a redistribution element including a surface on which the semiconductor element overlaps, and a first molding resin layer attached to a surface of the redistribution element located opposite to the surface on which the semiconductor element overlaps, the first molding resin layer including a resin; the redistribution element includes an insulating layer having insulating properties and a first redistribution layer covered by the insulating layer, and the first redistribution layer includes a first conductive portion at least a part of which is located on a surface of the redistribution element that overlaps with the semiconductor element; the interposer includes a second redistribution layer including a second conductive portion located on a surface of the interposer on which the semiconductor element overlaps; The semiconductor element is electrically connected to the first conductive portion and the second conductive portion.

[0008] [2] further comprising a support carrier that is arranged at a position facing the semiconductor element via the interposer and the redistribution layer chip, and supports the interposer and the redistribution layer chip; The semiconductor package according to [1], wherein the support carrier is releasable from the interposer and the redistribution layer chip.

[0009] [3] A semiconductor package according to [1] or [2], further comprising a second molding resin layer that covers the interposer and the rewiring layer chip, is attached to the interposer and the rewiring layer chip, and holds the semiconductor element.

[0010] [4] The semiconductor package according to any one of [1] to [3], wherein the linear expansion coefficient of the first molding resin layer is smaller than the linear expansion coefficient of the insulating layer.

[0011] [5] The semiconductor package according to any one of [1] to [4], wherein the Young's modulus of the first molding resin layer is greater than the Young's modulus of the insulating layer.

[0012] [6] The semiconductor package according to any one of [1] to [5], wherein the bending rigidity of the first mold resin layer is greater than the bending rigidity of the insulating layer.

[0013] [7] The semiconductor package according to any one of [1] to [6], wherein the thickness of the first molding resin layer is greater than the thickness of the insulating layer.

[0014] [8] The semiconductor package according to any one of [1] to [7], wherein the first molding resin layer contains granular filler dispersed in the resin.

[0015] [9] The semiconductor package according to [8], wherein the thermal conductivity of the filler is greater than the thermal conductivity of the resin.

[0016]

[10] The semiconductor package according to [8] or [9], wherein the filler is formed of an inorganic material.

[0017]

[11] A semiconductor package, wherein the filler is black in color.

[0018]

[12] The semiconductor package according to any one of [1] to

[11] , wherein the rewiring layer chip further includes a through electrode located in a through hole formed in the first molding resin layer.

[0019]

[13] A semiconductor package described in any one of [1] to

[12] , wherein the first conductive portion includes a first wiring, the second conductive portion includes a second wiring, and the line width of the first wiring is smaller than the line width of the second wiring.

[0020]

[14] The semiconductor package according to any one of [1] to

[13] , wherein the first conductive portion includes a first wiring, and the line width of the first wiring is 10 μm or less.

[0021]

[15] A semiconductor package according to any one of [1] to

[14] , wherein the resin contained in the first molded resin layer is at least one of epoxy resin, polyimide, acrylic, bismaleimide, polybenzoxazole, and benzocyclobutene.

[0022]

[16] an interposer; a redistribution layer chip adjacent to the interposer; a supporting carrier substrate supporting the interposer and the redistribution layer chip; the redistribution layer chip includes a redistribution element and a molding resin layer attached to the redistribution element and containing a resin, the redistribution layer chip being attached to the supporting carrier substrate with the molding resin layer in contact with the supporting carrier substrate; the supporting carrier substrate is releasable from the interposer and the redistribution layer chip; A semiconductor package intermediate body, wherein the rewiring element includes an insulating layer having insulating properties and a first rewiring layer covered by the insulating layer, the first rewiring layer including a first conductive portion at least partially located on a surface of the rewiring element opposite to the surface to which the molding resin layer is attached, and the interposer includes a second rewiring layer including a second conductive portion located on a surface opposite to the surface facing the supporting carrier substrate.

[0023]

[17] A rewiring element including an insulating layer having insulating properties and a rewiring layer covered by the insulating layer, the rewiring element including a first surface and a second surface located opposite to the first surface, the rewiring layer including a conductive portion at least a portion of which is located on the first surface; a mold resin layer attached to the second surface and containing a resin;

[0024]

[18] The redistribution layer chip described in

[17] further comprises an adhesive layer attached to a surface of the molded resin layer opposite to the surface attached to the second surface, the adhesive layer having heat-sensitive adhesive properties, photosensitive adhesive properties, or pressure-sensitive adhesive properties.

[0025]

[19] A rewiring element portion including an insulating layer having insulating properties and a plurality of rewiring layers covered by the insulating layer, the rewiring element portion including a first surface and a second surface located opposite to the first surface, and each of the rewiring layers including a conductive portion at least a portion of which is located on the first surface; a rewiring layer chip intermediate body comprising: a mold resin layer portion attached to the second surface and containing resin; and a chip carrier substrate joined to the first surface;

[0026]

[20] placing a redistribution layer chip adjacent to the interposer; and mounting a semiconductor element on the interposer and the redistribution layer chip so as to overlap the semiconductor element. the redistribution layer chip includes a redistribution element including a surface on which the semiconductor element overlaps, and a first molding resin layer attached to a surface of the redistribution element located opposite to the surface on which the semiconductor element overlaps, the first molding resin layer including a resin; the rewiring element includes an insulating layer having insulating properties and a first rewiring layer covered by the insulating layer, the first rewiring layer includes a first conductive portion at least a part of which is located on a surface of the rewiring element where the semiconductor element overlaps, and the interposer includes a second rewiring layer including a second conductive portion located on a surface of the interposer where the semiconductor element overlaps, A method for manufacturing a semiconductor package, wherein the mounting step electrically connects the semiconductor element to the first conductive portion and the second conductive portion.

[0027]

[21] Providing a supporting carrier substrate; forming an interposer on the supporting carrier substrate; and attaching a redistribution layer chip to the supporting carrier substrate adjacent to the interposer; the redistribution layer chip includes a redistribution element and a molding resin layer attached to the redistribution element and containing a resin, the redistribution layer chip being attached to the supporting carrier substrate with the molding resin layer in contact with the supporting carrier substrate; the supporting carrier substrate is releasable from the interposer and the redistribution layer chip; A method for manufacturing a semiconductor package intermediate, wherein the rewiring element includes an insulating layer having insulating properties and a first rewiring layer covered by the insulating layer, the first rewiring layer including a first conductive portion at least partially located on a surface of the rewiring element opposite to a surface to which the molding resin layer is attached, and the interposer includes a second rewiring layer including a second conductive portion located on a surface opposite to a surface facing the supporting carrier substrate.

[0028] In an embodiment of the present disclosure, the insulating layer of the redistribution element may include a side facing the interposer in a direction in which the redistribution layer chip is adjacent to the interposer, the semiconductor element may include a first semiconductor element and a second semiconductor element, and the first conductive portion of the first redistribution layer of the redistribution element may include a first wiring that electrically connects the first semiconductor element and the second semiconductor element. [Effects of the Invention]

[0029] According to the embodiments of the present disclosure, large semiconductor packages can be provided at low cost. [Brief explanation of the drawings]

[0030] [Figure 1] 1 is a plan view showing a semiconductor package according to an embodiment; [Figure 2] 2 is a cross-sectional view of the semiconductor package taken along line AA in FIG. 1. [Figure 3] 3 is an enlarged cross-sectional view showing a redistribution layer chip that constitutes the semiconductor package of FIG. 2. FIG. [Figure 4] 4 is a cross-sectional view of the redistribution layer chip of FIG. 3 taken along line BB. [Figure 5] 2 is a cross-sectional view of a redistribution layer chip before being incorporated as part of the semiconductor package of FIG. 1. [Figure 6] 6A to 6C are diagrams illustrating a method for manufacturing the redistribution layer chip of FIG. 5. [Figure 7A] 6A to 6C are diagrams illustrating a method for manufacturing the redistribution layer chip of FIG. 5. [Figure 7B] FIG. 7B is a plan view corresponding to FIG. 7A. [Figure 8] 6A to 6C are diagrams illustrating a method for manufacturing the redistribution layer chip of FIG. 5. [Figure 9A] 6A to 6C are diagrams illustrating a method for manufacturing the redistribution layer chip of FIG. 5. [Figure 9B] FIG. 9B is a plan view corresponding to FIG. 9A. [Figure 10A] 6A to 6C are diagrams illustrating a method for manufacturing the redistribution layer chip of FIG. 5. [Figure 10B] FIG. 10B is a plan view corresponding to FIG. 10A. [Figure 11] 2A to 2C are diagrams illustrating a method for manufacturing the semiconductor package of FIG. [Figure 12A] 2A to 2C are diagrams illustrating a method for manufacturing the semiconductor package of FIG. [Figure 12B] 2A to 2C are diagrams illustrating a method for manufacturing the semiconductor package of FIG. [Figure 12C] FIG. 12C is a plan view corresponding to FIG. 12B. [Figure 13A] 2A to 2C are diagrams illustrating a method for manufacturing the semiconductor package of FIG. [Figure 13B] FIG. 13B is a plan view corresponding to FIG. 13A. [Figure 14] 2A to 2C are diagrams illustrating a method for manufacturing the semiconductor package of FIG. [Figure 15A] 2A to 2C are diagrams illustrating a method for manufacturing the semiconductor package of FIG. [Figure 15B] FIG. 15B is a plan view corresponding to FIG. 15A. [Figure 16A] 2A to 2C are diagrams illustrating a method for manufacturing the semiconductor package of FIG. [Figure 16B] 2A to 2C are diagrams illustrating a method for manufacturing the semiconductor package of FIG. [Figure 17] FIG. 6 is a diagram showing a modified example of the redistribution layer chip of FIG. 5. [Figure 18] FIG. 2 is a diagram showing a modified example of the semiconductor package of FIG. [Figure 19] FIG. 2 is a diagram showing a modified example of the semiconductor package of FIG. [Figure 20] 20 is a cross-sectional view of the semiconductor package taken along line CC in FIG. 19. [Figure 21] FIG. 2 is a diagram showing a modified example of the semiconductor package of FIG. [Figure 22] 22 is a cross-sectional view of the semiconductor package taken along line DD in FIG. 21. [Figure 23] FIG. 2 is a diagram showing a modified example of the semiconductor package of FIG. [Figure 24] 13B is a diagram showing a modified example of the semiconductor package intermediate body of FIG. 13A. FIG. [Figure 25] 25A to 25C are diagrams illustrating a method for manufacturing the intermediate semiconductor package of FIG. 24. [Figure 26A] 25A to 25C are diagrams illustrating a method for manufacturing a rewiring layer chip that constitutes the semiconductor package intermediate of FIG. 24. [Figure 26B] FIG. 26B shows a step performed after the step shown in the manufacturing method of FIG. 26A. [Figure 26C]25A to 25C are diagrams illustrating another method for manufacturing a rewiring layer chip that constitutes the semiconductor package intermediate of FIG. 24. [Figure 26D] FIG. 26D shows a step performed after the step shown in the manufacturing method of FIG. 26C. [Figure 27] 13B is a diagram showing another modified example of the semiconductor package intermediate body of FIG. 13A. FIG. [Figure 28] 28A to 28D are diagrams illustrating a method for manufacturing the intermediate semiconductor package of FIG. 27. [Figure 29] FIG. 6 is a diagram showing a modification of the redistribution layer chip of FIG. 5. [Figure 30] 1A and 1B are diagrams illustrating examples of products in which a semiconductor package is mounted. DETAILED DESCRIPTION OF THE INVENTION

[0031] The configuration of a semiconductor package and its manufacturing method will be described in detail below with reference to the drawings. The following embodiments are merely examples of embodiments of the present disclosure, and the present disclosure should not be construed as being limited to these embodiments. In this specification, terms such as "substrate," "base material," "sheet," and "film" are not distinguished from one another solely based on differences in name. For example, the term "substrate" encompasses components that may be called sheets or films. The normal direction used with respect to a plate-like component refers to the normal direction to the surface of the component. Terms used in this specification that specify shape, geometric conditions, and their degrees, such as "parallel" and "orthogonal," as well as length and angle values, are not limited to their strict meanings but are interpreted to encompass a range within which similar functions can be expected.

[0032] In this specification, when multiple upper limit candidates and multiple lower limit candidate values ​​are listed for a certain parameter, the numerical range of the parameter may be constructed by combining any one upper limit candidate with any one lower limit candidate. For example, consider a description that reads, "Parameter B is, for example, A1 or more, or may be A2 or more, or may be A3 or more. Parameter B is, for example, A4 or less, or may be A5 or less, or may be A6 or less." In this case, the numerical range of parameter B may be A1 or more and A4 or less, A1 or more and A5 or less, A1 or more and A6 or less, A2 or more and A4 or less, A2 or more and A5 or less, A2 or more and A6 or less, A3 or more and A4 or less, A3 or more and A5 or less, or A3 or more and A6 or less.

[0033] In the drawings referred to in this embodiment, the same parts or parts having similar functions are denoted by the same or similar reference numerals, and repeated explanations thereof may be omitted. Furthermore, the dimensional ratios of the drawings may differ from the actual ratios for the convenience of explanation, and some components may be omitted from the drawings.

[0034] FIG. 1 is a plan view showing a semiconductor package 1 according to an embodiment. FIG. 2 is a cross-sectional view of the semiconductor package 1 of FIG. 1 taken along line AA. The semiconductor package 1 has a first direction D1, a second direction D2, and a third direction D3. The first direction D1 and the second direction D2 are included in the surface direction of the semiconductor package 1. The first direction D1 is perpendicular to the second direction D2. The third direction D3 is the thickness direction of the semiconductor package 1. The third direction D3 is perpendicular to the first direction D1 and the second direction D2.

[0035] The semiconductor package 1 includes an interposer 20, a redistribution layer chip 30, a first semiconductor element 40, a second semiconductor element 45, a support carrier 50, and a second molding resin layer 60. The redistribution layer chip 30 includes a redistribution element 31 and a first molding resin layer 32.

[0036] The support carrier 50 supports the interposer 20 and the redistribution layer chip 30. The interposer 20 and the redistribution layer chip 30 are adjacent to each other on the support carrier 50 in the plane direction of the semiconductor package 1, in this example, the first direction D1. A first semiconductor element 40 is mounted on the interposer 20 and the redistribution layer chip 30 so as to overlap in a direction intersecting the direction in which the interposer 20 and the redistribution layer chip 30 are adjacent to each other, in this example, the thickness direction of the semiconductor package 1, i.e., the third direction D3. In other words, when viewed in the third direction D3, which is a plan view, the first semiconductor element 40 is positioned so as to overlap the interposer 20 and the redistribution layer chip 30. A second semiconductor element 45 is mounted on the interposer 20 and the redistribution layer chip 30 so as to overlap in a direction intersecting the direction in which the interposer 20 and the redistribution layer chip 30 are adjacent to each other, in this example, the thickness direction of the semiconductor package 1, i.e., the third direction D3. In other words, when viewed in the third direction D3, which is a plan view, the second semiconductor element 45 is positioned so as to overlap the interposer 20 and the redistribution layer chip 30. The second molding resin layer 60 covers the interposer 20, the redistribution layer chip 30, the first semiconductor element 40, and the second semiconductor element 45.

[0037] The illustrated interposer 20 has, as an example, a through-hole 21 formed by a hole penetrating in the thickness direction. The redistribution layer chip 30 is disposed in the through-hole 21. This causes the redistribution layer chip 30 to be adjacent to the interposer 20. The interposer 20 and the redistribution layer chip 30 extend in the first direction D1 and the second direction D2. The shape of the interposer 20 is not particularly limited. The interposer 20 may be, for example, a rectangular plate. In this case, the redistribution layer chip 30 may be disposed adjacent to the interposer 20 in the first direction D1 or the second direction D2.

[0038] As shown in FIG. 1 , the redistribution layer chip 30 arranged in the through-hole 21 may be spaced apart from the interposer 20 along the entire periphery of the redistribution layer chip 30. The space between the redistribution layer chip 30 and the interposer 20 is, for example, 0.03 mm or more, or may be 0.05 mm or more, or may be 0.1 mm or more. The space between the redistribution layer chip 30 and the interposer 20 is, for example, 3.0 mm or less, or may be 1.0 mm or less, or may be 0.5 mm or less. The space between the redistribution layer chip 30 and the interposer 20 here is the shortest distance from a point on the periphery of the redistribution layer chip 30 to the through-hole 21.

[0039] The shapes of the redistribution layer chip 30 and the through portion 21 are not particularly limited. As shown in FIG. 1, the redistribution layer chip 30 and the through portion 21 may be rectangular in a plan view. The shape of the through portion 21 in a plan view may be larger than the redistribution layer chip 30 and similar to the redistribution layer chip 30. The redistribution layer chip 30 is one of multiple redistribution layer chips 30 cut out from a redistribution layer chip intermediate 300 (see FIGS. 9 and 10) described below. Considering ease of processing, a rectangular shape is preferable for the redistribution layer chip 30.

[0040] As shown in FIG. 1 , the first semiconductor element 40 overlaps the interposer 20 and the redistribution layer chip 30 in a plan view, in other words, when viewed in the third direction D3. Specifically, the first semiconductor element 40 is mounted on the interposer 20 and the redistribution layer chip 30 in a state where the first semiconductor element 40 overlaps the interposer 20 and the redistribution layer chip 30. The first semiconductor element 40 is electrically connected to both the interposer 20 and the redistribution layer chip 30. Specifically, referring to FIG. 2 , the redistribution layer chip 30 includes a first conductive portion 30E including first wiring 35 electrically connected to the first semiconductor element 40. The first conductive portion 30E is included in the first redistribution layer 34 of the redistribution element 31. The interposer 20 includes a second conductive portion 20E including a plurality of through electrodes 14 and second wiring 15. The second conductive portion 20E is included in the second redistribution layer 24 included in the interposer 20. In the illustrated example, one or more of the plurality of through electrodes 14 in the second conductive portion 20E are electrically connected to the first semiconductor element 40.

[0041] The second semiconductor element 45 overlaps the interposer 20 and the redistribution layer chip 30 at a position different from that of the first semiconductor element 40 when viewed in a plan view, in other words, when viewed in the third direction D3. Specifically, the second semiconductor element 45 is mounted so as to overlap the interposer 20 and the redistribution layer chip 30. The second semiconductor element 45 is electrically connected to both the interposer 20 and the redistribution layer chip 30. Specifically, the first conductive portion 30E in the redistribution layer chip 30 includes first wiring 35 electrically connected to the second semiconductor element 45. The second semiconductor element 45 is electrically connected to one or more of the through electrodes 14 of the second conductive portion 20E in the interposer 20. The first wiring 35 may electrically connect the first semiconductor element 40 and the second semiconductor element 45.

[0042] The interposer 20 includes a first surface 20A and a second surface 20B. The second surface 20B is located on the opposite side of the first surface 20A. The through electrodes 14 are located in through holes 22A extending from the first surface 20A to the second surface 20B. Specifically, the interposer 20 includes an interposer insulating layer 22 in which a second conductive portion 20E (second redistribution layer 24) including the through electrodes 14 and second wiring 15 is provided. The interposer insulating layer 22 has a plurality of through holes 22A penetrating the interposer insulating layer 22 in the thickness direction. A through electrode 14 is located in each through hole 22A. The first semiconductor element 40 is electrically connected to the through electrodes 14 in the second conductive portion 20E, but may also be electrically connected to an electrode located in a hole with a bottom extending from the first surface 20A. The second wiring 15 is embedded in the interposer insulating layer 22. In other words, the second wiring 15 is covered by the interposer insulating layer 22. The illustrated second wiring 15 is embedded in the interposer insulating layer 22, with a portion thereof exposed to the outside of the interposer insulating layer 22. The second wiring 15 may be connected to the semiconductor elements 40, 45 at the portion exposed to the outside of the interposer insulating layer 22. The second wiring 15 may also be provided on the surface of the interposer insulating layer 22.

[0043] The first surface 20A is formed by the surface on one side in the thickness direction of the interposer insulating layer 22, the surface of the through electrode 14 exposed from the through hole 22A on one side in the thickness direction of the interposer insulating layer 22, and the surface of the second wiring 15 exposed from the interposer insulating layer 22 on one side in the thickness direction of the interposer insulating layer 22. The second surface 20B is formed by the surface on the other side in the thickness direction of the interposer insulating layer 22, the surface of the through electrode 14 exposed from the through hole 22A on the other side in the thickness direction of the interposer insulating layer 22, and the surface of the second wiring 15 exposed from the interposer insulating layer 22 on the other side in the thickness direction of the interposer insulating layer 22.

[0044] Furthermore, the through portion 21 is formed in the interposer insulating layer 22. A plurality of through holes 22A are formed in the interposer insulating layer 22 in a portion surrounding the through portion 21. Therefore, a plurality of through electrodes 14 are located around the through portion 21 in the interposer insulating layer 22. Similarly, the second wiring 15 is located around the through portion 21 in the interposer insulating layer 22. The through electrodes 14 and the second wiring 15 may be electrically connected.

[0045] The redistribution layer chip 30 includes a first surface 30A and a second surface 30B. The second surface 30B is located opposite the first surface 30A. The first surface 30A of the redistribution layer chip 30 faces the same direction as the first surface 20A of the interposer 20. The second surface 30B of the redistribution layer chip 30 faces the same direction as the second surface 20B of the interposer 20. The first surface 20A of the interposer 20 and the first surface 30A of the redistribution layer chip 30 are surfaces where the first semiconductor element 40 and the second semiconductor element 45 overlap. The first semiconductor element 40 and the second semiconductor element 45 are mounted on the first surface 20A of the interposer 20 and the first surface 30A of the redistribution layer chip 30. A portion of the first wiring 35 in the above-mentioned first conductive portion 30E is located on the first surface 30A. The first wiring 35 is connected to the semiconductor elements 40 and 45 at a portion located on the first surface 30A.

[0046] The support carrier 50 is disposed at a position facing the first semiconductor element 40 and the second semiconductor element 45 via the interposer 20 and the redistribution layer chip 30. The support carrier 50 supports the interposer 20 and the redistribution layer chip 30. The second surface 20B of the interposer 20 faces the support carrier 50. Specifically, the interposer 20 is formed on the support carrier 50 so that the second surface 20B contacts the release layer 51. The redistribution layer chip 30 is attached to the support carrier 50 by bonding the second surface 30B to the support carrier 50 via the release layer 51. The support carrier 50 is releasable from the interposer 20 and the redistribution layer chip 30. The support carrier 50 is peeled off from the interposer 20 and the redistribution layer chip 30 together with the release layer 51.

[0047] The second molding resin layer 60 covers the interposer 20 and the redistribution layer chip 30 and is attached to the interposer 20 and the redistribution layer chip 30. Specifically, the second molding resin layer 60 is bonded to the first surface 20A of the interposer 20 and the first surface 30A of the redistribution layer chip 30. The second molding resin layer 60 is also bonded to the first semiconductor element 40 and the second semiconductor element 45, and holds the first semiconductor element 40 and the second semiconductor element 45. This makes it possible to maintain the integrated state of the interposer 20, the redistribution layer chip 30, the first semiconductor element 40, and the second semiconductor element 45 even if the support carrier 50 is peeled off from the interposer 20 and the redistribution layer chip 30.

[0048] Each component of the semiconductor package 1 will now be described in detail.

[0049] The interposer 20 includes an interposer insulating layer 22 and a second redistribution layer 24. The second redistribution layer 24 includes a second conductive portion 20E, which includes a through electrode 14 and a second wiring 15. The through electrode 14 and the second wiring 15 are conductive. As shown in FIG. 2, the interposer 20 may include a pad 16 provided on the first surface 20A. Although not shown, the interposer 20 may also include wiring and an insulating layer provided on the first surface 20A.

[0050] The interposer insulating layer 22 may be formed of an insulating resin. The insulating resin forming the interposer insulating layer 22 may be, for example, polyimide, epoxy resin, acrylic resin, or a combination of two or more of these. In this embodiment, the interposer insulating layer 22 is formed of polyimide. The interposer insulating layer 22 may also be a glass substrate, a quartz substrate, a sapphire substrate, a silicon substrate, a silicon carbide substrate, an alumina (Al2O3) substrate, an aluminum nitride (AlN) substrate, a zirconium oxide (ZrO2) substrate, a lithium niobate substrate, a tantalum niobate substrate, or a laminate of these substrates. The interposer insulating layer 22 may partially include a substrate made of a conductive material, such as an aluminum substrate or a stainless steel substrate. The thickness of the interposer insulating layer 22 is, for example, 0.01 mm or more, 0.1 mm or more, or 0.2 mm or more. The thickness of the interposer insulating layer 22 is, for example, 2.0 mm or less, may be 1.5 mm or less, or may be 1.0 mm or less.

[0051] The through electrode 14 extends in the thickness direction from one surface to the other surface of the interposer insulating layer 22 in the through hole 22A of the interposer insulating layer 22. The through electrode 14 may be located over the entire area of ​​the through hole 22A. That is, the through electrode 14 may be a so-called filled via that is filled in the through hole 22A. The through electrode 14 does not have to be filled in the through hole 22A.

[0052] The through electrode 14 may include multiple layers. For example, the through electrode 14 may include a first layer located on the side surface of the through hole 22A and a second layer located on the first layer. The second layer may extend to the center of the through hole 22A in a plan view.

[0053] The first layer is formed on the side surface of through-hole 22A by a physical film formation method such as sputtering or vapor deposition. The thickness of the first layer is, for example, 0.05 μm or more. The thickness of the first layer is, for example, 1.0 μm or less. Note that other layers may be provided between the first layer and the side surface of through-hole 22A. The material constituting the first layer may be metal such as titanium, chromium, nickel, copper, or an alloy using these, or a laminate of these.

[0054] The second layer may contain copper as a main component. For example, the second layer may contain 80 mass % or more of copper. The second layer may also contain a metal such as gold, silver, platinum, rhodium, tin, aluminum, nickel, or chromium, or an alloy using any of these metals. The second layer is formed on the first layer by, for example, electrolytic plating.

[0055] The second wiring 15 includes a conductive layer. The materials exemplified for the through electrode 14 can be used as materials for forming the second wiring 15. The thickness of the second wiring 15 is, for example, 0.5 μm or more, and may be 1.0 μm or more. The thickness of the second wiring 15 is, for example, 10.0 μm or less, and may be 5.0 μm or less. The line width of the second wiring 15 is, for example, 5 μm or more, and may be 10 μm or more. The line width of the second wiring 15 is, for example, 30 μm or less, and may be 20 μm or less.

[0056] The pad 16 includes a conductive layer. The pad 16 may be located on the through electrode 14 on the first surface 20A side. The materials constituting the pad 16 may be the same as those listed for the through electrode 14. The thickness of the pad 16 is, for example, 0.5 μm or more, and may be 1.0 μm or more. The thickness of the pad 16 is, for example, 10.0 μm or less, and may be 5.0 μm or less.

[0057] FIG. 3 is an enlarged cross-sectional view of the redistribution layer chip 30. The redistribution layer chip 30 includes a redistribution element 31, a first molding resin layer 32, and an adhesive layer 36. The redistribution element 31 includes an insulating layer 33 and a first redistribution layer 34 embedded in the insulating layer 33. In other words, the redistribution element 31 includes an insulating layer 33 and a first redistribution layer 34 covered by the insulating layer 33. In this disclosure, the redistribution layer chip 30 is referred to as a "redistribution layer" chip because it is used for redistribution purposes. However, the redistribution layer chip 30 may also be simply referred to as a redistribution layer chip, and the redistribution element 31 may also be simply referred to as a wiring element.

[0058] The rewiring element 31 includes a first surface 31A and a second surface 31B located opposite the first surface 31A. In the state shown in FIG. 2, the first surface 31A forms the surface where the first semiconductor element 40 and the second semiconductor element 45 overlap. That is, in the state shown in FIG. 2, the first surface 31A forms the first surface 30A of the rewiring layer chip 30. The first molding resin layer 32 is attached to the second surface 31B. The adhesive layer 36 is attached to the surface of the first molding resin layer 32 located opposite the surface attached to the second surface 31B of the rewiring element 31. The adhesive layer 36 forms the second surface 30B of the rewiring layer chip 30.

[0059] 2, the redistribution layer chip 30 may include pads 37 provided on the first surface 31A. The first redistribution layer 34 also includes a first conductive portion 30E including the above-described first wiring 35. In the illustrated example, at least a portion of the first wiring 35 in the first conductive portion 30E is located on the first surface 31A of the redistribution element 31. In other words, at least a portion of the first wiring 35 forms the first surface 31A. At least a portion of the first wiring 35 in the first conductive portion 30E located on the first surface 31A is connected to the semiconductor elements 40, 45.

[0060] The insulating layer 33 may be made of, for example, polyimide, epoxy resin, acrylic resin, or a combination of two or more of these. The thickness of the insulating layer 33 is, for example, 3 μm or more, and may be 5 μm or more. The thickness of the insulating layer 33 is, for example, 20 μm or less, and may be 10 μm or less.

[0061] The first conductive portion 30E including the first wiring 35 may be made of the same materials as those listed for the through electrode 14. The thickness of the first wiring 35 is, for example, 0.5 μm or more, and may be, for example, 1 μm or more. The thickness of the first wiring 35 is, for example, 5 μm or less, and may be, for example, 3 μm or less. The line width of the first wiring 35 is, for example, 10 μm or less. The line width of the first wiring 35 may be, for example, 5 μm or less, 3 μm or less, or 2 μm or less. The line width of the first wiring 35 may be smaller than the line width of the second wiring 15 of the interposer 20. The minimum line width of the first wiring 35 is, for example, ½ or less, or may be ⅕ or less, or may be 1 / 10 or less of the minimum line width of the second wiring 15 of the interposer 20. The plurality of first wirings 35 may be provided in a line-and-space pattern. In this case, the line width of the first wiring 35 and the interval (space) between adjacent first wirings 35 may be the same or different. The interval between adjacent first wirings 35 may be, for example, 1 μm to 5 μm, 1 μm to 3 μm, or 1 μm to 2 μm. Furthermore, the aspect ratio (thickness / line width) of the first wiring 35 may be, for example, 1 to 4, or 1 to 2.5.

[0062] FIG. 4 is a cross-sectional view of the redistribution layer chip 30 taken along line BB in FIG. 3. The first wiring 35 extends linearly in the second direction D2. The first redistribution layer 34 includes multiple first wirings 35, which are formed in a line-and-space pattern extending parallel to one another. Each first wiring 35 has a rectangular cross section in a direction perpendicular to the longitudinal direction, with only one of the four sides of the rectangle exposed to the outside of the insulating layer 33. The surface of the first wiring 35 exposed to the outside of the insulating layer 33 forms the first surface 31A. The formation pattern of the first wiring 35 is not particularly limited. The first redistribution layer 34 may include wiring that is completely embedded in, or in other words, covered by, the insulating layer 33. The first conductive portion 30E in the first redistribution layer 34 may include a through electrode. The first conductive portion 30E in the first redistribution layer 34 may include wiring located on the second surface 31B.

[0063] The pad 37 includes a conductive layer. The pad 37 may be located on the first wiring 35 on the first surface 31A side. The materials exemplified for the through electrode 14 may be used as materials for forming the pad 37. The thickness of the pad 37 is, for example, 0.5 μm or more, and may be 1.0 μm or more. The thickness of the pad 37 is, for example, 10.0 μm or less, and may be 5.0 μm or less.

[0064] The first molded resin layer 32 contains a resin. The resin contained in the first molded resin layer 32 may be, for example, any one of polyimide, epoxy resin, acrylic, bismaleimide, polybenzoxazole, and benzocyclobutene, or a combination of two or more of these. The first molded resin layer 32 is provided to suppress deformation of the rewiring element 31. The first molded resin layer 32 may have at least one of the following characteristics (1) to (4) to suitably suppress deformation of the rewiring element 31.

[0065] (1) The coefficient of thermal expansion, ie, the linear expansion coefficient, of first mold resin layer 32 is smaller than the coefficient of thermal expansion, ie, the linear expansion coefficient, of insulating layer 33 . (2) The Young's modulus of the first molding resin layer 32 is greater than the Young's modulus of the insulating layer 33 . (3) The bending rigidity of first mold resin layer 32 is greater than the bending rigidity of insulating layer 33 . (4) The thickness of first mold resin layer 32 is greater than the thickness of insulating layer 33 .

[0066] The thermal expansion coefficients of first molded resin layer 32 and insulating layer 33 are measured in accordance with JIS K7197:2012. That is, in this specification, thermal expansion coefficient means the linear expansion coefficient measured in accordance with JIS K7197:2012. The Young's modulus of first molded resin layer 32 and insulating layer 33 are determined by measuring the mechanical properties of first molded resin layer 32 and insulating layer 33 using a nanoindentation method. The bending rigidity of first molded resin layer 32 and insulating layer 33 is calculated by determining the Young's modulus of first molded resin layer 32 and insulating layer 33 using the nanoindentation method and by determining the cross-sectional shapes of first molded resin layer 32 and insulating layer 33.

[0067] The measurement of Young's modulus by the nanoindentation method is carried out as follows. First, the first mold resin layer 32 and the insulating layer 33 are placed in a measuring device, a BRUKER "TI950 TriboIndenter." At this time, if the redistribution layer chip 30 is already incorporated into the semiconductor package 1, the redistribution layer chip 30 is cut out and placed in the measuring device. Furthermore, if the redistribution layer chip 30 has not yet been incorporated into the semiconductor package 1, the unassembled redistribution layer chip 30 is placed in the measuring device. Then, measurement by nanoindentation is started on the side surface of first mold resin layer 32 or insulating layer 33. At this time, an indenter is pressed in the surface direction at an arbitrary midpoint in the thickness direction on the side surface of first mold resin layer 32 or insulating layer 33 for 10 seconds until it reaches a depth of 100 nm, and then held in that state for 5 seconds, after which it is unloaded for 10 seconds until it reaches an indentation depth of 0 nm. This indentation is performed separately on first mold resin layer 32 and insulating layer 33. This allows the Young's modulus of the object to be measured to be calculated. A diamond indenter (Berkovich indenter TI-0039) with an opposing angle of 142.3° is used as the indenter.

[0068] The thermal expansion coefficient (linear expansion coefficient) of the first molded resin layer 32 may be 2 ppm / °C or more and 12 ppm / °C or less, or 5 ppm / °C or more and 9 ppm / °C or less. As described above, in order to suppress deformation of the rewiring element 31, the linear expansion coefficient of the first molded resin layer 32 may be smaller than the linear expansion coefficient of the insulating layer 33. As described above, the insulating layer 33 may be, for example, polyimide, epoxy resin, acrylic resin, or a combination of two or more of these. The resin contained in the first molded resin layer 32 may be, for example, one of polyimide, epoxy resin, acrylic, bismaleimide, polybenzoxazole, and benzocyclobutene, or a combination of two or more of these. Here, the following relationship usually holds: linear expansion coefficient of polyimide > linear expansion coefficient of acrylic > linear expansion coefficient of epoxy. Therefore, when the linear expansion coefficient of first mold resin layer 32 is to be smaller than that of insulating layer 33, for example, when first mold resin layer 32 contains polyimide, insulating layer 33 may also contain polyimide. To make the linear expansion coefficient of first mold resin layer 32 smaller than that of insulating layer 33, the molecular weight of the polyimide contained in first mold resin layer 32 may be increased relative to the molecular weight of the polyimide contained in insulating layer 33. As the molecular weight increases, molecular movement tends to be restricted, resulting in a lower linear expansion coefficient. When first mold resin layer 32 and insulating layer 33 contain the same resin, when the linear expansion coefficient of first mold resin layer 32 is to be smaller than that of insulating layer 33, the molecular weight of the resin contained in first mold resin layer 32 may be increased relative to the molecular weight of the resin contained in insulating layer 33. Furthermore, when first mold resin layer 32 and insulating layer 33 contain the same resin, the adhesion strength between first mold resin layer 32 and insulating layer 33 may also be improved.

[0069] The Young's modulus of first mold resin layer 32 may be 12 GPa or more and 30 GPa or less, or 18 GPa or more and 22 GPa or less. As described above, from the viewpoint of suppressing deformation of rewiring element 31, the Young's modulus of first mold resin layer 32 may be greater than the Young's modulus of insulating layer 33. Here, the relationship of Young's modulus of polyimide > Young's modulus of acrylic > Young's modulus of epoxy usually holds. Therefore, when the linear expansion coefficient of first mold resin layer 32 is to be smaller than the linear expansion coefficient of insulating layer 33, for example, if first mold resin layer 32 contains polyimide, it is preferable that insulating layer 33 also contains polyimide. Then, to make the Young's modulus of first mold resin layer 32 greater than the Young's modulus of insulating layer 33, the molecular weight of the polyimide contained in first mold resin layer 32 may be greater than the molecular weight of the polyimide contained in insulating layer 33. On the other hand, when the first mold resin layer 32 and the insulating layer 33 contain the same resin without adjusting the molecular weight, the bending rigidity of the first mold resin layer 32 can be made greater than the bending rigidity of the insulating layer 33 by making the thickness of the first mold resin layer 32 greater than that of the insulating layer 33. The first mold resin layer 32 may contain a filler dispersed in a resin such as an epoxy-based resin. When a filler is dispersed in the resin, the heat dissipation of heat generated by the first wiring 35, for example, can be improved. The filler may be a granular material made of, for example, silica, alumina, or the like. The filler may be a granular material made of silicon oxide or silicon nitride. The silicon oxide or silicon nitride may contain fluorine or nitrogen. The filler may be a granular material made of carbon black. Furthermore, when the physical properties of the redistribution layer chip 30 and the interposer 20 are similar, deformation of the semiconductor package 1 due to differences in the physical properties between the two is suppressed, making it easier to maintain flatness and increase the size of the semiconductor package 1. From this perspective, the first mold resin layer 32 and the insulating layer 33 in the redistribution layer chip 30 and the interposer insulating layer 22 in the interposer 20 may contain the same resin.

[0070] When first mold resin layer 32 contains a filler, it is desirable that the thermal conductivity of the filler be greater than the thermal conductivity of the resin in which the filler is dispersed, in order to improve heat dissipation. The filler may be made of an inorganic material. The filler may also be black in color. When first mold resin layer 32 is black due to the inclusion of a black filler, for example, it is possible to suppress light from passing through the redistribution layer chip.

[0071] The thickness of first molded resin layer 32 is, for example, 5 μm or more, and may be 10 μm or more. The thickness of first molded resin layer 32 is, for example, 50 μm or less, and may be 20 μm or less. Furthermore, through holes for providing through electrodes may be formed in first molded resin layer 32.

[0072] The redistribution layer chip 30 is attached to the support carrier 50 with the first mold resin layer 32 in contact with the support carrier 50. Specifically, the first mold resin layer 32 is in contact with the support carrier 50 via the adhesive layer 36 and the release layer 51, and the adhesive layer 36 is bonded to the release layer 51. This attaches the redistribution layer chip 30 to the support carrier 50. The adhesive layer 36 has heat-sensitive, photo-sensitive, or pressure-sensitive adhesive properties. The adhesive layer 36 may be formed of a thermoplastic polyimide, which is a material having heat-sensitive adhesive properties. Note that the adhesive layer 36 may be omitted as long as the first mold resin layer 32 and the support carrier 50 are bonded together. An NCF (Non-Conductive Film) or NCP (Non-Conductive Paste) for semiconductor packaging may also be used as the adhesive layer 36. When an NCF or NCP is used as the adhesive layer 36, the redistribution layer chip 30 and the support carrier 50 can be bonded together by the NCF or NCP by heating and then cooling the adhesive layer 36.

[0073] The thickness of the adhesive layer 36 is, for example, 5 μm or more, and may be 10 μm or more. The thickness of the adhesive layer 36 is, for example, 100 μm or less, and may be 30 μm or less.

[0074] 5 is a cross-sectional view of the redistribution layer chip 30 before being incorporated as part of the semiconductor package 1. The redistribution layer chip 30 before being incorporated as part of the semiconductor package 1 (hereinafter, may be referred to as the pre-embedded redistribution layer chip 30′) shown in FIG. 5 may include a chip carrier 38 in contact with the first surface 31A of the rewiring element 31. The chip carrier 38 may be attached to the first surface 31A via a release layer 39. In the pre-embedded redistribution layer chip 30′ before being incorporated as part of the semiconductor package 1, the first wiring 35 located on the first surface 31A is covered and protected by the chip carrier 38.

[0075] The chip carrier 38 may include, for example, a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, a silicon substrate, a silicon carbide substrate, an alumina (Al2O3) substrate, an aluminum nitride (AlN) substrate, a zirconium oxide (ZrO2) substrate, a lithium niobate substrate, or a tantalum niobate substrate. The resin substrate may include an organic material. For example, the resin substrate may include epoxy resin, polyethylene, polypropylene, or the like. The release layer 39 is bonded to the first surface 31A of the rewiring element 31 and to the chip carrier 38. The release layer 39 can be peeled from a portion of the first wiring 35 forming the first surface 31A and the insulating layer 33, for example, by heating. In this case, the release layer 39 may include a thermoplastic resin. The release layer may be a polyimide resin-type release layer that can be peeled off with a laser beam of about 355 nm. When the release layer 39 is peeled off, the chip carrier 38 is also peeled off. The thickness of chip carrier 38 is, for example, 700 μm or more and may be 1000 μm or more. The thickness of chip carrier 38 is, for example, 2000 μm or less and may be 1200 μm or less. The thickness of release layer 39 is, for example, 0.3 μm or more and may be 1 μm or more. The thickness of release layer 39 is, for example, 30 μm or less and may be 100 μm or less.

[0076] When the redistribution layer chip 30 is incorporated as part of the semiconductor package 1, the chip carrier 38 and the release layer 39 are removed from the pre-embedded redistribution layer chip 30′. Then, the redistribution layer chip 30 is attached to the support carrier 50 by being bonded to the release layer 51 via the adhesive layer 36. If the adhesive layer 36 has, for example, heat-sensitive adhesive properties, the redistribution layer chip 30 is placed with the adhesive layer 36 in contact with the release layer 51. Thereafter, the adhesive layer 36 and the release layer 51 may be bonded together by heating the adhesive layer 36.

[0077] 1 and 2, the first semiconductor element 40 includes a transistor formed of a semiconductor such as silicon. The first semiconductor element 40 is, for example, a CPU, a GPU, an FPGA, a sensor, a memory, or the like. The first semiconductor element 40 may be a chiplet in which semiconductor elements such as a CPU, a GPU, an FPGA, a sensor, or a memory are divided according to function. The first semiconductor element 40 may include multiple stacked substrates.

[0078] The first semiconductor element 40 is electrically connected to the interposer 20 via the pads 16. Bumps may be provided between the pads 16 of the interposer 20 and the first semiconductor element 40. The first semiconductor element 40 is electrically connected to the first wiring 35 in the first conductive portion 30E of the redistribution layer chip 30 via pads 37. Bumps may be provided between the pads 37 of the redistribution layer chip 30 and the first semiconductor element 40.

[0079] The second semiconductor element 45 includes a transistor formed of a semiconductor such as silicon. The second semiconductor element 45 is, for example, a CPU, a GPU, an FPGA, a sensor, a memory, etc. The second semiconductor element 45 may be a chiplet in which semiconductor elements such as a CPU, a GPU, an FPGA, a sensor, a memory, etc. are divided according to function. The second semiconductor element 45 may include multiple stacked substrates. The shape, function, performance, etc. of the second semiconductor element 45 may be the same as or different from the shape, function, performance, etc. of the first semiconductor element 40.

[0080] The second semiconductor element 45 is electrically connected to the interposer 20 via the pads 16. Bumps may be provided between the pads 16 of the interposer 20 and the second semiconductor element 45. The second semiconductor element 45 is electrically connected to the first wiring 35 of the redistribution layer chip 30 via pads 37. Bumps may be provided between the pads 37 of the redistribution layer chip 30 and the second semiconductor element 45.

[0081] The support carrier 50 supports the interposer 20 and the redistribution layer chip 30. The support carrier 50 can be peeled off from the interposer 20 and the redistribution layer chip 30. When the support carrier 50 is peeled off, the release layer 51 is also peeled off. When the support carrier 50 and the release layer 51 are peeled off, the through electrodes 14 and the second wiring 15 are exposed to the outside. This allows the through electrodes 14 and the second wiring 15 to be electrically connected to, for example, another semiconductor package or a wiring board. The support carrier 50 has a size sufficient to encompass the entire combination of the interposer 20 and the redistribution layer chip 30. The shape of the support carrier 50 may be, for example, rectangular. Note that in the illustrated example, the support carrier 50 supports one combination of the interposer 20 and the redistribution layer chip 30, but it may support multiple combinations of the interposer 20 and the redistribution layer chip 30.

[0082] The semiconductor package 1 according to this embodiment is formed by cutting out from a support carrier substrate 50P (see FIG. 16A ) described below that supports a plurality of combinations of interposers 20 and redistribution layer chips 30. The support carrier 50 is a part of the support carrier substrate 50P cut out from the support carrier substrate 50P. The cut-out support carrier 50 has the corresponding interposers 20, redistribution layer chips 30, semiconductor elements 40 and 45, and a second mold resin layer 60 mounted thereon.

[0083] The support carrier 50 may include, for example, a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, a silicon substrate, a silicon carbide substrate, an alumina (Al2O3) substrate, an aluminum nitride (AlN) substrate, a zirconium oxide (ZrO2) substrate, a lithium niobate substrate, or a tantalum niobate substrate. The resin substrate may include an organic material. For example, the resin substrate may include an epoxy resin, polyethylene, or polypropylene. The thickness of the support carrier 50 is, for example, 100 μm or more, or may be 200 μm or more, or may be 500 μm or more. The thickness of the support carrier 50 is, for example, 2 mm or less, or may be 1.5 mm or less, or may be 1 mm or less.

[0084] The release layer 51 is bonded to the second surface 20B of the interposer 20 and the second surface 30B of the redistribution layer chip 30, and is also bonded to the support carrier 50. The release layer 51 can be peeled off from the second surface 20B of the interposer 20 and the second surface 30B of the redistribution layer chip 30, for example, by heating. In this case, the release layer 51 may contain a thermoplastic resin. The thickness of the release layer 51 is, for example, 0.3 μm or more, and may be 1 μm or more. The thickness of the release layer 51 is, for example, 30 μm or less, and may be 50 μm or less.

[0085] The second mold resin layer 60 includes a resin, and the resin included in the second mold resin layer 60 may be, for example, any one of polyimide, epoxy resin, acrylic, bismaleimide, polybenzoxazole, and benzocyclobutene, or a combination of two or more of these. The second mold resin layer 60 may include a thermosetting resin. The resin included in the second mold resin layer 60 may be a thermosetting epoxy-based resin. The second mold resin layer 60 covers the interposer 20, the redistribution layer chip 30, the first semiconductor element 40, and the second semiconductor element 45. The second mold resin layer 60 is bonded to the interposer 20, the redistribution layer chip 30, the first semiconductor element 40, and the second semiconductor element 45. As a result, the second mold resin layer 60 holds the first semiconductor element 40 and the second semiconductor element 45 while attached to the interposer 20 and the redistribution layer chip 30.

[0086] The second mold resin layer 60 may cover the entire first semiconductor element 40 and the second semiconductor element 45 as shown in FIG. 2 . The second mold resin layer 60 may cover the first semiconductor element 40 and the second semiconductor element 45 while leaving portions of them exposed. The second mold resin layer 60 may fill the gap between the through portion 21 in the interposer 20 and the redistribution layer chip 30. The second mold resin layer 60 may also be bonded to the through portion 21 and the side surface of the redistribution layer chip 30. The thickness of the second mold resin layer 60 is, for example, 30 μm or more and may be 100 μm or more. The thickness of the second mold resin layer 60 is, for example, 300 μm or less and may be 600 μm or less. The thickness of the second mold resin layer 60 is the distance from the surface in contact with the interposer 20 to the surface opposite thereto.

[0087] Next, a method for manufacturing the semiconductor package 1 according to this embodiment will be described. In the manufacturing method described below, first, a manufacturing procedure for the redistribution layer chip intermediate 300 that serves as the base material for the redistribution layer chip 30 will be described. Next, a manufacturing procedure for the redistribution layer chip 30 manufactured from the redistribution layer chip intermediate 300 will be described. Then, a manufacturing procedure for the semiconductor package 1 manufactured using the redistribution layer chip 30 will be described.

[0088] First, when manufacturing redistribution layer chip intermediate body 300, chip carrier substrate 38M is prepared as shown in FIG. 6. A release layer 39M is formed on chip carrier substrate 38M. Redistribution layer chip 30 is one of multiple chips cut out from redistribution layer chip intermediate body 300. Release layer 39M corresponds to a portion including release layer 39 before being cut out as a component of redistribution layer chip 30.

[0089] The chip carrier substrate 38M may be, for example, a glass substrate or a silicon substrate (wafer). The shape of the chip carrier substrate 38M may be circular like a wafer. The diameter of the chip carrier substrate 38M may be, for example, 100 mm or more, 150 mm or more, or 200 mm or more. The diameter of the chip carrier substrate 38M may be, for example, 400 mm or less, 350 mm or less, or 300 mm or less. In this case, when forming the first rewiring layer 34 described below, a smaller exposure device can be used to form fine wiring compared to when forming the first rewiring layer 34 on a support carrier substrate 50P (described later) that is larger than the chip carrier substrate 38M. The release layer 39M may contain, for example, a thermoplastic resin. The release layer 39M may be formed by bonding, for example, a thermoplastic resin film to the chip carrier substrate 38M.

[0090] Next, as shown in FIG. 7A, multiple first redistribution layers 34 are formed on the release layer 39M. As shown in FIG. 7B, in this example, the first redistribution layers 34 are formed on a circular chip carrier substrate 38M. The multiple first redistribution layers 34 shown in FIGS. 7A and 7B include wiring that constitutes multiple redistribution layer chips 30. Such multiple first redistribution layers 34 are also referred to as a redistribution layer group 34M. The redistribution layer group 34M may be formed by photolithography. In this case, for example, a conductive layer made of copper or the like is first provided on the chip carrier substrate 38M. Next, a photosensitive resist film is provided on the conductive layer. Next, the resist film is exposed by an exposure device in a desired pattern corresponding to the first redistribution layers 34. Next, the resist film is removed. Thereafter, the conductive layer is etched to form the redistribution layer group 34M.

[0091] Next, as shown in FIG. 8 , the rewiring layer group 34M is covered with an insulating layer 33M. The insulating layer 33M corresponds to a portion including the insulating layer 33 before being cut out as a component of the rewiring layer chip 30. The insulating layer 33M may be formed by curing a material formed from, for example, polyimide, epoxy resin, acrylic resin, or a combination of two or more of these. The insulating layer 33M covers the surfaces of the rewiring layer group 34M other than the surface that contacts the release layer 39M so as to prevent the rewiring layer group 34M from being exposed. Here, the rewiring layer group 34M and the insulating layer 33M form a rewiring element portion 31M. The rewiring element portion 31M corresponds to a portion including the rewiring element 31 before being cut out as a component of the rewiring layer chip 30.

[0092] Next, as shown in FIG. 9A , the insulating layer 33M is covered with a first mold resin layer portion 32M. The first mold resin layer portion 32M corresponds to a portion including the first mold resin layer 32 before being cut out as a component of the redistribution layer chip 30. The first mold resin layer portion 32M may be formed by curing a material formed from, for example, one of polyimide, epoxy resin, acrylic, bismaleimide, polybenzoxazole, and benzocyclobutene, or a combination of two or more of these. Thereafter, as shown in FIGS. 9A and 9B , the first mold resin layer portion 32M is covered with an adhesive layer 36M. The adhesive layer 36M corresponds to a portion including the adhesive layer 36 before being cut out as a component of the redistribution layer chip 30. The adhesive layer 36M may be formed of a thermoplastic polyimide having heat-sensitive adhesive properties.

[0093] The rewiring layer chip intermediate body 300 is manufactured by the above procedure. The rewiring layer chip intermediate body 300 includes a rewiring element portion 31M, a first mold resin layer portion 32M containing resin, and a chip carrier substrate 38M. The rewiring element portion 31M has an insulating layer 33M and a plurality of first rewiring layers 34 embedded in, or in other words covered by, the insulating layer 33M. The rewiring element portion 31M includes a first surface (the lower surface in FIG. 9A ) and a second surface (the upper surface in FIG. 9A ) located opposite the first surface. Each first rewiring layer 34 includes a first conductive portion 30E including a first wiring 35, at least a portion of which is located on the first surface. The first mold resin layer portion 32M is attached to the second surface of the rewiring element portion 31M. The chip carrier substrate 38M contacts the first surface of the rewiring element portion 31M via a release layer 39M and supports the rewiring element portion 31M and the first mold resin layer portion 32M. The rewiring layer chip intermediate 300 further includes an adhesive layer 36M attached to the first molding resin layer portion 32M, and a release layer 39M provided between the rewiring element portion 31M and the chip carrier substrate 38M.

[0094] The rewiring layer chip intermediate 300 is then cut into a plurality of pieces as shown in FIGS. 10A and 10B. This cuts out a plurality of rewiring layer chips 30 from the rewiring layer chip intermediate 300. This manufactures the rewiring layer chip 30. Strictly speaking, FIGS. 10A and 10B show the pre-assembly rewiring layer chip 30′. FIG. 11 shows the rewiring layer chip 30 from which the chip carrier 38 and the release layer 39 have been removed. After the chip carrier 38 and the release layer 39 have been removed, the rewiring layer chip 30 is assembled as part of the semiconductor package 1. Although not shown, after the chip carrier substrate 38M and the release layer 39M are peeled off from the rewiring element portion 31M, the laminate including the rewiring element portion 31M and the first mold resin layer portion 32M may be cut into a plurality of pieces.

[0095] The following describes the manufacturing procedure of the semiconductor package 1. First, as shown in FIG. 12A, a support carrier substrate 50P is prepared. The area of ​​the support carrier substrate 50P is, for example, 0.5 m 2 More than 1.0m 2 It may be more than 2.0m 2 It may be more than 3.0m 2 A release layer 51M is formed on the support carrier substrate 50P. The release layer 51M corresponds to a portion including the release layer 51 before being cut out as a component of the semiconductor package 1.

[0096] 12B and 12C, an interposer layer 20M is formed on the supporting carrier substrate 50P. The interposer layer 20M corresponds to a portion including a plurality of interposers 20 before being cut out as components of the semiconductor package 1. The interposer layer 20M includes a plurality of through holes 21. In addition, a plurality of redistribution layer chips 30 are prepared.

[0097] Then, a redistribution layer chip 30 is disposed in each of the plurality of through holes 21. Specifically, as shown in FIGS. 13A and 13B , each redistribution layer chip 30 is disposed adjacent to a corresponding interposer 20 among the plurality of interposers 20 included in the interposer layer 20M, and the redistribution layer chip 30 is attached to the support carrier substrate 50P. The redistribution layer chip 30 is attached to the support carrier substrate 50P by being bonded to the release layer 51M via an adhesive layer 36. If the adhesive layer 36 has, for example, heat-sensitive adhesive properties, the redistribution layer chip 30 is disposed with the adhesive layer 36 in contact with the release layer 51M. Then, for example, the adhesive layer 36 may be heated to bond the adhesive layer 36 to the release layer 51M.

[0098] 13A and 13B is manufactured by attaching the redistribution layer chip 30 to the support carrier substrate 50P as described above. The semiconductor package intermediate 1M includes an interposer 20, a redistribution layer chip 30 adjacent to the interposer 20, and a support carrier substrate 50P that supports the interposer 20 and the redistribution layer chip 30. More specifically, the semiconductor package intermediate 1M includes an interposer layer 20M including a plurality of interposers 20, a plurality of redistribution layer chips 30 adjacent to the plurality of interposers 20, and a support carrier substrate 50P that supports the plurality of interposers 20 and the redistribution layer chips 30.

[0099] 14, pads 16 are provided on the first surface 20A of the interposer 20. The pads 16 are electrically connected to the through electrodes 14. Pads 37 are formed on the first surface 31A formed by part of the first wiring 35 of the redistribution layer chip 30. The pads 37 are electrically connected to the first wiring 35.

[0100] Next, as shown in FIGS. 15A and 15B , a first semiconductor element 40 and a second semiconductor element 45 are mounted so as to overlap the interposer 20 and the redistribution layer chip 30. Here, a plurality of combinations of the first semiconductor element 40 and the second semiconductor element 45 are arranged so as to overlap the corresponding interposer 20 and the redistribution layer chip 30. The first semiconductor element 40 is electrically connected to the through electrodes 14 of the interposer 20 via the pads 16. The first semiconductor element 40 is electrically connected to the first wiring 35 of the redistribution layer chip 30 via the pads 37. The second semiconductor element 45 is electrically connected to the through electrodes 14 of the interposer 20 via the pads 16. The second semiconductor element 45 is electrically connected to the first wiring 35 of the redistribution layer chip 30 via the pads 37.

[0101] Next, as shown in FIG. 16A, a second mold resin layer portion 60M is provided. The second mold resin layer portion 60M corresponds to a portion including the second mold resin layer 60 before being cut out as a component of the rewiring layer chip 30. This forms a semiconductor package block including a plurality of semiconductor packages 1. Thereafter, as shown in FIGS. 16A and 16B, the semiconductor packages 1 are cut out from the block. The second mold resin layer portion 60M is bonded to the first surfaces 20A of the plurality of interposers 20 and the first surface 30A of the rewiring layer chip 30. The second mold resin layer portion 60M is also bonded to the plurality of first semiconductor elements 40 and second semiconductor elements 45, and holds the plurality of first semiconductor elements 40 and second semiconductor elements 45. As a result, even if the support carrier 50 is peeled off from the interposer 20 and the rewiring layer chip 30 after the semiconductor package 1 is cut out from the block, the second mold resin layer 60 maintains the interposer 20, the rewiring layer chip 30, the first semiconductor element 40, and the second semiconductor element 45 in an integrated state. The second mold resin layer portion 60M may be formed by hardening a softened material. The second mold resin layer portion 60M may be formed by hardening a liquid material.

[0102] The semiconductor package 1 described above includes an interposer 20, a redistribution layer chip 30 adjacent to the interposer 20, and semiconductor elements 40 and 45 overlapping the interposer 20 and the redistribution layer chip 30. The redistribution layer chip 30 includes a redistribution element 31 including a first surface 31A on which the semiconductor elements 40 and 45 overlap, and a first mold resin layer 32 including a resin attached to a second surface 31B of the redistribution element 31 opposite the surface on which the semiconductor elements 40 and 45 overlap. The redistribution element 31 includes an insulating layer 33 having insulating properties and a first redistribution layer 34 covered by the insulating layer 33. The first redistribution layer 34 includes a first conductive portion 30E including a first wiring 35 at least a portion of which is located on the first surface 31A of the redistribution element 31 on which the semiconductor elements 40 and 45 overlap. The interposer 20 includes a second conductive portion 20E including through electrodes 14 located on the surface of the interposer 20 where the semiconductor elements 40 and 45 overlap. The semiconductor elements 40 and 45 are electrically connected to the first conductive portion 30E and the second conductive portion 20E.

[0103] In such a semiconductor package 1, the interposer 20 and the redistribution layer chip 30 are manufactured separately. The interposer 20 and the redistribution layer chip 30 are then integrated to manufacture the semiconductor package 1. This allows for the provision of large-sized semiconductor packages 1 at low cost. Specifically, if the interposer 20 and a portion corresponding to the redistribution layer chip 30 are simultaneously formed on a single support carrier substrate 50P or support carrier 50, the overall size increases, which may require the use of larger equipment, such as an exposure device, to form the fine wiring pattern included in the redistribution layer chip 30. This may increase facility costs. In contrast, if the redistribution layer chip 30 is manufactured at a location separate from the support carrier substrate 50P or support carrier 50, the redistribution layer chip 30 can be manufactured using, for example, existing small-sized equipment. This allows for the provision of large-sized semiconductor packages 1 at low cost and efficiently.

[0104] Furthermore, when the interposer 20 and the rewiring layer chip 30 are manufactured separately, the semiconductor package 1 is manufactured by integrating the interposer 20 and the rewiring layer chip 30. In this case, the rewiring layer chip 30 includes a rewiring element 31 and a first mold resin layer 32. The first mold resin layer 32 functions to suppress deformation of the rewiring element 31. Specifically, in the rewiring layer chip 30, the insulating layer 33 and the first rewiring layer 34 have different thermal expansion coefficients, which causes the rewiring element 31 to warp. In this case, the first mold resin layer 32 reinforces the insulating layer 33 and suppresses warping of the rewiring element 31. Therefore, deformation such as partial warping or distortion of the rewiring layer chip 30 in the semiconductor package 1 is suppressed. As a result, the portion where the interposer 20 and the rewiring layer chip are connected can be flattened, allowing the entire semiconductor package 1 to be formed flat. This allows the semiconductor package 1 to be formed large in the planar direction.

[0105] Therefore, according to this embodiment, it is possible to provide a large semiconductor package 1 at low cost, and deformation of the semiconductor package 1 can also be suppressed.

[0106] The above-described embodiment can be modified in various ways. Modifications will be described below with reference to the drawings as necessary. In the following description and the drawings used in the following description, parts that can be configured similarly to the above-described embodiment will be designated by the same reference numerals as those used for the corresponding parts in the above-described embodiment. Duplicate descriptions will be omitted. Furthermore, if it is clear that the effects obtained in the above-described embodiment can also be obtained in other embodiments, the descriptions of those effects may be omitted.

[0107] (Variation) Fig. 17 is a diagram showing a modified example of the redistribution layer chip 30. The redistribution layer chip 30 according to the modified example shown in Fig. 17 further includes a through electrode 32E located in a through hole 32A formed in the first molding resin layer 32. The through electrode 32E is electrically connected to the first redistribution layer 34.

[0108] In FIG. 17, a portion of the first rewiring layer 34 in the rewiring element 31 is located on the first surface 31A and the second surface 31B of the rewiring element 31. Specifically, a portion of the first wiring 35 located on the first surface 31A and a conductive portion 34E extending from the portion of the first wiring 35 through the insulating layer 33 to the second surface 31B are located on the first surface 31A and the second surface 31B of the rewiring element 31. The through electrode 32E is connected to the conductive portion 34E. To form the conductive portion 34E, for example, the first wiring 35 is formed on the release layer 39 (39M) and then the first wiring 35 is covered with the insulating layer 33. Then, a hole is formed in the insulating layer 33 to expose a portion of the first wiring 35 to the second surface 31B, and the conductive portion 34E is provided in the hole. The conductive portion 34E may be formed by electrolytic plating.

[0109] Fig. 18 is a diagram showing a modified example of the semiconductor package 1 of Fig. 1. In the semiconductor package 1 according to the modified example shown in Fig. 18, no gap is formed between the interposer 20 and the redistribution layer chip 30 disposed in the through-hole 21 of the interposer 20. The gap between the redistribution layer chip 30 and the interposer 20 may be filled with the same material as the material for forming the insulating layer 33, or may be filled with the second mold resin layer 60.

[0110] FIG. 19 is a diagram showing a semiconductor package 1′ according to one modified example. FIG. 20 is a cross-sectional view of the semiconductor package 1′ of FIG. 19 taken along line CC. The semiconductor package 1′ includes an interposer 20, a redistribution layer chip 30, two first semiconductor elements 40, two second semiconductor elements 45, one third semiconductor element 48, a support carrier 50, and a second molded resin layer 60. The interposer 20 has one through-hole 21 formed by a hole penetrating in the thickness direction. The redistribution layer chip 30 is disposed in the through-hole 21.

[0111] One of the two first semiconductor elements 40 overlaps the interposer 20 and the redistribution layer chip 30 in a plan view, in other words, when viewed in the third direction D3. The other of the two first semiconductor elements 40 overlaps the interposer 20 and the redistribution layer chip 30 in a position different from that of the first semiconductor element 40 in a plan view, in other words, when viewed in the third direction D3. The first semiconductor element 40 is electrically connected to both the interposer 20 and the redistribution layer chip 30. More specifically, one or more of the through electrodes 14 in the interposer 20 are electrically connected to each of the two first semiconductor elements 40. The redistribution layer chip 30 includes a first conductive portion 30E including first wiring 35 electrically connected to each of the first semiconductor elements 40.

[0112] One of the two second semiconductor elements 45 overlaps the interposer 20 and the redistribution layer chip 30 in a plan view, in other words, when viewed in the third direction D3. The other of the two second semiconductor elements 45 overlaps the interposer 20 and the redistribution layer chip 30 in a position different from that of the other second semiconductor element 45 in a plan view, in other words, when viewed in the third direction D3. The second semiconductor element 45 is electrically connected to both the interposer 20 and the redistribution layer chip 30. More specifically, one or more of the plurality of through electrodes 14 in the second conductive portion 20E of the interposer 20 are electrically connected to each of the two second semiconductor elements 45. The redistribution layer chip 30 includes first wiring 35 electrically connected to each of the second semiconductor elements 45.

[0113] The third semiconductor element 48 overlaps the redistribution layer chip 30 in a plan view, in other words, when viewed in the third direction D3. The third semiconductor element 48 is electrically connected to the first wiring 35 of the redistribution layer chip 30. More specifically, the third semiconductor element 48 is electrically connected to the first wiring 35 that is electrically connected to the first semiconductor element 40. The third semiconductor element 48 is electrically connected to the first wiring 35 that is electrically connected to the second semiconductor element 45. As a result, the first semiconductor element 40, the third semiconductor element 48, and the second semiconductor element 45 are electrically connected to one another.

[0114] FIG. 21 is a diagram showing a semiconductor package 1'' according to one modified example. FIG. 22 is a cross-sectional view of the semiconductor package 1'' of FIG. 21 taken along line DD. The semiconductor package 1'' includes an interposer 20, four redistribution layer chips 30, two first semiconductor elements 40, two second semiconductor elements 45, one third semiconductor element 48, a support carrier 50, and a second molded resin layer 60. The interposer 20 has four through holes 21 that penetrate the interposer 20 in the thickness direction. The four redistribution layer chips 30 are arranged in different through holes 21.

[0115] As in the modified examples shown in FIGS. 21 and 22, a plurality of redistribution layer chips 30 may be incorporated into one interposer 20. In the modified examples shown in FIGS.

[0116] FIG. 23 is a diagram showing a semiconductor package 1''' according to one modified example. The semiconductor package 1''' differs from the semiconductor package 1 shown in FIG. 2 in that a second insulating layer 70 is provided between the interposer 20 and the redistribution layer chip 30 and the second molded resin layer 60. The second insulating layer 70 may be, for example, polyimide, epoxy resin, acrylic resin, or a combination of two or more of these. In the illustrated example, the pads 16, 37 are embedded in the second insulating layer 70.

[0117] 24 is a diagram showing a semiconductor package intermediate 1M' according to one modified example. The semiconductor package intermediate 1M' includes an interposer 20, a redistribution layer chip 30 adjacent to the interposer 20, and a supporting carrier substrate 50P that supports the interposer 20 and the redistribution layer chip 30. Note that FIG. 24 shows only a portion of the semiconductor package intermediate 1M'. In reality, the semiconductor package intermediate 1M' includes an interposer layer 20M including a plurality of interposers 20, a plurality of redistribution layer chips 30 adjacent to the plurality of interposers 20, and a supporting carrier substrate 50P that supports the plurality of interposers 20 and the redistribution layer chips 30.

[0118] In the semiconductor package intermediate 1M′ of FIG. 24, the first surface 20A of the interposer 20 is covered with a third insulating layer 80. Pads 16 are provided on the third insulating layer 80. The pads 16 protrude from the first surface 20A. The pads 16 are electrically connected to the through electrodes 14 of the interposer 20 exposed from the first surface 20A via connection conductive portions 16a that penetrate the third insulating layer 80. Furthermore, the insulating layer 33 of the rewiring element 31 of the rewiring layer chip 30 embeds first wiring 35, and the insulating layer 33 is provided with connection conductive portions 37a that are electrically connected to part of the first wiring 35. Furthermore, the rewiring layer chip 30 is provided with pads 37. The pads 37 protrude from the first surface 30A of the rewiring layer chip 30. The pads 37 are electrically connected to the first wiring 35 via the connection conductive portions 37a.

[0119] That is, the semiconductor package intermediate 1M' integrally includes pads 16 and 37, with the pad 16 held by the third insulating layer 80 and the pad 37 held by the insulating layer 33. When the first semiconductor element 40 and the second semiconductor element 45 are mounted on this semiconductor package intermediate 1M', the first semiconductor element 40 and the second semiconductor element 45 overlap the third insulating layer 80 and the insulating layer 33, and thereby overlap the interposer 20 and the redistribution layer chip 30. The third insulating layer 80 may be made of, for example, polyimide, epoxy resin, acrylic resin, or a combination of two or more of these. Note that bumps may be formed in the semiconductor package intermediate 1M' instead of the pads 16 and 37.

[0120] 25A and 25B are diagrams illustrating an example of a method for manufacturing a semiconductor package intermediate 1M'. First, as shown in FIG. 25A, a support carrier substrate 50P having an interposer layer 20M formed thereon is prepared. The interposer layer 20M corresponds to a portion including a plurality of interposers 20 before being cut out as components of the semiconductor package 1. The interposer layer 20M includes a plurality of through holes 21.

[0121] Next, a plurality of redistribution layer chips 30 are prepared. Here, in the redistribution layer chip 30 according to the modified example, the connection conductive portions 37a are integrated with the redistribution elements 31 in a state where they are exposed from the insulating layer 33. Then, as shown in FIG. 25(B), the redistribution layer chip 30 is placed in each of the plurality of through holes 21, and the redistribution layer chip 30 is attached to the supporting carrier substrate 50P. The redistribution layer chip 30 is attached to the supporting carrier substrate 50P by being bonded to the release layer 51M via the adhesive layer 36.

[0122] 25(C), a forming material 80M for forming a third insulating layer 80 is applied to the interposer 20 and the redistribution layer chip 30. The forming material 80M covers the first surface 20A of the interposer 20 and also covers the redistribution layer chip 30. The forming material 80M may be, for example, a film, and may be applied in a state of being in close contact with the interposer 20 and the redistribution layer chip 30 by vacuum lamination. In the illustrated example, a portion of the forming material 80M is filled in the gap between the interposer 20 and the redistribution layer chip 30.

[0123] The forming material 80M is a photosensitive material, and is exposed to light in areas other than the non-exposed portions NE shown in FIG. 25(C). This exposure hardens a portion of the forming material 80M, leaving the non-exposed portions NE unhardened. The non-exposed portions NE are then removed to form the third insulating layer 80 with through holes. The redistribution layer chip 30 is also exposed to the outside. Then, plating is grown within the through holes in the third insulating layer 80, for example, by electrolytic plating.

[0124] Then, plating grows sufficiently in the through holes in the third insulating layer 80, thereby forming the connection conductive portions 16a as shown in FIG. 25(D). Thereafter, plating is grown from the connection conductive portions 16a, 37a to form the pads 16, 37. This results in a semiconductor package intermediate 1M'. When bumps are formed instead of the pads 16, 37, the bumps may be formed by plating or printing.

[0125] 26A and 26B are diagrams illustrating a method for manufacturing the rewiring layer chip 30 that constitutes the semiconductor package intermediate 10M'.

[0126] In this example, first, as shown in FIG. 26A(A), a pre-process chip carrier substrate 38M' is prepared. Then, a pre-process release layer 39M' is formed on the pre-process chip carrier substrate 38M'. Next, as shown in FIG. 26A(B), multiple first redistribution layers 34 are formed on the pre-process release layer 39M'. Note that although only one first redistribution layer 34 is shown in FIG. 26A(B), multiple first redistribution layers 34 are actually formed. The multiple first redistribution layers 34 include wiring that constitutes multiple redistribution layer chips 30.

[0127] 26A(C), the first redistribution layers 34 are covered with a pre-processing insulating layer 33M1. The pre-processing insulating layer 33M1 is made of a photosensitive material. The pre-processing insulating layer 33M1 may be formed by curing a material such as polyimide, epoxy resin, acrylic resin, or a combination of two or more of these.

[0128] Next, the area of ​​the previous-process insulating layer 33M1 other than the non-exposed portion NE shown in FIG. 26A(C) is exposed. The non-exposed portion NE is then removed, and the remaining portion of the previous-process insulating layer 33M1 is hardened. This forms a hole that exposes a portion of the wiring in the first redistribution layer 34. Then, plating is grown in the hole formed in the previous-process insulating layer 33M1, for example, by electrolytic plating, to form the connecting conductive portion 37a as shown in FIG. 26A(D).

[0129] Then, as shown in FIG. 26A(E), the pre-process chip carrier substrate 38M' and the pre-process release layer 39M' are peeled off from the pre-process insulating layer 33M1 on which the first rewiring layer 34 and the connection conductive portions 37a are formed.

[0130] Next, as shown in FIG. 26B(F), a chip carrier substrate 38M is prepared, and a release layer 39M is formed on the chip carrier substrate 38M. Then, the release layer 39M and a pre-process insulating layer 33M1 are bonded together so that the connection conductive portions 37a contact the release layer 39M. Next, as shown in FIG. 26B(G), a post-process insulating layer 33M2 is provided on the pre-process insulating layer 33M1. The post-process insulating layer 33M2 covers the first redistribution layer 34. Here, the pre-process insulating layer 33M1 and the post-process insulating layer 33M2 form the insulating layer 33M. Thereafter, as shown in FIG. 26B(H), the insulating layer 33M is covered with a first mold resin layer portion 32M and an adhesive layer 36M. This forms a redistribution layer chip intermediate body. Then, a plurality of redistribution layer chips 30 are cut out from the redistribution layer chip intermediate body.

[0131] 26C and 26D are diagrams illustrating another method for manufacturing the redistribution layer chip 30. In this example, the redistribution layer chip 30 before being incorporated into the interposer 20 has the connection conductive portions 37a and the pads 37 integrated therewith.

[0132] In this example, first, as shown in FIG. 26C(A), a pre-process chip carrier substrate 38M' is prepared. Then, a pre-process release layer 39M' is formed on the pre-process chip carrier substrate 38M'. Next, as shown in FIG. 26C(B), a plurality of first rewiring layers 34 are formed on the pre-process release layer 39M'. The plurality of first rewiring layers 34 include wiring that constitutes a plurality of rewiring layer chips 30. Next, as shown in FIG. 26C(C), the plurality of first rewiring layers 34 are covered with a pre-process insulating layer 33M1.

[0133] Next, the pre-process chip carrier substrate 38M' and the pre-process release layer 39M' are peeled off from the first redistribution layer 34 and the pre-process insulating layer 33M1. Then, as shown in FIG. 26C(D), a middle-process chip carrier substrate 38M" and a middle-process release layer 39M" are provided on the surface of the first redistribution layer 34 and the pre-process insulating layer 33M1 opposite to the surfaces on which the middle-process chip carrier substrate 38M' and the pre-process release layer 39M' were provided.

[0134] Thereafter, as shown in FIG. 26C(E), a post-process insulating layer 33M2 is provided on the surface where the first redistribution layer 34 is exposed. The post-process insulating layer 33M2 covers the first redistribution layer 34. Next, the region of the post-process insulating layer 33M2 other than the non-exposed portion NE shown in FIG. 26C(E) is exposed. The non-exposed portion NE is then removed, and the remaining portion of the post-process insulating layer 33M2 is hardened. This forms a hole exposing a portion of the wiring in the first redistribution layer 34. Then, by growing a plating by, for example, electrolytic plating, in the hole formed in the post-process insulating layer 33M2, the connecting conductive portion 37a is formed as shown in FIG. 26C(F). The pre-process insulating layer 33M1 and the post-process insulating layer 33M2 form the insulating layer 33M.

[0135] Thereafter, as shown in FIG. 26D(G), plating is grown from the connection conductive portions 37a to form pads 37. Thereafter, as shown in FIG. 26D(H), a chip carrier substrate 38M on which a release layer 39M is formed is prepared. Then, the chip carrier substrate 38M is provided on the insulating layer 33M so that the release layer 39M and the pads 37 are in contact with each other. Thereafter, as shown in FIG. 26D(I), the intermediate process chip carrier substrate 38M″ and the intermediate process release layer 39M″ are peeled off. Thereafter, as shown in FIG. 26D(J), the insulating layer 33M is covered with the first mold resin layer portion 32M and the adhesive layer 36M. This forms a rewiring layer chip intermediate body. Then, a plurality of rewiring layer chips 30 are cut out from the rewiring layer chip intermediate body.

[0136] FIG. 27 is a diagram showing a semiconductor package intermediate 1M″ according to yet another modified example. The semiconductor package intermediate 1M″ includes an interposer 20, a redistribution layer chip 30 adjacent to the interposer 20, and a supporting carrier substrate 50P that supports the interposer 20 and the redistribution layer chip 30. The redistribution layer chip 30 is fabricated by the process described with reference to FIGS. 26C and 26D, and has pads 37 before being incorporated into the interposer 20. Note that FIG. 27 shows only a portion of the semiconductor package intermediate 1M″. In reality, the semiconductor package intermediate 1M″ includes an interposer layer 20M including a plurality of interposers 20, a plurality of redistribution layer chips 30 adjacent to the plurality of interposers 20, and a supporting carrier substrate 50P that supports the plurality of interposers 20 and the redistribution layer chips 30.

[0137] In the semiconductor package intermediate 1M'', the interposer layer 20M has a multi-layer structure and includes a first interposer layer 20M1 and a second interposer layer 20M2 stacked on the first interposer layer 20M1. The redistribution layer chip 30 is arranged so as to overlap the first interposer layer 20M1, and in this state is adjacent to the second interposer layer 20M2.

[0138] FIG. 28 is a diagram illustrating an example of a method for manufacturing a semiconductor package intermediate 1M″. First, as shown in FIG. 28(A), a support carrier substrate 50P having a first interposer layer 20M1 formed thereon is prepared. Next, as shown in FIG. 28(B), a redistribution layer chip 30 is provided on the first interposer layer 20M1. Thereafter, as shown in FIG. 28(C), a second interposer layer 20M2 is provided so as to surround the redistribution layer chip 30. Then, connection conductive portions 16a and pads 16 are formed on the second interposer layer 20M2. These connection conductive portions 16a and pads 16 can be formed by the same process as the process described in FIG. 25.

[0139] The semiconductor package intermediate 1M'' shown in Figures 27 and 28 described above includes an interposer 20, a redistribution layer chip 30 adjacent to the interposer 20, and a support carrier substrate 50P that supports the interposer 20 and the redistribution layer chip 30. More specifically, the interposer 20 has a multi-layer structure, and some of the layers constituting the interposer 20 are adjacent to the redistribution layer chip 30. Needless to say, in a semiconductor package formed using the semiconductor package intermediate 1M'', some of the layers constituting the interposer 20 are adjacent to the redistribution layer chip 30.

[0140] Next, FIG. 29 is a diagram showing a modification of the redistribution layer chip shown in FIG. 5. In the example shown in FIG. 29, each first wiring 35 of the first redistribution layer 34 is covered with an inorganic film 35a. The inorganic film 35a has insulating properties. The inorganic film 35a may be formed of, for example, silicon oxide (SiO2) or silicon nitride (SiN). The inorganic film 35a suppresses loss of electrical energy when a high-frequency current flows. Here, the dielectric loss tangent of the insulating layer 33 is preferably 0.01 or less. In this case, the inorganic film 35a and the insulating layer 33 with a low dielectric loss tangent can effectively suppress loss of electrical energy. The insulating layer 33 may be formed of polyimide. In the illustrated example, the inorganic film 35a covers exposed portions of each first wiring 35 provided on the surface of the release layer 39. The exposed portions of the first wiring 35 are the side and front surfaces of the first wiring 35, excluding the back surface of the first wiring 35 that contacts the surface of the release layer 39, but the connection portions with other conductive portions are not covered by the inorganic film 35a. In the illustrated example, the inorganic film 35a covers the entire surface of the release layer 39 where the first wiring 35 is not provided. As a result, the inorganic film 35a covers the portions of the surface of the release layer 39 that are located between adjacent first wirings 35. The inorganic film 35a also covers the portion of the surface of the release layer 39 from its outer edge to the first wiring 35 located on the outermost periphery. In the illustrated example, the multiple first wirings 35 are provided in a line-and-space pattern, and the line width of the first wiring 35 and the spacing between adjacent first wirings 35 are the same, e.g., 1.5 μm. The aspect ratio of the first wiring 35 is approximately 2.5. However, the dimensional conditions are not particularly limited. The inorganic film 35a does not have to cover the entire surface of the release layer 39. For example, by removing a portion of the inorganic film 35a from the state shown in Figure 29, a state may be created in which the inorganic film 35a does not cover the portion of the surface of the peeling layer 39 from its outer edge to the first wiring 35 located on the outermost side.

[0141] (Examples of products equipped with semiconductor packages) 30 is a diagram showing an example of a product equipped with the semiconductor package 1. The semiconductor package 1 can be used in a variety of products. For example, it can be equipped in a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smartphone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server, etc.

[0142] It is also possible to combine the multiple components disclosed in the above-described embodiments and modifications as needed, or to delete some of the components disclosed in the above-described embodiments and modifications. [Explanation of symbols]

[0143] 1,1',1'',1'''...Semiconductor package 1M: Semiconductor packaging intermediates 14...Through electrode 15…Second wiring 16...Pad 20...Interposer 20A…1st surface 20B…Second surface 20E...Second conductive part 20M...Interposer layer 21...Penetration section 22...Interposer insulating layer 22A…Through hole 24…Second redistribution layer 30...Rewiring layer chip 30'...Pre-embedded rewiring layer chip 30A…1st surface 30B…Second surface 30E...First conductive part 31…Rewiring element 31M…Rewiring element part 31A…Side 1 31B…Second side 32...First mold resin layer 32M: First mold resin layer 32A…Through hole 32E…Through electrode 33...insulating layer 33M...insulating layer 34…1st redistribution layer 34M…Rewiring layer group 35...1st wiring 36...adhesive layer 37...Pad 38...Chip carrier 38M...Chip carrier board 39...Peeling layer 39M...peeling layer 40...First semiconductor element 45...Second semiconductor element 50...Support carrier 50P...Support carrier board 51...peeling layer 51M...peeling layer 60...Second mold resin layer 60M: Second mold resin layer 70...Second insulating layer 110...Notebook personal computer 120...Tablet device 130...Mobile phone 140...Smartphone 150...Digital video camera 160...Digital camera 170...Digital clock 180...server 300...Rewiring layer chip intermediate D1…first direction D2…Second direction D3…Third direction

Claims

[Claim 1] an interposer; a redistribution layer chip adjacent to the interposer; a semiconductor element overlying the interposer and the redistribution layer chip; the redistribution layer chip includes a redistribution element including a surface on which the semiconductor element overlaps, and a first molding resin layer attached to a surface of the redistribution element located opposite to the surface on which the semiconductor element overlaps, the first molding resin layer including a resin; the rewiring element includes an insulating layer having insulating properties and a first rewiring layer covered by the insulating layer, the first rewiring layer including a first conductive portion at least part of which is located on a surface of the rewiring element that overlaps with the semiconductor element; the insulating layer of the redistribution element includes a side surface facing the interposer in a direction in which the redistribution layer chip is adjacent to the interposer; the interposer includes a second redistribution layer including a second conductive portion located on a surface of the interposer on which the semiconductor element overlaps; the semiconductor element is electrically connected to the first conductive portion and the second conductive portion; the semiconductor device includes a first semiconductor device and a second semiconductor device; a first conductive portion of the first rewiring layer of the rewiring element including a first wiring that electrically connects the first semiconductor element and the second semiconductor element;

Images