Power conversion device

Abstract

To provide an MMC type power conversion device that can stably continue its operation.SOLUTION: An embodiment comprises an arm that has a plurality of unit converters, and a control section that generates a plurality of gate signals for controlling the plurality of unit converters. Each of the plurality of unit converters includes a series circuit of two switching elements, and a capacitor that is connected in parallel with the two switching elements. The control section has a phase shift PWM control circuit, a DC voltage increase prevention control circuit, and a gate signal rearrangement circuit. The phase shift PWM control circuit generates a plurality of phase-shifted gate signals. The DC voltage increase prevention control circuit performs monitoring so that the voltage across both ends of the plurality of capacitors does not exceed a predetermined upper limit value. The signal gate rearrangement circuit rearranges the output order of the plurality of gate signals when the voltage of the capacitor is estimated to exceed the upper limit value.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a power conversion device using a modular multilevel converter. [Background technology]

[0002] Power conversion devices that use the modular multilevel converter (MMC) method are increasingly being introduced into the market.

[0003] MMC power conversion devices are easily adaptable to high power output, and are therefore used in infrastructure-related power equipment such as power grids. When applied to such power equipment, stable and continuous operation is desirable. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 7387062 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of an embodiment of the present invention is to provide an MMC type power conversion device that can continue to operate stably. [Means for solving the problem]

[0006] A power conversion device according to an embodiment of the present invention comprises an arm having a plurality of unit converters connected in series, and a control unit that generates a plurality of gate signals for controlling each of the plurality of unit converters. Each of the plurality of unit converters includes a capacitor and two switching elements that are connected in series and operate complementarily to charge and discharge the capacitor. The control unit comprises a phase-shift PWM control circuit that generates the plurality of gate signals based on a voltage reference signal and each of a plurality of carrier signals that are set with a phase shift according to the number of the plurality of unit converters, a DC voltage rise prevention control circuit that receives as input the voltage values ​​across the capacitors of each of the plurality of unit converters and generates an on / off priority command that prioritizes and activates a gate signal for a unit converter with a lower voltage value across the capacitor, and and a gate signal switching circuit that switches and sets the order in which the plurality of gate signals become active based on the on / off priority command. When the DC voltage rise prevention control circuit estimates that a first voltage across both ends of a capacitor of one of the plurality of unit converters will reach a preset upper limit value in each period of the plurality of carrier signals corresponding to the plurality of unit converters respectively, it changes the on / off priority command so that, in a period following the period, a unit converter of the plurality of unit converters that has a capacitor with a voltage value lower than the first voltage is preferentially turned on. [Effects of the Invention]

[0007] According to the embodiment of the present invention, it is possible to provide an MMC type power conversion device that can continue to operate stably. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic block diagram illustrating a power conversion device according to an embodiment; [Figure 2] 2 is a schematic equivalent circuit diagram illustrating a unit converter that is a part of the power conversion device according to the embodiment. FIG. [Figure 3]FIG. 2 is a schematic block diagram illustrating a control unit that is a part of the power conversion device according to the embodiment. [Figure 4] 3 is a schematic operational waveform diagram showing the operation of the power conversion device according to the embodiment. FIG. [Figure 5] FIG. 10 is a schematic block diagram illustrating a control unit that is a part of a power conversion device of a comparative example. [Figure 6] FIG. 10 is a schematic operational waveform diagram showing the operation of a power conversion device of a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In the present specification and the drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0010] FIG. 1 is a schematic block diagram illustrating a power conversion device according to an embodiment. 1, the power converter 100 includes a plurality of arms 10. The power converter 100 has AC terminals 101a to 101c and DC terminals 101d and 101e.

[0011] A three-phase AC power supply or a load operated by three-phase AC is connected to the AC terminals 101a to 101c. The three-phase AC power supply is, for example, an AC power system. The load operated by AC is, for example, an AC motor. A DC power supply or a load operated by DC is connected to the DC terminals 101d and 101e. The DC power supply is, for example, a DC power system. Also, for example, a storage battery may be connected to the DC terminals 101d and 101e as a DC power supply or a DC load. A DC voltage is output or input between the DC terminals 101d and 101e. The DC voltage output from or applied to the DC terminal 101d is higher than the DC voltage output from or applied to the DC terminal 101e.

[0012] The power conversion device 100 converts AC to DC and DC to AC. For example, the power conversion device 100 is a bidirectional AC / DC power conversion device.

[0013] Six arms 10 are provided. The power conversion device 100 includes a U-phase upper arm, a V-phase upper arm, a W-phase upper arm, a U-phase lower arm, a V-phase lower arm, and a W-phase lower arm. The U-phase upper arm is connected between the DC terminal 101d and the AC terminal 101a. The V-phase upper arm is connected between the DC terminal 101d and the AC terminal 101b. The W-phase upper arm is connected between the DC terminal 101d and the AC terminal 101c. The U-phase lower arm is connected between the AC terminal 101a and the DC terminal 101e. The V-phase lower arm is connected between the AC terminal 101b and the DC terminal 101e. The W-phase lower arm is connected between the AC terminal 101c and the DC terminal 101e.

[0014] The U-phase upper arm, V-phase upper arm, W-phase upper arm, U-phase lower arm, V-phase lower arm, and W-phase lower arm all have the same configuration. Each arm 10 has a plurality of unit converters (referred to as "cells" in FIG. 1) 20 connected in series. The plurality of unit converters 20 have the same configuration. Each arm 10 further has a reactor 40, which is connected in series to the series circuit of the plurality of unit converters 20.

[0015] FIG. 2 is a schematic equivalent circuit diagram illustrating a unit converter that is a part of the power conversion device according to the embodiment. As shown in FIG. 2, unit converter 20 includes switching elements 22a and 22b, a capacitor 24, and connection terminals 21a and 21b.

[0016] The switching element 22a is composed of a self-extinguishing switching element such as an IGBT or MOSFET and a diode connected in anti-parallel to the self-extinguishing switching element. The switching element 22b is composed of a self-extinguishing switching element such as an IGBT or MOSFET and a diode connected in anti-parallel to the self-extinguishing switching element. The switching element 22a is connected in series to the switching element 22b. The switching element 22a is connected to the high-potential side of the switching element 22b.

[0017] The series circuit of the switching elements 22a and 22b is connected in parallel to a capacitor 24.

[0018] The connection terminal 21a is connected to a connection node of the series circuit of the switching elements 22a and 22b, and the connection terminal 21b is connected to a terminal on the low potential side of the capacitor.

[0019] A gate signal VG1 is input to the gate terminal of switching element 22a. A gate signal VG2 is input to the gate terminal of switching element 22b. The gate signals VG1 and VG2 are complementary signals. When the gate signal VG1 is active, the gate signal VG2 is inactive, and when the gate signal VG2 is active, the gate signal VG1 is inactive. Below, it may be stated that when the gate signal VG1 is active, the unit converter 20 is ON, and when the gate signal VG1 is inactive, the unit converter 20 is OFF.

[0020] When the switching element 22a is turned on, the unit converter 20 charges or discharges the capacitor 24, and outputs the voltage VCELL across the capacitor 24 between the connection terminals 21a and 21b.

[0021] As shown in FIG. 1, N unit converters 20 are connected in series. Hereinafter, the N unit converters 20 may be referred to as the first unit converter, the second unit converter, the third unit converter, ... the i-th unit converter, ... the N-th unit converter, etc., from the high-potential side. For the i-th unit converter, where "i" is an integer satisfying 1≦i≦N, the gate signal for switching element 22a may be represented as VG1(i), the gate signal for switching element 22b may be represented as VG2(i), and the voltage across capacitor 24 may be represented as VCELL(i). The symbol for the i-th unit converter may also be represented as "20_i." Note that FIG. 2 shows an example of the first unit converter 20_1. The value of voltage VCELL is measured relative to the potential of the low-potential terminal of capacitor 24, i.e., connection terminal 21b.

[0022] Connecting the unit converters 20 in series means connecting the high-potential side connection terminal 21a of the ith unit converter 20_i to the low-potential side connection terminal 21b of the (i-1)th unit converter 20_i-1, and connecting the low-potential side connection terminal 21b of the ith unit converter 20_i to the high-potential side connection terminal 21a of the (i+1)th unit converter 20_i+1. However, the high-potential side connection terminal 21a of the first unit converter 20_1 is connected to the DC terminal 101d, for example. Furthermore, the low-potential side connection terminal 21b of the Nth unit converter 20_N is connected to the AC terminal 101a, for example, via the reactor 40.

[0023] In the power conversion device 100, the ON phases of the N unit converters 20 in the arm 10 are set according to the phase of the input or output AC voltage. The phases in which the N unit converters 20 are turned ON are set to be shifted by 360° / N. In the power conversion device 100, the order in which the unit converters 20 are turned ON is set according to the value of the voltage VCELL across the capacitor 24 of the unit converter 20, for example, for each cycle of the AC voltage.

[0024] The N unit converters 20 are turned on in ascending order of voltage VCELL during the charging period of the capacitor 24 when the value of the voltage VCELL increases. The N unit converters 20 are turned on in descending order of voltage VCELL during the discharging period of the capacitor 24 when the value of the voltage VCELL decreases.

[0025] For example, in the case of the upper arm, a current flows from the DC terminal 101d side to the AC terminal side during charging of the capacitor 24. For example, in the case of the upper arm, a current flows from the AC terminal side to the DC terminal 101d side during discharging of the capacitor 24.

[0026] FIG. 3 is a schematic block diagram illustrating a control unit that is a part of the power conversion device according to the embodiment. In the power conversion device 100 according to the embodiment, the control unit 60 measures the voltage VCELL for each arm 10 in the carrier cycle set for all of the unit converters 20. The control unit 60 sets the order in which the unit converters 20 are turned on according to the value of the measured voltage VCELL. When the control unit 60 estimates that the value of the measured voltage VCELL will reach the upper limit value VOV0, it changes the order in which the unit converters 20 are turned on in the next carrier cycle, regardless of the set order in which they are turned on. The control unit 60 changes the order in which the unit converters 20 are turned on so that the value of the voltage VCELL does not reach the upper limit value VOV0.

[0027] 3, the power conversion device 100 includes a control unit 60. The control unit 60 includes a phase shift PWM control circuit 62, a gate signal switching circuit 64, a DC voltage rise prevention control circuit 66, and a control trigger timing generation circuit 68.

[0028] The phase-shift PWM control circuit 62 receives a voltage reference signal Vref and a carrier signal Vc0. The voltage reference signal Vref is generated for each phase of the three-phase AC voltage. The voltage reference signal Vref is a reference signal for outputting a voltage of, for example, the U phase. The carrier signal Vc0 is a triangular wave signal having a carrier frequency for PWM control. The carrier frequency is the reciprocal of the carrier period. The carrier signal Vc0 is generated according to the number of unit converters 20 in one arm 10. More specifically, in the case of an arm consisting of N unit converters 20, N carrier signals Vc0 are generated with their phases shifted by 360° / N.

[0029] The phase-shift PWM control circuit 62 compares the input voltage reference signal Vref with the carrier signal Vc0, and, for example, when the voltage value of the voltage reference signal Vref is higher than the voltage value of the carrier signal Vc0, generates gate signals VG1 and VG2 so as to turn on the unit converter 20. The phase-shift PWM control circuit 62 outputs the generated N gate signals VG1(1) to VG1(N) to the gate signal switching circuit 64.

[0030] The gate signal switching circuit 64 receives the gate signals VG1(1) to VG1(N) output from the phase shift PWM control circuit 62 for all the unit converters 20_1 to 20_N.

[0031] The gate signal switching circuit 64 switches the order of the gate signals VG1(1) to VG1(N) so as to set the order of turning on the unit converters 20_1 to 20_N based on the on / off priority command output from the DC voltage rise prevention control circuit 66. For example, if the on / off priority command is set to turn on the i-th unit converter 20_i, the second unit converter 20_2, the third unit converter 20_3, ..., the first unit converter 20_1, ..., the N-th unit converter 20_N in that order, the output order of the gate signals is switched on so that the unit converters are turned on in this order.

[0032] The DC voltage rise prevention control circuit 66 receives as input the voltages VCELL(1) to VCELL(N) across the capacitors 24 of all the unit converters 20_1 to 20_N. The DC voltage rise prevention control circuit 66 also receives as input a control trigger signal output from a control trigger timing generation circuit 68.

[0033] The order in which the unit converters 20 are turned on is set as an initial value of the on / off priority command in the DC voltage rise prevention control circuit 66. The order in which the unit converters 20 are turned on is, for example, in ascending order of the value of the voltage VCELL during the charging period of the capacitor 24, and in descending order of the value of the voltage VCELL during the discharging period of the capacitor 24.

[0034] A threshold value VOV1 is preset in the DC voltage rise prevention control circuit 66. The threshold value VOV1 is set to estimate that the absolute value of the voltage VCELL will increase and reach the upper limit value VOV0. The threshold value VOV1 has a voltage value lower than the upper limit value VOV0. The DC voltage rise prevention control circuit 66 compares each value of the voltages VCELL(1) to VCELL(N) with the threshold value VOV1 at the timing when the control trigger signal is input. When the DC voltage rise prevention control circuit 66 detects that any one of the values ​​of the voltages VCELL(1) to VCELL(N) has reached the threshold value VOV1, it generates an on / off priority command to change the order in which the unit converters 20 are turned on, and outputs the command to the gate signal switching circuit 64.

[0035] The DC voltage rise prevention control circuit 66 generates an ON / OFF priority command to change the order in which the unit converters 20 are turned ON so that the value of the voltage VCELL does not reach the upper limit value VOV0. When changing the order in which the unit converters 20 are turned ON, for example, during the period in which the capacitor 24 is being charged, the DC voltage rise prevention control circuit 66 generates an ON / OFF priority command to turn ON, in place of the unit converter 20 that is currently turned ON, a unit converter 20 that has a voltage VCELL value lower than that of that unit converter.

[0036] The control trigger timing generation circuit 68 receives the voltage reference signal Vref and the estimation carrier signal Vc1. The voltage reference signal Vref is the same signal as the signal input to the phase shift PWM control circuit 62. The estimation carrier signal Vc1 is generated for every unit converter 20 in one arm. The estimation carrier signal Vc1 is a triangular wave signal having the same period and amplitude as the carrier signal Vc0. The estimation carrier signal Vc1 has a phase that is more advanced than the carrier signal Vc0.

[0037] Carrier signal Vc1 for estimation leads by a fixed phase from carrier signal Vc0 generated for each unit converter 20. For example, for unit converter 20_1, carrier signal Vc1(1) for estimation leads by a phase θ from carrier signal Vc0(1). For the other unit converters 20_2 to 20_N, carrier signals Vc1(2) to Vc1(N) for estimation also lead by a phase θ from carrier signals Vc0(2) to Vc(N), respectively.

[0038] The phase lead of the estimation carrier signal Vc1 relative to the carrier signal Vc0 is set in accordance with the calculation processing time, delay time, etc. of the circuits constituting the control unit 60. More specifically, the control trigger timing generation circuit 68 generates a control trigger signal, and the phase is set to a time that is sufficiently longer than the time it takes for the gate signal switching circuit 64 to switch the ON order of the unit converters 20.

[0039] The control trigger timing generation circuit 68 compares the voltage reference signal Vref with the estimation carrier signal Vc1, and generates a control trigger signal at the timing when the voltage value of the estimation carrier signal Vc1 reaches the voltage value of the voltage reference signal Vref, and outputs the control trigger signal to the DC voltage rise prevention control circuit 66.

[0040] The operation of the control unit 60 will be described in detail with reference to operating waveforms. FIG. 4 is a schematic operational waveform diagram showing the operation of the power conversion device according to the embodiment. The signal waveforms at the top of Fig. 4 show the time change of the carrier signal Vc0(1) for the unit converter 20_1, the carrier signal Vc1(1) for estimation, and the voltage reference signal Vref for the arm 10 including the unit converters 20_1 to 20_N. Note that in Fig. 4, the frequency of the voltage reference signal Vref is sufficiently lower than the frequencies of the carrier signal Vc0(1) etc., so it looks like a DC voltage on the drawing, but the voltage reference signal is, for example, a sine wave of a commercial frequency. The signal waveforms in the second and third stages of FIG. 4 show the time changes of the gate signals VG1(1) and VG2(1) for the unit converter 20_1. 4 shows the change over time of the voltage VCELL(1) of the unit converter 20_1, and for comparison, the threshold value VOV1 and the upper limit value VOV0 are also shown. Note that the upper limit value VOV0 is shown for comparison purposes and is not necessarily set in the DC voltage rise prevention control circuit 66. The horizontal axis of these operation waveform diagrams represents time.

[0041] As shown in FIG. 4, the phase of the carrier signal Vc1(1) for estimation leads the phase of the carrier signal Vc0(1) by a phase θ corresponding to the period t2-t1. Time t1 is the time when the voltage value of the carrier signal Vc1(1) for estimation reaches the voltage value of the voltage reference signal Vref. Time t2 is the time when the voltage value of the carrier signal Vc0(1) reaches the voltage value of the voltage reference signal Vref. At time t1, the DC voltage rise prevention control circuit 66 outputs a control trigger signal to the DC voltage rise prevention control circuit 66.

[0042] At time t1, DC voltage rise prevention control circuit 66 receives a control trigger signal and compares the voltage value of voltage VCELL(1) with threshold value VOV1. In the example of Fig. 4, the voltage value of voltage VCELL(1) is higher than threshold value VOV1, so DC voltage rise prevention control circuit 66 generates an ON / OFF priority command to turn on, for example, the unit converter having the lowest value of voltage VCELL, and outputs the command to gate signal switching circuit 64. If the value of voltage VCELL(i) is the lowest among the values ​​of voltages VCELL(1) to VCELL(N), the order in which unit converter 20_1 is turned on is switched to the order in which unit converter 20_i is turned on, as shown in Fig. 3.

[0043] The gate signal switching circuit 64 that has received the ON / OFF priority command switches the gate signal for the unit converter that will be turned ON next in accordance with the ON / OFF priority command.

[0044] In addition, if the value of voltage VCELL(1) is lower than threshold value VOV1 at time t1 when the control trigger signal is received, DC voltage rise prevention control circuit 66 maintains the previous on / off priority command so that unit converter 20_2 will be turned ON next.

[0045] At time t2, when the voltage value of carrier signal Vc0(1) becomes equal to or greater than the voltage value of voltage reference signal Vref, phase-shift PWM control circuit 62 causes gate signal VG1(1) to transition to OFF and gate signal VG2(1) to transition to ON, thereby turning unit converter 20_1 OFF.

[0046] Here, between time t1 and time t2, because the unit converter 20_1 is ON, the value of the voltage VCELL(1) increases over time. At time t2, the value of the voltage VCELL(1) increases to near the upper limit value VOV0. Thereafter, because the unit converter 20_1 is turned OFF, the value of the voltage VCELL(1) falls below the voltage value of the voltage reference signal Vref at time t3. Therefore, if there is no change in the ON / OFF priority command, the value of the voltage VCELL(1) can reach the upper limit value VOV0. In the power conversion device 100 according to the embodiment, the unit converter 20_i is turned ON instead of the unit converter 20_1 at time t3 in response to the ON / OFF priority command, and therefore the voltage VCELL(1) of the unit converter 20_1 does not exceed the upper limit value VOV0.

[0047] After time t2 has passed, the value of voltage VCELL(1) decreases over time due to current consumption by a control circuit inside unit converter 20_1, etc. For example, when the value of voltage VCELL(1) becomes lower than any of voltages VCELL(2) to VCELL(N), unit converter 20_1 can be turned ON. In the example of FIG. 4, the value of voltage VCELL(1) of unit converter 20_1 is lower than threshold value VOV1 at times t4 and t5, but is higher than the values ​​of voltages VCELL(2) to VCELL(N), so unit converter 20_1 remains OFF.

[0048] In this way, the unit converter 20_1, which detects that the value of the voltage VCELL has exceeded the threshold value VOV1 at the input timing of the control trigger signal, is turned OFF in the next carrier period, and another unit converter 20_i is turned ON, thereby preventing the value of the voltage VCELL from rising excessively.

[0049] Whether the value of voltage VCELL reaches upper limit value VOV0 can be calculated by setting the capacitance value of capacitor 24 to a given value and the value of the current flowing through unit converter 20, including its sign (direction). Therefore, threshold value VOV1 can be set to an appropriate value based on upper limit value VOV0, the capacitance value of capacitor 24, and the current flowing through unit converter 20.

[0050] To more clearly understand the operation of the power conversion device 100 according to the embodiment, the operation of a power conversion device of a comparative example will be described using operating waveforms. FIG. 5 is a schematic block diagram illustrating a control unit that is a part of a power conversion device of a comparative example. The control unit 60a of the comparative example is different from the control unit 60 of the power conversion device 100 according to the embodiment shown in FIG. 3 in the generation of the control trigger signal and the comparison level of the value of the voltage VCELL, but is otherwise the same.

[0051] As shown in Fig. 5, the control unit 60a includes a DC voltage rise prevention control circuit 66a. The DC voltage rise prevention control circuit 66a receives a control trigger signal. The control trigger signal is a pulsed signal having a frequency higher than the carrier frequency. The control trigger signal is not necessarily synchronized with the carrier frequency.

[0052] An upper limit value VOV0 of voltage VCELL is preset in DC voltage rise prevention control circuit 66a. DC voltage rise prevention control circuit 66a compares the value of voltage VCELL with upper limit value VOV0 each time a control trigger signal is input. When the value of voltage VCELL becomes equal to or greater than upper limit value VOV0, DC voltage rise prevention control circuit 66 generates an on / off priority command to switch the order in which the unit converters are turned on, and outputs the command to gate signal switching circuit 64.

[0053] This will be explained using specific operating waveforms. FIG. 6 is a schematic operational waveform diagram showing the operation of the power conversion device of the comparative example. The signal waveforms at the top of FIG. 6 show the time changes of the carrier signal Vc0(1) for the unit converter 20_1 and the voltage reference signal Vref for the arm 10 including the unit converters 20_1 to 20_N. The signal waveform in the second row of FIG. 6 shows the change over time of the control trigger signal. 6 show the time changes of the gate signals VG1(1) and VG2(1) for the unit converter 20_1. This diagram is the same as that in FIG. The signal waveform at the bottom of FIG. 6 shows the change over time of the voltage VCELL(1), and for comparison, the upper limit value VOV0 is also shown. The horizontal axis of these operation waveform diagrams represents time, as in FIG.

[0054] 6, the control trigger signal is input at a constant frequency to the DC voltage rise prevention control circuit 66a. Every time the control trigger signal is input, the DC voltage rise prevention control circuit 66a compares the value of the voltage VCELL(1) with the upper limit value VOV0.

[0055] At time t11, the voltage value of the carrier signal Vc0 becomes equal to or greater than the voltage value of the voltage reference signal Vref, causing the unit converter 20_1 to transition from ON to OFF. At time t12, the voltage value of the carrier signal Vc0 becomes lower than the voltage value of the voltage reference signal Vref, causing the unit converter 20_1 to turn ON again.

[0056] Between time t13 and time t14, the DC voltage rise prevention control circuit 66a detects that the voltage VCELL(1) has exceeded the upper limit value VOV0. As shown in FIG. 5, the DC voltage rise prevention control circuit 66a changes the ON / OFF priority command so that the unit converter 20_i is turned ON instead of the unit converter 20_1 that was turned ON. At time t14, the unit converter 20_1 is forcibly turned OFF, and the switching frequency of the unit converter 20_1 increases during the period up to time t14. This increases the loss in the switching elements 22a and 22b that constitute the unit converter 20_1, and in an extreme case, this may lead to damage to the switching elements 22a and 22b due to overheating or the like.

[0057] The effects of the power conversion device 100 according to the embodiment will be described. The power conversion device 100 according to the embodiment includes a control unit 60 having a control trigger timing generation circuit 68. The control trigger timing generation circuit 68 compares an estimation carrier signal Vc1, which has a phase that leads the carrier signal Vc0, with a voltage reference signal Vref, generates a control trigger signal at the timing at which these signals intersect, and outputs the control trigger signal to the DC voltage rise prevention control circuit 66. This makes it possible to estimate that the value of voltage VCELL will exceed the upper limit value VOV0 before actually detecting that the value of voltage VCELL has exceeded the upper limit value VOV0. By estimating that the value of voltage VCELL will exceed the upper limit value VOV0, it becomes possible to change the on / off priority without forcibly transitioning a currently ON unit converter 20 to OFF.

[0058] 5 and 6, when detecting in real time whether the value of voltage VCELL has exceeded upper limit value VOV0, the on / off priority of the unit converters is forcibly changed at the time of detection. As a result, the switching frequency of the unit converters that have been forcibly turned off temporarily increases, which may lead to increased loss in switching elements 22a and 22b or damage to them.

[0059] In the power conversion device 100 according to the embodiment, even if the on / off priority is changed due to the above-described operation, the unit converter 20 does not experience a change in switching frequency, and therefore, accidents or the like that occur in the comparative example do not occur. The power conversion device 100 according to the embodiment can continue to operate stably.

[0060] In the above-described specific example, the control trigger timing generation circuit 68 uses the estimation carrier signal Vc1, which is phase-advanced relative to the carrier signal Vc0. However, other methods may be used as long as they can generate a control trigger signal in synchronization with the carrier period, which is the period of the carrier signal Vc0.

[0061] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0062] 10...Arm, 20...Unit converter, 21a, 21b...Connection terminal, 22a, 22b...Switching element, 24...Capacitor, 40...Reactor, 60...Control unit, 62...Phase shift PWM control circuit, 64...Gate signal switching circuit, 66...DC voltage rise prevention control circuit, 68...Control trigger timing generation circuit, 100...Power conversion device, 101a to 101c...AC terminal, 101d, 101e...DC terminal

Claims

1. an arm having a plurality of unit converters connected in series; a control unit that generates a plurality of gate signals that control the plurality of unit converters, respectively; Equipped with Each of the plurality of unit converters A capacitor, two switching elements connected in series and operating in a complementary manner to charge and discharge the capacitor; Including, The control unit a phase shift PWM control circuit that generates the gate signals based on a voltage reference signal and each of a plurality of carrier signals that are set by shifting the phase according to the number of the plurality of unit converters; a DC voltage rise prevention control circuit that receives input of a voltage value across each capacitor of the plurality of unit converters and generates an on / off priority command that prioritizes a unit converter having a lower voltage value across the capacitor and activates a gate signal; a gate signal switching circuit that switches and sets the order in which the plurality of gate signals become active based on the on / off priority command; and When the DC voltage rise prevention control circuit estimates that a first voltage across both ends of a capacitor of one of the plurality of unit converters will reach a predetermined upper limit value in each period of the plurality of carrier signals corresponding respectively to the plurality of unit converters, the power conversion device changes the on / off priority command so that, in the period following the period, a unit converter among the plurality of unit converters that has a capacitor with a voltage value lower than the first voltage is preferentially turned on.

2. the control unit further includes a control trigger timing generation circuit that receives a plurality of carrier signals for estimation, each of which has the same period and phase difference as those of the plurality of carrier signals, generates a control trigger signal based on the carrier signals for estimation and the voltage reference signal, and outputs the control trigger signal to the DC voltage rise prevention control circuit; 2. The power conversion device according to claim 1, wherein the DC voltage rise prevention control circuit changes the on / off priority command when it estimates that the first voltage will reach the upper limit value when the control trigger signal is input.

3. 3. The power conversion device according to claim 2, wherein the DC voltage prevention control circuit has a threshold voltage value lower than the upper limit voltage, and when the control trigger signal is input, the control circuit changes the on / off priority command when the first voltage reaches the threshold voltage.

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