Nitride semiconductor device and method for manufacturing nitride semiconductor device

Abstract

To provide a nitride semiconductor device that has high breakdown voltage and a method for manufacturing the nitride semiconductor device.SOLUTION: A nitride semiconductor device includes: a first nitride semiconductor layer including a channel layer and a barrier layer that overlap along a first axis, the first nitride semiconductor layer having a first surface intersecting the first axis; an insulating layer provided on the first surface, and having a second surface facing the first surface and a third surface opposite the second surface; and a second nitride semiconductor layer and a third nitride semiconductor layer which hold the channel layer and the barrier layer therebetween along a second axis intersecting the first axis. In a cross-sectional view including the first axis and the second axis, the second nitride semiconductor layer includes a first covering portion covering a portion of the third surface, and the third nitride semiconductor layer includes a second covering portion covering a portion of the third surface.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device. [Background technology]

[0002] 2. Description of the Related Art In order to reduce contact resistance and the like in nitride semiconductor devices, a structure has been proposed in which a nitride semiconductor layer containing a high concentration of impurities is regrown. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-329350 [Patent Document 2] Special Publication No. 2007-538402 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, there has been an increasing demand for further improvement in pressure resistance.

[0005] An object of the present disclosure is to provide a nitride semiconductor device that can obtain a high breakdown voltage and a method for manufacturing the nitride semiconductor device. [Means for solving the problem]

[0006] The nitride semiconductor device of the present disclosure comprises: a first nitride semiconductor layer including a channel layer and a barrier layer overlapping along a first axis, the first nitride semiconductor layer having a first surface intersecting the first axis; an insulating layer provided on the first surface, the insulating layer having a second surface facing the first surface and a third surface opposite the second surface; and a second nitride semiconductor layer and a third nitride semiconductor layer sandwiching the channel layer and the barrier layer along a second axis intersecting the first axis, wherein, in a cross-sectional view including the first axis and the second axis, the second nitride semiconductor layer has a first covering portion covering a portion of the third surface, and the third nitride semiconductor layer has a second covering portion covering a portion of the third surface. [Effects of the Invention]

[0007] According to the present disclosure, a high breakdown voltage can be obtained. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing a nitride semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a plan view showing the nitride semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a cross-sectional view (part 1) illustrating a method for manufacturing a nitride semiconductor device according to an embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 2) showing the method for manufacturing the nitride semiconductor device according to the embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 3) showing the method for manufacturing the nitride semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 4) showing the method for manufacturing the nitride semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 5) showing the method for manufacturing the nitride semiconductor device according to the embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 6) showing the method for manufacturing the nitride semiconductor device according to the embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 7) showing the method for manufacturing a nitride semiconductor device according to the embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 8) showing the method for manufacturing the nitride semiconductor device according to the embodiment. [Figure 11] FIG. 11 is a ninth cross-sectional view showing the method for manufacturing a nitride semiconductor device according to the embodiment. [Figure 12] FIG. 12 is a cross-sectional view (part 10) showing the method for manufacturing the nitride semiconductor device according to the embodiment. [Figure 13] FIG. 13 is a cross-sectional view (part 11) showing the method for manufacturing the nitride semiconductor device according to the embodiment. [Figure 14] FIG. 14 is a twelfth cross-sectional view showing the method for manufacturing the nitride semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] A nitride semiconductor device according to one embodiment of the present disclosure includes: a first nitride semiconductor layer including a channel layer and a barrier layer overlapping along a first axis, the first nitride semiconductor layer having a first surface intersecting the first axis; an insulating layer provided on the first surface, the insulating layer having a second surface facing the first surface and a third surface opposite the second surface; and a second nitride semiconductor layer and a third nitride semiconductor layer sandwiching the channel layer and the barrier layer along a second axis intersecting the first axis, wherein, in a cross-sectional view including the first axis and the second axis, the second nitride semiconductor layer has a first covering portion covering a portion of the third surface, and the third nitride semiconductor layer has a second covering portion covering a portion of the third surface.

[0011] When the second nitride semiconductor layer and the third nitride semiconductor layer are formed, an unnecessary nitride semiconductor layer containing polycrystals is formed on the third surface. The second nitride semiconductor layer has a first covering portion, and the third nitride semiconductor layer has a second covering portion, so that the etchant does not come into contact with the first nitride semiconductor layer when removing the unnecessary nitride semiconductor layer. Therefore, the barrier layer and the channel layer are not etched, and a high breakdown voltage is obtained for the nitride semiconductor device.

[0012] [2] In [1], the first nitride semiconductor layer may have a fourth surface opposite to the first surface, the first covering portion may have a fifth surface that is farther from the fourth surface than a reference distance between the first surface and the fourth surface, and the second covering portion may have a sixth surface that is farther from the fourth surface than the reference distance. In this case, etching of the barrier layer and the channel layer is easily prevented.

[0013] [3] In [2], the distance between the third surface and the fifth surface may be 10 nm or more and 100 nm or less, and the distance between the third surface and the sixth surface may be 10 nm or more and 100 nm or less. When these distances are 10 nm or more, etching of the barrier layer and the channel layer is more easily prevented. When these distances are 100 nm or less, excessive steps are more easily prevented.

[0014] [4] In any one of [1] to [3], the first covering portion and the second covering portion may contain polycrystalline. Even if the first covering portion and the second covering portion contain polycrystalline, etching of the barrier layer and the channel layer can be prevented.

[0015] [5] In any one of [1] to [4], the first nitride semiconductor layer may have a cap layer having the first surface. In this case, the barrier layer can be protected from damage caused by plasma or the like that occurs during the manufacturing process of the nitride semiconductor device.

[0016] [6] In any of [1] to [5], the length of the first covering portion in the direction along the second axis may be 50 nm or more and 300 nm or less, and the length of the second covering portion in the direction along the second axis may be 50 nm or more and 300 nm or less. When these lengths are 50 nm or more, etching of the barrier layer and the channel layer is more easily prevented. When these lengths are 300 nm or less, short-circuiting between a gate electrode provided between the second nitride semiconductor layer and the third nitride semiconductor layer and the second nitride semiconductor layer and the third nitride semiconductor layer is more easily prevented.

[0017] [7] In any of [1] to [6], the channel layer may have a channel region containing two-dimensional electron gas, and the electrical resistance of the second nitride semiconductor layer and the electrical resistance of the third nitride semiconductor layer may be lower than the electrical resistance of the channel region. In this case, the electrical resistance between the electrodes provided on the second nitride semiconductor layer and the third nitride semiconductor layer can be reduced.

[0018] [8] In any one of [1] to [7], the second nitride semiconductor layer and the third nitride semiconductor layer may contain n-type impurities, which makes it easier to obtain low electrical resistance in the second nitride semiconductor layer and the third nitride semiconductor layer.

[0019] [9] In [8], the concentration of the impurity is 1×10 20 cm -3 In this case, it is easy to obtain particularly low electrical resistance in the second nitride semiconductor layer and the third nitride semiconductor layer.

[0020]

[10] In any of [1] to [9], a first recess and a second recess may be formed in the first nitride semiconductor layer along the second axis, sandwiching the channel layer and the barrier layer therebetween, the second nitride semiconductor layer being provided in the first recess, and the third nitride semiconductor layer being provided in the second recess. In this case, it is easy to form the second nitride semiconductor layer and the third nitride semiconductor layer.

[0021]

[11] A method for manufacturing a nitride semiconductor device according to another aspect of the present disclosure includes the steps of: preparing a first nitride semiconductor layer having a first surface, the first nitride semiconductor layer including a channel layer and a barrier layer overlapping along a first axis; forming a first insulating layer on the first surface, the first insulating layer having a second surface facing the first surface and a third surface opposite the second surface; forming a first opening and a second opening in the first insulating layer along a second axis intersecting the first axis in a plan view, the first opening and the second opening sandwiching the channel layer and the barrier layer therebetween; forming a first recess connected to the first opening and a second recess connected to the second opening in the first nitride semiconductor layer; and forming a first recess and a second recess connected to the second opening in the first insulating layer. forming a fourth nitride semiconductor layer including polycrystals on the first insulating layer by a sputtering method; forming a second insulating layer on the fourth nitride semiconductor layer, the second insulating layer covering the first recess and the portion of the fourth nitride semiconductor layer within the first opening and a portion on a portion of the first insulating layer; and forming a third insulating layer on the fourth nitride semiconductor layer, the second recess and the portion of the fourth nitride semiconductor layer within the second opening and a portion on a portion of the first insulating layer; and removing the portions of the fourth nitride semiconductor layer exposed from the second insulating layer and the third insulating layer to form a second nitride semiconductor layer having a first covering portion covering a portion of the third surface and a third nitride semiconductor layer having a second covering portion covering a portion of the third surface.

[0022] As described above, the etchant does not come into contact with the first nitride semiconductor layer when removing the unnecessary nitride semiconductor layer, and therefore the barrier layer and the channel layer are not etched, resulting in a high breakdown voltage for the nitride semiconductor device.

[0023] [Details of the embodiments of the present disclosure] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description. In the following description, an XYZ Cartesian coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of the nitride semiconductor device. An XY plane view is referred to as a planar view, and the +Z direction from an arbitrary point may be referred to as upward, upper side, or top, and the −Z direction may be referred to as downward, lower side, or bottom.

[0024] An embodiment of the present disclosure relates to a nitride semiconductor device including a high electron mobility transistor (HEMT). Fig. 1 is a cross-sectional view showing a nitride semiconductor device according to an embodiment. Fig. 2 is a plan view showing a nitride semiconductor device according to an embodiment. Fig. 1 corresponds to a cross-sectional view taken along line II in Fig. 2.

[0025] As shown in FIGS. 1 and 2, the nitride semiconductor device 100 according to the embodiment includes a substrate 110, a first nitride semiconductor layer 120, a second nitride semiconductor layer 142S, a third nitride semiconductor layer 142D, an insulating layer 130, a gate electrode 50, a source electrode 44S, a drain electrode 44D, an insulating layer 172S, and an insulating layer 172D.

[0026] The substrate 110 is, for example, a substrate for growing a gallium nitride (GaN)-based semiconductor layer, such as a semi-insulating silicon carbide (SiC) substrate. When the substrate 110 is a SiC substrate, the upper surface of the substrate 110 is a silicon (Si) polar plane. When the surface of the substrate 110 is a Si polar plane, the first nitride semiconductor layer 120 undergoes crystal growth with the gallium (Ga) polar plane as the growth plane.

[0027] The first nitride semiconductor layer 120 has a buffer layer 122, a channel layer 124, a barrier layer 126, and a cap layer 128. The buffer layer 122, the channel layer 124, the barrier layer 126, and the cap layer 128 are stacked in this order along the Z axis. The first nitride semiconductor layer 120 has an upper surface 161 and a lower surface 164 that intersect with the Z axis. The upper surface 161 is located on the cap layer 128. The Z axis is an example of a first axis. The upper surface 161 is an example of a first surface, and the lower surface 164 is an example of a fourth surface opposite the first surface.

[0028] The buffer layer 122 is on the substrate 110. The buffer layer 122 is, for example, an aluminum nitride (AlN) layer. The buffer layer 122 may include an AlN layer and a GaN layer or an aluminum gallium nitride (AlGaN) layer on the AlN layer. The channel layer 124 is on the buffer layer 122. The channel layer 124 is, for example, an undoped gallium nitride (GaN) layer. The barrier layer 126 is on the channel layer 124. The barrier layer 126 is, for example, an n-type AlGaN layer. A channel region 155 including a two-dimensional electron gas (2DEG) exists near the top surface of the channel layer 124. The cap layer 128 is on the barrier layer 126. The cap layer 128 is, for example, an n-type GaN layer.

[0029] A first recess 140S for a source and a second recess 140D for a drain are formed in the cap layer 128, the barrier layer 126, and a part of the channel layer 124. The first recess 140S and the second recess 140D penetrate the cap layer 128 and the barrier layer 126 along the Z axis and extend into the channel layer 124. The channel layer 124 is exposed from the first recess 140S and the second recess 140D.

[0030] The insulating layer 130 is on the cap layer 128. The insulating layer 130 is, for example, a silicon nitride (SiN) film. The insulating layer 130 has a thickness of, for example, 1 nm or more and 20 nm or less. The insulating layer 130 has an upper surface 163 and a lower surface 162 that intersect with the Z axis. An opening 130S for a source and an opening 130D for a drain are formed in the insulating layer 130. The opening 130S connects to the first recess 140S, and the opening 130D connects to the second recess 140D. The opening 130D is on the +X side of the opening 130S. The lower surface 162 is an example of a second surface, and the upper surface 163 is an example of a third surface opposite the second surface. The X axis is an example of the second axis.

[0031] The second nitride semiconductor layer 142S is located on the channel layer 124 within the first recess 140S and the opening 130S. In a ZX cross-sectional view including the Z axis and the X axis, the second nitride semiconductor layer 142S has a first covering portion 144S covering a part of the upper surface 163. The first covering portion 144S may include polycrystals. The first covering portion 144S has an upper surface 165. The distance of the upper surface 165 from the lower surface 164 of the first nitride semiconductor layer 120 may be greater than a reference distance L0 between the upper surface 161 and the lower surface 164 of the first nitride semiconductor layer 120. Note that if the distance between the upper surface 161 and the lower surface 164 varies depending on the position in the X axis direction and the position in the Y axis direction depending on the flatness of each of the upper surface 161 and the lower surface 164, the reference distance L0 may be a maximum value estimated from distance values ​​at multiple different positions. For example, if the flatness of each of upper surface 161 and lower surface 164 is good and the difference between the average value and the maximum value of the distance measured at multiple different positions is 0.5 nm or less, the average value may be used as reference distance L0. Second nitride semiconductor layer 142S contacts the sidewall surface of opening 130S and the sidewall surface of first recess 140S. Upper surface 165 is an example of a fifth surface.

[0032] The third nitride semiconductor layer 142D is located on the channel layer 124 within the second recess 140D and the opening 130D. In a ZX cross-sectional view including the Z axis and the X axis, the third nitride semiconductor layer 142D has a second covering portion 144D covering a portion of the upper surface 163. The second covering portion 144D may include polycrystal. The second covering portion 144D has an upper surface 166. The distance of the upper surface 166 from the lower surface 164 of the first nitride semiconductor layer 120 may be greater than the reference distance L0 between the upper surface 161 and the lower surface 164 of the first nitride semiconductor layer 120. The third nitride semiconductor layer 142D contacts the sidewall surface of the opening 130D and the sidewall surface of the second recess 140D. The upper surface 166 is an example of a sixth surface.

[0033] The second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D sandwich a portion of the channel layer 124 and the barrier layer 126 along the X-axis. The second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are, for example, n-type GaN layers. The electrical resistances of the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are lower than the electrical resistance of the channel region 155.

[0034] The insulating layer 172S is on the second nitride semiconductor layer 142S. The insulating layer 172S covers the upper surface 165 of the first covering portion 144S. The insulating layer 172D is on the third nitride semiconductor layer 142D. The insulating layer 172D covers the upper surface 166 of the second covering portion 144D. The insulating layers 172S and 172D are, for example, silicon nitride (SiN) films. The insulating layers 172S and 172D have a thickness of, for example, 5 nm or more and 20 nm or less. An opening 170S for a source is formed in the insulating layer 172S. The opening 170S reaches the second nitride semiconductor layer 142S. That is, the second nitride semiconductor layer 142S is exposed from the opening 170S. An opening 170D for a drain is formed in the insulating layer 172D. The opening 170D reaches the third nitride semiconductor layer 142D. That is, the third nitride semiconductor layer 142D is exposed from the opening 170D. For example, the opening 170S is spaced apart from the first covering portion 144S, and the opening 170D is spaced apart from the second covering portion 144D.

[0035] The source electrode 44S is on the second nitride semiconductor layer 142S inside the opening 170S, and the drain electrode 44D is on the third nitride semiconductor layer 142D inside the opening 170D. The source electrode 44S is in direct contact with the second nitride semiconductor layer 142S, and the drain electrode 44D is in direct contact with the third nitride semiconductor layer 142D. The source electrode 44S is in ohmic contact with the second nitride semiconductor layer 142S, and the drain electrode 44D is in ohmic contact with the third nitride semiconductor layer 142D.

[0036] An opening 130G for a gate is formed in the insulating layer 130. The opening 130G is located between the openings 130S and 130D along the X-axis. The gate electrode 50 is provided on the insulating layer 130 and is in Schottky contact with the first nitride semiconductor layer 120 through the opening 130G. The current flowing between the drain electrode 44D and the source electrode 44S via the channel region 155 changes depending on the voltage applied to the gate electrode 50.

[0037] Next, a method for manufacturing the nitride semiconductor device 100 according to the embodiment will be described. Figures 3 to 14 are cross-sectional views showing the method for manufacturing the nitride semiconductor device 100 according to the embodiment. Figures 11 to 14 show enlarged views of parts of Figures 6 to 9, respectively.

[0038] First, as shown in FIG. 3, a buffer layer 122, a channel layer 124, a barrier layer 126, and a cap layer 128 are formed on a substrate 110. The buffer layer 122, the channel layer 124, the barrier layer 126, and the cap layer 128 can be formed by, for example, a metal organic chemical vapor deposition (MOCVD) method. Next, an insulating layer 130 is formed on the cap layer 128. The insulating layer 130 can be formed by, for example, a CVD method. In this manner, a first nitride semiconductor layer 120 is obtained. The insulating layer 130 is an example of a first insulating layer.

[0039] 4, a mask 200 is formed on the insulating layer 130. The mask 200 has an opening 201 for the first recess 140S and an opening 202 for the second recess 140D. For example, the mask 200 is made of photoresist.

[0040] Next, as shown in FIG. 5 , the insulating layer 130 is etched through the openings 201 and 202 to form an opening 130S connected to the opening 201 and an opening 130D connected to the opening 202 in the insulating layer 130. For example, the insulating layer 130 is etched under conditions that make side etching unlikely. In a plan view along the Z axis, the opening 130S is formed to be the same size as the opening 201, and the opening 130D is formed to be the same size as the opening 202. For example, in the X axis direction, the +X side edge of the opening 130S coincides with the +X side edge of the opening 201, and the -X side edge of the opening 130D coincides with the -X side edge of the opening 202. However, these do not need to coincide perfectly; there may be a manufacturing error or a predetermined offset. The openings 130S and 130D can be formed by reactive ion etching (RIE) using a reactive gas containing, for example, fluorine (F). The opening 130S is an example of a first opening, and the opening 130D is an example of a second opening.

[0041] Next, the first nitride semiconductor layer 120 is etched through the openings 201 and 202 to form a first recess 140S connected to the opening 130S and a second recess 140D connected to the opening 130D in the first nitride semiconductor layer 120. The first recess 140S and the second recess 140D sandwich a portion of the channel layer 124 and the barrier layer 126 between them along the X-axis. The first recess 140S and the second recess 140D can be formed by RIE using a reactive gas containing chlorine (Cl), for example. For example, the angles formed by the sidewall surfaces of the first recess 140S and the second recess 140D and the top surface 161 of the first nitride semiconductor layer 120 are set to be close to 90 degrees. In the ZX cross section shown in FIG. 5, the angle formed between the side wall surface of the first recess 140S and the upper surface 161 of the first nitride semiconductor layer 120 and the angle formed between the side wall surface of the second recess 140D and the upper surface 161 of the first nitride semiconductor layer 120 may each be greater than 90 degrees.

[0042] Next, as shown in FIG. 6 , the mask 200 is removed. Next, the fourth nitride semiconductor layer 142, which will become the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D, is formed. The fourth nitride semiconductor layer 142 can be formed by, for example, a sputtering method. When forming the fourth nitride semiconductor layer 142 by a sputtering method, Ga and n-type impurities may be supplied intermittently while nitrogen radicals are continuously supplied. The fourth nitride semiconductor layer 142 is formed in the first recess 140S and the opening 130S, in the second recess 140D and the opening 130D, and on the insulating layer 130. The portions of the fourth nitride semiconductor layer 142 in the first recess 140S and the opening 130S grow epitaxially and include a single crystal. The portions of the fourth nitride semiconductor layer 142 in the second recess 140D and the opening 130D also grow epitaxially and include a single crystal. The fourth nitride semiconductor layer 142 contacts the channel layer 124 at the bottom of the first recess 140S and the second recess 140D. On the other hand, the upper portion of the insulating layer 130 does not grow epitaxially and contains polycrystals.

[0043] 11 , a recess 167 may be formed inside opening 130S near the sidewall of opening 130S on the upper surface of fourth nitride semiconductor layer 142. Similarly, a recess 167 may be formed inside opening 130D near the sidewall of opening 130D on the upper surface of fourth nitride semiconductor layer 142. This is because part of the flow of raw material coming from the target is blocked by fourth nitride semiconductor layer 142 that has already been formed on insulating layer 130. Furthermore, the shape and size of recess 167 in the ZX cross section are non-uniform along the Y-axis direction.

[0044] 7 and 12, an insulating layer 170 is formed on the fourth nitride semiconductor layer 142. The insulating layer 170 can be formed by, for example, a CVD method. The insulating layer 170 covers the recess 167.

[0045] Next, as shown in FIGS. 8 and 13 , a mask 210S and a mask 210D are formed on the insulating layer 170. The mask 210S covers the region where the insulating layer 172S is to be formed, and the mask 210D covers the region where the insulating layer 172D is to be formed. The mask 210S covers at least the edge of the cap layer 128 on the −X side, and the mask 210D covers at least the edge of the cap layer 128 on the +X side. For example, the masks 210S and 210D are formed from photoresist. For example, the masks 210S and 210D are formed by removing portions of photoresist other than the masks 210S and 210D from a uniformly formed layer of photoresist on the insulating layer 170 through patterning. Next, the portions of the insulating layer 170 exposed by the masks 210S and 210D are etched to form the insulating layers 172S and 172D from the insulating layer 170. The insulating layer 172S covers the portions of the fourth nitride semiconductor layer 142 within the first recess 140S and the opening 130S, and a portion on a part of the insulating layer 130. The insulating layer 172D covers the portions of the fourth nitride semiconductor layer 142 within the second recess 140D and the opening 130D, and a portion on a part of the insulating layer 130. The insulating layer 170 may be etched by RIE using a reactive gas containing fluorine (F), for example. The insulating layer 170 may also be etched by wet etching using buffered hydrofluoric acid. The insulating layer 172S is an example of a second insulating layer, and the insulating layer 172D is an example of a third insulating layer.

[0046] Next, as shown in FIG. 9 , mask 210S and mask 210D are removed. Next, portions of fourth nitride semiconductor layer 142 exposed from insulating layer 172S and insulating layer 172D are removed to form second nitride semiconductor layer 142S and third nitride semiconductor layer 142D from fourth nitride semiconductor layer 142. Second nitride semiconductor layer 142S has first covering portion 144S covering a portion of upper surface 163, and third nitride semiconductor layer 142D has second covering portion 144D covering a portion of upper surface 163. As described above, portions of fourth nitride semiconductor layer 142 exposed from insulating layer 172S and insulating layer 172D contain polycrystalline silicon. These portions can be removed using an alkaline etchant such as tetramethylammonium hydroxide (TMAH). The temperature of TMAH is, for example, 70°C or higher and 80°C or lower.

[0047] 14, when the second nitride semiconductor layer 142S is formed, the recess 167 inside the opening 130S is covered with the insulating layer 172S. Similarly, when the third nitride semiconductor layer 142D is formed, the recess 167 inside the opening 130D is covered with the insulating layer 172D.

[0048] 10, an opening 170S is formed in the insulating layer 172S, and an opening 170D is formed in the insulating layer 172D. The openings 170S and 170D can be formed by, for example, RIE using a reactive gas containing fluorine (F). Next, a source electrode 44S is formed on the second nitride semiconductor layer 142S inside the opening 170S, and a drain electrode 44D is formed on the third nitride semiconductor layer 142D inside the opening 170D. The source electrode 44S and the drain electrode 44D can be formed by, for example, evaporation and lift-off. The source electrode 44S contacts the second nitride semiconductor layer 142S, and the drain electrode 44D contacts the third nitride semiconductor layer 142D.

[0049] Next, an opening 130G is formed in the insulating layer 130. The opening 130G can be formed by RIE using a reactive gas containing fluorine (F), for example. Next, a gate electrode 50 is formed on the insulating layer 130, making Schottky contact with the first nitride semiconductor layer 120 through the opening 130G (see FIG. 1).

[0050] In this manner, the nitride semiconductor device 100 according to the embodiment can be manufactured.

[0051] In this embodiment, the second nitride semiconductor layer 142S has a first covering portion 144S, and the third nitride semiconductor layer 142D has a second covering portion 144D. Therefore, the removal (wet etching) of a portion of the fourth nitride semiconductor layer 142 to form the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D is completed before the openings 130S and 130D are exposed. Therefore, an etchant such as TMAH used in the wet etching does not reach the sidewall surfaces of the openings 130S and 130D.

[0052] When the etchant reaches the sidewall surfaces of openings 130S and 130D, the low-crystallinity portions near recesses 167 may be slightly etched. When the low-crystallinity portions in second nitride semiconductor layer 142S are slightly etched, the cap layer 128 and barrier layer 126 may be etched depending on the shape and size of recesses 167 in the ZX cross section. Similarly, when the low-crystallinity portions in third nitride semiconductor layer 142D are slightly etched, the cap layer 128 and barrier layer 126 may be etched depending on the shape and size of recesses 167 in the ZX cross section. Furthermore, the degree of etching of barrier layer 126 becomes non-uniform along the Y-axis direction. This causes the 2DEG concentration to become non-uniform along the Y-axis direction, and current tends to concentrate in areas with high 2DEG concentration and low electrical resistance. This can result in a decrease in breakdown voltage.

[0053] In this embodiment, as described above, the etchant does not reach the sidewall surfaces of openings 130S and 130D, and does not come into contact with first nitride semiconductor layer 120. Therefore, cap layer 128, barrier layer 126, and channel layer 124 are not etched, and a high breakdown voltage is obtained for nitride semiconductor device 100.

[0054] The distance from the upper surface 165 to the lower surface 164 is greater than the reference distance L0 between the upper surface 161 and the lower surface 164 of the first nitride semiconductor layer 120, which makes it easier to prevent etching of the barrier layer 126 and the channel layer 124 in the vicinity of the second nitride semiconductor layer 142S. The distance from the lower surface 164 of the upper surface 166 is greater than the reference distance L0 between the upper surface 161 and the lower surface 164 of the first nitride semiconductor layer 120, which makes it easier to prevent etching of the barrier layer 126 and the channel layer 124 in the vicinity of the third nitride semiconductor layer 142D.

[0055] The distance L1 between the upper surface 163 and the upper surface 165 is, for example, not less than 10 nm and not more than 100 nm. When the distance L1 is 10 nm or more, etching of the barrier layer 126 and the channel layer 124 near the second nitride semiconductor layer 142S is easily prevented. Furthermore, when the distance L1 is 100 nm or less, an excessive step due to the first covering portion 144S is easily prevented. The distance L1 may be not less than 20 nm and not more than 90 nm, or may be not less than 30 nm and not more than 80 nm.

[0056] The distance L2 between the upper surface 163 and the upper surface 166 is, for example, not less than 10 nm and not more than 100 nm. When the distance L2 is 10 nm or more, etching of the barrier layer 126 and the channel layer 124 near the third nitride semiconductor layer 142D is easily prevented. Furthermore, when the distance L2 is 100 nm or less, an excessive step due to the second covering portion 144D is easily prevented. The distance L2 may be not less than 20 nm and not more than 90 nm, or may be not less than 30 nm and not more than 80 nm.

[0057] The first nitride semiconductor layer 120 has the cap layer 128 with the upper surface 161, so that the barrier layer 126 can be protected from damage caused by plasma or the like that occurs during the manufacturing process of the nitride semiconductor device 100.

[0058] The length W1 of the first covering portion 144S in the X-axis direction is, for example, 50 nm or more and 300 nm or less. A length W1 of 50 nm or more facilitates preventing etching of the barrier layer 126 and the channel layer 124 near the second nitride semiconductor layer 142S. The length W1 is the length in the X-axis direction of a portion of the first covering portion 144S that contacts the upper surface 163 of the insulating layer 130, and does not include the length in the X-axis direction of a portion of the first covering portion 144S that does not contact the upper surface 163 of the insulating layer 130. The length W1 can be set independently of the distance L1 between the upper surface 163 and the upper surface 165. Furthermore, a length W1 of 300 nm or less facilitates preventing a short circuit between the gate electrode 50 and the second nitride semiconductor layer 142S. The length W1 may be 70 nm or more and 280 nm or less, or 100 nm or more and 250 nm or less.

[0059] The length W2 of the second covering portion 144D in the X-axis direction is, for example, 50 nm or more and 300 nm or less. A length W2 of 50 nm or more facilitates preventing etching of the barrier layer 126 and the channel layer 124 near the third nitride semiconductor layer 142D. The length W2 is the length in the X-axis direction of a portion of the second covering portion 144D that contacts the upper surface 163 of the insulating layer 130, and does not include the length in the X-axis direction of a portion of the second covering portion 144D that does not contact the upper surface 163 of the insulating layer 130. The length W2 can be set independently of the distance L2 between the upper surface 163 and the upper surface 166. Furthermore, a length W2 of 300 nm or less facilitates preventing a short circuit between the gate electrode 50 and the third nitride semiconductor layer 142D. The length W2 may be 70 nm or more and 280 nm or less, or 100 nm or more and 250 nm or less. The lengths W1 and W2 may be equal to or different from each other.

[0060] The electrical resistance of the second nitride semiconductor layer 142S and the electrical resistance of the third nitride semiconductor layer 142D are lower than the electrical resistance of the channel region 155, thereby making it possible to reduce the electrical resistance between the source electrode 44S and the drain electrode 44D.

[0061] By including n-type impurities in the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D, low electrical resistance can be easily obtained in the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D. The n-type impurities are not limited to germanium (Ge) and may be silicon (Si). The concentration of the n-type impurities is, for example, 1×10 20 cm -3 The concentration of n-type impurities is 1×10 20 cm -3 When the concentration of n-type impurities is 5×10 or more, it is easy to obtain a particularly low electrical resistance in the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D. 20 cm -3 May be greater than 1 x 10 21 cm -3 The concentration of n-type impurities may be 1×10 or more. 20 cm -3 The second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D can be formed by, for example, sputtering, but it is difficult to form them by MOCVD. The concentration of n-type impurities can be measured by secondary ion mass spectrometry (SIMS).

[0062] When the second nitride semiconductor layer 142S is provided in the first recess 140S and the third nitride semiconductor layer 142D is provided in the second recess 140D, the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are easily formed.

[0063] The insulating layer 130 is provided on the upper surface 161 and is in contact with the first covering portion 144S and the second covering portion 144D, so that the first nitride semiconductor layer 120 can be protected by the insulating layer 130.

[0064] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0065] 44D: Drain electrode 44S: Source electrode 50: Gate electrode 100: Nitride semiconductor device 110: Substrate 120: First nitride semiconductor layer 122: Buffer layer 124: Channel layer 126: Barrier layer 128: Cap layer 130, 170, 172D, 172S: Insulating layer 130D, 130G, 130S, 170D, 170S, 201, 202: Aperture 140D: Second recess 140S: First recess 142: Fourth nitride semiconductor layer 142D: Third nitride semiconductor layer 142S: Second nitride semiconductor layer 144D: Second coating part 144S: First coated part 155: Channel region 161, 163, 165, 166: Top surface 162, 164: Bottom surface 167: Depression 200, 210D, 210S: Mask L0: Reference distance L1, L2: distance

Claims

1. a first nitride semiconductor layer including a channel layer and a barrier layer overlapping along a first axis and having a first surface intersecting the first axis; an insulating layer provided on the first surface and having a second surface facing the first surface and a third surface opposite the second surface; a second nitride semiconductor layer and a third nitride semiconductor layer sandwiching the channel layer and the barrier layer along a second axis intersecting the first axis; and In a cross-sectional view including the first axis and the second axis, the second nitride semiconductor layer has a first covering portion that covers a part of the third surface, the third nitride semiconductor layer has a second covering portion that covers a part of the third surface.

2. the first nitride semiconductor layer has a fourth surface opposite to the first surface; the first covering portion has a fifth surface that is farther from the fourth surface than a reference distance between the first surface and the fourth surface, The nitride semiconductor device according to claim 1 , wherein said second covering portion has a sixth surface that is farther from said fourth surface than said reference distance.

3. the distance between the third surface and the fifth surface is 10 nm or more and 100 nm or less; The nitride semiconductor device according to claim 2 , wherein the distance between said third plane and said sixth plane is not less than 10 nm and not more than 100 nm.

4. The nitride semiconductor device according to claim 1 , wherein the first covering portion and the second covering portion include polycrystals.

5. The nitride semiconductor device according to claim 1 , wherein the first nitride semiconductor layer has a cap layer that is provided with the first surface.

6. a length of the first covering portion in a direction along the second axis is not less than 50 nm and not more than 300 nm; The nitride semiconductor device according to claim 1 , wherein the second covering portion has a length in the direction along the second axis of not less than 50 nm and not more than 300 nm.

7. the channel layer has a channel region containing a two-dimensional electron gas; 4. The nitride semiconductor device according to claim 1, wherein the electric resistance of said second nitride semiconductor layer and the electric resistance of said third nitride semiconductor layer are lower than the electric resistance of said channel region.

8. The nitride semiconductor device according to claim 1 , wherein said second nitride semiconductor layer and said third nitride semiconductor layer contain n-type impurities.

9. The concentration of the impurity is 1×10 ２０ cm －３ The nitride semiconductor device according to claim 8 .

10. a first recess and a second recess are formed in the first nitride semiconductor layer along the second axis, with the channel layer and the barrier layer sandwiched therebetween; the second nitride semiconductor layer is provided in the first recess; The nitride semiconductor device according to claim 1 , wherein the third nitride semiconductor layer is provided in the second recess.

11. providing a first nitride semiconductor layer having a first surface, the first nitride semiconductor layer including a channel layer and a barrier layer overlapping along a first axis; forming a first insulating layer on the first surface, the first insulating layer having a second surface opposite the first surface and a third surface opposite the second surface; forming a first opening and a second opening in the first insulating layer along a second axis intersecting the first axis in a plan view, the first opening and the second opening sandwiching the channel layer and the barrier layer therebetween; forming a first recess connected to the first opening and a second recess connected to the second opening in the first nitride semiconductor layer; forming a fourth nitride semiconductor layer including polycrystals on the first insulating layer by a sputtering method in the first recess and the first opening, in the second recess and the second opening, and on the first insulating layer; forming a second insulating layer on the fourth nitride semiconductor layer, the second insulating layer covering the first recess and the first opening of the fourth nitride semiconductor layer and a portion on the first insulating layer, and a third insulating layer covering the second recess and the second opening of the fourth nitride semiconductor layer and a portion on the first insulating layer; removing portions of the fourth nitride semiconductor layer exposed from the second insulating layer and the third insulating layer to form a second nitride semiconductor layer having a first covering portion covering a portion of the third surface, and a third nitride semiconductor layer having a second covering portion covering a portion of the third surface; The present invention relates to a method for manufacturing a nitride semiconductor device.

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