Manufacturing method for semiconductor device and inspecting method for semiconductor device

Abstract

To provide a manufacturing method for a semiconductor device, capable of manufacturing a chip whose variation in gate threshold voltage is small, and an inspecting method for the semiconductor device.SOLUTION: A manufacturing method for a semiconductor device including a field effect transistor, includes the steps of: acquiring first relation information expressing a relation between a gate-source voltage and a drain current of the field effect transistor; calculating a first voltage value that is the gate-source voltage when the drain current becomes a first current value on the basis of the first relation information; calculating a second voltage value that is the gate-source voltage when the drain current becomes a second current value that is smaller than the first current value on the basis of the first relation information; and determining that, when a value obtained by subtracting the second current value from the first current value is ΔId and a value obtained by subtracting the second voltage value from the first voltage value is ΔVth, the field effect transistor is defective if the calculation value calculated by ΔVth / ΔId is more than a determination value.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a method for inspecting a semiconductor device. [Background technology]

[0002] A semiconductor device is disclosed in which the surface of a metal electrode, excluding the portion covered with a passivation film, is covered with a nickel plating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-047675 Summary of the Invention [Problem to be solved by the invention]

[0004] The plating solution used to form the nickel plating film contains metal ions such as sodium ions. These metal ions can diffuse into the interlayer insulating film and gate insulating film through corrosion of the embrittled parts of the metal electrode. This can cause a decrease in the gate threshold voltage when a voltage is applied at high temperatures.

[0005] An object of the present disclosure is to provide a method for manufacturing a semiconductor device and a method for inspecting a semiconductor device that enable the manufacture of chips with small variations in gate threshold voltage. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor device disclosed herein is a method for manufacturing a semiconductor device including a field effect transistor, and includes the steps of: acquiring first relationship information representing the relationship between the drain current and the gate-source voltage of the field effect transistor; calculating a first voltage value, which is the gate-source voltage when the drain current is a first current value, based on the first relationship information; calculating a second voltage value, which is the gate-source voltage when the drain current is a second current value smaller than the first current value, based on the first relationship information; and determining that the field effect transistor is defective if the calculated value calculated by ΔVth / ΔId is greater than a determination value, where ΔId is the value obtained by subtracting the second current value from the first current value and ΔVth is the value obtained by subtracting the second voltage value from the first voltage value. [Effects of the Invention]

[0007] According to the present disclosure, chips with small variations in gate threshold voltage can be manufactured. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a diagram showing a chip area of ​​the semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a cross-sectional view showing a chip region of the semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a flow diagram showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 1) showing a step of forming a chip region. [Figure 6] FIG. 6 is a cross-sectional view (part 2) showing the step of forming the chip region. [Figure 7] FIG. 7 is a cross-sectional view (part 3) showing the step of forming the chip region. [Figure 8] FIG. 8 is a flow diagram showing the steps of inspecting the chip area. [Figure 9]FIG. 9 is a characteristic diagram showing the relationship between the drain current and the gate-source voltage of a field effect transistor formed in the chip region. DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments for carrying out the invention are described below.

[0010] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, identical or corresponding elements will be assigned the same reference numerals, and the same description will not be repeated. In the following description, an XYZ Cartesian coordinate system will be used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of the silicon carbide semiconductor device. The XY plane view will be referred to as a planar view, and the +Z direction from an arbitrary point will sometimes be referred to as upward, upper side, or top, and the -Z direction will sometimes be referred to as downward, lower side, or bottom.

[0011] [1] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device includes a field-effect transistor, the method comprising the steps of: acquiring first relationship information representing a relationship between a drain current and a gate-source voltage of the field-effect transistor; calculating a first voltage value, which is the gate-source voltage when the drain current is a first current value, based on the first relationship information; calculating a second voltage value, which is the gate-source voltage when the drain current is a second current value smaller than the first current value, based on the first relationship information; and determining the field-effect transistor as defective if a value calculated by ΔVth / ΔId, where ΔId is the value obtained by subtracting the second current value from the first current value and ΔVth is the value obtained by subtracting the second voltage value from the first voltage value, is greater than a determination value. In this case, a chip region including a field-effect transistor that contains a locally low gate threshold voltage and therefore causes a decrease in gate threshold voltage when a voltage is applied at a high temperature, can be extracted and removed. This allows the manufacture of chips with small variations in gate threshold voltage.

[0012] [2] In [1], the first relationship information may be acquired while the field-effect transistor is heated to a first temperature higher than room temperature. At temperatures higher than room temperature, carriers trapped at the interface between the gate insulating film and the body region in the channel region are more easily expelled, and the effective band gap of the body region is narrowed, resulting in a lower gate threshold voltage. The degree of decrease in gate threshold voltage increases as the channel region is contaminated with metal ions. Therefore, when the first relationship information is acquired while the field-effect transistor is heated to a first temperature higher than room temperature, the value of ΔVth / ΔId is larger than when the first relationship information is acquired at room temperature, thereby improving the sensitivity of defective product detection.

[0013] [3] In [2], the first temperature may be 150° C. or higher and 250° C. or lower. When the first temperature is 150° C. or higher, sensitivity in detecting defective products is likely to be improved. When the first temperature is 250° C. or lower, warpage of the semiconductor device can be reduced.

[0014] [4] In any one of [1] to [3], the semiconductor device may have a semiconductor substrate and a plurality of chip regions formed in a plane of the semiconductor substrate, the field effect transistor being formed in each of the plurality of chip regions, and the judgment value may be determined based on a median of the calculated values ​​calculated for each of the chip regions. In this case, the sensitivity of defective product detection may be improved.

[0015] [5] In [1] to [4], the value obtained by dividing the first current value by the second current value is 10 3 Over 10 5 In this case, the sensitivity of detecting defective products is improved.

[0016] [6] According to another aspect of the present disclosure, a semiconductor device inspection method for a semiconductor device including a field-effect transistor includes the steps of: acquiring first relationship information representing a relationship between a drain current and a gate-source voltage of the field-effect transistor; calculating a first voltage value, which is the gate-source voltage when the drain current is a first current value, based on the first relationship information; calculating a second voltage value, which is the gate-source voltage when the drain current is a second current value smaller than the first current value, based on the first relationship information; and determining that the field-effect transistor is defective if a value calculated by ΔVth / ΔId, where ΔId is the value obtained by subtracting the second current value from the first current value and ΔVth is the value obtained by subtracting the second voltage value from the first voltage value, is greater than a determination value. In this case, chip regions including field-effect transistors that contain locally low gate threshold voltages and therefore cause a decrease in gate threshold voltage when a voltage is applied at high temperatures, can be extracted and removed. This allows the manufacture of chips with small variations in gate threshold voltage.

[0017] [Details of the embodiments of the present disclosure] [Configuration of Semiconductor Device] An embodiment of the present disclosure relates to a so-called vertical MOS (Metal Oxide Semiconductor) field effect transistor (FET) using silicon carbide. FIG. 1 is a diagram showing a semiconductor device 200 according to the embodiment. FIG. 2 is a diagram showing a chip region 100 of the semiconductor device 200 according to the embodiment. FIG. 3 is a cross-sectional view showing the chip region 100 of the semiconductor device 200 according to the embodiment. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIG. 2.

[0018] As shown in FIG. 1, a semiconductor device 200 according to the embodiment has a plurality of chip regions 100. The plurality of chip regions 100 are arranged in an array. For example, the planar shape of each chip region 100 is rectangular. Each chip region 100 has a common configuration. A dicing region is provided between adjacent chip regions 100. A plurality of chips are obtained by dividing along the dicing region.

[0019] As shown in FIGS. 2 and 3, the chip region 100 has a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, and a drain electrode .

[0020] The silicon carbide substrate 10 is an example of a semiconductor substrate. When the silicon carbide substrate 10 is used, an excellent breakdown voltage can be easily obtained. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane. The first main surface 1 is in the +Z direction as viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide epitaxial layer 40 includes the first main surface 1. The silicon carbide single crystal substrate 50 includes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 include, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has n-type conductivity (first conductivity type).

[0021] The silicon carbide epitaxial layer 40 includes a drift region 11, a body region 12, a source region 13, and a contact region 18.

[0022] Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. Drift region 11 is provided on silicon carbide single crystal substrate 50. An electric field relaxation region may be provided in drift region 11. The electric field relaxation region has p-type conductivity (second conductivity type).

[0023] The body region 12 contains p-type impurities such as aluminum (Al) and has p-type conductivity. The body region 12 is provided on the drift region 11. The lower end surface of the body region 12 contacts the upper end surface of the drift region 11.

[0024] The source region 13 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity. The source region 13 is provided on the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. The source region 13 includes the first main surface 1.

[0025] A plurality of gate trenches 5 defined by side surfaces 3 and bottom surfaces 4 are provided on the first main surface 1. The gate trenches 5 extend, for example, along the Y axis. The plurality of gate trenches 5 are provided at regular intervals along the X axis. The side surfaces 3 penetrate the source region 13, the body region 12, and part of the drift region 11, and reach the drift region 11. The bottom surfaces 4 are continuous with the side surfaces 3. The bottom surfaces 4 are located in the drift region 11. The bottom surfaces 4 are, for example, parallel to the first main surface 1 and the second main surface 2. The side surfaces 3 are inclined with respect to a plane including the bottom surfaces 4.

[0026] The contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 18 penetrates the source region 13 and the body region 12 and is in contact with the drift region 11. The contact region 18 includes the first main surface 1. In a plan view perpendicular to the first main surface 1, the contact region 18 is located between adjacent gate trenches 5 along the X-axis.

[0027] The gate insulating film 81 includes, for example, silicon dioxide. The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the drift region 11 at the bottom surface 4. The gate insulating film 81 contacts the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 may contact the source region 13 at the first main surface 1.

[0028] The gate electrode 82 is formed of, for example, polysilicon containing conductive impurities. The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is disposed inside the gate trench 5. The gate electrode 82 faces the side surface 3 and the bottom surface 4. A portion of the gate electrode 82 may face the first main surface 1. The gate electrode 82 extends along the Y axis.

[0029] The interlayer insulating film 83 includes, for example, silicon dioxide. The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with the gate insulating film 81 and the gate electrode 82. The interlayer insulating film 83 electrically insulates the gate electrode 82 from the source electrode 60. A part of the interlayer insulating film 83 may be provided inside the gate trench 5. The upper surface of the interlayer insulating film 83 may be flat. The upper surface of the interlayer insulating film 83 may be a curved surface whose curvature changes continuously. The upper surface of the interlayer insulating film 83 may be a curved surface that is convex in the +Z direction above the gate trench 5.

[0030] Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals along the X-axis. The contact holes 90 are arranged such that the gate trench 5 is located between adjacent contact holes 90 along the X-axis. The contact holes 90 extend along the Y-axis. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0031] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 and a source wiring 62. The contact electrode 61 is provided in the contact hole 90. The contact electrode 61 is in contact with the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is formed of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be formed of a material containing, for example, titanium (Ti), aluminum, and silicon. The contact electrode 61 forms an ohmic junction with the source region 13 and the contact region 18. The source wiring 62 covers the upper surface and side surfaces of the interlayer insulating film 83 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the interlayer insulating film 83 and the contact electrode 61. The source wiring 62 is formed of a material containing, for example, aluminum.

[0032] The chip region 100 has a gate runner 63. The gate runner 63 is formed simultaneously with the source electrode 60 and is made of the same material as the source electrode 60. The gate runner 63 is electrically connected to the gate electrode 82.

[0033] The chip region 100 has a passivation film 87. The passivation film 87 covers the upper surface of the source electrode 60. An opening 121 is formed in the passivation film 87, exposing a portion of the source electrode 60. The opening 121 is formed between two gate runners 63 adjacent to each other along the Y axis. A plating film 86 for the source is formed in the opening 121. The plating film 86 is, for example, a nickel plating film. An opening 122 is formed in the passivation film 87, exposing a portion of the gate pad 65 connected to the gate runner 63. A plating film for the gate is formed in the opening 122. An opening 123 may be formed in the passivation film 87, in addition to the openings 121 and 122.

[0034] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is formed of a material containing nickel silicide, for example. The drain electrode 70 may be formed of a material containing titanium, aluminum, and silicon. The drain electrode 70 is in ohmic contact with the silicon carbide single crystal substrate 50.

[0035] [Method for manufacturing a semiconductor device] Next, a method for manufacturing the semiconductor device 200 will be described. Fig. 4 is a flow diagram showing a method for manufacturing the semiconductor device 200 according to the embodiment. As shown in Fig. 4, the method for manufacturing the semiconductor device 200 according to the embodiment includes a step S1 of forming the chip region 100 and a step S2 of inspecting the chip region 100.

[0036] A description will now be given of step S1 of forming the chip region 100. Figures 5 to 7 are cross-sectional views showing step S1 of forming the chip region 100.

[0037] First, as shown in Fig. 5, a silicon carbide single crystal substrate 50 is prepared. Next, a silicon carbide epitaxial layer 40 is formed on the silicon carbide single crystal substrate 50. For example, the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has n-type conductivity. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of n-type impurities such as nitrogen.

[0038] 6, ions are implanted into the silicon carbide epitaxial layer 40 to form the body region 12, the source region 13, and the contact region 18. The remaining portion of the silicon carbide epitaxial layer 40 becomes the drift region 11.

[0039] 7, a plurality of gate trenches 5 are formed. Next, a gate insulating film 81, a gate electrode 82, and an interlayer insulating film 83 are formed. Next, contact holes 90 are formed in the gate insulating film 81 and the interlayer insulating film 83.

[0040] Next, the source electrode 60, the gate pad 65, the drain electrode 70, the passivation film 87, and the plating film 86 are formed (see FIGS. 1 and 2). The plating film 86 can be formed by, for example, electroless plating. In this manner, a plurality of chip regions 100 in which field-effect transistors are formed can be formed.

[0041] The step S2 of inspecting the chip area 100 will be described. The step S2 of inspecting the chip area 100 is performed after the step S1 of forming the chip area 100. The step S2 of inspecting the chip area 100 is performed on all of the multiple chip areas 100 formed in the step S1 of forming the chip area 100, for example. The step S2 of inspecting the chip area 100 may also be performed on some of the multiple chip areas 100 formed in the step S1 of forming the chip area 100.

[0042] Fig. 8 is a flow diagram showing step S2 of inspecting the chip region 100. Fig. 9 is a characteristics diagram showing the relationship between the drain current Id and the gate-source voltage Vgs of a field-effect transistor formed in the chip region 100. In Fig. 9, the vertical axis represents the drain current Id [A], and the horizontal axis represents the gate-source voltage Vgs [V]. In Fig. 9, the solid line represents the characteristics when the field-effect transistor is a non-defective product, and the dashed line represents the characteristics when the field-effect transistor is a defective product.

[0043] First, in step S21, first relationship information is obtained that represents the relationship between the drain current and the gate-source voltage of the field-effect transistor formed in the chip region 100. The first relationship information includes a characteristics diagram that represents the relationship between the drain current Id and the gate-source voltage Vgs of the field-effect transistor formed in the chip region 100, as shown in, for example, FIG.

[0044] The first relationship information may be acquired while the field-effect transistor formed in the chip region 100 is heated to a first temperature higher than room temperature. At temperatures higher than room temperature, carriers captured at the interface between the gate insulating film 81 and the body region 12 in the channel region are more easily discharged, and the effective band gap of the body region 12 narrows, resulting in a lower gate threshold voltage. The degree of decrease in the gate threshold voltage increases as the channel region becomes more contaminated with metal ions. Therefore, when the first relationship information is acquired while the field-effect transistor is heated to a first temperature higher than room temperature, the value of ΔVth / ΔId calculated in step S24 is larger than when the first relationship information is acquired at room temperature, thereby improving the sensitivity of defective product detection in step S25.

[0045] The first temperature may be 150° C. or higher and 250° C. or lower. When the first temperature is 150° C. or higher, the sensitivity of detecting defective products in step S25 is likely to be improved. When the first temperature is 250° C. or lower, warping of the semiconductor device 200 can be reduced.

[0046] Next, in step S22, a first voltage value Vth1, which is the gate-source voltage Vgs when the drain current Id becomes the first current value Id1, is calculated based on the first relationship information. For example, when the rated current of the field-effect transistor is 200 A, the first current value Id1 is 1×10 -3 A or higher 2 x 10 -3 In the characteristic diagram of FIG. 9, the first current value Id1 is 1×10 -3 A, and the first voltage value Vth1 is 4.0 V when the field effect transistor is a non-defective product (see the solid line in FIG. 9), and is 4.0 V when the field effect transistor is a defective product (see the dashed line in FIG. 9).

[0047] Next, in step S23, a second voltage value Vth2 is calculated based on the first relationship information, which is the gate-source voltage Vgs when the drain current Id becomes a second current value Id2. The second current value Id2 is smaller than the first current value Id1. The value obtained by dividing the first current value Id1 by the second current value Id2 is 10. 3 Over 105 In this case, the sensitivity of the defective product detection in step S25 is improved. In the characteristic diagram of FIG. 9, the second current value Id2 is 1×10 -7 A, and the second voltage value Vth2 is 3.0 V when the field effect transistor is a good product (see the solid line in FIG. 9), and 2.7 V when the field effect transistor is a defective product (see the dashed line in FIG. 9).

[0048] Next, in step S24, the value obtained by subtracting the second current value Id2 from the first current value Id1 is defined as ΔId, and the value obtained by subtracting the second voltage value Vth2 from the first voltage value Vth1 is defined as ΔVth, and the value of ΔVth / ΔId is calculated. In the characteristic diagram of FIG. 9, the value of ΔVth / ΔId is (4.0-3.0) / (1×10 -3 -1×10 -7 ), and if the field-effect transistor is defective, the error is (4.0-2.7) / (1×10 -3 -1×10 -7 )

[0049] Next, in step S25, it is determined whether the value of ΔVth / ΔId calculated in step S24 is greater than a judgment value. If the value of ΔVth / ΔId is greater than the judgment value (YES in step S25), the field-effect transistor is determined to be defective (step S26), the chip region 100 including the field-effect transistor is designated as a removal target (step S27), and the process ends. The chip region 100 designated as a removal target is removed after being singulated along the dicing region. If the value of ΔVth / ΔId is equal to or less than the judgment value (NO in step S25), the chip region 100 including the field-effect transistor is determined to be non-defective (step S28), and the process ends. The judgment value may be determined based on the median of the ΔVth / ΔId values ​​calculated for each of the multiple chip regions 100 included in the same semiconductor device 200. In this case, the sensitivity of defect detection is improved. The judgment value may be a value obtained by multiplying the median value of ΔVth / ΔId calculated for each of the multiple chip regions 100 included in the same semiconductor device 200 by 1.1.

[0050] In the manufacturing method of the semiconductor device 200, metal ions are contained in the plating solution used to form the plating film 86 in the step S1 of forming the chip region 100. The metal ions include sodium ions (Na + ), potassium ions (K + ), calcium ions (Ca + ), lithium ion (Li + ), chloride ions (Cl - ) Metal ions may diffuse into the interlayer insulating film 83 and the gate insulating film 81 through the corrosion of the embrittled portion of the source electrode 60. When metal ions diffuse into the gate insulating film 81, this causes a decrease in the gate threshold voltage when a voltage is applied at a high temperature (for example, 150° C. or higher and 200° C. or lower).

[0051] According to the manufacturing method of the semiconductor device 200 according to the embodiment, first, in step S21, first relationship information representing the relationship between the drain current Id and the gate-source voltage Vgs of the field-effect transistor is acquired. Next, in step S22, a first voltage value Vth1, which is the gate-source voltage Vgs when the drain current Id is a first current value Id1, is calculated based on the first relationship information. Next, in step S23, a second voltage value Vth2, which is the gate-source voltage Vgs when the drain current Id is a second current value Id2 that is smaller than the first current value Id1, is calculated based on the first relationship information. Next, in step S24, a value ΔVth / ΔId is calculated, where ΔId is the value obtained by subtracting the second current value Id2 from the first current value Id1, and ΔVth is the value obtained by subtracting the second voltage value Vth2 from the first voltage value Vth1. Next, in step S25, if the value ΔVth / ΔId is greater than a determination value, the field-effect transistor is determined to be defective. In this case, it is possible to extract and remove chip region 100 including a field-effect transistor that causes a drop in gate threshold voltage when voltage is applied at high temperature due to the inclusion of a region with a locally low gate threshold voltage, thereby enabling the manufacture of a chip with small fluctuations in gate threshold voltage.

[0052] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0053] 1 First main surface 2 Second main surface 3. Aspects 4 Bottom 5 Gate trench 10 Silicon carbide substrate 11 Drift Region 12 Body Region 13 Source Region 18 Contact Area 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 63 Gate Runner 65 Gate Pad 70 drain electrode 81 Gate insulating film 82 gate electrode 83 Interlayer insulating film 86 Plating film 87 Passivation Film 90 Contact Holes 100 chip area 121 Opening 122 Opening 123 Opening 200 Semiconductor device Id Drain current Id1 First current value Id2 Second current value Vgs Gate-source voltage Vth1 First voltage value Vth2 Second voltage value

Claims

1. A method for manufacturing a semiconductor device including a field effect transistor, comprising: acquiring first relationship information representing a relationship between a drain current and a gate-source voltage of the field effect transistor; calculating a first voltage value, which is the gate-source voltage when the drain current has a first current value, based on the first relationship information; calculating a second voltage value, which is the gate-source voltage when the drain current becomes a second current value smaller than the first current value, based on the first relationship information; a step of determining that the field effect transistor is defective when a value calculated by ΔVth / ΔId is greater than a determination value, where ΔId is a value obtained by subtracting the second current value from the first current value and ΔVth is a value obtained by subtracting the second voltage value from the first voltage value; The method for manufacturing a semiconductor device comprising the steps of:

2. the first relationship information is acquired in a state in which the field-effect transistor is heated to a first temperature higher than room temperature; The method for manufacturing a semiconductor device according to claim 1 .

3. The first temperature is 150°C or higher and 250°C or lower. The method for manufacturing a semiconductor device according to claim 2 .

4. The semiconductor device has a semiconductor substrate and a plurality of chip regions formed within a surface of the semiconductor substrate, the field effect transistor is formed in each of the plurality of chip regions, the judgment value is determined based on a median of the calculated values ​​calculated for each of the chip regions; The method for manufacturing a semiconductor device according to any one of claims 1 to 3.

5. The value obtained by dividing the first current value by the second current value is 10 ３ 10 above ５ Below is the The method for manufacturing a semiconductor device according to any one of claims 1 to 3.

6. A method for testing a semiconductor device including a field effect transistor, comprising: acquiring first relationship information representing a relationship between a drain current and a gate-source voltage of the field effect transistor; calculating a first voltage value, which is the gate-source voltage when the drain current has a first current value, based on the first relationship information; calculating a second voltage value, which is the gate-source voltage when the drain current becomes a second current value smaller than the first current value, based on the first relationship information; a step of determining that the field effect transistor is defective when a value calculated by ΔVth / ΔId is greater than a determination value, where ΔId is a value obtained by subtracting the second current value from the first current value and ΔVth is a value obtained by subtracting the second voltage value from the first voltage value; A semiconductor device inspection method comprising the steps of:

Images