Manufacturing method for semiconductor device and inspecting method for semiconductor device

Abstract

To provide a manufacturing method for a chip whose variation in gate threshold voltage is small, and an inspecting method for a semiconductor device.SOLUTION: In a manufacturing method for a semiconductor device, a step of inspecting a chip includes the steps of: acquiring first relation information expressing a relation between a drain-source voltage and a drain current when a gate-source voltage of a field effect transistor is a first voltage value; acquiring second relation information expressing a relation between the drain-source voltage and the drain current when the gate-source voltage is a second voltage value that is smaller than the first voltage value; calculating a first current value that is the drain current when the drain-source voltage becomes a third voltage value on the basis of the first relation information; calculating a second current value that is the drain current when the drain-source voltage becomes the third voltage value on the basis of the second relation information; and determining that the field effect transistor is defective when the calculation value calculated by (Id1-Id2) / Id2 is more than a determination value.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a method for inspecting a semiconductor device. [Background technology]

[0002] A semiconductor device is disclosed in which the surface of a metal electrode, excluding the portion covered with a passivation film, is covered with a nickel plating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-047675 Summary of the Invention [Problem to be solved by the invention]

[0004] The plating solution used to form the nickel plating film contains metal ions such as sodium ions. These metal ions can diffuse into the interlayer insulating film and gate insulating film through corrosion of the embrittled parts of the metal electrode. This can cause a decrease in the gate threshold voltage when a voltage is applied at high temperatures.

[0005] An object of the present disclosure is to provide a method for manufacturing a semiconductor device and a method for inspecting a semiconductor device that enable the manufacture of chips with small variations in gate threshold voltage. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor device according to the present disclosure is a method for manufacturing a semiconductor device including a field effect transistor, and includes the steps of: acquiring first relationship information representing a relationship between the drain current and drain-source voltage of the field effect transistor when the gate-source voltage of the field effect transistor is a first voltage value; acquiring second relationship information representing a relationship between the drain current and drain-source voltage of the field effect transistor when the gate-source voltage of the field effect transistor is a second voltage value smaller than the first voltage value; calculating a first current value, which is the drain current when the drain-source voltage is a third voltage value, based on the first relationship information; calculating a second current value, which is the drain current when the drain-source voltage is the third voltage value, based on the second relationship information; and determining that the field effect transistor is defective if a value calculated using (Id1-Id2) / Id2, where Id1 is the first current value and Id2 is greater than a determination value. [Effects of the Invention]

[0007] According to the present disclosure, chips with small variations in gate threshold voltage can be manufactured. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a diagram showing a chip area of ​​the semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a cross-sectional view showing a chip region of the semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a flow diagram showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 1) showing a step of forming a chip region. [Figure 6] FIG. 6 is a cross-sectional view (part 2) showing the step of forming the chip region. [Figure 7]FIG. 7 is a cross-sectional view (part 3) showing the step of forming the chip region. [Figure 8] FIG. 8 is a flow diagram showing the steps of inspecting the chip area. [Figure 9] FIG. 9 is a characteristic diagram showing the relationship between the drain current and the drain-source voltage of a field effect transistor formed in the chip region. [Figure 10] FIG. 10 is a diagram showing fluctuations in the gate threshold voltage of a field effect transistor formed in a chip region. DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments for carrying out the invention are described below.

[0010] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, identical or corresponding elements will be assigned the same reference numerals, and the same description will not be repeated. In the following description, an XYZ Cartesian coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of the silicon carbide semiconductor device. The XY plane view is referred to as a planar view, and the +Z direction from an arbitrary point may be referred to as upward, upper side, or top, and the -Z direction may be referred to as downward, lower side, or bottom.

[0011] [1] A method for manufacturing a semiconductor device according to one embodiment of the present disclosure is a method for manufacturing a semiconductor device including a field-effect transistor, the method comprising the steps of: acquiring first relationship information representing a relationship between a drain current and a drain-source voltage of the field-effect transistor when the gate-source voltage of the field-effect transistor is a first voltage value; acquiring second relationship information representing a relationship between the drain current and a drain-source voltage of the field-effect transistor when the gate-source voltage of the field-effect transistor is a second voltage value smaller than the first voltage value; calculating a first current value, which is the drain current when the drain-source voltage is a third voltage value, based on the first relationship information; calculating a second current value, which is the drain current when the drain-source voltage is the third voltage value, based on the second relationship information; and determining that the field-effect transistor is defective if a value calculated using (Id1-Id2) / Id2, where Id1 is the first current value and Id2 is greater than a determination value. In this case, it is possible to extract and remove chip regions including field-effect transistors that cause a drop in gate threshold voltage when voltage is applied at high temperatures due to the inclusion of regions with locally low gate threshold voltages, thereby manufacturing chips with small variations in gate threshold voltage.

[0012] [2] In [1], the first relationship information may be acquired while the field-effect transistor is heated to a first temperature higher than room temperature. At temperatures higher than room temperature, carriers trapped at the interface between the gate insulating film and the body region in the channel region are more easily expelled, and the effective band gap of the body region is narrowed, resulting in a lower gate threshold voltage. The degree of decrease in gate threshold voltage increases as the channel region is contaminated with metal ions. Therefore, when the first relationship information is acquired while the field-effect transistor is heated to a first temperature higher than room temperature, the value of Id1-Id2 is larger than when the first relationship information is acquired at room temperature, thereby improving the sensitivity of defective product detection.

[0013] [3] In [2], the first temperature may be 150° C. or higher and 250° C. or lower. When the first temperature is 150° C. or higher, sensitivity in detecting defective products is likely to be improved. When the first temperature is 250° C. or lower, warpage of the semiconductor device can be reduced.

[0014] [4] In any one of [1] to [3], the semiconductor device may have a semiconductor substrate and a plurality of chip regions formed in a plane of the semiconductor substrate, the field effect transistor being formed in each of the plurality of chip regions, and the judgment value may be determined based on a median of the calculated values ​​calculated for each of the chip regions. In this case, the sensitivity of defective product detection may be improved.

[0015] [5] In [1] to [4], the judgment value may be 1.0%, which improves the sensitivity of detecting defective products.

[0016] [6] In any of [1] to [5], the first voltage value may be smaller than a gate threshold voltage, and the third voltage value may be equal to or smaller than 0.9 times the breakdown voltage of the field-effect transistor. In this case, the sensitivity of detecting defective products is improved.

[0017] [7] A method for inspecting a semiconductor device according to another aspect of the present disclosure is a method for inspecting a semiconductor device including a field-effect transistor, the method comprising the steps of: acquiring first relationship information representing a relationship between a drain current and a drain-source voltage of the field-effect transistor when the gate-source voltage of the field-effect transistor is a first voltage value; acquiring second relationship information representing a relationship between the drain current and a drain-source voltage of the field-effect transistor when the gate-source voltage of the field-effect transistor is a second voltage value smaller than the first voltage value; calculating a first current value, which is the drain current when the drain-source voltage is a third voltage value, based on the first relationship information; calculating a second current value, which is the drain current when the drain-source voltage is the third voltage value, based on the second relationship information; and determining that the field-effect transistor is defective if a value calculated using (Id1-Id2) / Id2, where Id1 is the first current value and Id2 is greater than a determination value. In this case, it is possible to extract and remove chip regions including field-effect transistors that cause a drop in gate threshold voltage when voltage is applied at high temperatures due to the inclusion of regions with locally low gate threshold voltages, thereby manufacturing chips with small variations in gate threshold voltage.

[0018] [Details of the embodiments of the present disclosure] [Configuration of Semiconductor Device] An embodiment of the present disclosure relates to a so-called vertical MOS (Metal Oxide Semiconductor) field effect transistor (FET) using silicon carbide. FIG. 1 is a diagram showing a semiconductor device 200 according to the embodiment. FIG. 2 is a diagram showing a chip region 100 of the semiconductor device 200 according to the embodiment. FIG. 3 is a cross-sectional view showing the chip region 100 of the semiconductor device 200 according to the embodiment. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIG. 2.

[0019] As shown in FIG. 1, a semiconductor device 200 according to the embodiment has a plurality of chip regions 100. The plurality of chip regions 100 are arranged in an array. For example, the planar shape of each chip region 100 is rectangular. Each chip region 100 has a common configuration. A dicing region is provided between adjacent chip regions 100. A plurality of chips are obtained by dividing along the dicing region.

[0020] As shown in FIGS. 2 and 3, the chip region 100 has a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, and a drain electrode .

[0021] The silicon carbide substrate 10 is an example of a semiconductor substrate. When the silicon carbide substrate 10 is used, an excellent breakdown voltage can be easily obtained. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane. The first main surface 1 is in the +Z direction as viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide epitaxial layer 40 includes the first main surface 1. The silicon carbide single crystal substrate 50 includes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 include, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has n-type conductivity (first conductivity type).

[0022] The silicon carbide epitaxial layer 40 includes a drift region 11, a body region 12, a source region 13, and a contact region 18.

[0023] Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. Drift region 11 is provided on silicon carbide single crystal substrate 50. An electric field relaxation region may be provided in drift region 11. The electric field relaxation region has p-type conductivity (second conductivity type).

[0024] The body region 12 contains p-type impurities such as aluminum (Al) and has p-type conductivity. The body region 12 is provided on the drift region 11. The lower end surface of the body region 12 contacts the upper end surface of the drift region 11.

[0025] The source region 13 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity. The source region 13 is provided on the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. The source region 13 includes the first main surface 1.

[0026] A plurality of gate trenches 5 defined by side surfaces 3 and bottom surfaces 4 are provided on the first main surface 1. The gate trenches 5 extend, for example, along the Y axis. The plurality of gate trenches 5 are provided at regular intervals along the X axis. The side surfaces 3 penetrate the source region 13, the body region 12, and part of the drift region 11, and reach the drift region 11. The bottom surfaces 4 are continuous with the side surfaces 3. The bottom surfaces 4 are located in the drift region 11. The bottom surfaces 4 are, for example, parallel to the first main surface 1 and the second main surface 2. The side surfaces 3 are inclined with respect to a plane including the bottom surfaces 4.

[0027] The contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 18 penetrates the source region 13 and the body region 12 and is in contact with the drift region 11. The contact region 18 includes the first main surface 1. In a plan view perpendicular to the first main surface 1, the contact region 18 is located between adjacent gate trenches 5 along the X-axis.

[0028] The gate insulating film 81 includes, for example, silicon dioxide. The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the drift region 11 at the bottom surface 4. The gate insulating film 81 contacts the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 may contact the source region 13 at the first main surface 1.

[0029] The gate electrode 82 is formed of, for example, polysilicon containing conductive impurities. The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is disposed inside the gate trench 5. The gate electrode 82 faces the side surface 3 and the bottom surface 4. A portion of the gate electrode 82 may face the first main surface 1. The gate electrode 82 extends along the Y axis.

[0030] The interlayer insulating film 83 includes, for example, silicon dioxide. The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with the gate insulating film 81 and the gate electrode 82. The interlayer insulating film 83 electrically insulates the gate electrode 82 from the source electrode 60. A part of the interlayer insulating film 83 may be provided inside the gate trench 5. The upper surface of the interlayer insulating film 83 may be flat. The upper surface of the interlayer insulating film 83 may be a curved surface whose curvature changes continuously. The upper surface of the interlayer insulating film 83 may be a curved surface that is convex in the +Z direction above the gate trench 5.

[0031] Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals along the X-axis. The contact holes 90 are arranged such that the gate trench 5 is located between adjacent contact holes 90 along the X-axis. The contact holes 90 extend along the Y-axis. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0032] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 and a source wiring 62. The contact electrode 61 is provided in the contact hole 90. The contact electrode 61 is in contact with the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is formed of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be formed of a material containing, for example, titanium (Ti), aluminum, and silicon. The contact electrode 61 forms an ohmic junction with the source region 13 and the contact region 18. The source wiring 62 covers the upper surface and side surfaces of the interlayer insulating film 83 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the interlayer insulating film 83 and the contact electrode 61. The source wiring 62 is formed of a material containing, for example, aluminum.

[0033] The chip region 100 has a gate runner 63. The gate runner 63 is formed simultaneously with the source electrode 60 and is made of the same material as the source electrode 60. The gate runner 63 is electrically connected to the gate electrode 82.

[0034] The chip region 100 has a passivation film 87. The passivation film 87 covers the upper surface of the source electrode 60. An opening 121 is formed in the passivation film 87, exposing a portion of the source electrode 60. The opening 121 is formed between two gate runners 63 adjacent to each other along the Y axis. A plating film 86 for the source is formed in the opening 121. The plating film 86 is, for example, a nickel plating film. An opening 122 is formed in the passivation film 87, exposing a portion of the gate pad 65 connected to the gate runner 63. A plating film for the gate is formed in the opening 122. An opening 123 may be formed in the passivation film 87, in addition to the openings 121 and 122.

[0035] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is formed of a material containing nickel silicide, for example. The drain electrode 70 may be formed of a material containing titanium, aluminum, and silicon. The drain electrode 70 is in ohmic contact with the silicon carbide single crystal substrate 50.

[0036] [Method for manufacturing semiconductor device] Next, a method for manufacturing the semiconductor device 200 will be described. Fig. 4 is a flow diagram showing a method for manufacturing the semiconductor device 200 according to the embodiment. As shown in Fig. 4, the method for manufacturing the semiconductor device 200 according to the embodiment includes a step S1 of forming the chip region 100 and a step S2 of inspecting the chip region 100.

[0037] A description will now be given of step S1 of forming the chip region 100. Figures 5 to 7 are cross-sectional views showing step S1 of forming the chip region 100.

[0038] First, as shown in Fig. 5, a silicon carbide single crystal substrate 50 is prepared. Next, a silicon carbide epitaxial layer 40 is formed on the silicon carbide single crystal substrate 50. For example, the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has n-type conductivity. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of n-type impurities such as nitrogen.

[0039] 6, ions are implanted into the silicon carbide epitaxial layer 40 to form the body region 12, the source region 13, and the contact region 18. The remaining portion of the silicon carbide epitaxial layer 40 becomes the drift region 11.

[0040] 7, a plurality of gate trenches 5 are formed. Next, a gate insulating film 81, a gate electrode 82, and an interlayer insulating film 83 are formed. Next, contact holes 90 are formed in the gate insulating film 81 and the interlayer insulating film 83.

[0041] Next, the source electrode 60, the gate pad 65, the drain electrode 70, the passivation film 87, and the plating film 86 are formed (see FIGS. 1 and 2). The plating film 86 can be formed by, for example, electroless plating. In this manner, a plurality of chip regions 100 in which field-effect transistors are formed can be formed.

[0042] The step S2 of inspecting the chip area 100 will be described. The step S2 of inspecting the chip area 100 is performed after the step S1 of forming the chip area 100. The step S2 of inspecting the chip area 100 is performed on all of the multiple chip areas 100 formed in the step S1 of forming the chip area 100, for example. The step S2 of inspecting the chip area 100 may also be performed on some of the multiple chip areas 100 formed in the step S1 of forming the chip area 100.

[0043] Fig. 8 is a flow diagram showing step S2 of inspecting the chip region 100. Fig. 9 is a characteristics diagram showing the relationship between the drain current Id and the drain-source voltage Vds of a field-effect transistor formed in the chip region 100. In Fig. 9, the vertical axis represents the drain current Id, and the horizontal axis represents the drain-source voltage Vds. In Fig. 9, the solid line represents the characteristics when the gate-source voltage of the field-effect transistor is a first voltage value Vgs1, and the dashed line represents the characteristics when the gate-source voltage of the field-effect transistor is a second voltage value Vgs2.

[0044] First, in step S21, first relationship information is acquired that represents the relationship between the drain current and the drain-source voltage of the field-effect transistor formed in the chip region 100 when the gate-source voltage of the field-effect transistor is a first voltage value. The first voltage value may be smaller than the gate threshold voltage. The first voltage value may be equal to or smaller than 0.5 times the gate threshold voltage. The first threshold voltage may be equal to or greater than 0 V. The first relationship information includes a characteristics diagram that represents the relationship between the drain current Id and the drain-source voltage Vds of the field-effect transistor formed in the chip region 100 when the gate-source voltage of the field-effect transistor is a first voltage value Vgs1 (see the solid line in FIG. 9).

[0045] Next, in step S22, second relationship information is acquired that represents the relationship between the drain current and the drain-source voltage of the field-effect transistor formed in the chip region 100 when the gate-source voltage of the field-effect transistor is a second voltage value. The second voltage value is smaller than the first voltage value. The second voltage value may be less than 0 V. The second relationship information includes a characteristics diagram that represents the relationship between the drain current Id and the drain-source voltage Vds of the field-effect transistor formed in the chip region 100 when the gate-source voltage of the field-effect transistor is a second voltage value Vgs2 (see the dashed line in FIG. 9).

[0046] The first and second relationship information may be acquired while the field-effect transistor formed in the chip region 100 is heated to a first temperature higher than room temperature. At temperatures higher than room temperature, carriers captured at the interface between the gate insulating film 81 and the body region 12 in the channel region are more easily expelled, and the effective band gap of the body region 12 narrows, resulting in a lower gate threshold voltage. The degree of decrease in the gate threshold voltage increases as the channel region becomes more contaminated with metal ions. Therefore, when the first and second relationship information are acquired while heated to a first temperature higher than room temperature, the value of Id1-Id2 is larger than when the first and second relationship information are acquired at room temperature, thereby improving the sensitivity of defective product detection.

[0047] The first temperature may be 150° C. or higher and 250° C. or lower. When the first temperature is 150° C. or higher, the sensitivity of detecting defective products in step S26 is likely to be improved. When the first temperature is 250° C. or lower, warping of the semiconductor device 200 can be reduced.

[0048] Next, in step S23, a first current value Id1 is calculated based on the first relationship information, which is the drain current Id when the drain-source voltage Vds reaches a third voltage value Vds1. The third voltage value Vds1 may be 0.9 times or less the breakdown voltage of the field-effect transistor formed in the chip region 100. In this case, the sensitivity of detecting defective products is improved. The breakdown voltage may be the drain-source voltage Vds when the drain current Id reaches 1 mA.

[0049] Next, in step S24, a second current value Id2, which is the drain current Id when the drain-source voltage Vds becomes the third voltage value Vds1, is calculated based on the second relationship information.

[0050] Next, in step S25, the value (Id1-Id2) / Id2 is calculated by subtracting the second current value Id2 calculated in step S24 from the first current value Id1 calculated in step S23 and dividing the result by the second current value Id2 calculated in step S24.

[0051] Next, in step S26, it is determined whether the value of (Id1-Id2) / Id2 calculated in step S25 is greater than a judgment value. If the value of (Id1-Id2) / Id2 is greater than the judgment value (YES in step S26), the field-effect transistor is determined to be defective (step S27), the chip region 100 including the field-effect transistor is designated as a removal target (step S28), and the process ends. The chip region 100 designated as a removal target is removed after being singulated along the dicing region. If the value of (Id1-Id2) / Id2 is equal to or less than the judgment value (NO in step S26), the chip region 100 including the field-effect transistor is determined to be non-defective (step S29), and the process ends. The judgment value may be determined based on the median of the values ​​of (Id1-Id2) / Id2 calculated for each of the multiple chip regions 100 included in the same semiconductor device 200. In this case, the sensitivity of defect detection is improved. The judgment value may be 1.1 times the median of the values ​​of (Id1-Id2) / Id2 calculated for each of the multiple chip regions 100 included in the same semiconductor device 200. The judgment value may be 1.0%, which improves the sensitivity of detecting defective products.

[0052] In the manufacturing method of the semiconductor device 200, metal ions are contained in the plating solution used to form the plating film 86 in the step S1 of forming the chip region 100. The metal ions include sodium ions (Na + ), potassium ions (K + ), calcium ions (Ca + ), lithium ion (Li + ), chloride ions (Cl - ) Metal ions may diffuse into the interlayer insulating film 83 and the gate insulating film 81 through the corrosion of the embrittled portion of the source electrode 60. When metal ions diffuse into the gate insulating film 81, this causes a decrease in the gate threshold voltage when a voltage is applied at a high temperature (for example, 150° C. or higher and 200° C. or lower).

[0053] According to the manufacturing method of the semiconductor device 200 according to the embodiment, first, in step S21, first relationship information is acquired. The first relationship information is information representing the relationship between the drain current Id and the drain-source voltage Vds of the field-effect transistor formed in the chip region 100 when the gate-source voltage Vgs of the field-effect transistor is a first voltage value Vgs1. Next, in step S22, second relationship information is acquired. The second relationship information is information representing the relationship between the drain current Id and the drain-source voltage Vds of the field-effect transistor formed in the chip region 100 when the gate-source voltage Vgs of the field-effect transistor is a second voltage value Vgs2. Next, in step S23, a first current value Id1 is calculated based on the first relationship information, which is the drain current Id when the drain-source voltage Vds is a third voltage value Vds1. Next, in step S24, a second current value Id2 is calculated based on the second relationship information, which is the drain current Id when the drain-source voltage Vds is the third voltage value Vds1. Next, in step S25, the value (Id1-Id2) / Id2 is calculated by subtracting the second current value Id2 calculated in step S24 from the first current value Id1 calculated in step S23 and dividing the result by the second current value Id2 calculated in step S24. Next, in step S26, if the value (Id1-Id2) / Id2 calculated in step S25 is greater than a judgment value, the field-effect transistor is judged to be defective. In this case, chip region 100 including field-effect transistors that cause a drop in gate threshold voltage when voltage is applied at high temperatures due to the inclusion of locally low gate threshold voltage regions can be extracted and removed. This allows the manufacture of chips with small variations in gate threshold voltage.

[0054] FIG. 10 is a diagram showing the variation in gate threshold voltage of a field-effect transistor formed in the chip region 100. In FIG. 10, the vertical axis represents the variation in gate threshold voltage [V], and the horizontal axis represents the value of (Id1-Id2) / Id2. As shown in FIG. 10, when the value of (Id1-Id2) / Id2 is greater than 1.0%, the variation in gate threshold voltage is -0.7V, whereas when the value of (Id1-Id2) / Id2 is 1.0% or less, there is almost no variation in gate threshold voltage. From this result, it can be said that setting the judgment value to 1.0% improves the sensitivity of defective product detection.

[0055] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0056] 1 First main surface 2 Second main surface 3. Aspects 4 Bottom 5. Gate trench 10 Silicon carbide substrate 11 Drift Region 12 Body Region 13 Source Region 18 Contact Area 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 63 Gate Runner 65 Gate Pad 70 drain electrode 81 Gate insulating film 82 gate electrode 83 Interlayer insulating film 86 Plating film 87 Passivation Film 90 Contact Holes 100 chip area 121 Opening 122 Opening 123 Opening 200 Semiconductor device Id Drain current Id1 First current value Id2 Second current value Vds Drain-source voltage Vds1 Third voltage value Vgs Gate-source voltage Vgs1 First voltage value Vgs2 Second voltage value

Claims

1. A method for manufacturing a semiconductor device including a field effect transistor, comprising: acquiring first relationship information representing a relationship between a drain current and a drain-source voltage of the field effect transistor when the gate-source voltage of the field effect transistor is a first voltage value; acquiring second relationship information representing a relationship between a drain current and a drain-source voltage of the field effect transistor when the gate-source voltage of the field effect transistor is a second voltage value smaller than the first voltage value; calculating a first current value, which is the drain current when the drain-source voltage becomes a third voltage value, based on the first relationship information; calculating a second current value, which is the drain current when the drain-source voltage becomes the third voltage value, based on the second relationship information; determining that the field effect transistor is defective if a value calculated by (Id1-Id2) / Id2 is greater than a determination value, where Id1 is the first current value and Id2 is the second current value; The method for manufacturing a semiconductor device includes the steps of:

2. the first relationship information is acquired in a state in which the field-effect transistor is heated to a first temperature higher than room temperature; The method for manufacturing a semiconductor device according to claim 1 .

3. The first temperature is 150°C or higher and 250°C or lower. The method for manufacturing a semiconductor device according to claim 2 .

4. The semiconductor device has a semiconductor substrate and a plurality of chip regions formed within a surface of the semiconductor substrate, the field effect transistor is formed in each of the plurality of chip regions, the judgment value is determined based on a median of the calculated values ​​calculated for each of the chip regions; The method for manufacturing a semiconductor device according to any one of claims 1 to 3.

5. The judgment value is 1.0%. The method for manufacturing a semiconductor device according to any one of claims 1 to 3.

6. the first voltage value is less than a gate threshold voltage; the third voltage value is equal to or less than 0.9 times the breakdown voltage of the field effect transistor; The method for manufacturing a semiconductor device according to any one of claims 1 to 3.

7. A method for testing a semiconductor device including a field effect transistor, comprising: acquiring first relationship information representing a relationship between a drain current and a drain-source voltage of the field effect transistor when the gate-source voltage of the field effect transistor is a first voltage value; acquiring second relationship information representing a relationship between a drain current and a drain-source voltage of the field effect transistor when the gate-source voltage of the field effect transistor is a second voltage value smaller than the first voltage value; calculating a first current value, which is the drain current when the drain-source voltage becomes a third voltage value, based on the first relationship information; calculating a second current value, which is the drain current when the drain-source voltage becomes the third voltage value, based on the second relationship information; determining that the field effect transistor is defective if a value calculated by (Id1-Id2) / Id2 is greater than a determination value, where Id1 is the first current value and Id2 is the second current value; A semiconductor device inspection method comprising:

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