Semiconductor device

Abstract

To attain reduction of on-resistance.SOLUTION: A semiconductor device 10 includes a semiconductor layer 30, a plurality of body regions 32, a source region 34, a channel region 36, a gate electrode 42, a collector region 54, and a column region 48. The semiconductor layer 30 includes a first face 30A, and a second face 30B on the opposite side to the first face 30A. The plurality of body regions 32 are disposed separately in an X-axis direction on the first face 30A of the semiconductor layer 30. The source region 34 is provided within the body region 32 and disposed at a position away from an end face 32A of the body region 32 in the X-axis direction. The gate electrode 42 is provided above the channel region 36 between the end face 32A in the body region 32 and the source region 34 and opposed with the channel region 36 via a gate insulator film 40. The collector region 54 is provided on the second face 30B of the semiconductor layer 30. The column region 48 is provided at a position away from the body region 32 in the semiconductor layer 30.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a MOSFET having a superjunction structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-041972

[0004] [overview] In the semiconductor device described above, it is desirable to reduce the on-resistance.

[0005] a gate electrode provided above the channel region and facing the channel region via a gate insulating film; a collector region of the second conductivity type provided on the second surface; and a column region of the second conductivity type provided in the semiconductor layer at a position spaced apart from the body region, wherein the first surface of the semiconductor layer includes an inter-element region between the body regions, and the column region is the inter-element region when viewed from the thickness direction of the semiconductor layer and is located closer to the second surface than the body region. [Brief explanation of the drawings]

[0006] [Figure 1]FIG. 1 is a schematic plan view of an exemplary semiconductor device according to one embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view of the semiconductor device taken along line F2-F2 in FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view showing an enlarged portion of FIG. [Figure 4] FIG. 4 is a schematic plan view showing the arrangement of the components of the semiconductor device of FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view showing the operation of the semiconductor device of FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a semiconductor device as a comparative example to the semiconductor device of FIG. [Figure 7] 7A to 7C are schematic cross-sectional views illustrating exemplary manufacturing steps for the semiconductor device of FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 19]FIG. 19 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 20] FIG. 20 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 21] FIG. 21 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 22] FIG. 22 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 23] FIG. 23 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 24] FIG. 24 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 25] FIG. 25 is a schematic cross-sectional view showing a semiconductor device according to a modified example.

[0007] [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure. Terms such as "first," "second," and "third" in the present disclosure are used merely to distinguish between objects and do not rank the objects.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] (Embodiment) A semiconductor device 10 according to one embodiment will be described with reference to FIGS. FIG. 1 is a schematic plan view of an exemplary semiconductor device 10 according to one embodiment. FIG. 2 is a schematic cross-sectional view of the semiconductor device 10 taken along line F2-F2 in FIG. 1. FIG. 3 is a schematic cross-sectional view showing an enlarged portion of FIG. 2. FIG. 4 is a schematic plan view showing the arrangement of components of the semiconductor device 10 in FIG. 2. FIG. 4 shows an example of the arrangement of the gate electrodes 42, column regions 48, and collector regions 54 in FIG. 2.

[0010] The term "plan view" used in this disclosure refers to viewing the semiconductor device 10 in the Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in Figure 1. Unless explicitly stated otherwise, "plan view" refers to viewing the semiconductor device 10 from above along the Z-axis.

[0011] (Schematic configuration of semiconductor device) The semiconductor device 10 is, for example, a semiconductor switching device including a metal oxide semiconductor field effect transistor (MOSFET), such as a super junction MOSFET (SJ-MOSFET).

[0012] In one example, the semiconductor device 10 may have a quadrangular shape in a plan view. The semiconductor device 10 includes a first surface 11 and a second surface 12 opposite to the first surface 11. The semiconductor device 10 includes a plurality of side surfaces 13, 14, 15, and 16 connecting the first surface 11 and the second surface 12. The first side surface 13 and the second side surface 14 extend along the X-axis direction. The first side surface 13 and the second side surface 14 form both end surfaces of the semiconductor device 10 in the Y-axis direction. The third side surface 15 and the fourth side surface 16 extend along the Y-axis direction. The third side surface 15 and the fourth side surface 16 form both end surfaces of the semiconductor device 10 in the X-axis direction.

[0013] The semiconductor device 10 may include a passivation layer 20. The passivation layer 20 may cover the first surface 11. The passivation layer 20 may be made of any material capable of protecting the underlying structure. In one example, the passivation layer 20 may be made of silicon nitride (SiN). The passivation layer 20 may include pad openings 20A and 20B.

[0014] The semiconductor device 10 may further include an electrode film 22. The electrode film 22 is provided on the first surface 11. The passivation layer 20 at least partially covers the electrode film 22. The electrode film 22 may be made of a material containing at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a Cu alloy, and an Al alloy. In one example, the electrode film 22 is made of a material containing an AlCu alloy.

[0015] The electrode film 22 may include a source electrode film 24 and a gate electrode film 26. The source electrode film 24 and the gate electrode film 26 are spaced apart from each other. In one example, the gate electrode film 26 may be disposed so as to surround the source electrode film 24.

[0016] A portion of the source electrode film 24 is exposed through the first pad opening 20A of the passivation layer 20. It can be said that the passivation layer 20 includes the first pad opening 20A that exposes a portion of the source electrode film 24. The portion of the source electrode film 24 exposed through the first pad opening 20A functions as a pad to which a conductor such as a bonding wire is connected. The pad of the source electrode film 24 may be called a source pad.

[0017] The source electrode film 24 may have a recess 24A in a plan view. In one example, the source electrode film 24 has the recess 24A in a corner of the semiconductor device 10 in a plan view. In the example shown in Fig. 1 , the recess 24A may be provided in a corner including the first side surface 13 and the third side surface 15 of the semiconductor device 10.

[0018] The gate electrode film 26 may include a pad portion 26A and a finger portion 26B. The pad portion 26A is disposed in a recess 24A of the source electrode film 24. The finger portion 26B extends from the pad portion 26A along the side surfaces 13 to 16 of the semiconductor device 10. In one example, the finger portion 26B may have a closed loop shape surrounding the source electrode film 24. In the semiconductor device 10, the finger portion 26B may have an open loop shape with an end at a corner diagonally opposite the pad portion 26A.

[0019] A portion of the pad portion 26A of the gate electrode film 26 is exposed by the second pad opening 20B in the passivation layer 20. It can be said that the passivation layer 20 includes the second pad opening 20B that exposes a portion of the gate electrode film 26. The portion of the gate electrode film 26 exposed by the second pad opening 20B functions as a pad to which a conductor such as a bonding wire is connected. The pad of the gate electrode film 26 may be called a gate pad.

[0020] The semiconductor device 10 may include a drain electrode 28 provided on the second surface 12. The drain electrode 28 may be made of a material containing at least one of Ti, Ni, Au, Ag, Cu, Al, a Cu alloy, and an Al alloy. In one example, the drain electrode 28 is made of a material containing Al.

[0021] (Detailed configuration of semiconductor device) As shown in FIGS. 2 and 3, the semiconductor device 10 may include a semiconductor layer 30. The semiconductor layer 30 includes a first surface 30A and a second surface 30B opposite the first surface 30A. In one example, the second surface 30B of the semiconductor layer 30 may constitute the second surface 12 of the semiconductor device 10.

[0022] The semiconductor layer 30 may be formed of, for example, an epitaxial layer. The semiconductor layer 30 may be formed of a material containing Si. The semiconductor layer 30 may be formed as a first conductivity type containing a predetermined impurity. The first conductivity type may be, for example, n-type. The semiconductor layer 30 may contain n-type impurities. The first conductivity type semiconductor layer 30 may contain, for example, phosphorus (P), arsenic (As), or the like as an impurity.

[0023] The semiconductor device 10 may include a plurality of body regions 32. The plurality of body regions 32 may be provided on the first surface 30A of the semiconductor layer 30. The plurality of body regions 32 may be provided on the first surface 30A and spaced apart from each other in the X-axis direction. As shown in Fig. 4, the plurality of body regions 32 may extend in the Y-axis direction intersecting the arranged X-axis direction in a plan view.

[0024] The body region 32 can be configured as a second conductivity type containing predetermined impurities. The second conductivity type may be different from the first conductivity type. The second conductivity type may be, for example, p-type. The body region 32 may contain p-type impurities. The second conductivity type body region 32 may contain, for example, boron (B), Al, or the like as impurities.

[0025] The semiconductor device 10 may include a source region 34. In one example, the source region 34 may be of a first conductivity type. The impurities contained in the source region 34 may be the same as or different from the impurities contained in the semiconductor layer 30.

[0026] A source region 34 is provided in each body region 32. The source region 34 may be selectively formed on the first surface 30A of the semiconductor layer 30, which is the surface portion of the body region 32. The source region 34 is provided at a position away from the end face 32A of the body region 32 in the X-axis direction. As shown in FIG. 4 , the source region 34 may extend in the Y-axis direction. The surface portion of the body region 32 between the end face 32A of the body region 32 and the source region 34 is configured as a channel region 36.

[0027] The semiconductor device 10 may include a channel contact region 38 . The channel contact region 38 may be disposed below a source contact portion 24B of the source electrode film 24, which will be described later. The channel contact region 38 may be adjacent to the channel region 36 and the source region 34. The channel contact region 38 may be a region of a second conductor containing a predetermined impurity in the channel region 36 and the source region 34. The impurity concentration of the channel contact region 38 may be higher than that of the channel region 36.

[0028] The semiconductor device 10 may include a gate insulating film 40 and a gate electrode 42. The gate insulating film 40 is disposed on the first surface 30A of the semiconductor layer 30. The gate insulating film 40 may cover at least the surface of the body region 32 in the channel region 36. In one example, the gate insulating film 40 may cover a part of the source region 34, the channel region 36, and the first surface 30A of the semiconductor layer 30. The gate insulating film 40 may be composed of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a hafnium oxide film, an alumina film, or a tantalum oxide film.

[0029] The gate electrode 42 is disposed on the gate insulating film 40. The gate electrode 42 may be electrically connected to the gate electrode film 26 shown in FIG. 1. The gate electrode 42 may be made of polysilicon containing impurities. The gate electrode 42 may be disposed across the body regions 32 disposed apart in the X-axis direction.

[0030] The semiconductor device 10 may include an insulating film 44 covering the gate electrode 42. The insulating film 44 may be made of an insulating material such as a silicon dioxide film (SiO), a silicon nitride film (SiN), or TEOS (tetraethoxysilane). For example, the insulating film 44 may be an SiO film. The SiO film may be a film formed by chemical vapor deposition (CVD).

[0031] The insulating film 44 may include a contact hole 44A that exposes the channel contact region 38. The contact hole 44A penetrates the gate insulating film 40. The semiconductor device 10 may include an electrode film 22 provided on the insulating film 44. A source electrode film 24 is shown in Figures 2 and 3. The source electrode film 24 may be simply referred to as a source electrode.

[0032] The source electrode film 24 may include a source contact portion 24B disposed in the contact hole 44A of the insulating film 44. The source contact portion 24B is in contact with the channel contact region 38. This allows the source electrode film 24 to be electrically connected to the source region 34.

[0033] The first surface 30A of the semiconductor layer 30 may include inter-element regions 46 which are regions between the body regions 32. The semiconductor device 10 includes a column region 48. The column region 48 may be a semiconductor region of a second conductivity type containing a predetermined impurity. The impurity in the column region 48 may be the same as or different from the impurity contained in the body region 32.

[0034] The semiconductor device 10 may include a plurality of column regions 48. The plurality of column regions 48 are arranged to be spaced apart in the X-axis direction in a plan view. As shown in Fig. 4, the plurality of column regions 48 extend in the Y-axis direction, which intersects with the X-axis direction, in a plan view. The plurality of column regions 48 can be said to have a stripe shape extending in the Y-axis direction as a whole in a plan view.

[0035] The column region 48 is disposed in the inter-element region 46 when viewed from the Z-axis direction, which is the thickness direction of the semiconductor layer 30. The inter-element region 46 is a region between the body regions 32 arranged at a distance in the X-axis direction. In the X-axis direction, the center 48C of the column region 48 may be located between the body regions 32 arranged at a distance. The column region 48 may partially overlap with the body region 32 in a plan view. The column region 48 does not have to overlap with the body region 32 in a plan view.

[0036] The column region 48 is disposed at a distance from the body region 32 in the Z-axis direction. The column region 48 extends in the Z-axis direction. The column region 48 may include a top portion 48A that is closer to the first surface 30A of the semiconductor layer 30 and a bottom portion 48B that is closer to the second surface 30B of the semiconductor layer 30 in the Z-axis direction. The column region 48 is disposed with the top portion 48A spaced apart from the first surface 30A of the semiconductor layer 30. The column region 48 is disposed with the bottom portion 48B spaced apart from the second surface 30B of the semiconductor layer 30. The top portion 48A of the column region 48 is disposed closer to the second surface 30B of the semiconductor layer 30 than the body region 32 in the Z-axis direction. It can be said that the column region 48 is disposed closer to the second surface 30B of the semiconductor layer 30 than the body region 32 in the Z-axis direction.

[0037] The semiconductor layer 30 may include a drift region 50 sandwiched between column regions 48 in the X-axis direction. The drift region 50 may be a semiconductor region of a first conductivity type containing predetermined impurities.

[0038] The column region 48 includes side surfaces 48D, which are both end surfaces in the X-axis direction. In one example, the side surfaces 48D of the column region 48 may be uneven surfaces. As shown in FIG. 3 , the first length L11 of the column region 48 in the X-axis direction may be smaller than the second length L12 of the drift region 50 between two adjacent column regions 48 in the X-axis direction. It can be said that the column region 48 has the first length L11 that is smaller than the second length L12 of the drift region 50. The first length L11 of the column region 48 may be equal to the second length L12 of the drift region 50. It can be said that the column region 48 has the first length L11 that is equal to the second length L12 of the drift region 50. The first length L11 of the column region 48 may be defined as the width of the widest portion of the column region 48 in the X-axis direction. The second length L12 of the drift region 50 may be defined as the width of the narrowest portion of the drift region 50.

[0039] A distance D12 from the second surface 30B of the semiconductor layer 30 to the bottom 48B of the column region 48 may be greater than a distance D11 from the first surface 30A of the semiconductor layer 30 to the top 48A of the column region 48.

[0040] 3 , a distance D22 between the body region 32 and the column region 48 in the Z-axis direction may be greater than a distance D21 from the first surface 30A of the semiconductor layer 30 to the bottom surface 32B of the body region 32 in the Z-axis direction. The distance D22 may be defined as the distance from the bottom surface 32B of the body region 32 to the top 48A of the column region 48 in the Z-axis direction. The bottom surface 32B of the body region 32 may be defined as the distance to the portion of the body region 32 that is farthest from the first surface of the semiconductor layer 30.

[0041] The semiconductor device 10 may include a contact region 52. The contact region 52 may be provided over the entire second surface 30B of the semiconductor layer 30. The semiconductor device 10 may include a collector region 54. The collector region 54 is provided on the second surface 30B of the semiconductor layer 30. The collector region 54 may be configured as a second conductivity type containing a predetermined impurity. The collector region 54 may be a semiconductor region formed by implanting a predetermined impurity into the second surface 30B of the semiconductor layer 30. The impurity contained in the collector region 54 may be the same as or different from the impurity contained in the body region 32.

[0042] The collector regions 54 may be selectively formed on the second surface 30B of the semiconductor layer 30. In one example, the semiconductor device 10 may include a plurality of collector regions 54 arranged at a distance in the X-axis direction. As shown in FIG. 4 , the plurality of collector regions 54 may extend in the Y-axis direction intersecting the arranged X-axis direction. The semiconductor device 10 may include contact regions 52 sandwiched between the collector regions 54. In one example, the plurality of collector regions 54 and the plurality of contact regions 52 may be arranged alternately in the X-axis direction. The plurality of collector regions 54 and the plurality of contact regions 52 may be arranged in a stripe pattern.

[0043] The collector regions 54 have a third length L13 in the arranged X-axis direction in plan view. The contact regions 52 have a fourth length L14 in the arranged X-axis direction in plan view. The third length L13 of the collector regions 54 may be greater than the fourth length L14 of the contact regions 52.

[0044] 4, the collector region 54 may be arranged so that at least a portion thereof overlaps with the contact region 52 in a plan view. The collector region 54 may be arranged so that at least a portion thereof overlaps with the column region 48 in a plan view. In one example, the collector region 54 may be arranged across two column regions 48 adjacent to each other in the X-axis direction in a plan view.

[0045] The ratio of the area of ​​the collector region 54 to the area in which the collector region 54 and the contact region 52 are disposed in the X-axis direction can be referred to as the occupancy rate of the collector region 54. The occupancy rate of the collector region 54 may be expressed as the ratio of the third length L13 of the collector region 54 to the sum of the third length L13 of the collector region 54 and the fourth length L14 of the contact region 52. The occupancy rate of the collector region 54 is preferably greater than 50% and not more than 90%, and more preferably 80% or more and not more than 90%. In one example, the occupancy rate of the collector region 54 may be 80%.

[0046] The drain electrode 28 is provided on the second surface 30B of the semiconductor layer 30. The drain electrode 28 is in contact with the contact region 52 and the collector region 54. The drain electrode 28 is in ohmic contact with the first conductivity type semiconductor layer 30 via the first conductivity type contact region 52.

[0047] (Operation of the embodiment) As shown in FIG. 5, the semiconductor device 10 of the embodiment includes a semiconductor layer 30, a plurality of body regions 32, a source region 34, a channel region 36, a gate electrode 42, a collector region 54, and a column region 48.

[0048] The semiconductor layer 30 includes a first surface 30A and a second surface 30B opposite to the first surface 30A. A plurality of body regions 32 are provided on the first surface 30A of the semiconductor layer 30 to be spaced apart in the X-axis direction. The source region 34 is provided in the body region 32 and arranged at a position spaced apart from an end surface 32A of the body region 32 in the X-axis direction. The gate electrode 42 is provided above a channel region 36 located between the end surface 32A of the body region 32 and the source region 34, and faces the channel region 36 via a gate insulating film 40. The collector region 54 is provided on the second surface 30B of the semiconductor layer 30. The column region 48 is provided in the semiconductor layer 30 at a position spaced apart from the body region 32.

[0049] In this semiconductor device 10, a voltage is applied to the drain electrode 28 and the source electrode film 24, with the drain electrode 28 at a high potential and the source electrode film 24 at a low potential. When a gate voltage equal to or greater than the threshold voltage is applied to the gate electrode 42, an inversion layer (channel) is formed in the channel region 36, establishing electrical continuity between the source region 34 and the drift region 50. Electrons serving as carriers are injected from the source electrode film 24 through the source region 34 and the channel region 36 into the drift region 50. Holes 60 are also injected into the semiconductor layer 30 from a collector region 54 selectively disposed on the second surface 30B of the semiconductor layer 30. This allows conductivity modulation to occur in the drift region 50, thereby achieving a low on-resistance in the semiconductor device 10.

[0050] Here, a comparative example to the semiconductor device 10 of the above embodiment will be described. 6 shows a cross-sectional structure of a semiconductor device 10X of the comparative example. In the description of the comparative example, the same components as those of the semiconductor device 10 of the above-described embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

[0051] FIG. 6 corresponds to the cross-sectional structure of the semiconductor device 10X shown in FIG. In the semiconductor device 10X of the comparative example, the column region 48X is electrically connected to the body region 32. The column region 48X extends from the body region 32 toward the second surface 30B of the semiconductor layer 30. Therefore, in the semiconductor device 10X of the comparative example, holes 60 injected from the collector region 54 may invade the column region 48X. The holes 60 that invade the column region 48X tend to move from the column region 48X to the body region 32 to which the column region 48X is connected. As a result, the carrier density in the drift region 50X is unlikely to increase, and the effect of conductivity modulation is unlikely to be obtained. In other words, the on-resistance is unlikely to decrease in conductivity modulation.

[0052] The semiconductor device 10 of the embodiment includes a column region 48 provided in the semiconductor layer 30 at a position separated from the body region 32. In other words, the column region 48 is not electrically connected to the body region 32. Even if holes 60 enter the column region 48, the holes 60 are unlikely to move from the column region 48 to the body region 32. Therefore, in the semiconductor device 10 of the embodiment, the holes 60 injected into the semiconductor layer 30 are unlikely to enter the column region 48. This makes it possible to increase the carrier concentration in the drift region 50, and the on-resistance can be further reduced by the effect of conductivity modulation.

[0053] The distance between the column region 48 and the body region 32 is preferably small in order to reduce the on-resistance of the semiconductor device 10. However, if the column region 48 and the body region 32 are brought close to each other, the column region 48 and the body region 32 may be connected to each other.

[0054] In the semiconductor device 10 of the embodiment, the column regions 48 are arranged in the inter-element regions 46, which are regions between the plurality of body regions 32 in a plan view. This makes it difficult for the column regions 48 to be connected to the body regions 32. In other words, the column regions 48 and the body regions 32 can be prevented from being connected to each other.

[0055] The column region 48 is disposed closer to the second face 30B of the semiconductor layer 30 than the body region 32. Therefore, the semiconductor layer 30 can be provided between the column region 48 and the body region 32, which further reduces the connection between the column region 48 and the body region 32.

[0056] (Method of manufacturing a semiconductor device) An example of a method for manufacturing the semiconductor device 10 shown in FIGS. 1 to 4 will now be described. 7 to 19 are schematic cross-sectional views showing exemplary manufacturing processes for the semiconductor device 10. Figures 7 to 19 correspond to the cross-sectional structure of the semiconductor device 10 shown in Figure 2. In Figures 7 to 19, components that are the same as the final components of the semiconductor device 10 are denoted by the same reference numerals as in Figure 2.

[0057] 7, the method for manufacturing the semiconductor device 10 may include preparing a substrate 800. As an example, the substrate 800 may be a silicon substrate of a first conductivity type.

[0058] The method for manufacturing the semiconductor device 10 may include forming the semiconductor layer 30 . The semiconductor layer 30 may include an initial base layer 802 and multiple semiconductor layers 804 stacked on the initial base layer 802. First, the initial base layer 802 is formed on the substrate 800 by epitaxial growth. Next, second-conductivity-type impurities 808 are selectively implanted into the surface of the initial base layer 802 at positions where the column regions 48 should be formed. Next, multiple semiconductor layers 804 are stacked on the initial base layer 802 by multi-epitaxial growth, in which the process of forming first-conductivity-type semiconductor layers 804 while selectively implanting second-conductivity-type impurities into the positions where the column regions 48 should be formed is repeated. Furthermore, a topmost semiconductor layer 806 is stacked without implanting impurities. In this way, the initial base layer 802, the multiple semiconductor layers 804, and the semiconductor layer 806 are integrated to form the semiconductor layer 30.

[0059] As shown in FIG. 8 , the method for manufacturing the semiconductor device 10 may include forming a column region 48. By performing an annealing process on the structure shown in FIG. 7 , which includes a substrate 800, an initial base layer 802, and semiconductor layers 804 and 806, impurities 808 in the initial base layer 802 and the semiconductor layer 804 are diffused. The temperature of the annealing process may be, for example, 1000° C. or higher and 1200° C. or lower. This forms the column region 48 in the semiconductor layer 30.

[0060] 9, the method for manufacturing the semiconductor device 10 may include forming an insulating film 40. The insulating film 40 is formed so as to cover the first surface 30A of the semiconductor layer 30. The insulating film 40 may be, for example, a SiO film formed by thermal oxidation.

[0061] 10, the method for manufacturing the semiconductor device 10 may include forming a gate electrode 42. The gate electrode 42 is formed by selectively removing a metal layer formed on the insulating film 40. The metal layer may be, for example, conductive polysilicon.

[0062] 11 , the manufacturing method of the semiconductor device 10 may include forming a body region 32. The body region 32 is formed by injecting impurities into the semiconductor layer 30 between the gate electrodes 42 and diffusing the injected impurities by annealing. The column region 48 is disposed in the inter-element region 46 between the body regions 32. Therefore, even if the impurities are diffused when forming the body region 32, the body region 32 can be prevented from being connected to the column region 48.

[0063] 12, the method for manufacturing the semiconductor device 10 may include forming a source region 34. The source region 34 is formed by injecting impurities into the body region 32 between the gate electrodes 42 and diffusing the injected impurities by annealing.

[0064] 13, the method for manufacturing the semiconductor device 10 may include forming an insulating film 44. The insulating film 44 may be, for example, an SiO 2 film formed by a CVD method.

[0065] 14, the manufacturing method of the semiconductor device 10 may include forming a channel contact region 38 and forming a source electrode film 24. First, a contact hole 44A is formed in the insulating film 44, and the channel contact region 38 is formed in the body region 32. Then, the source electrode film 24 including a source contact portion 24B in contact with the channel contact region 38 is formed.

[0066] 15, the manufacturing method of the semiconductor device 10 may include forming the second surface 30B of the semiconductor layer 30. First, the substrate 800 shown in FIG. 14 is removed. In one example, the substrate 800 may be removed by grinding. Then, the back surface of the semiconductor layer 30 is etched, for example, to form the second surface 30B.

[0067] In this way, the semiconductor layer 30 is supported by the substrate 800 until partway through the manufacturing process, which facilitates transport and handling of the semiconductor layer 30. Furthermore, by grinding the semiconductor layer 30 consecutively after grinding the substrate 800, it becomes possible to easily adjust the distance D12 between the column region 48 and the second surface 30B of the semiconductor layer 30.

[0068] 16, the method for manufacturing the semiconductor device 10 may include forming a contact region 52. The contact region 52 is formed by implanting impurities of the first conductivity type into the entire second surface 30B of the semiconductor layer 30 and performing an annealing treatment.

[0069] As shown in FIGS. 17 and 18, the method of manufacturing the semiconductor device 10 may include forming the collector region 54. First, as shown in FIG. 17, a mask 810 is formed on the second surface 30B of the semiconductor layer 30. The mask 810 is formed so as to expose a portion of the second surface 30B of the semiconductor layer 30 that corresponds to the collector region 54. Then, predetermined ions are implanted into the semiconductor layer 30 through an opening 810A of the mask 810. The ions to be implanted may be, for example, B ions or BF ions. Thereafter, the mask 810 is removed by, for example, ashing.

[0070] Next, as shown in FIG. 18, the ions implanted into the semiconductor layer 30 are activated by annealing, thereby forming the collector region 54. 19, the method for manufacturing the semiconductor device 10 may include forming a drain electrode 28. The drain electrode 28 may be formed by sputtering Ti, Ni, Au, and Ag. Through the above steps, the semiconductor device 10 shown in FIG. 2 is formed.

[0071] (Effects of the embodiment) As described above, the semiconductor device 10 of the embodiment provides the following advantages. (1) The semiconductor device 10 includes a semiconductor layer 30, a plurality of body regions 32, a source region 34, a channel region 36, a gate electrode 42, a collector region 54, and a column region 48. The semiconductor layer 30 includes a first surface 30A and a second surface 30B opposite the first surface 30A. The plurality of body regions 32 are provided on the first surface 30A of the semiconductor layer 30, spaced apart in the X-axis direction. The source region 34 is provided in the body region 32 and positioned away from an end surface 32A of the body region 32 in the X-axis direction. The gate electrode 42 is provided above a channel region 36 between the end surface 32A of the body region 32 and the source region 34, and faces the channel region 36 via a gate insulating film 40. The collector region 54 is provided on the second surface 30B of the semiconductor layer 30. The column region 48 is provided in the semiconductor layer 30, spaced apart from the body region 32.

[0072] In this semiconductor device 10, a voltage is applied to the drain electrode 28 and the source electrode film 24, with the drain electrode 28 at a high potential and the source electrode film 24 at a low potential. When a gate voltage equal to or greater than the threshold voltage is applied to the gate electrode 42, an inversion layer (channel) is formed in the channel region 36, establishing electrical continuity between the source region 34 and the semiconductor layer 30 (drift region 50). Electrons serving as carriers are injected from the source electrode film 24 through the source region 34 and the channel region 36 into the drift region 50. Holes 60 are also injected into the semiconductor layer 30 from a collector region 54 selectively disposed on the second surface 30B of the semiconductor layer 30. This allows conductivity modulation to occur in the drift region 50, thereby achieving a low on-resistance in the semiconductor device 10.

[0073] (2) The semiconductor device 10 includes a column region 48 provided in the semiconductor layer 30 at a position separated from the body region 32. In other words, the column region 48 is not electrically connected to the body region 32. Even if holes 60 enter the column region 48, the holes 60 are unlikely to move from the column region 48 to the body region 32. Therefore, in the semiconductor device 10 of the embodiment, the holes 60 injected into the semiconductor layer 30 are unlikely to enter the column region 48. This makes it possible to increase the carrier concentration in the drift region 50, and the on-resistance can be reduced by the effect of conductivity modulation.

[0074] (3) The distance between the column region 48 and the body region 32 is preferably small in order to reduce the on-resistance of the semiconductor device 10. However, if the column region 48 and the body region 32 are brought close to each other, the column region 48 and the body region 32 may be connected to each other.

[0075] (4) In the semiconductor device 10, the column regions 48 are arranged in the inter-element regions 46, which are regions between the body regions 32 in a plan view. This makes it difficult for the column regions 48 to be connected to the body regions 32. In other words, the column regions 48 and the body regions 32 can be prevented from being connected to each other.

[0076] (5) The column region 48 is disposed closer to the second face 30B of the semiconductor layer 30 than the body region 32. Therefore, the semiconductor layer 30 can be provided between the column region 48 and the body region 32, which further reduces the connection between the column region 48 and the body region 32.

[0077] (Example of change) The above embodiment can be modified, for example, as follows: The above embodiment and each of the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts common to the above embodiment will be assigned the same reference numerals as in the above embodiment, and their description will be omitted.

[0078] The configuration of the semiconductor device 10 may be changed as appropriate. 20 , the semiconductor device 100 of the modified example may include a plurality of collector regions 54 arranged at a distance from each other in a direction intersecting the X-axis direction in a plan view. In one example, the plurality of collector regions 54 may be arranged along the Y-axis direction, which is a direction perpendicular to the X-axis direction in a plan view. The semiconductor device 100 of this modified example can be said to include collector regions 54 extending in the X-axis direction, which intersects the Y-axis direction in which the column regions 48 extend.

[0079] 21 , a semiconductor device 110 according to a modified example may include a plurality of body regions 32 arranged side by side in the X-axis direction and the Y-axis direction. The body regions 32 may have a rectangular shape in a plan view. The source regions 34 are provided at positions away from end faces 32A of the body regions 32. The source regions 34 may have a rectangular shape in a plan view.

[0080] As shown in FIG. 22, a semiconductor device 120 of the modified example may include column regions 48 arranged side by side in the X-axis direction and the Y-axis direction, as compared to the semiconductor device 110 of the modified example shown in FIG. 21. The column regions 48 may have a circular shape in a plan view. The column regions 48 may have a columnar shape extending in the Z-axis direction. The column regions 48 may be provided adjacent to corners of a body region 32 that has a rectangular shape in a plan view. The column regions 48 may be arranged side by side with the body region 32 in at least one of the X-axis direction and the Y-axis direction.

[0081] 23, a modified semiconductor device 130 may include multiple collector regions 54 arranged at intervals in the X-axis direction and the Y-axis direction. The multiple collector regions 54 may have a rectangular shape in a plan view. The multiple collector regions 54 may have any shape in a plan view, such as a circular shape, a polygonal shape, or the like.

[0082] As in a semiconductor device 140 of a modified example shown in FIG. 24, the arrangement direction of the plurality of collector regions 54 may be arranged in a direction forming a predetermined angle with respect to the X-axis direction and the Y-axis direction.

[0083] As shown in FIG. 25 , a semiconductor device 150 of the modified example may include a semiconductor layer 200. The semiconductor layer 200 includes a configuration similar to that of the semiconductor layer 30 of the above embodiment. The semiconductor layer 200 may include a first surface 200A and a second surface 200B opposite to the first surface 200A. The first surface 200A of the semiconductor layer 200 corresponds to the surface 30A of the semiconductor layer 30, and the second surface 200B of the semiconductor layer 200 corresponds to the surface 30B of the semiconductor layer 30. The semiconductor layer 200 may include a semiconductor substrate 210 and a semiconductor layer 220 on the semiconductor substrate 210. The lower surface 210B of the semiconductor substrate 210 constitutes the second surface 200B of the semiconductor layer 200. The collector region 54 and the contact region 52 may be provided in the semiconductor substrate 210. The semiconductor device 150 can be said to include a collector region 54 and a contact region 52 disposed in a semiconductor substrate 210 .

[0084] The term "on" as used in this disclosure includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0085] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (for example, the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0086] The phrase "at least one" as used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" as used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0087] (Addendum) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0088] (Appendix 1) a semiconductor layer (30, 200) of a first conductivity type including a first surface (30A) and a second surface (30B) opposite to the first surface (30A); a plurality of body regions (32) of a second conductivity type provided on the first surface (30A) and spaced apart in a first direction (X); a first conductivity type source region (34) provided in the body region (32) and arranged at a position away from an end face of the body region (32) in the first direction (X); a channel region (36) between the end face of the body region (32) and the source region (34); a gate electrode (42) provided above the channel region (36) and facing the channel region (36) via a gate insulating film (40); a collector region (54) of a second conductivity type provided on the second surface (30B); a column region (48) of a second conductivity type provided in the semiconductor layer (30) at a position separated from the body region (32); Including, the first surface (30A) of the semiconductor layer (30) includes an inter-element region (46) that is a region between the plurality of body regions (32); The column region (48) is the inter-element region (46) when viewed in a thickness direction (Z) of the semiconductor layer (30), and is disposed closer to the second surface (30B) than the body region (32). Semiconductor device.

[0089] (Appendix 2) The column region (48) extends in a second direction (Y) intersecting the first direction (X) when viewed from the thickness direction (Z). 2. The semiconductor device according to claim 1.

[0090] (Appendix 3) The collector region (54) extends in the first direction (X) when viewed from the thickness direction (Z). 10. The semiconductor device according to claim 1 or 2.

[0091] (Appendix 4) The collector region (54) extends in a second direction (Y) when viewed from the thickness direction (Z). 10. The semiconductor device according to claim 1 or 2.

[0092] (Appendix 5) The collector region (54) has a polygonal or circular shape when viewed from the thickness direction (Z). 10. The semiconductor device according to claim 1 or 2.

[0093] (Appendix 6) the gate electrode (42) overlaps the inter-element region (46) when viewed from the thickness direction (Z) and is disposed across the body regions (32) adjacent to each other in the first direction (X); When viewed from the thickness direction (Z), the column region (48) is disposed at a position overlapping the gate electrode (42). 6. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0094] (Appendix 7) a contact region (52) disposed between the collector regions (54); 7. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0095] (Appendix 8) In a direction in which the collector region (54) and the contact region (52) are arranged, a length (L13) of the collector region (54) is greater than a length (L14) of the contact region (52). 8. The semiconductor device according to claim 7.

[0096] (Appendix 9) The collector region (54) overlaps with the column region (48) when viewed from the thickness direction (Z). 9. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0097] (Appendix 10) When viewed from the thickness direction (Z), the collector region (54) is disposed across two of the column regions (48) adjacent to each other in the first direction (X). 10. The semiconductor device according to claim 1.

[0098] (Appendix 11) The occupancy rate of the collector region (54) is 80% or more and 90% or less. 11. The semiconductor device according to claim 1.

[0099] (Appendix 12) a distance (D22) between the body region (32) and the column region (48) in the thickness direction (Z) is smaller than a distance (D21) from the first surface (30A) to a bottom surface (48A) of the body region (32) in the thickness direction (Z); 12. The semiconductor device according to claim 1.

[0100] (Appendix 13) a distance (D22) between the body region (32) and the column region (48) in the thickness direction (Z) is equal to a distance (D21) from the first surface (30A) to a bottom surface (48A) of the body region (32) in the thickness direction (Z); 13. The semiconductor device according to claim 1.

[0101] (Appendix 14) a distance between the body region (32) and the column region (48) in the thickness direction (Z) is greater than a distance (D21) from the first surface (30A) to a bottom surface (48A) of the body region (32) in the thickness direction (Z); 14. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer.

[0102] (Appendix 15) a length (L11) of the column region (48) in the first direction (X) is shorter than a length (L12) of a drift region between two adjacent column regions (48) in the first direction (X); 15. The semiconductor device according to any one of claims 1 to 14.

[0103] (Appendix 16) In the thickness direction (Z), a distance (D12) from the second surface (30B) to the column region (48) is greater than a distance (D11) from the first surface (30A) to the column region (48). 16. The semiconductor device according to any one of claims 1 to 15.

[0104] (Appendix 17) the first conductivity type is n-type, The second conductivity type is p-type. 17. The semiconductor device according to any one of claims 1 to 16.

[0105] (Appendix 18) The semiconductor layer (200) includes a semiconductor substrate (210) including a lower surface (210B) that constitutes the second surface (200B), the collector region (54) is disposed in the semiconductor substrate (210); 18. The semiconductor device according to any one of claims 1 to 17.

[0106] (Appendix 19) a source electrode connected to the source region (34); a drain electrode disposed on the second surface (30B); Including, 19. The semiconductor device according to any one of claims 1 to 18.

[0107] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0108] 10 Semiconductor devices 11 Page 1 12 Side 2 13~16 Side 20 Passivation Layer 20A 1st pad opening 20A Pad Opening 20B Second pad opening 20B Pad Opening 22 Electrode membrane 24 Source electrode film 24A Recess 24B Source contact part 26 Gate electrode film 26A Pad section 26B Finger part 28 Drain electrode 30 Semiconductor layer 30A 1st side 30B 2nd side 32 Body Region 32A end face 32B Bottom 34 Source Region 36 channel region 38 Channel contact region 40 Gate insulating film 42 gate electrode 44 insulating film 44A contact hole 46 Inter-element region 48 Column Area 48A Top 48B Bottom 48C center 48D side 50 Drift Region 52 Contact Area 54 Collector Region 100 Semiconductor device 110 Semiconductor device 120 Semiconductor device 130 Semiconductor devices 140 Semiconductor devices 150 Semiconductor devices 200 Semiconductor layer 200A 1st page 200B 2nd side 210 Semiconductor substrate 210B Bottom 220 Semiconductor layer D11,D12 distance D21,D22 distance L11 First length L12 Second length L13 Third length L14 4th length

Claims

1. a semiconductor layer of a first conductivity type including a first surface and a second surface opposite to the first surface; a plurality of body regions of a second conductivity type provided in the first surface and spaced apart in a first direction; a first conductivity type source region provided in the body region and arranged at a position away from an end face of the body region in the first direction; a channel region between the end face of the body region and the source region; a gate electrode provided above the channel region and facing the channel region via a gate insulating film; a collector region of a second conductivity type provided on the second surface; a column region of a second conductivity type provided in the semiconductor layer at a position separated from the body region; Including, the first surface of the semiconductor layer includes an inter-element region that is a region between the plurality of body regions, the column region is the inter-element region when viewed in a thickness direction of the semiconductor layer, and is disposed closer to the second surface than the body region. Semiconductor device.

2. the column region extends in a second direction intersecting the first direction when viewed from the thickness direction; The semiconductor device according to claim 1 .

3. the collector region extends in the first direction when viewed in the thickness direction.

3. The semiconductor device according to claim 1.

4. the collector region extends in a second direction when viewed from the thickness direction.

3. The semiconductor device according to claim 1.

5. The collector region has a polygonal or circular shape when viewed from the thickness direction.

3. The semiconductor device according to claim 1.

6. the gate electrode overlaps the inter-element region when viewed in the thickness direction and is disposed across the body regions adjacent to each other in the first direction; When viewed from the thickness direction, the column region is disposed at a position overlapping the gate electrode. The semiconductor device according to claim 1 .

7. a contact region disposed between the collector regions; The semiconductor device according to claim 1 .

8. In a direction in which the collector region and the contact region are arranged, the width of the collector region is larger than the width of the contact region. The semiconductor device according to claim 7 .

9. the collector region overlaps with the column region when viewed in the thickness direction. The semiconductor device according to claim 1 .

10. When viewed from the thickness direction, the collector region is disposed across two of the column regions adjacent to each other in the first direction. The semiconductor device according to claim 1 .

11. the occupancy rate of the collector region is 80% or more and 90% or less; The semiconductor device according to claim 1 .

12. a distance between the body region and the column region in the thickness direction is smaller than a distance from the first surface to a bottom surface of the body region in the thickness direction; The semiconductor device according to claim 1 .

13. a distance between the body region and the column region in the thickness direction is equal to a distance from the first surface to a bottom surface of the body region in the thickness direction; The semiconductor device according to claim 1 .

14. a distance between the body region and the column region in the thickness direction is greater than a distance from the first surface to a bottom surface of the body region in the thickness direction; The semiconductor device according to claim 1 .

15. a width of the column region in the first direction is smaller than a width of a drift region between two adjacent column regions in the first direction; The semiconductor device according to claim 1 .

16. a distance from the second surface to the column region in the thickness direction is greater than a distance from the first surface to the column region; The semiconductor device according to claim 1 .

17. the first conductivity type is n-type, the second conductivity type is p-type; The semiconductor device according to claim 1 .

18. the semiconductor layer includes a semiconductor substrate including a lower surface that constitutes the second surface, the collector region is disposed in the semiconductor substrate; The semiconductor device according to claim 1 .

19. a source electrode connected to the source region; a drain electrode disposed on the second surface; Including, The semiconductor device according to claim 1 .

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