Synchronization device, synchronization system, synchronization method, and program

Abstract

To provide a synchronization device, a synchronization system, a synchronization method, and a program capable of maintaining synchronization accuracy regardless of a load condition of a network or a computer by reducing computational resources occupied or power consumption.SOLUTION: A synchronization device includes a synchronization information reception part, a downlink delay calculation part, a synchronization request transmission part, an uplink delay calculation part, an uplink delay storage part, an uplink delay selection part, a phase difference calculation part, a phase error correction part, and a synchronization state determination part. The uplink delay storage part stores the uplink delay output by the uplink delay calculation part. The uplink delay selection part selects and outputs the output of the uplink delay calculation part or the output of the uplink delay storage part. The phase difference calculation part calculates a phase difference between a synchronization signal source and a client clock based on a down delay and the output of the up delay selection part. The state determination part outputs a synchronization state between the synchronization signal source and the client clock based on the phase difference.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a synchronization device, a synchronization system, a synchronization method, and a program. [Background technology]

[0002] According to Patent Document 1, in a frequency / time synchronization method between devices connected via a packet network, a higher-level device transmits a signal containing frequency information synchronized with a standard frequency and a time synchronization packet containing time information synchronized with a standard time superimposed on the signal. A lower-level device receiving the signal extracts the frequency information and uses it to count up the time in its own device, and sets the time in its own device using the time information in the time synchronization packet. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-034157 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, a method has been proposed to reduce capital and operational costs by using general-purpose computer products instead of dedicated hardware for the Distributed Unit (DU), which controls the Radio Unit (RU) among the devices that make up a 5G (5th Generation) mobile base station.

[0005] To make effective use of radio wave resources, DUs are required to synchronize with neighboring base stations. The synchronization accuracy should be, for example, + / - 1.5 μsec. To meet this requirement, a technology is used to receive synchronization signals broadcast from GNSS (Global Navigation Satellite System) satellites using a GNSS receiver and generate a synchronization signal to synchronize the device's timing with TAI (French Temps Atomique International) or UTC (Universal Time, Coordinated).

[0006] However, depending on the location of the DU device, it may be difficult to receive GNSS signals directly. Therefore, as a method of transmitting synchronization signals to devices in remote locations, the Precision Time Protocol (PTP) method has been proposed, in which synchronization signals are distributed from a GNSS receiving device over a packet network and received and used by the remote device.

[0007] However, when implementing a DU device using a general-purpose computer product instead of dedicated hardware, PTP processing, which must be performed continuously at regular intervals, is partially implemented by software running on the computer. This requirement requires a certain amount of computer computing resources to be allocated to PTP processing, such as a dedicated CPU (Central Processing Unit) core, which reduces the computing resources available for other processes.

[0008] In view of the above-mentioned problems, the object of the present disclosure is to provide a synchronization device, a synchronization system, a synchronization method, and a program that can reduce the computational resources occupied and the power consumption, and maintain synchronization accuracy regardless of the load status of the network or computer. [Means for solving the problem]

[0009] A synchronization device according to the present disclosure includes a synchronization information receiving unit, a downstream delay calculation unit, a synchronization request transmitting unit, an upstream delay calculation unit, an upstream delay storage unit, an upstream delay selection unit, a phase difference calculation unit, a phase error correction unit, and a synchronization state determination unit. The synchronization information receiving unit generates a reception time of downstream phase synchronization information received from a synchronization signal source via a transmission path based on the time of a client clock. The downstream delay calculation unit calculates a downstream delay of the downstream phase synchronization information on the transmission path based on the reception time and the downstream phase synchronization information. The synchronization request transmitting unit generates a transmission time of an upstream phase synchronization request transmitted to the synchronization signal source based on the time of the client clock. The upstream delay calculation unit receives an upstream phase synchronization response, which is a response to the upstream phase synchronization request, from the synchronization signal source via the transmission path, and calculates an upstream delay on the transmission path based on the upstream phase synchronization response and the transmission time. The upstream delay storage unit stores the upstream delay output by the upstream delay calculation unit. The upstream delay selection unit selects and outputs the output of the upstream delay calculation unit or the output of the upstream delay storage unit. The phase difference calculation unit calculates the phase difference between the synchronization signal source and the client clock based on the downstream delay and the output of the upstream delay selection unit. The phase error correction unit generates a phase control value based on the phase difference and corrects the output phase of the client clock based on the phase control value. The state determination unit outputs the synchronization state between the synchronization signal source and the client clock based on the phase difference.

[0010] A synchronization system according to the present disclosure includes a server device serving as a synchronization signal source and a client device. The server device includes a synchronization signal transmission unit that transmits a synchronization signal to the client device. The client device includes a synchronization information receiving unit, a downstream delay calculation unit, a synchronization request transmitting unit, an upstream delay calculation unit, an upstream delay storage unit, an upstream delay selection unit, a phase difference calculation unit, a phase error correction unit, and a synchronization state determination unit. The receiving unit generates a reception time of downstream phase synchronization information received from the synchronization signal source via a transmission path based on the time of a client clock. The downstream delay calculation unit calculates a downstream delay of the downstream phase synchronization information on the transmission path based on the reception time and the downstream phase synchronization information. The synchronization request transmitting unit generates a transmission time of an upstream phase synchronization request transmitted to the synchronization signal source based on the time of the client clock. The upstream delay calculation unit receives an upstream phase synchronization response, which is a response to the upstream phase synchronization request, from the synchronization signal source via the transmission path, and calculates an upstream delay on the transmission path based on the upstream phase synchronization response and the transmission time. The upstream delay memory unit stores the upstream delay output by the upstream delay calculation unit. The upstream delay selection unit selects and outputs the output of the upstream delay calculation unit or the output of the upstream delay memory unit. The phase difference calculation unit calculates the phase difference between the synchronization signal source and the client clock based on the downstream delay and the output of the upstream delay selection unit. The phase error correction unit generates a phase control value based on the phase difference and corrects the output phase of the client clock based on the phase control value. The state determination unit outputs the synchronization state between the synchronization signal source and the client clock based on the phase difference.

[0011] In the synchronization method according to the present disclosure, a computer executes the following steps: a synchronization information receiving step, a downstream delay calculation step, a synchronization request transmitting step, an upstream delay calculation step, an upstream delay storage step, an upstream delay selection step, a phase difference calculation step, a phase error correction step, and a synchronization state determination step. In the synchronization information receiving step, a reception time of downstream phase synchronization information received from a synchronization signal source via a transmission path is generated based on the time of a client clock. In the downstream delay calculation step, a downstream delay of the downstream phase synchronization information on the transmission path is calculated based on the reception time and the downstream phase synchronization information. In the synchronization request transmitting step, a transmission time of an upstream phase synchronization request transmitted to the synchronization signal source is generated based on the time of the client clock. In the upstream delay calculation step, an upstream phase synchronization response, which is a response to the upstream phase synchronization request, is received from the synchronization signal source via the transmission path, and an upstream delay on the transmission path is calculated based on the upstream phase synchronization response and the transmission time. In the upstream delay storage step, the upstream delay output in the upstream delay calculation step is stored. In the upstream delay selection step, the upstream delay output in the upstream delay calculation step or the upstream delay storage step is selected and output. In the phase difference calculation step, the phase difference between the synchronization signal source and the client clock is calculated based on the downstream delay and the upstream delay output in the upstream delay selection step. In the phase error correction step, a phase control value is generated based on the phase difference, and the output phase of the client clock is corrected based on the phase control value. In the synchronization state determination step, the synchronization state between the synchronization signal source and the client clock is output based on the phase difference.

[0012] A program according to the present disclosure causes a computer to execute a synchronization information reception procedure, a downstream delay calculation procedure, a synchronization request transmission procedure, an upstream delay calculation procedure, a phase difference calculation procedure, a phase error correction procedure, and a synchronization state determination procedure. In the synchronization information reception procedure, a reception time of downstream phase synchronization information received from a synchronization signal source via a transmission path is generated based on the time of a client clock. In the downstream delay calculation procedure, a downstream delay of the downstream phase synchronization information on the transmission path is calculated based on the reception time and the downstream phase synchronization information. In the synchronization request transmission procedure, a transmission time of an upstream phase synchronization request transmitted to the synchronization signal source is generated based on the time of the client clock. In the upstream delay calculation procedure, an upstream phase synchronization response, which is a response to the upstream phase synchronization request, is received from the synchronization signal source via the transmission path, and an upstream delay on the transmission path is calculated based on the upstream phase synchronization response and the transmission time. In the upstream delay storage procedure, the upstream delay output in the upstream delay calculation procedure is stored. In the upstream delay selection procedure, the upstream delay output in the upstream delay calculation procedure or the upstream delay storage procedure is selected and output. The phase difference calculation procedure calculates the phase difference between the synchronization signal source and the client clock based on the downstream delay and the upstream delay output in the upstream delay selection procedure. The phase error correction procedure generates a phase control value based on the phase difference and corrects the output phase of the client clock based on the phase control value. The synchronization state determination procedure outputs the synchronization state between the synchronization signal source and the client clock based on the phase difference. [Effects of the Invention]

[0013] According to the present disclosure, it is possible to provide a synchronization device, a synchronization system, a synchronization method, and a program that reduce the computational resources occupied and the power consumption, and maintain synchronization accuracy regardless of the load status of the network or computer. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a block diagram of a synchronization system according to the present disclosure. [Figure 2] 1 is a configuration diagram of a synchronization system according to the present disclosure. [Figure 3] FIG. 1 is a configuration diagram of a synchronization system according to a comparative example. [Figure 4] 1 is a flowchart of a synchronization device according to the present disclosure. [Figure 5] 1 is a flowchart of a synchronization device according to the present disclosure. [Figure 6] FIG. 1 illustrates a message flow according to the present disclosure. [Figure 7] 10A and 10B are diagrams illustrating a method for determining a synchronization state of a synchronization device according to the present disclosure. [Figure 8] FIG. 10 is a configuration diagram of a multi-client operation according to a comparative example. [Figure 9] FIG. 1 is a configuration diagram of a multi-client operation according to the present disclosure. [Figure 10] FIG. 2 is a block diagram illustrating an example of a hardware configuration of a computer. DETAILED DESCRIPTION OF THE INVENTION

[0015] The present disclosure will be described below through embodiments, but the disclosure according to the claims is not limited to the following embodiments. Furthermore, not all of the configurations described in the embodiments are necessarily essential as means for solving the problems. For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. In each drawing, the same elements are denoted by the same reference numerals, and repeated explanations are omitted as necessary.

[0016] First, one of the simplest forms of time synchronization is a method in which a time reference device synchronized with a GNSS (Global Navigation Satellite System) or the like transmits a timestamp to a device installed at a remote location, and the device corrects the time using the received timestamp. However, this method has the problem of reducing the accuracy of time synchronization because it does not take into account the time it takes for the timestamp transmitted from the time reference device to reach the device installed at the remote location, i.e., the propagation delay on the transmission path.

[0017] Therefore, PTP (Precision Time Protocol) has been proposed as a method that enables time synchronization that takes propagation delay into account.In the following explanation, a device that synchronizes with GNSS or the like and serves as a time reference will be referred to as a server device, and a device installed in a remote location that performs time synchronization processing based on time synchronization information distributed from the server device will be referred to as a client device.

[0018] When defining PTP specifications, the terms "master" and "slave" are sometimes used as equivalents to "server" and "client," respectively. However, there is criticism among those skilled in the art that "master" and "slave" are discriminatory terms depending on the context, and in recent years there has been a movement to replace them with inclusive language, that is, a movement to replace them with more neutral and comprehensive terms. For this reason, the following explanations will replace "master" with "server" and "slave" with "client."

[0019] In PTP time synchronization, a server device, which is the synchronization signal source, sends a Sync message, which is downstream phase synchronization information, to a client device, which is the synchronization device. The client device then sends a Delay_Req (delay measurement request) message, which is an upstream phase synchronization request, to the server device in response to the Sync message. The server device then sends a Delay_Resp (delay measurement response) message, which is an upstream phase synchronization response, to the client device in response to the Delay_Req message. The client device measures the propagation delay of the transmission path from the timestamps included in these messages and the timestamp measured by the client device's clock (client clock) when the message was received. The client device achieves highly accurate time synchronization by offsetting the effects of the propagation delay of the transmission path when correcting the time.

[0020] The above method for measuring propagation delay is defined as the E2E (End-to-End) method in PTP. PTP also defines a P2P (Peer-to-Peer) method for measuring propagation delay, but the following explanation assumes the E2E method.

[0021] In PTP, the time synchronization process is repeated at regular intervals. This is because the clock of the client device is generally not frequency-synchronized with the clock of the server device, and so performing time synchronization once will result in the time deviation between the two devices over time. As an example, the ITU-T (International Telecommunication Union Telecommunication Standardization Sector) recommendation G.8275.1 profile, which is used in the operation of 5G base stations, specifies a time synchronization frequency of 16 times per second. The time synchronization frequency refers to the frequency at which the unit process is repeated, which is completed by sending and receiving Sync, Delay_Req, and Delay_Resp messages between the server device and the client device and performing the time synchronization process on the client device.

[0022] Therefore, when a synchronization signal is transmitted over a network using PTP, depending on the network load, the packet containing the synchronization signal may compete with other packets, causing fluctuations in the time at which the packet arrives at a device installed in a remote location, degrading synchronization accuracy.

[0023] Furthermore, when DU devices are implemented using general-purpose computers instead of dedicated hardware, PTP processing, which must be performed continuously at regular intervals, is partially implemented by software running on the computer. This requirement requires that a certain amount of computer computing resources be allocated to PTP processing, such as a dedicated CPU core, which reduces the computing resources available for other processes.

[0024] Furthermore, due to the same requirement, the CPU that performs PTP processing cannot enter a sleep state, which prevents the reduction of computer power consumption.

[0025] Furthermore, even if a specific CPU core is dedicated to PTP processing, in a general-purpose computer, resources such as the data bus cannot be separated from other processes running on the DU device, which causes the PTP processing to temporarily stop, resulting in a deterioration in synchronization accuracy.

[0026] The time synchronization system according to the present disclosure will be described below.

[0027] 1 is a block diagram of a synchronization system 1 according to the present disclosure. The synchronization system 1 mainly comprises a synchronization signal source 10, a transmission path 20, and a synchronization device 30. The synchronization signal source 10 and the synchronization device 30 are connected via the transmission path 20. The synchronization system 1 is used when the synchronization device 30 performs time synchronization with the synchronization signal source 10, which is connected via the transmission path 20, as a synchronization target.

[0028] The synchronization signal source 10 transmits downstream phase synchronization information to the synchronization device 30 via the transmission path 20. The synchronization signal source 10 receives an upstream phase synchronization request from the synchronization device 30 via the transmission path 20, and returns an upstream phase synchronization response.

[0029] The downstream phase synchronization information is transmitted from the synchronization signal source 10 in order to measure the downstream delay that occurs when a signal propagates from the synchronization signal source 10 to the synchronization device 30 via the transmission path 20. The downstream phase synchronization information includes the transmission time of the downstream phase synchronization information based on the server clock, which is the clock of the synchronization signal source 10.

[0030] The upstream phase synchronization request is transmitted from the synchronization device 30 in order to measure the upstream delay that occurs when a signal propagates from the synchronization device 30 to the synchronization signal source 10 via the transmission path 20. The upstream phase synchronization response is transmitted from the synchronization signal source 10 in response to the upstream phase synchronization request. The upstream phase synchronization response includes the time of reception of the upstream phase synchronization request based on the server clock of the synchronization signal source 10.

[0031] The transmission path 20 connects the synchronization signal source 10 and the synchronization device 30. The transmission path 20 is an information communication path formed by wire or wirelessly.

[0032] The synchronization device 30 includes a synchronization information receiving unit 31, a downstream delay calculation unit 32, a synchronization request transmitting unit 33, an upstream delay calculation unit 34, an upstream delay memory unit 35, an upstream delay selection unit 36, a phase difference calculation unit 37, a phase error correction unit 38, and a synchronization state determination unit 39.

[0033] The synchronization information receiver 31 generates the reception time of the downstream phase synchronization information received from the synchronization signal source 10 via the transmission path 20 based on the time of the client clock, which is the clock of the synchronization device 30. The synchronization information receiver 31 outputs the generated reception time to the downstream delay calculator 32.

[0034] The downstream delay calculation unit 32 calculates the downstream delay of the downstream phase synchronization information on the transmission path 20 based on the reception time of the downstream phase synchronization information input from the synchronization information reception unit 31 and the transmission time included in the downstream phase synchronization information.

[0035] The synchronization request transmitter 33 transmits an upstream phase synchronization request to the synchronization signal source 10 and generates a transmission time based on the time of the client clock of the synchronization device 30. The synchronization request transmitter 33 outputs the generated transmission time to the upstream delay calculator 34.

[0036] The upstream delay calculation unit 34 receives an upstream phase synchronization response from the synchronization information receiving unit 31, which has received the response from the synchronization signal source 10 via the transmission path 20. The upstream delay calculation unit 34 also receives a transmission time of the upstream phase synchronization request from the synchronization request transmitting unit 33. The upstream delay calculation unit 34 calculates the upstream delay on the transmission path 20 based on the reception time of the upstream phase synchronization request at the synchronization signal source 10, which are included in the upstream phase synchronization response, and the transmission time of the upstream phase synchronization request. The upstream delay calculation unit 34 also outputs the calculated upstream delay to the upstream delay storage unit 35 and the upstream delay selecting unit 36.

[0037] The upstream delay memory unit 35 stores the upstream delay output by the upstream delay calculation unit 34. The upstream delay memory unit 35 also outputs the stored upstream delay to the upstream delay selection unit 36. The upstream delay selection unit 36 ​​selects the output of the upstream delay calculation unit 34 or the output of the upstream delay memory unit 35 and outputs it to the phase difference calculation unit 37.

[0038] The phase difference calculation unit 37 calculates the phase difference between the server clock of the synchronization signal source 10 and the client clock of the synchronization device 30 based on the output of the downstream delay and upstream delay selection unit 36 ​​.

[0039] The phase error correction unit 38 generates a phase control value based on the phase difference calculated by the phase difference calculation unit 37, and corrects the output phase of the client clock based on the phase control value. The synchronization state determination unit 39 outputs the synchronization state between the server clock of the synchronization signal source 10 and the client clock of the synchronization device 30 based on the phase difference calculated by the phase difference calculation unit 37.

[0040] <First Embodiment> 2 is a configuration diagram of a synchronization system 1 according to the present disclosure. The synchronization system 1 includes a server device 100, a transmission path 20, and a client device 300. The server device 100 functions as the synchronization signal source 10 in FIG. 1. The client device 300 functions as the synchronization device 30 in FIG. 1.

[0041] The server device 100 includes a server clock 101, a server control unit 102, a server packet transmission unit 103, a server data modulation unit 104, a server data demodulation unit 105, and a server packet reception unit 106. The server device 100 is also connected to a time reference source 2 such as a GNSS reception device.

[0042] The server clock 101 controls its own time so that it matches the time of the time reference source 2. The server clock 101 is generally realized by combining a high-precision oscillator such as an OCXO (Oven-Controlled Crystal Oscillator) with a DPLL (Digital Phase Locked Loop) circuit.

[0043] Server control unit 102 generates a Sync message at regular time intervals and transmits it to server packet transmitting unit 103. When server control unit 102 receives a Delay_Req message from server packet receiving unit 106, it also receives the reception time t4 of the Delay_Req message from server packet receiving unit 106. Server control unit 102 generates a Delay_Resp message in which reception time t4 is embedded and transmits it to server packet transmitting unit 103. Embedding a time in a message is sometimes referred to as "stamping." The Delay_Req message will be described in detail later.

[0044] Server packet transmitter 103 receives a Sync message from server control unit 102. Server packet transmitter 103 embeds transmission time t1 in the Sync message by referring to the time of server clock 101. Server packet transmitter 103 outputs the Sync message to server data modulator 104. Server packet transmitter 103 also receives a Delay_Resp message from server control unit 102 and outputs it to server data modulator 104. Server data modulator 104 transmits the received information to client device 300 via transmission path 20.

[0045] In one form of PTP implementation, a timestamp is not embedded in the Sync message itself, but the time (t1) at which the Sync message is sent is embedded when a message called Follow_Up is subsequently sent. This is known as a two-step timestamp technique. On the other hand, when t1 is embedded in the Sync message itself, it is known as a one-step timestamp technique. Both the one-step timestamp technique and the two-step timestamp technique have in common that t1 is sent from the server device 100 to the client device 300. Since the outline of the operation is the same, the following explanation will be given assuming that the one-step timestamp technique is used.

[0046] The server data demodulation unit 105 receives the Delay_Req message from the transmission path 20 and outputs it to the server packet reception unit 106. The server packet reception unit 106 receives the Delay_Req message from the server data demodulation unit 105. The server packet reception unit 106 measures the reception time t4 of the Delay_Req message by referring to the server clock 101 and transmits it to the server control unit 102. The Delay_Req message will be described in detail later.

[0047] The server device 100 may also include a frequency synchronization information generating unit 107. The frequency synchronization information generating unit 107 is, for example, a PLL (Phase Locked Loop) circuit, and outputs a clock to the server data modulating unit 104. The frequency synchronization information generating unit 107 transmits frequency synchronization information to the client device 300 via the server data modulating unit 104. The frequency synchronization information generating unit 107 is an element for configuring SyncE (Synchronous Ethernet), which is a technology for performing frequency synchronization between network nodes via Ethernet (registered trademark), which is a type of packet network. In this case, the server data modulating unit 104 has a function of performing data modulation using the clock output by the frequency synchronization information generating unit 107.

[0048] The transmission path 20 transmits information from the server device 100 to the client device 300 and information from the client device 300 to the server device 100 .

[0049] The client device 300 is, for example, a computer. The client device 300 is also called a slave device. The client device 300 mainly includes a client packet receiving unit 302, a downstream delay calculation unit 32, a client packet transmitting unit 304, an upstream delay calculation unit 34, an upstream delay storage unit 35, an upstream delay selection unit 36, a phase difference calculation unit 37, a phase error correction unit 38, and a phase error determination unit 306. The client device 300 according to this embodiment further includes a client data demodulation unit 301, a client control unit 303, a client data modulation unit 305, and a client clock 307.

[0050] The client data demodulation unit 301 demodulates data from information received from the server device 100 via the transmission path 20. Here, the information received by the client data demodulation unit 301 is, for example, an electrical signal. More specifically, the information received by the client data demodulation unit 301 may be the received waveform of a signal. Then, the client data demodulation unit 301 receives a Sync message or a Delay_Resp message and outputs it to the client packet receiving unit 302.

[0051] 1. The client packet receiver 302 receives a Sync message from the client data demodulator 301. Furthermore, the client packet receiver 302 outputs the Sync message to the client control unit 303. The client packet receiver 302 also extracts time t1 included in the Sync message and outputs it to the downlink delay calculator 32. Furthermore, when the client packet receiver 302 receives the Sync message, it generates reception time t2 of the Sync message based on the time of the client clock 307 and outputs it to the downlink delay calculator 32. Furthermore, when the client packet receiver 302 receives a Delay_Resp message from the client data demodulator 301, it extracts time t4 included in the Delay_Resp message and outputs it to the uplink delay calculator 34.

[0052] The downstream delay calculation unit 32 calculates the downstream delay tsc based on the reception time t2 of the Sync message, which is downstream phase synchronization information, and the time t1 extracted from the Sync message. The downstream delay tsc is the time required for the Sync message to arrive at the client device 300 from the server device 100 on the transmission path 20.

[0053] When the client control unit 303 receives the Sync message, it outputs a Delay_Req message to the client data modulation unit 305 via the client packet transmission unit 304 .

[0054] 1. Client packet transmitting unit 304 transmits a Delay_Req message to server device 100. Furthermore, client packet transmitting unit 304 generates transmission time t3 of the Delay_Req message based on the time of client clock 307, and outputs the generated time t3 to upstream delay calculating unit 34.

[0055] The upstream delay calculation unit 34 receives a Delay_Resp message, which is a response to the Delay_Req message, from the server device 100 via the transmission path 20. Furthermore, the upstream delay calculation unit 34 calculates the upstream delay tcs on the transmission path 20 based on the time t4 included in the Delay_Resp message and the transmission time t3 of the Delay_Req message. The upstream delay tcs is the time required for the Delay_Req message to arrive at the server device 100 from the client device 300 via the transmission path 20.

[0056] The upstream delay storage unit 35 retains the previous stored content when the server device 100 and the client device 300 are synchronized. When they are asynchronous, the upstream delay storage unit 35 updates the stored content to the upstream delay tcs output by the upstream delay calculation unit 34. In detail, the upstream delay storage unit 35 receives the upstream delay tcs output by the upstream delay calculation unit 34 as an input. When the synchronization flag 311 output by the phase error determination unit 306 is False, the input tcs is stored as the upstream delay memory tcs_mem. When the synchronization flag 311 is True, the previous upstream delay memory tcs_mem is stored as is. The phase error determination unit 306 and the synchronization flag 311 will be described in detail later.

[0057] The upstream delay selection unit 36 ​​has as inputs the upstream delay tcs output by the upstream delay calculation unit 34 and the upstream delay memory tcs_mem output by the upstream delay memory unit 35. Furthermore, the upstream delay selection unit 36 ​​selects the upstream delay tcs when the synchronization flag 311 is False, and selects the upstream delay memory tcs_mem when the synchronization flag 311 is True, and outputs it as the post-switching upstream delay tcs_sel.

[0058] The phase difference calculation unit 37 receives as input the downstream delay tsc output by the downstream delay calculation unit 32 and the post-switching upstream delay tcs_sel output by the upstream delay selection unit 36, and calculates the phase difference te between the server clock 101 and the client clock 307. The phase difference calculation unit 37 outputs the calculated phase difference te to the phase error correction unit 38 and the phase error determination unit 306.

[0059] According to this, the client device 300 has a means for storing the upstream delay measured by transmitting and receiving PTP messages, and a means for using the stored upstream delay to calculate the downstream and upstream delays of the transmission path 20. Therefore, since it is possible to calculate the downstream and upstream delays of the transmission path 20 using the upstream delay measured in the past by transmitting and receiving PTP messages, it is not necessary to transmit multicast packets related to the upstream delay measurement, and it is possible to reduce the network load.

[0060] The phase error correction unit 38 receives the phase difference te as an input, generates a phase control value, and corrects the output phase of the client clock 307 based on the phase control value.

[0061] Phase error determination unit 306 functions as synchronization state determination unit 39 in FIG. 1. Phase error determination unit 306 outputs the synchronization state between server clock 101 and client clock 307 based on phase difference te. In this embodiment, client device 300 can be in two states: an "asynchronous state" and a "synchronous state." This state is managed by synchronization flag 311 shown in FIG. 2, and when synchronization flag 311 is set to False, it corresponds to the asynchronous state, and when synchronization flag 311 is set to True, it corresponds to the synchronous state. Note that the initial state of client device 300 before synchronization control starts is the asynchronous state.

[0062] In this embodiment, the client device 300 may include a clock generating unit 308. The clock generating unit 308 is, for example, a PLL circuit, and generates a frequency-synchronized clock based on frequency synchronization information. In this case, the client data demodulating unit 301 has a function of extracting a clock from a received data waveform. The client clock 307 may operate using the frequency-synchronized clock generated by the clock generating unit 308. The elements within the dashed line in FIG. 2 constitute SyncE between the server device 100 and the client device 300. Specifically, the server clock 101, the frequency synchronization information generating unit 107, the server data modulating unit 104, the client data demodulating unit 301, the clock generating unit 308, and the client clock 307 constitute SyncE. This allows the client device 300 to operate in frequency synchronization with the server device 100.

[0063] When configuring SyncE, the frequency synchronization information generating unit 107 in the server device 100 generates a transmission clock by multiplying the clock output by the server clock 101. The server data modulating unit 104 uses this transmission clock to modulate the data received from the server packet transmitting unit 103, and transmits the data to the client device 300 via the transmission path 20.

[0064] On the client device 300 side, a client data demodulation unit 301 demodulates the received data and outputs it to a client packet reception unit 302, and also outputs a demodulation clock extracted from the waveform of the received data to a clock generation unit 308. The clock generation unit 308 divides the demodulation clock and outputs the divided clock to a client clock 307. The client clock 307 operates based on the divided clock.

[0065] Here, the demodulation clock is a clock extracted from a data waveform modulated with the transmission clock generated by the frequency synchronization information generator 107 in the server device 100, so the two clocks are frequency-synchronized. As a result, the server clock 101 before the transmission clock is multiplied by the frequency synchronization information generator 107 and the client clock 307, which operates using the frequency-divided clock output by the clock generator 308, are also frequency-synchronized. In this way, the essence of SyncE is that the data receiving device generates a clock that is frequency-synchronized with the clock used for data transmission by the data transmitting device.

[0066] Note that SyncE frequency synchronization is controlled independently of PTP, and SyncE and PTP can operate simultaneously in parallel. SyncE is primarily implemented in hardware, so it does not require the use of computer resources like PTP.

[0067] 3 is a configuration diagram of a comparative example. According to FIG. 3, the synchronization system 1A does not include the upstream delay storage unit 35 and the upstream delay selection unit 36, and also does not include the phase error determination unit 306.

[0068] Therefore, it is not possible to reduce computational costs and communication volume by determining the synchronization state between the server device 100 and the client device 300 and, in the synchronized state, by referring to information on past upstream delay tcs and reducing the number of times the upstream delay tcs is measured.

[0069] 3, server device 100A does not include a frequency synchronization generation unit, and client device 300A does not include clock generation unit 308. In this case, client clock 307A operates using clock source 309 as its clock source.

[0070] Although the control for correcting the phase error differs depending on the PTP implementation, the phase error correction unit 38A in the synchronization system 1A corrects the phase error (time error) of the client clock 307A based on the input phase difference te. At this time, a common implementation is to servo-control the frequency of the client clock 307A as the control target so that the phase difference te gradually converges toward zero in the next and subsequent control periods.

[0071] If the server clock and client clock are not synchronized in frequency, there will be a frequency difference between them. Since the time difference (phase difference) is the integral of the frequency, in this case the time difference (phase difference) between the two will increase over the observation period. Therefore, it is necessary to continuously correct the client clock.

[0072] In contrast, between frequency-synchronized clocks, phase fluctuations over relatively short periods and relatively long periods are observed due to the effects of noise and temperature. Relatively short-term phase fluctuations are known as jitter. Relatively long-term phase fluctuations are known as wander. However, the time difference between the two clocks remains within these fluctuation ranges, and its time average converges to zero. In other words, in this embodiment, the client device 300 has frequency synchronization means and uses a clock frequency-synchronized with the server device 100, thereby preventing phase drift of the client clock 307 over time. Therefore, it is expected that the rates of time advance (phase advance) between the two clocks will be equalized. This eliminates the need to correct the phase error of the client clock 307 by continuously transmitting and receiving PTP messages, thereby reducing the network load and the processing load on both the server device 100 and the client device 300.

[0073] 4 and 5 are flow diagrams of the client device 300 in this embodiment. Figures 4 and 5 show a series of flows, with the flows connected at A, B, and C in each figure. The client device 300 executes time synchronization with the server device 100 in steps S1 to S7.

[0074] In step S1, the client device 300 sets an initial synchronization state. The phase error determination unit 306 sets the synchronization flag 311 to False. After step S1 is completed, the process proceeds to step S2.

[0075] In step S2, client device 300 receives a Sync message from server device 100 via transmission path 20. First, client data demodulation unit 301 receives and demodulates the Sync message. Having received the Sync message, client data demodulation unit 301 generates time t2 at which the Sync message was received based on client clock 307. Thereafter, client data demodulation unit 301 outputs time t1 and time t2 included in the demodulated Sync message to downstream delay calculation unit 32. After completing step S2, the process proceeds to step S3.

[0076] In step S3, the client device 300 calculates the downstream delay tsc in the downstream delay calculation unit 32. Referring to FIG. 6, which shows a sequence diagram of time synchronization using PTP, time t1 is the transmission time of the Sync message observed by the server clock 101. Also, time t2 is the reception time of the Sync message observed by the client clock 307. The downstream delay tsc can be expressed as tsc=t2-t1. After step S3 is completed, the process proceeds to step S4.

[0077] In step S4, the client device 300 determines the synchronization state with the server device 100. If the synchronization flag 311 set by the phase error determination unit 306 is False, the process proceeds to step S5. If the synchronization flag 311 is True, the process proceeds to step S6.

[0078] In step S5, the client device 300 performs uplink delay calculation, round trip delay calculation, phase error determination, and phase correction. Step S5 includes sub-steps S51 to S59B.

[0079] In sub-step S51, client device 300 transmits a Delay_req message to server device 100. If synchronization flag 311 is False, client control unit 303 generates a Delay_Req message and outputs it to client packet transmitting unit 304. Having received the Delay_Req message, client packet transmitting unit 304 transmits the Delay_Req message to server device 100 via client data modulation unit 305 and transmission path 20. In addition, client packet transmitting unit 304 generates transmission time t3 of the Delay_Req message based on client clock 307 and outputs it to upstream delay calculation unit 34. After completing sub-step S51, the process proceeds to sub-step S52.

[0080] In sub-step S52, client device 300 receives a Delay_resp message from server device 100 via transmission path 20. Client packet receiver 302 extracts reception time t4 of the Delay_req message at server device 100, which is included in the Delay_resp message demodulated by client data demodulator 301, and outputs this to upstream delay calculator 34. After completion of sub-step S52, the process proceeds to sub-step S53.

[0081] In sub-step S53, client device 300 calculates the upstream delay tcs. Referring to Figure 6, time t3 is the transmission time of the Delay_req message observed by client clock 307, and time t4 is the reception time of the Delay_req message observed by server clock 101. The upstream delay tcs can be expressed as tcs = t4 - t3. After completing sub-step S53, the process proceeds to sub-step S54.

[0082] In sub-step S54, the client device 300 selects an upstream delay tcs. The upstream delay selector 36 sets the upstream delay tcs to the post-switching upstream delay tcs_sel. After completing sub-step S54, the process proceeds to sub-step S55.

[0083] In sub-step S55, the client device 300 stores the upstream delay tcs. The upstream delay storage unit 35 sets the upstream delay tcs as the upstream delay memory tcs_mem. After completing sub-step S55, the process proceeds to sub-step S56.

[0084] In sub-step S56, the client device 300 calculates a round-trip propagation delay td. In PTP, the average of the propagation delays in both directions is used as the round-trip propagation delay td for time synchronization. That is, the phase difference calculation unit 37 calculates the round-trip propagation delay td as follows: round-trip propagation delay td = (tsc + tcs_sel) / 2 = ((t2 - t1) + (t4 - t3)) / 2. After completing sub-step S56, the process proceeds to sub-step S57.

[0085] The phase difference calculation unit 37 may obtain the phase difference te by acquiring the upstream delay tcs and the downstream delay tsc multiple times and performing statistical processing on the acquired values. Specifically, if the fluctuations of the timestamps t1, t2, t3, and t4 are large, the values ​​of t1, t2, t3, and t4 may not be used directly, but may be obtained multiple times and subjected to statistical processing. For example, the effect of fluctuations can be reduced by acquiring multiple calculation results of the round-trip propagation delay td=(tsc+tcs_sel) / 2=((t2-t1)+(t4-t3)) / 2 and applying a moving median filter or a moving average filter.

[0086] In sub-step S57, client device 300 calculates the phase difference te between server clock 101 and client clock 307. If there is no difference in the propagation delay in both directions, the time difference between server device 100 and client device 300, i.e., the phase difference te, can be expressed as te = tsc - td = t2 - t1 - td. Therefore, by substituting td = ((t2 - t1) + (t4 - t3)) / 2 and eliminating td, te = (t2 - t1 + t3 - t4) / 2 is obtained. In other words, the calculation formula for phase difference te is te = (tsc - tcs_sel) / 2. Furthermore, phase difference calculation unit 37 outputs phase difference te to phase error correction unit 38 and phase error determination unit 306. After completing sub-step S57, the process proceeds to sub-step S58.

[0087] In sub-step S58, client device 300 determines whether server clock 101 and client clock 307 are synchronized. If the synchronization state between server device 100 and client device 300 is asynchronous (i.e., synchronization flag 311 is False), phase error determination unit 306 compares the magnitude of phase difference te output by phase difference calculation unit 37 with first reference value tein and determines whether phase difference te is smaller than first reference value tein. If phase difference te is equal to or greater than first reference value tein, sub-step S59A is executed. If phase difference te is smaller than first reference value tein, sub-step S59B is executed. However, since the phase error has not yet been corrected in the first round of control in the asynchronous state, sub-step S59A is executed.

[0088] In sub-step S59A, the client device 300 considers the client device 300 to be in an asynchronous state, leaves the synchronization flag 311 set to False, and corrects the phase of the client clock 307. In the comparative example, the phase correction control generally targets the frequency of the client clock 307A. However, in this embodiment, the phase error correction unit 38 sets the phase control value to -te and shifts the phase of the client clock 307 by -te. When sub-step S59A is completed, step S5 ends.

[0089] In sub-step S59B, the client device 300 updates the synchronization flag 311. The phase error determination unit 306 updates the synchronization state to true and sets the synchronization flag 311 to True. When sub-step S59B is completed, step S5 ends.

[0090] As described above, by executing sub-steps S51 to S59A or S59B, the client device 300 performs uplink delay calculation, round-trip path delay calculation, phase error determination, and phase correction in step S5. This completes one cycle of time synchronization control when the client device is in an asynchronous state. After step S5 is completed, step S7 is executed.

[0091] In step S6, the client device 300 calculates the phase difference te from the uplink delay memory tcs_mem and determines the synchronization state. Step S6 includes sub-steps S61 to S65.

[0092] In substep S61, the client device 300 sets the post-switching upstream delay tcs_sel to the upstream delay memory tcs_mem. Here, the client control unit 303 does not need to generate or send a Delay_Req message. This reduces the number of communications between the server device 100 and the client device 300, and reduces the computational resources and power consumption required for the time synchronization process. After completing substep S61, the process proceeds to substep S62.

[0093] In sub-step S62, the client device 300 calculates a round-trip propagation delay td. In PTP, the average of the propagation delays in both directions is used as the round-trip propagation delay td for time synchronization. That is, the phase difference calculation unit 37 calculates the round-trip propagation delay td as follows: round-trip propagation delay td=(tsc+tcs_sel) / 2=((t2-t1)+(t4-t3)) / 2. After completing sub-step S62, the process proceeds to sub-step S63.

[0094] The phase difference calculation unit 37 may obtain the phase difference te by acquiring the upstream delay tcs and the downstream delay tsc multiple times and performing statistical processing on the acquired values. Specifically, if the fluctuations of the timestamps t1, t2, t3, and t4 are large, the values ​​of t1, t2, t3, and t4 may not be used directly, but may be obtained multiple times and subjected to statistical processing. For example, the effect of fluctuations can be reduced by acquiring multiple calculation results of the round-trip propagation delay td=(tsc+tcs_sel) / 2=((t2-t1)+(t4-t3)) / 2 and applying a moving median filter or a moving average filter.

[0095] In sub-step S63, client device 300 calculates the phase difference te between server clock 101 and client clock 307. If there is no difference in the propagation delay in both directions, the time difference between server device 100 and client device 300, i.e., the phase difference te, can be expressed as te = tsc - td = t2 - t1 - td. Therefore, by substituting td = ((t2 - t1) + (t4 - t3)) / 2 and eliminating td, te = (t2 - t1 + t3 - t4) / 2 is obtained. In other words, the calculation formula for phase difference te is te = (tsc - tcs_sel) / 2. Furthermore, phase difference calculation unit 37 outputs the phase difference te to phase error correction unit 38 and phase error determination unit 306. After completing sub-step S63, the process proceeds to sub-step S64.

[0096] In sub-step S64, client device 300 determines whether server clock 101 and client clock 307 are synchronized. If server device 100 and client device 300 are synchronized (i.e., if the synchronization flag is True), phase error determination unit 306, functioning as synchronization state determination unit 39, compares the magnitude of phase difference te with second reference value teout, and if phase difference te is equal to or greater than second reference value teout, proceeds to sub-step S65. If not, it is determined that the synchronization state is established, synchronization flag 311 remains True, and step S6 is terminated.

[0097] Here, the second reference value teout has a minimum value of tein, which is the first reference value that sets the synchronization flag 311 from False to True. In other words, the first reference value tein is smaller than the second reference value teout. Note that, referring to the sequence diagram shown in FIG. 7, by setting teout > tein, it is possible to impart hysteresis characteristics to the determination of the synchronization state of the client device 300.

[0098] In sub-step S65, the client device 300 updates the synchronization flag 311. The phase error determination unit 306 sets the synchronization flag 311 to False. Upon completion of sub-step S65, step S6 ends.

[0099] As described above, by executing sub-steps S61 to S64 or S65, the client device 300 calculates the phase difference te from the uplink delay memory tcs_mem in step S6 and determines the synchronization state. This completes one cycle of control when the client device 300 is in the synchronization state. After step S6 is completed, step S7 is executed.

[0100] In step S7, the client device 300 waits until the next control cycle. When it detects that a Sync message has been transmitted from the server device 100 via the transmission path 20, the client device 300 proceeds to step S2.

[0101] As described above, through steps S1 to S7, the client device 300 executes time synchronization with the server device 100. Note that the client device 300 executes step S1 only the first time, and repeatedly executes steps S2 to S7 during startup or until it receives an end command.

[0102] In other words, when the client device 300 is in a synchronized state, it does not correct the phase error, but only monitors that the phase difference te with the server device 100 remains within a certain range. Specifically, when the client control unit 303 receives a Sync message, if the synchronized state is true and the synchronization flag 311 is True, it does not generate or transmit a Delay_req message. Also, the uplink delay selection unit 36 ​​outputs the uplink delay memory tcs_mem stored when the synchronization flag 311 is False as the post-switching uplink delay tcs_sel. As a result, the phase difference calculation unit 37 outputs te = (tsc + tcs_sel) / 2 = (tsc + tcs_mem) / 2 as the phase difference te.

[0103] Note that when SyncE is configured and frequency synchronization is performed between the server device 100 and the client device 300, the frequency is not controlled, unlike in the comparative example. The reason why the information processing device according to the present disclosure directly corrects the phase error is because the client clock 307 is frequency-synchronized with the server clock 101 of the server device 100 by SyncE. In this embodiment, the phase advance rates of the server clock 101 and the client clock 307 are maintained equal by SyncE (frequency synchronization). Therefore, once phase correction control is performed, the subsequent phase error remains within the range of phase fluctuation due to jitter or wander associated with frequency synchronization. Therefore, in the second cycle of control in the asynchronous state, the phase difference te becomes smaller than the first reference value tein, and the phase error determination unit 306 sets the synchronization flag 311 to True.

[0104] Furthermore, after the phase error of the client clock 307 is corrected, that is, after the synchronization state of the client device becomes true, monitoring of the phase error may be stopped.

[0105] As described above, the monitoring period for the phase error after the phase error correction of client clock 307 is completed depends on the transmission interval of the Sync message sent from the server device. The transmission interval of the Sync message may be changed before and after the phase error correction of client clock 307. In this case, this may be achieved by transmitting a message from client device 300 to server device 100 via the network requesting a change in the transmission interval of the Sync message.

[0106] In addition, in the embodiment, SyncE is used as the frequency synchronization method and PTP is used as the phase synchronization method, but the present invention is not limited to the above standards and may be applied to other methods that perform similar frequency synchronization and phase synchronization.

[0107] (for multi-client) In the explanation up to this point, it has been assumed that one server device 100 and one client device 300 are directly opposed to each other, but generally, a network consisting of a network switch or the like may be interposed between the server device 100 and the client device 300. It is also common to install multiple client devices 300 and distribute time synchronization information from one server device 100 to these multiple client devices 300. This method is called a multi-slave configuration or a multi-client configuration.

[0108] FIG. 8 is a configuration diagram of multi-client operation according to a comparative example. Synchronization system 1B includes one server device 100 and three client devices 300X, 300Y, and 300Z. Server device 100 is connected to the three client devices 300X, 300Y, and 300Z via a network. For simplicity, server device 100 is represented as S, and client devices 300X, 300Y, and 300Z are represented as C1, C2, and C3. The connections between server device S and the network, between the network and client device C1, between the network and client device C2, and between the network and client device C3 are referred to as transmission paths 21, 22, 23, and 24, respectively. Arrows within the dashed lines indicate the messages passing through each transmission path and their direction.

[0109] PTP defines the types of network transport to be used as L2, Ipv4+UDP, Ipv6+UDP, L2:layer2, Ipv4:Internet Protocol Version 4, Ipv6:Internet Protocol Version 6, UDP:User Datagram Protocol), but here we will assume that L2 transport will be used.

[0110] In PTP, which uses the E2E method, PTP-compatible devices on the network must mutually announce their presence. For this reason, when using L2 transport, a forwardable multicast address is used as the destination MAC address of PTP messages. A forwardable multicast address is an address that allows packets arriving at a port on a switch to pass through the switch and be output from another port when there is a device on the network that does not support PTP, such as a switch. In the following explanation, a forwardable multicast address will simply be referred to as a multicast address.

[0111] As explained above, the synchronization process begins by sending a Sync message from the server device, which is sent to a multicast address. Therefore, the Sync message propagates through the network onto transmission paths 22, 23, and 24 and arrives at client devices C1, C2, and C3. At this point, client devices C1, C2, and C3 obtain the time t1 when server device S sent Sync and the times t2-C1, t2-C2, and t2-C3 when Sync was received by each client device.

[0112] Next, client devices C1, C2, and C3 transmit Delay_Req messages Delay_Req(C1), Delay_Req(C2), and Delay_Req(C3), respectively, to the network. Furthermore, client devices C1, C2, and C3 store transmission times t3-C1, t3-C2, and t3-C3. Because these Delay_Req messages are also addressed to a multicast address, they also arrive at server device S and client devices 300 other than the client device 300 in question.

[0113] The server device S stores the times at which it received Delay_Req(C1), Delay_Req(C2), and Delay_Req(C3) as t4-C1, t4-C2, and t4-C3, respectively. Furthermore, the server device S transmits these messages to the network as Delay_Resp(C1), Delay_Resp(C2), and Delay_Resp(C3) messages. Since the Delay_Resp message is also addressed to a multicast address, it arrives at each of the three client devices C1, C2, and C3.

[0114] The client devices C1, C2, and C3 store the times at which they received Delay_Resp(C1), Delay_Resp(C2), and Delay_Resp(C3) as t4-C1, t4-C2, and t4-C3, respectively.

[0115] At this point, each of the client devices C1, C2, and C3 has obtained the four timestamps necessary to calculate the upstream and downstream propagation delays, so it is possible for each of the client devices C1, C2, and C3 to calculate the time difference between itself and the server device S.

[0116] However, because PTP uses multicast addresses for communication, in a multi-client configuration where multiple client devices are synchronized, the number of packets on the network increases in proportion to the number of client devices. In other words, the so-called multicast flooding phenomenon occurs. This creates a problem in that the system scale is limited by the available network bandwidth and the processing power of each device.

[0117] <Embodiment 2> As one form of time synchronization in the multi-client configuration described above, an embodiment of multi-client operation will be described below. Note that for the sake of simplicity, the description of the components included in the server device 100 and client device 300 described in the first embodiment will be omitted.

[0118] 9 shows a simplified block diagram of multi-client operation according to the present disclosure. The synchronization system 1C further includes a plurality of client devices 300 and a selection unit 3. The synchronization system 1C is used to perform time synchronization when a plurality of client devices 300 exist within one synchronization system 1C. Here, the configuration of the server device 100 is the same as the configuration described in the first embodiment.

[0119] The selector 3 selects a reference client device 300C suitable to be used as a synchronization reference from among the multiple client devices 300. A client device 300 equipped with multiple network ports may be selected as the reference client device 300C. For example, a client device 300 having a communication strength higher than a preset reference value may be selected. The selector 3 may be provided on the server device 100 or the client device 300, or on another device connected to the synchronization system 1C.

[0120] The reference client device 300C includes the same components as those of the client device described in the first embodiment, and further includes a secondary synchronization signal transmitter 310. The reference client device 300C synchronizes with the server device 100 in time, and transmits a secondary synchronization signal (a Sync message that is downlink phase synchronization information) from the secondary synchronization signal transmitter 310 to the other client devices 300 of the plurality of client devices 300. This allows the reference client device 300C to function as the server device 100 in the first embodiment with respect to the other client devices 300.

[0121] The other client devices 300 use the reference client device 300C as a synchronization signal source instead of the server device 100. The other client devices 300 have the same configuration as the client device 300 described in the first embodiment. This distributes the communication traffic on the network and the processing load for time synchronization, and enables the multiple client devices 300 to synchronize their times with the server device 100 without increasing the processing load of the server device 100.

[0122] In other words, in this embodiment, when the client device 300 in Figure 2 is a DU of a 5G base station, one of the multiple ports is directed to the server device 100 to synchronize the client clock 307, and another port is directed to the RU to transmit a synchronization signal.

[0123] In other words, if the reference client device 300C has multiple network ports, one of them is used to interface with the server device 100. Furthermore, the other network ports are used as server ports for PTP or SyncE, and the client clock 307 is referenced as a time reference source to transmit synchronization information to other client devices 300. This is a type of PTP configuration called a BC (boundary clock).

[0124] If the number of client devices 300 is large and the burden on the reference client device 300C becomes excessive, multiple reference client devices 300C may be selected. This makes it possible to increase the number of client devices 300 that perform time synchronization while suppressing an increase in the amount of information.

[0125] As described above, the client device 300 according to the embodiment of the present disclosure includes the phase error determination unit 306, the upstream delay storage unit 35, and the upstream delay selection unit 36. This makes it possible to eliminate the step of measuring the upstream delay tcs when the phase difference te between the server device 100 and the client device 300 is within the standard range, thereby reducing the calculation load and the amount of communication on the network.

[0126] Furthermore, since the client clock 307 is frequency-synchronized with the server clock 101 of the server device 100, the phase lead between the server device 100 and the client device 300 is kept constant. Therefore, if the phase difference te of the client clock 307 is corrected once, the accuracy of the time synchronization thereafter is maintained by frequency synchronization.

[0127] This eliminates the need to repeat PTP processing at regular intervals to maintain time synchronization accuracy, as is the case with related technologies. This allows CPU cores and other computer resources that were previously allocated to PTP processing to be used for other processes, and also reduces power consumption by stopping CPU cores.

[0128] Furthermore, even if the network load increases after the phase error of the client clock has been corrected, the time synchronization accuracy will not decrease because frequency synchronization control using SyncE is independent of the network load.

[0129] After the phase difference te of the client clock 307 is corrected, the time synchronization accuracy is maintained by frequency synchronization. However, it is possible to monitor the phase difference te with the server device 100 using the upstream delay memory tcs_mem stored before the phase error was corrected. In this case, the client device 300 does not transmit a Delay_Req message related to the measurement of the upstream delay tcs. Therefore, the server device does not generate a Delay_Resp message, and therefore the PTP messages generated on the network are limited to Sync messages transmitted from the server device 100, thereby reducing the network load. The monitoring interval depends on the Sync message transmission interval of the server device 100, but this transmission interval can be set arbitrarily according to the requirements of system operation.

[0130] <Example of hardware configuration> Hereinafter, an example will be described in which each functional configuration of an information processing device according to the present disclosure is realized by a combination of hardware and software.

[0131] FIG. 10 is a block diagram illustrating an example of a hardware configuration of a computer. The information processing device of the present disclosure can realize the above-described functions by a computer 500 including the hardware configuration shown in the figure. The computer 500 may be a portable computer such as a smartphone or tablet terminal, or a stationary computer such as a PC. The computer 500 may be a dedicated computer designed to realize each device, or may be a general-purpose computer. The computer 500 can realize desired functions by installing a predetermined application.

[0132] The computer 500 has a bus 502, a processor 504, a memory 506, a storage device 508, an input / output interface (I / F) 510, and a network interface (I / F) 512. The bus 502 is a data transmission path for the processor 504, the memory 506, the storage device 508, the input / output interface 510, and the network interface 512 to transmit and receive data to and from each other. However, the method for connecting the processor 504 and the like to each other is not limited to a bus connection.

[0133] The processor 504 is one of various processors such as a CPU, a GPU, an FPGA, etc. The memory 506 is a main storage device realized using a RAM (Random Access Memory) or the like.

[0134] The storage device 508 is an auxiliary storage device realized using a hard disk, an SSD, a memory card, a ROM (Read Only Memory), or the like. The storage device 508 stores programs for realizing desired functions. The processor 504 reads the programs into the memory 506 and executes them to realize the respective functional components of each device.

[0135] The input / output interface 510 is an interface for connecting the computer 500 to an input / output device. For example, an input device such as a keyboard and an output device such as a display device are connected to the input / output interface 510. The network interface 512 is an interface for connecting the computer 500 to a network.

[0136] Although the present disclosure has been described with reference to the embodiments, the present disclosure is not limited to the above-described embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. Furthermore, each embodiment can be combined with other embodiments as appropriate.

[0137] Each drawing is merely an example for describing one or more embodiments. Each drawing may relate not only to one particular embodiment, but also to one or more other embodiments. As will be understood by those skilled in the art, various features or steps described with reference to any one drawing can be combined with features or steps shown in one or more other drawings to create, for example, an embodiment not explicitly shown or described. Not all features or steps shown in any one drawing are necessary to describe an exemplary embodiment, and some features or steps may be omitted. The order of steps described in any drawing may be changed as appropriate.

[0138] A part or all of the above-described embodiments can be described as, but not limited to, the following supplementary notes.

[0139] Some or all of the elements (e.g., configurations and functions) described in Supplementary Notes 2 to 8 that are dependent on Supplementary Notes 1 may also be dependent on Supplementary Notes 9, 10, 11, and 12 in the same dependent relationship as Supplementary Notes 2 to 8. Some or all of the elements described in Supplementary Notes 10 may also be described as appendices that are dependent on Supplementary Notes 11 and 12 in the same dependent relationship as Supplementary Notes 10. Some or all of the elements described in any appendix may be applicable to various hardware, software, recording means for recording software, systems, and methods.

[0140] (Appendix 1) a synchronization information receiving unit that generates a reception time of downstream phase synchronization information received from a synchronization signal source via a transmission line based on the time of a client clock; a downstream delay calculation unit that calculates a downstream delay of the downstream phase synchronization information on the transmission path based on the reception time and the downstream phase synchronization information; a synchronization request transmitting unit that generates a transmission time of an upstream phase synchronization request transmitted to the synchronization signal source based on the time of the client clock; an upstream delay calculation unit that receives an upstream phase synchronization response, which is a response to the upstream phase synchronization request, from the synchronization signal source via the transmission path, and calculates an upstream delay on the transmission path based on the upstream phase synchronization response and the transmission time; an upstream delay storage unit that stores the upstream delay output by the upstream delay calculation unit; an upstream delay selection unit that selects and outputs the output of the upstream delay calculation unit or the output of the upstream delay storage unit; a phase difference calculation unit that calculates a phase difference between the synchronization signal source and the client clock based on the downstream delay and the output of the upstream delay selection unit; a phase error correction unit that generates a phase control value based on the phase difference and corrects the output phase of the client clock based on the phase control value; a synchronization state determination unit that outputs a synchronization state between the synchronization signal source and the client clock based on the phase difference; A synchronization device comprising: (Appendix 2) 2. The synchronization device according to claim 1, further comprising a clock generation unit that generates a frequency-synchronized clock based on frequency synchronization information transmitted from the synchronization signal source via a transmission path. (Appendix 3) 3. The synchronization device of claim 2, wherein the client clock operates according to the frequency-synchronized clock. (Appendix 4) The synchronization state determination unit updating the synchronization state to true if the phase difference is smaller than a predetermined first reference value when the synchronization state between the synchronization signal source and the client clock is false; updating the synchronization state to false if the phase difference is equal to or greater than a predetermined second reference value when the synchronization state is true; 4. A synchronization device according to any one of claims 1 to 3. (Appendix 5) The synchronization device described in Appendix 4, wherein the delay memory unit retains the previous memory contents when the synchronization state is true, and updates the memory contents to the upstream delay output by the upstream delay calculation unit when the synchronization state is false. (Appendix 6) 6. The synchronization device according to claim 5, wherein the synchronization request transmission unit does not transmit the phase synchronization request if the synchronization state is true. (Appendix 7) 5. The synchronization device of claim 4, wherein the first reference value is smaller than the second reference value. (Appendix 8) 5. The synchronization device according to claim 4, wherein the phase difference calculation unit acquires the phase difference by acquiring the upstream delay and the downstream delay multiple times and performing statistical processing. (Appendix 9) The system includes a server device that serves as a synchronization signal source and a client device, the server device includes a synchronization signal transmission unit that transmits a synchronization signal to the client device; The client device a synchronization information receiving unit that generates a reception time of the downstream phase synchronization information received from the synchronization signal source via a transmission line based on the time of a client clock; a downstream delay calculation unit that calculates a downstream delay of the downstream phase synchronization information on the transmission path based on the reception time and the downstream phase synchronization information; a synchronization request transmitting unit that generates a transmission time of an upstream phase synchronization request transmitted to the synchronization signal source based on the time of the client clock; an upstream delay calculation unit that receives an upstream phase synchronization response, which is a response to the upstream phase synchronization request, from the synchronization signal source via the transmission path, and calculates an upstream delay on the transmission path based on the upstream phase synchronization response and the transmission time; an upstream delay storage unit that stores the upstream delay output by the upstream delay calculation unit; an upstream delay selection unit that selects and outputs the output of the upstream delay calculation unit or the output of the upstream delay storage unit; a phase difference calculation unit that calculates a phase difference between the synchronization signal source and the client clock based on the downstream delay and the output of the upstream delay selection unit; a phase error correction unit that generates a phase control value based on the phase difference and corrects the output phase of the client clock based on the phase control value; a synchronization state determination unit that outputs a synchronization state between the synchronization signal source and the client clock based on the phase difference; Equipped with Synchronous system. (Appendix 10) the synchronization system includes a plurality of the client devices; a selection unit for selecting a reference client device suitable as a synchronization reference from the plurality of client devices; the reference client device further includes a secondary synchronization signal transmitter configured to transmit a synchronization signal to other client devices of the plurality of client devices; the other client devices use the reference client device as the synchronization signal source instead of the server device; 10. The synchronization system of claim 9. (Appendix 11) The computer a synchronization information receiving step of generating a reception time of downstream phase synchronization information received from a synchronization signal source via a transmission line based on the time of a client clock; a downstream delay calculation step of calculating a downstream delay of the downstream phase synchronization information on the transmission path based on the reception time and the downstream phase synchronization information; a synchronization request transmitting step of generating a transmission time of an upstream phase synchronization request transmitted to the synchronization signal source based on the time of the client clock; an upstream delay calculation step of receiving an upstream phase synchronization response, which is a response to the upstream phase synchronization request, from the synchronization signal source via a transmission path, and calculating an upstream delay on the transmission path based on the upstream phase synchronization response and the transmission time; an upstream delay storage step of storing the upstream delay output in the upstream delay calculation step; an upstream delay selection step of selecting and outputting the upstream delay outputted in the upstream delay calculation step or the upstream delay storage step; a phase difference calculation step of calculating a phase difference between the synchronization signal source and the client clock based on the downstream delay and the upstream delay output in the upstream delay selection step; a phase error correction step of generating a phase control value based on the phase difference and correcting the output phase of the client clock based on the phase control value; a synchronization state determination step of outputting a synchronization state between the synchronization signal source and the client clock based on the phase difference; The synchronization method to perform. (Appendix 12) On the computer, a synchronization information receiving procedure for generating a reception time of downstream phase synchronization information received from a synchronization signal source via a transmission line based on the time of a client clock; a downstream delay calculation step of calculating a downstream delay of the downstream phase synchronization information on the transmission path based on the reception time and the downstream phase synchronization information; a synchronization request transmission step of generating a transmission time of an upstream phase synchronization request transmitted to the synchronization signal source based on the time of the client clock; an upstream delay calculation step of receiving an upstream phase synchronization response, which is a response to the upstream phase synchronization request, from the synchronization signal source via a transmission path, and calculating an upstream delay on the transmission path based on the upstream phase synchronization response and the transmission time; an upstream delay storage step of storing the upstream delay outputted in the upstream delay calculation step; an upstream delay selection step of selecting and outputting the upstream delay outputted in the upstream delay calculation step or the upstream delay storage step; a phase difference calculation step of calculating a phase difference between the synchronization signal source and the client clock based on the downstream delay and the upstream delay output in the upstream delay selection step; a phase error correction procedure for generating a phase control value based on the phase difference and correcting the output phase of the client clock based on the phase control value; a synchronization state determination step of outputting a synchronization state between the synchronization signal source and the client clock based on the phase difference; A program to execute. [Explanation of symbols]

[0141] t1, t2, t3, t4 time tcs upstream delay tcs_mem upstream delay memory tcs_sel Upstream delay after switching te phase difference tein first standard value teout Second standard value tsc downstream delay 1 Synchronous System 2 Time reference source 3 Selection section 10 Synchronous signal source 20 Transmission Line 30 Synchronous Device 31 Synchronization information receiver 32 Downstream delay calculation unit 33 Synchronous request transmission part 34 Upstream delay calculation unit 35 Upstream delay memory unit 36 Upstream delay selection unit 37 Phase difference calculation section 38 Phase error correction section 39 Synchronization status determination unit 310 Secondary synchronization signal transmitter 100 Server device 101 Server Clock 102 Server control unit 103 Server packet transmitter 104 Server data modulation unit 105 Server data demodulation unit 106 Server packet receiver 107 Frequency synchronization information generation unit 300 Client Device 300C Reference Client Device 301 Client data demodulation unit 302 Client packet receiver 303 Client control section 304 Client packet sender 305 Client Data Modulation Unit 306 Phase error determination section 307 Client Clock 308 Clock Generation Unit 309 Clock Source 311 Synchronous Flag 500 computers 502 Bus 504 processor 506 memory 508 Storage Devices 510 Input / Output Interface 512 network interface

Claims

1. a synchronization information receiving unit that generates a reception time of downstream phase synchronization information received from a synchronization signal source via a transmission line based on the time of a client clock; a downstream delay calculation unit that calculates a downstream delay of the downstream phase synchronization information on the transmission path based on the reception time and the downstream phase synchronization information; a synchronization request transmitting unit that generates a transmission time of an upstream phase synchronization request transmitted to the synchronization signal source based on the time of the client clock; an upstream delay calculation unit that receives an upstream phase synchronization response, which is a response to the upstream phase synchronization request, from the synchronization signal source via the transmission path, and calculates an upstream delay on the transmission path based on the upstream phase synchronization response and the transmission time; an upstream delay storage unit that stores the upstream delay output by the upstream delay calculation unit; an upstream delay selection unit that selects and outputs the output of the upstream delay calculation unit or the output of the upstream delay storage unit; a phase difference calculation unit that calculates a phase difference between the synchronization signal source and the client clock based on the downstream delay and the output of the upstream delay selection unit; a phase error correction unit that generates a phase control value based on the phase difference and corrects the output phase of the client clock based on the phase control value; a synchronization state determination unit that outputs a synchronization state between the synchronization signal source and the client clock based on the phase difference; A synchronization device comprising:

2. 2. The synchronization device according to claim 1, further comprising a clock generation unit that generates a frequency-synchronized clock based on frequency synchronization information transmitted from said synchronization signal source via a transmission line.

3. 3. The synchronizer of claim 2, wherein the client clock operates according to the frequency-synchronized clock.

4. The synchronization state determination unit updating the synchronization state to true if the phase difference is smaller than a predetermined first reference value when the synchronization state between the synchronization signal source and the client clock is false; If the phase difference is equal to or greater than a predetermined second reference value when the synchronization state is true, the synchronization state is updated to false. The synchronizer of claim 1 .

5. The synchronization device according to claim 4, wherein the delay memory unit retains the previous memory contents when the synchronization state is true, and updates the memory contents to the upstream delay output by the upstream delay calculation unit when the synchronization state is false.

6. The synchronization device according to claim 5 , wherein the synchronization request transmitter does not transmit the phase synchronization request when the synchronization state is true.

7. The system includes a server device that serves as a synchronization signal source and a client device, the server device includes a synchronization signal transmission unit that transmits a synchronization signal to the client device; The client device a synchronization information receiving unit that generates a reception time of downstream phase synchronization information received from the synchronization signal source via a transmission line based on a time of a client clock; a downstream delay calculation unit that calculates a downstream delay of the downstream phase synchronization information on the transmission path based on the reception time and the downstream phase synchronization information; a synchronization request transmitting unit that generates a transmission time of an upstream phase synchronization request transmitted to the synchronization signal source based on the time of the client clock; an upstream delay calculation unit that receives an upstream phase synchronization response, which is a response to the upstream phase synchronization request, from the synchronization signal source via the transmission path, and calculates an upstream delay on the transmission path based on the upstream phase synchronization response and the transmission time; an upstream delay storage unit that stores the upstream delay output by the upstream delay calculation unit; an upstream delay selection unit that selects and outputs the output of the upstream delay calculation unit or the output of the upstream delay storage unit; a phase difference calculation unit that calculates a phase difference between the synchronization signal source and the client clock based on the downstream delay and the output of the upstream delay selection unit; a phase error correction unit that generates a phase control value based on the phase difference and corrects the output phase of the client clock based on the phase control value; a synchronization state determination unit that outputs a synchronization state between the synchronization signal source and the client clock based on the phase difference; Equipped with Synchronous system.

8. the synchronization system includes a plurality of the client devices; a selection unit for selecting a reference client device suitable as a synchronization reference from the plurality of client devices; the reference client device further includes a secondary synchronization signal transmitter configured to transmit a synchronization signal to other client devices of the plurality of client devices; the other client devices use the reference client device as the synchronization signal source instead of the server device; The synchronization system of claim 7.

9. The computer a synchronization information receiving step of generating a reception time of downstream phase synchronization information received from a synchronization signal source via a transmission line based on the time of a client clock; a downstream delay calculation step of calculating a downstream delay of the downstream phase synchronization information on the transmission path based on the reception time and the downstream phase synchronization information; a synchronization request transmitting step of generating a transmission time of an upstream phase synchronization request transmitted to the synchronization signal source based on the time of the client clock; an upstream delay calculation step of receiving an upstream phase synchronization response, which is a response to the upstream phase synchronization request, from the synchronization signal source via a transmission path, and calculating an upstream delay on the transmission path based on the upstream phase synchronization response and the transmission time; an upstream delay storage step of storing the upstream delay output in the upstream delay calculation step; an upstream delay selection step of selecting and outputting the upstream delay outputted in the upstream delay calculation step or the upstream delay storage step; a phase difference calculation step of calculating a phase difference between the synchronization signal source and the client clock based on the downstream delay and the upstream delay output in the upstream delay selection step; a phase error correction step of generating a phase control value based on the phase difference and correcting the output phase of the client clock based on the phase control value; a synchronization state determination step of outputting a synchronization state between the synchronization signal source and the client clock based on the phase difference; The synchronization method to perform.

10. On the computer, a synchronization information receiving procedure for generating a reception time of downstream phase synchronization information received from a synchronization signal source via a transmission line based on the time of a client clock; a downstream delay calculation step of calculating a downstream delay of the downstream phase synchronization information on the transmission path based on the reception time and the downstream phase synchronization information; a synchronization request transmission step of generating a transmission time of an upstream phase synchronization request transmitted to the synchronization signal source based on the time of the client clock; an upstream delay calculation step of receiving an upstream phase synchronization response, which is a response to the upstream phase synchronization request, from the synchronization signal source via a transmission path, and calculating an upstream delay on the transmission path based on the upstream phase synchronization response and the transmission time; an upstream delay storage step of storing the upstream delay outputted in the upstream delay calculation step; an upstream delay selection step of selecting and outputting the upstream delay outputted in the upstream delay calculation step or the upstream delay storage step; a phase difference calculation step of calculating a phase difference between the synchronization signal source and the client clock based on the downstream delay and the upstream delay output in the upstream delay selection step; a phase error correction procedure for generating a phase control value based on the phase difference and correcting the output phase of the client clock based on the phase control value; a synchronization state determination step of outputting a synchronization state between the synchronization signal source and the client clock based on the phase difference; A program to execute.

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