Constant voltage generation circuit

Abstract

To provide a constant voltage generation circuit that offers both stable output and fast startup.SOLUTION: A constant voltage generation circuit 1 is provided, comprising: an output circuit 10 configured to generate a constant output voltage VOUT from an input voltage VIN using a first output transistor DM of a depression type and a second output transistor EM of an enhancement type; and an initiation circuit 20 configured to switch whether to augment the current capacity of the first output transistor DM according to the output voltage VOUT.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to a constant voltage generating circuit. [Background technology]

[0002] Conventionally, an ED type constant voltage source, which combines a depletion type NMOSFET (N-channel type metal oxide semiconductor field effect transistor) and an enhancement type NMOSFET, has been widely known as a type of constant voltage generating circuit.

[0003] As examples of the prior art related to the above, Patent Documents 1 and 2 proposed by the applicant of the present application can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2021 / 172001 [Patent Document 2] International Publication No. 2021 / 241257

[0005] [overview] Conventional constant voltage generating circuits have room for improvement in achieving both stable output and fast startup.

[0006] For example, a constant voltage generation circuit according to the present disclosure includes an output circuit configured to generate a constant output voltage from an input voltage using a first depletion-mode output transistor and a second enhancement-mode output transistor, and a startup circuit configured to switch whether or not to supplement the current capability of the first output transistor depending on the output voltage or a node voltage that fluctuates depending on the output voltage. [Brief explanation of the drawings]

[0007] [Figure 1]FIG. 1 is a diagram illustrating a first comparative example of a constant voltage generating circuit. [Figure 2] FIG. 2 is a diagram showing how output fluctuations occur when input fluctuations occur. [Figure 3] FIG. 3 is a diagram illustrating a second comparative example of a constant voltage generating circuit. [Figure 4] FIG. 4 is a diagram showing how output fluctuations are suppressed when input fluctuations occur. [Figure 5] FIG. 5 is a diagram showing the startup behavior of the second comparative example. [Figure 6] FIG. 6 is a diagram showing a first embodiment of a constant voltage generating circuit. [Figure 7] FIG. 7 is a diagram showing the startup behavior of the first embodiment. [Figure 8] FIG. 8 is a diagram showing a second embodiment of the constant voltage generating circuit. [Figure 9] FIG. 9 is a diagram showing a third embodiment of the constant voltage generating circuit. [Figure 10] FIG. 10 is a diagram showing a fourth embodiment of the constant voltage generating circuit. [Figure 11] FIG. 11 is a diagram showing a fifth embodiment of the constant voltage generating circuit. [Figure 12] FIG. 12 is a diagram showing a sixth embodiment of the constant voltage generating circuit. [Figure 13] FIG. 13 is a diagram showing a seventh embodiment of the constant voltage generating circuit. [Figure 14] FIG. 14 is a diagram illustrating an eighth embodiment of the constant voltage generating circuit. [Figure 15] FIG. 15 is a diagram illustrating a ninth embodiment of the constant voltage generating circuit. [Figure 16] FIG. 16 is a diagram showing a tenth embodiment of the constant voltage generating circuit. [Figure 17] FIG. 17 is a diagram showing an eleventh embodiment of the constant voltage generating circuit.

[0008] [Detailed explanation] <First Comparative Example> FIG. 1 is a diagram showing a first comparative example of a constant voltage generating circuit 1 (basic configuration to be compared with the embodiments described later). The constant voltage generating circuit 1 of this comparative example is a so-called ED-type reference voltage source. Referring to this diagram, the constant voltage generating circuit 1 includes transistors DM and EM. The transistor DM may be, for example, a depression-type NMOSFET. The transistor DM may be understood as a first output transistor. The transistor EM may be, for example, an enhancement-type NMOSFET. The transistor EM may be understood as a second output transistor.

[0009] The depletion type is a type in which a drain current flows even when the gate-source voltage is 0V, while the enhancement type is a type in which no drain current flows when the gate-source voltage is 0V.

[0010] The drain of transistor DM is connected to the application terminal of input voltage VIN. The source and back gate of transistor EM are connected to the application terminal of ground voltage GND (=ground terminal). The gate, source, and back gate of transistor DM and the gate and drain of transistor EM are connected to the application terminal of node voltage Vx. The application terminal of node voltage Vx is connected to the application terminal of output voltage VOUT.

[0011] In the constant voltage generating circuit 1 of this comparative example, the gate and source of transistor DM are short-circuited. Therefore, the gate-source voltage Vgs1 of transistor DM is 0V. Therefore, transistor DM functions as a constant current source that generates a constant drain current. In other words, a constant bias current (= drain current of transistor DM) flows through transistor EM. As a result, a constant node voltage Vx equivalent to the gate-source voltage Vgs2 of transistor EM, and therefore an output voltage VOUT, are generated.

[0012] As described above, the constant voltage generating circuit 1 of this comparative example includes an output circuit 10 that generates a constant output voltage VOUT from an input voltage VIN using transistors DM and EM. The output voltage VOUT can be used, for example, as a reference voltage VREF for an application.

[0013] 2 is a diagram showing how output fluctuations occur when input fluctuations occur in the constant voltage generating circuit 1 of the first comparative example. In this diagram, from top to bottom, the input voltage VIN and the output voltage VOUT are depicted.

[0014] The constant voltage generating circuit 1 of the first comparative example has a problem in that the output voltage VOUT is easily affected by input fluctuations. Referring to this figure, a sudden drop in the input voltage VIN can cause the output voltage VOUT to drop transiently. In particular, if the current capability of the transistor DM (i.e., the drain current flowing through the transistor DM) is reduced in order to reduce the current consumption of the constant voltage generating circuit 1, the amount of transient fluctuation in the output voltage VOUT increases. Furthermore, the time required for the output voltage VOUT to return to its target value after the fluctuation also increases.

[0015] <Second Comparative Example> 3 is a diagram showing a second comparative example of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this comparative example is based on the first comparative example (FIG. 1) described above, and further includes a capacitor C1 for smoothing the output voltage VOUT. The capacitor C1 is connected between the application terminal of the node voltage Vx and the application terminal of the ground voltage GND.

[0016] FIG. 4 is a diagram showing how output fluctuations are suppressed when input fluctuations occur in the constant voltage generating circuit 1 of the second comparative example. In this diagram, as in the above-mentioned FIG. 2, the input voltage VIN and the output voltage VOUT are depicted from top to bottom. The solid line of the output voltage VOUT shows the behavior of the second comparative example. On the other hand, the dashed line of the output voltage VOUT shows the behavior of the first comparative example.

[0017] As can be seen from this figure, the constant voltage generating circuit 1 of the second comparative example makes the output voltage VOUT less susceptible to input fluctuations than the first comparative example. That is, the amount of transient fluctuation in the output voltage VOUT caused by a sudden drop in the input voltage VIN is suppressed. In addition, the time required for the output voltage VOUT to return to the target value after fluctuation is also shortened.

[0018] 5 is a diagram showing the startup behavior of the constant voltage generating circuit 1 of the second comparative example. The solid line of the output voltage VOUT shows the behavior of the second comparative example, that is, the behavior when the capacitor C1 is introduced. On the other hand, the dashed line of the output voltage VOUT shows the behavior of the first comparative example, that is, the behavior when the capacitor C1 is not introduced.

[0019] As can be seen from this figure, in the constant voltage generating circuit 1 of the second comparative example, the startup time of the output voltage VOUT when the input voltage VIN is applied, that is, the time required for the output voltage VOUT to reach the target value from 0 V, becomes long.

[0020] It should be noted that the same problem as above may become apparent not only when the smoothing capacitor C1 is introduced, but also when a large parasitic capacitor is present at the application terminal of the output voltage VOUT.

[0021] In view of the above considerations, a new embodiment of the constant voltage generating circuit 1 that can achieve both stable output and fast startup will be proposed below.

[0022] First Embodiment 6 is a diagram showing a first embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment is based on the second comparative example (FIG. 3) described above, and further includes a start-up circuit 20.

[0023] The start-up circuit 20 switches whether to support the current capability of the transistor DM in accordance with the output voltage VOUT. For example, the start-up circuit 20 includes transistors M1 to M3 and resistors R1 and R2. The transistor M1 may be, for example, an NMOSFET. The transistors M2 and M3 may be, for example, PMOSFETs (P-channel type MOSFETs).

[0024] The drain of the transistor M1 is connected to a terminal to which a voltage signal V1 is applied. The source and back gate of the transistor M1 are both connected to a terminal to which a ground voltage GND is applied. The gate of the transistor M1 is connected to a terminal to which a node voltage Vx is applied, and further to a terminal to which an output voltage VOUT is applied. The transistor M1 is turned on when the output voltage VOUT applied to the gate is higher than the on-threshold voltage Vth(M1) of the transistor M1. On the other hand, the transistor M1 is turned off when the output voltage VOUT is lower than the on-threshold voltage Vth(M1). A current signal I1 flows through the transistor M1 in the on-state.

[0025] The source and back gate of transistor M2 are both connected to a terminal to which an input voltage VIN is applied. The drain of transistor M2 is connected to a terminal to which a voltage signal V2 is applied. The gate of transistor M2 is connected to a terminal to which a voltage signal V1 is applied. Transistor M2 is turned on when the voltage signal V1 applied to the gate is lower than the on-threshold voltage Vth(M2) of transistor M2. On the other hand, transistor M2 is turned off when the voltage signal V1 is higher than the on-threshold voltage Vth(M2). A current signal I2 flows through transistor M2 in the on-state.

[0026] The source and back gate of transistor M3 are both connected to the terminal to which the input voltage VIN is applied. The drain of transistor M3 is connected to the terminal to which the output voltage VOUT is applied. The gate of transistor M3 is connected to the terminal to which the voltage signal V2 is applied. Transistor M3 is turned on when the voltage signal V2 applied to the gate is lower than the on-threshold voltage Vth(M3) of transistor M3. On the other hand, transistor M3 is turned off when the voltage signal V2 is higher than the on-threshold voltage Vth(M3). An auxiliary current I3 flows through transistor M3 in the on-state to supplement the current capability of transistor DM.

[0027] Resistor R1 is connected between the application terminal of input voltage VIN and the application terminal of voltage signal V1. Resistor R1 converts current signal I1 flowing through transistor M1 into voltage signal V1 (=VIN-I1×R1). Resistor R1 can be understood as a current / voltage conversion circuit IVC.

[0028] Resistor R2 is connected between the application terminal of voltage signal V2 and the application terminal of ground voltage GND. Resistor R2 converts current signal I2 flowing through transistor M2 into voltage signal V2 (=I2×R2+GND).

[0029] 7 is a diagram showing the startup behavior of the constant voltage generating circuit 1 of the first embodiment. The solid line of the output voltage VOUT indicates the behavior of the first embodiment, that is, the behavior when the startup circuit 20 is introduced. On the other hand, the dashed line of the output voltage VOUT indicates the behavior of the second comparative example, that is, the behavior when the startup circuit 20 is not introduced.

[0030] After the input voltage VIN is applied, when the output voltage VOUT is lower than a predetermined threshold voltage Vth, specifically, when the output voltage VOUT is lower than the on-threshold voltage Vth(M1) of the transistor M1, the transistor M1 is turned off. At this time, the voltage signal V1 is pulled up to a high level (≒VIN) higher than the on-threshold voltage Vth(M2) via the resistor R1. Therefore, the transistor M2 is turned off. At this time, the voltage signal V2 is pulled down to a low level (≒GND) lower than the on-threshold voltage Vth(M3) via the resistor R2. Therefore, the transistor M3 is turned on. In other words, the application terminal of the output voltage VOUT and the application terminal of the input voltage VIN are short-circuited. As a result, the output voltage VOUT quickly starts up, following the input voltage VIN.

[0031] In this way, when the output voltage VOUT is lower than the threshold voltage Vth, and thus when the voltage signal V1 is at a low level, the start-up circuit 20 is in a state of supporting the current capability of the transistor DM, thereby significantly reducing the start-up time of the output voltage VOUT, i.e., the time required for it to reach the target value from 0 V.

[0032] Subsequently, when the output voltage VOUT becomes higher than the threshold voltage Vth, transistor M1 turns on. At this time, the voltage signal V1 is pulled down to a low level (≒VIN - I1 × R1) lower than the on-threshold voltage Vth (M2). Therefore, transistor M2 turns on. At this time, the voltage signal V2 is pulled up to a high level (≒I2 × R2 + GND) higher than the on-threshold voltage Vth (M3). Therefore, transistor M3 turns off. In other words, the connection between the application terminal of the output voltage VOUT and the application terminal of the input voltage VIN is opened. As a result, the output voltage VOUT continues to operate at a slope that corresponds to the current capability of transistor DM and the impedance of the load connected to the application terminal of the output voltage VOUT.

[0033] In this way, when the output voltage VOUT is higher than the threshold voltage Vth, and therefore when the voltage signal V1 is at a high level, the start-up circuit 20 does not support the current capability of the transistor DM, and therefore does not affect the operation of the constant voltage generating circuit 1 after the start-up of the output voltage VOUT is complete.

[0034] Furthermore, in the constant voltage generating circuit 1 of the first embodiment, the introduction of the capacitor C1 makes the output voltage VOUT less susceptible to input fluctuations. That is, as shown in FIG. 4 above, the amount of transient fluctuation in the output voltage VOUT caused by a sudden drop in the input voltage VIN is suppressed. Furthermore, the time required for the output voltage VOUT to return to the target value after fluctuation is also shortened. Therefore, both stable output and fast startup can be achieved.

[0035] Second Embodiment 8 is a diagram showing a second embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment is based on the first embodiment (FIG. 6) described above, and further includes transistors M4 and M5 (e.g., PMOSFETs) and resistors R3 and R4 as components of the start-up circuit 20.

[0036] The source and back gate of transistor M4 are both connected to the application terminal of input voltage VIN. The drain of transistor M4 is connected to the application terminal of voltage signal V4. The gate of transistor M4 is connected to the application terminal of voltage signal V1. Transistor M4 is turned on when the voltage signal V1 applied to the gate is lower than the on-threshold voltage Vth(M4) of transistor M4. On the other hand, transistor M4 is turned off when the voltage signal V1 is higher than the on-threshold voltage Vth(M4). A current signal I4 flows through transistor M4 in the on-state.

[0037] The source and back gate of transistor M5 are both connected to the application terminal of input voltage VIN. The drain of transistor M5 is connected to the connection node between resistors R1 and R3. The gate of transistor M5 is connected to the application terminal of voltage signal V4. Transistor M5 is turned on when the voltage signal V4 applied to the gate is lower than the on-threshold voltage Vth(M5) of transistor M5. On the other hand, transistor M5 is turned off when the voltage signal V4 is higher than the on-threshold voltage Vth(M5).

[0038] Resistors R1 and R3 are connected in series between the application terminal of the input voltage VIN and the application terminal of the voltage signal V1. When the transistor M5 is in the off state, the resistor R3 is incorporated as a component of the current / voltage conversion circuit IVC. Therefore, the current / voltage conversion circuit IVC converts the current signal I1 flowing through the transistor M1 into a voltage signal V1 (=VIN-I1×(R1+R3)) using the combined resistance (R1+R3) of the resistors R1 and R3. On the other hand, when the transistor M5 is in the on state, the resistor R3 is excluded from the components of the current / voltage conversion circuit IVC. Therefore, the current / voltage conversion circuit IVC converts the current signal I1 into a voltage signal V1 (=VIN-I1×R1) using the resistor R1.

[0039] The resistors R1 and R3 can be understood as a variable resistance circuit VR whose resistance value changes depending on the on / off state of the transistor M5. The current / voltage conversion circuit IVC passes the current signal I1 through the variable resistance circuit VR and converts it into a voltage signal V1.

[0040] Resistor R4 is connected between the application terminal of voltage signal V4 and the application terminal of ground voltage GND. Resistor R4 converts current signal I4 flowing through transistor M4 into voltage signal V4 (=I4×R4+GND).

[0041] When the output voltage VOUT is lower than the on-threshold voltage Vth(M1) of the transistor M1, the transistor M1 is turned off. At this time, V1≒VIN, so the transistor M2 is turned off. Therefore, V2≒GND, so the transistor M3 is turned on.

[0042] Furthermore, when transistor M1 is in the OFF state, transistor M4 is also in the OFF state. At this time, the voltage signal V4 is pulled down to a low level (≒GND) lower than the ON threshold voltage Vth(M5) of transistor M5 via resistor R4. Therefore, transistor M5 is in the ON state. In other words, resistor R3 is excluded from the components of the current / voltage conversion circuit IVC. As a result, the resistance value of the variable resistance circuit VR becomes equal to the resistance value of resistor R1.

[0043] After that, when the output voltage VOUT becomes higher than the threshold voltage Vth, the transistor M1 turns on. At this time, V1 is pulled down to V≒VIN-I1×R1, so the transistor M2 turns on. Therefore, V2 is pulled up to I2×R2+GND, so the transistor M3 turns off.

[0044] Furthermore, when transistor M1 is on, transistor M4 is on. At this time, the voltage signal V4 is pulled up to a high level (≈I4×R4+GND) higher than the on-threshold voltage Vth(M5) of transistor M5. Therefore, transistor M5 is turned off. That is, resistor R3 is incorporated as a component of the current / voltage conversion circuit IVC. At this time, the resistance value of the variable resistor circuit VR becomes equal to the combined resistance value (R1+R3) of resistors R1 and R3. As a result, the voltage signal V1 is further pulled down to VIN-I1×(R1+R3). In other words, it becomes difficult for transistor M2 to return to the off state.

[0045] In this way, among the components that form the start-up circuit 20, the transistors M4 and M5 and the resistor R4 can be understood as a hysteresis applying circuit HYS that applies hysteresis to the threshold voltage Vth (see FIG. 7) of the start-up circuit 20 by switching the resistance value of the variable resistance circuit VR in response to the voltage signal V1. The introduction of the hysteresis applying circuit HYS makes the start-up circuit 20 less susceptible to the effects of noise.

[0046] <Third embodiment> FIG. 9 is a diagram showing a third embodiment of the constant voltage generation circuit 1. The constant voltage generation circuit 1 of the present embodiment is based on the above-described first embodiment (FIG. 6), and further includes, as components of the startup circuit 20, a transistor M6 (e.g., NMOSFET), a resistor R5, a Schmitt buffer BUF, and an inverter INV.

[0047] The Schmitt buffer BUF receives an input of a voltage signal V1 and outputs a buffer output signal S1. The buffer output signal S1 switches from a low level to a high level when the voltage signal V1 becomes higher than the threshold voltage VthH. On the other hand, the buffer output signal S1 switches from a high level to a low level when the voltage signal V1 becomes lower than the threshold voltage VthL (where VthL < VthH).

[0048] The inverter INV inverts the logic level of the buffer output signal S1 to generate an inverter output signal S2. Therefore, the inverter output signal S2 becomes a low level when the buffer output signal S1 is at a high level. Also, the inverter output signal S2 becomes a high level when the buffer output signal S1 is at a low level.

[0049] The drain of the transistor M6 is connected to the application terminal of the voltage signal V6. Both the source and the back gate of the transistor M6 are connected to the application terminal of the ground voltage GND. The gate of the transistor M6 is connected to the application terminal of the inverter output signal S2. The transistor M6 turns on when the inverter output signal S2 applied to the gate is higher than the on-threshold voltage Vth(M6) of the transistor M6. On the other hand, the transistor M6 turns off when the inverter output signal S2 is lower than the on-threshold voltage Vth(M6). A current signal I6 flows through the on-state transistor M6.

[0050] Resistor R5 is connected between the application terminal of input voltage VIN and the application terminal of voltage signal V6. Resistor R5 converts current signal I6 flowing through transistor M6 into voltage signal V6 (=VIN-I6×R5). The gate of transistor M2 is connected to the application terminal of voltage signal V6, not the application terminal of voltage signal V1. In other words, start-up circuit 20 switches whether to supplement the current capability of transistor DM in response to buffer output signal S1.

[0051] In this way, among the components forming the start-up circuit 20, the transistor M6, the resistor R5, the Schmitt buffer BUF, and the inverter INV can be understood as a hysteresis applying circuit HYS that applies hysteresis to the threshold voltage Vth (see FIG. 7) of the start-up circuit 20. As with the second embodiment (FIG. 8) described above, the introduction of the hysteresis applying circuit HYS makes the start-up circuit 20 less susceptible to the effects of noise. Note that the hysteresis applying circuit HYS is not limited to the second embodiment (FIG. 8) and the third embodiment (FIG. 9), and may have other circuit configurations.

[0052] <Fourth embodiment> 10 is a diagram showing a fourth embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment is based on the first embodiment (FIG. 6) described above, and further includes a transistor M7 (e.g., an NMOSFET) as a component of the output circuit 10. The transistor M7 can be understood as a third output transistor.

[0053] The drain of the transistor M7 is connected to a terminal to which the input voltage VIN is applied. The source and back gate of the transistor M7 are connected to a terminal to which the output voltage VOUT is applied. The gate of the transistor M7 is connected to a terminal to which the node voltage Vx is applied. The transistor M7 is preferably an element having a current capability larger than that of the transistors DM and EM.

[0054] The transistor M7 functions as a voltage follower VF (a source follower in this figure). That is, in the constant voltage generating circuit 1 of this embodiment, the application terminal of the node voltage Vx is connected to the application terminal of the output voltage VOUT via the voltage follower VF. According to this embodiment, the current capability of the constant voltage generating circuit 1 is improved. Even with the introduction of the voltage follower VF, the output voltage VOUT is the gate-source voltage Vgs2 of the transistor EM, as in the first embodiment (FIG. 6) described above.

[0055] The gate of transistor EM is directly connected to the application terminal of output voltage VOUT. Therefore, negative feedback control is applied to transistor EM so that the output voltage VOUT is constant. Furthermore, the gate of transistor M1 is directly connected to the application terminal of output voltage VOUT. Therefore, the start-up circuit 20 switches whether to supplement the current capability of transistor DM depending on the output voltage VOUT, just like the first embodiment (FIG. 6) described above.

[0056] Fifth Embodiment 11 is a diagram showing a fifth embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment is based on the fourth embodiment (FIG. 10) described above, and further includes resistors R6 and R7 as components of the output circuit 10.

[0057] Resistor R6 is connected between the application terminal of output voltage VOUT and the application terminal of divided voltage Vd1. Resistor R7 is connected between the application terminal of divided voltage Vd1 and the application terminal of ground voltage GND. Resistors R6 and R7 connected in this manner function as a resistive voltage divider circuit DIV that divides the output voltage VOUT to generate divided voltage Vd1 (= VOUT × R7 / (R6 + R7)). The gates of transistors EM and M1 are both connected to the application terminal of divided voltage Vd1. The divided voltage Vd1 can be understood as an example of a node voltage that varies depending on the output voltage VOUT.

[0058] That is, in the constant voltage generating circuit 1 of this embodiment, the gate of the transistor EM is connected to the application terminal of the output voltage VOUT via the resistive voltage divider circuit DIV. With this configuration, the resistance values ​​of the resistors R6 and R7 (and therefore the voltage division ratio of the resistive voltage divider circuit DIV) are appropriately adjusted to generate an arbitrary output voltage VOUT (=Vgs2×(R6+R7) / R7).

[0059] Sixth Embodiment 12 is a diagram showing a sixth embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment is based on the fifth embodiment (FIG. 11) described above, and further includes a resistor R8 as a component of the output circuit 10.

[0060] Resistor R6 is connected between the application terminal of output voltage VOUT and the application terminal of divided voltage Vd1. Resistor R7 is connected between the application terminal of divided voltage Vd1 and the application terminal of divided voltage Vd2. Resistor R8 is connected between the application terminal of divided voltage Vd2 and the application terminal of ground voltage GND. The resistors R6, R7, and R8 connected in this manner function as a resistive voltage divider circuit DIV that divides the output voltage VOUT to generate divided voltage Vd1 (= VOUT × (R7 + R8) / (R6 + R7 + R8)) and divided voltage Vd2 (= VOUT × R8 / (R6 + R7 + R8)), respectively. The gate of transistor M1 is connected to the application terminal of divided voltage Vd1. The gate of transistor EM is connected to the application terminal of divided voltage Vd2. The divided voltages Vd1 and Vd2 can each be understood as examples of node voltages that vary depending on the output voltage VOUT.

[0061] In this embodiment, the threshold voltage Vth (see FIG. 7) of the start-up circuit 20, and therefore the time required for the transistor M1 to switch to the ON state after the input voltage VIN is applied, can be adjusted arbitrarily. For example, the threshold voltage Vth may be adjusted so that the transistor M1 switches to the ON state just before the output voltage VOUT reaches a target value.

[0062] Seventh Embodiment 13 is a diagram showing a seventh embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment is based on the first embodiment (FIG. 6) described above, and further includes resistors R9 and R10 as components of the output circuit 10.

[0063] The drain of transistor DM is connected to the application terminal of input voltage VIN. The source and back gate of transistor DM are both connected to a first terminal of resistor R9. The source and back gate of transistor EM are both connected to a first terminal of resistor R10. The second terminal of resistor R10 is connected to the application terminal of ground voltage GND. The gate of transistor DM, the gate and drain of transistor EM, and the second terminal of resistor R9 are all connected to the application terminal of node voltage Vx. The application terminal of node voltage Vx is directly connected to the application terminal of output voltage VOUT.

[0064] As such, resistor R9 is connected between the gate and source of transistor DM. Resistor R10 is also connected between the source of transistor EM and the terminal to which ground voltage GND is applied. In other words, resistors R9 and R10 are connected in series between the terminal to which input voltage VIN is applied and the terminal to which ground voltage GND is applied. As a result, a current I equal to the current I (=Vgs1 / R9) flowing through resistor R9 flows through resistor R10. Therefore, a voltage Vy (=Vgs1×(R10 / R9)) corresponding to the current I is generated across resistor R10.

[0065] Therefore, the constant voltage generating circuit 1 outputs the sum of the gate-source voltage Vgs2 of the transistor EM and the voltage Vy across the resistor R10 as the output voltage VOUT (=Vgs2+Vy).

[0066] The resistors R9 and R10 may be elements having the same temperature characteristic. For example, the resistors R9 and R10 may both be polysilicon resistors having a negative temperature characteristic. Alternatively, the resistors R9 and R10 may both be diffused resistors having a positive temperature characteristic.

[0067] Eighth Embodiment 14 is a diagram showing an eighth embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment is based on the seventh embodiment (FIG. 13) described above, but the gate of the transistor M1 is connected to the application terminal of the voltage Vy across the resistor R10, rather than the application terminal of the node voltage Vx. In this way, the gate of the transistor M1 does not necessarily have to be connected to the application terminal of the output voltage VOUT, and may be connected to the application terminal of a node voltage (for example, the voltage Vy across the resistor R10) that varies depending on the output voltage VOUT.

[0068] Ninth Embodiment 15 is a diagram showing a ninth embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment corresponds to a combination of the fourth embodiment (FIG. 10) and the seventh embodiment (FIG. 13). That is, the output circuit 10 may include the transistor M7 and resistors R9 and R10 described above.

[0069] Tenth Embodiment 16 is a diagram showing a tenth embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment is based on the previously described ninth embodiment (FIG. 15), but the gate of the transistor M1 is connected to the application terminal of the output voltage VOUT, not to the application terminal of the node voltage Vx. In this way, the output voltage VOUT may be directly applied to the gate of the transistor M1.

[0070] Eleventh Embodiment 17 is a diagram showing an eleventh embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment corresponds to a combination of the fifth embodiment (FIG. 11) and the seventh embodiment (FIG. 13). That is, the output circuit 10 may include resistors R6 and R7 in addition to the transistor M7 and resistors R9 and R10 described above.

[0071] <Combination of embodiments> The circuit configurations of the first to eleventh embodiments described above may be combined in any manner as long as no contradictions are present. For example, the hysteresis applying circuit HYS of the second embodiment (FIG. 8) or the third embodiment (FIG. 9) may be introduced based on the circuit configurations of the fourth to eleventh embodiments (FIGS. 10 to 17).

[0072] <Additional Notes> The constant voltage generating circuit according to the present disclosure can achieve both stable output and fast startup.

[0073] [Appendix 1] an output circuit (10) configured to generate a constant output voltage (VOUT) from an input voltage (VIN) using a first depletion mode output transistor (DM) and a second enhancement mode output transistor (EM); a start-up circuit (20) configured to switch whether or not to supplement the current capability of the first output transistor (DM) in accordance with the output voltage (VOUT) or node voltages (Vd1, Vd2, Vx, Vy) that vary depending on the output voltage (VOUT); A constant voltage generating circuit (1) comprising:

[0074] [Appendix 2] The constant voltage generating circuit (1) according to Appendix 1, wherein the start-up circuit (20) is in a state of assisting the current capacity of the first output transistor (DM) when the output voltage (VOUT) or the node voltages (Vd1, Vd2, Vx, Vy) are lower than a threshold voltage (Vth), and is in a state of not assisting the current capacity of the first output transistor (DM) when the output voltage (VOUT) or the node voltages (Vd1, Vd2, Vx, Vy) are higher than the threshold voltage (Vth).

[0075] [Appendix 3] The constant voltage generating circuit (1) described in Appendix 2, wherein the startup circuit (20) includes a transistor (M1) configured to have the output voltage (VOUT) or the node voltages (Vd1, Vd2, Vx, Vy) applied to a control electrode thereof, and a current / voltage conversion circuit (IVC) configured to convert a current signal (I1) flowing through the transistor (M1) into a voltage signal (V1), and switches whether or not to supplement the current capability of the first output transistor (DM) according to the voltage signal (V1).

[0076] [Appendix 4] 4. The constant voltage generating circuit (1) according to claim 3, wherein the startup circuit (20) further includes a hysteresis applying circuit (HYS) configured to apply hysteresis to the threshold voltage (Vth).

[0077] [Appendix 5] The constant voltage generating circuit (1) described in Appendix 4, wherein the current / voltage conversion circuit (IVC) passes the current signal (I1) through a variable resistance circuit (VR) to convert it into the voltage signal (V1), and the hysteresis imparting circuit (HYS) switches the resistance value of the variable resistance circuit (VR) according to the voltage signal (V1).

[0078] [Appendix 6] The constant voltage generating circuit (1) described in Appendix 4, wherein the hysteresis applying circuit (HYS) includes a Schmitt buffer (BUF) configured to receive an input of the voltage signal (V1), and the startup circuit (20) switches whether to supplement the current capability of the first output transistor (DM) depending on an output signal (S1) of the Schmitt buffer (BUF).

[0079] [Appendix 7] The constant voltage generating circuit (1) according to any one of appendices 1 to 6, wherein the output circuit (10) further includes a third output transistor (M7) having a first main electrode connected to an application terminal of the input voltage (VIN), a second main electrode connected between the application terminal of the output voltage (VOUT), and a control electrode connected to the first main electrode of the second output transistor (EM).

[0080] [Appendix 8] The constant voltage generating circuit (1) according to any one of appendices 1 to 7, wherein a control electrode of the second output transistor (EM) is connected to an application terminal of the output voltage (VOUT) directly or via a resistive voltage dividing circuit (DIV).

[0081] [Appendix 9] The output circuit (10) a first resistor (R9) connected between the control electrode and the second main electrode of the first output transistor (DM); a second resistor (R10) connected to the second output transistor (EM) so that a current (I) having the same value as the current (I) flowing through the first resistor (R9) flows; further comprising The constant voltage generating circuit (1) according to any one of appendices 1 to 8, which outputs, as the output voltage (VOUT), a voltage (Vgs2+Vy) obtained by adding together an inter-electrode voltage (Vgs2) between the control electrode and the second main electrode of the second output transistor (EM) and a voltage (Vy) across the second resistor (R10), or a voltage corresponding thereto.

[0082] [Appendix 10] 10. The constant voltage generating circuit (1) according to any one of appendices 1 to 9, further comprising a capacitor (C1) configured to smooth the output voltage (VOUT).

[0083] <Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0084] 1 Constant voltage generation circuit 10 Output circuit 20 Starter circuit BUF Schmitt buffer C1 capacitor DIV Resistor voltage divider circuit DM transistor (depletion-type NMOSFET) EM transistor (enhancement type NMOSFET) HYS Hysteresis circuit INV Inverter IVC Current / Voltage Conversion Circuit M1, M6, M7 transistors (NMOSFET) M2~M5 transistors (PMOSFET) R1~R10 Resistors VF Voltage Follower VR variable resistor circuit

Claims

1. an output circuit configured to generate a constant output voltage from an input voltage using a first output transistor of a depletion mode and a second output transistor of an enhancement mode; a start-up circuit configured to switch whether to supplement the current capability of the first output transistor in response to the output voltage or a node voltage that varies depending on the output voltage; A constant voltage generating circuit comprising:

2. 2. The constant voltage generating circuit according to claim 1, wherein the startup circuit is in a state of assisting the current capability of the first output transistor when the output voltage or the node voltage is lower than a threshold voltage, and is in a state of not assisting the current capability of the first output transistor when the output voltage or the node voltage is higher than the threshold voltage.

3. 3. The constant voltage generating circuit according to claim 2, wherein the startup circuit includes a transistor configured to have the output voltage or the node voltage applied to a control electrode thereof, and a current / voltage conversion circuit configured to convert a current signal flowing through the transistor into a voltage signal, and switches whether or not to supplement the current capability of the first output transistor in response to the voltage signal.

4. 4. The constant voltage generating circuit according to claim 3, wherein the startup circuit further includes a hysteresis applying circuit configured to apply hysteresis to the threshold voltage.

5. 5. The constant voltage generating circuit according to claim 4, wherein the current / voltage conversion circuit passes the current signal through a variable resistance circuit to convert it into the voltage signal, and the hysteresis applying circuit switches the resistance value of the variable resistance circuit in response to the voltage signal.

6. 5. The constant voltage generating circuit according to claim 4, wherein the hysteresis applying circuit includes a Schmitt buffer configured to receive the voltage signal as an input, and the startup circuit switches between assisting the current capability of the first output transistor and not assisting it depending on the output signal of the Schmitt buffer.

7. 2. The constant voltage generating circuit according to claim 1, wherein the output circuit further includes a third output transistor having a first main electrode connected to the input voltage application terminal, a second main electrode connected between the input voltage application terminal and the output voltage application terminal, and a control electrode connected to the first main electrode of the second output transistor.

8. 2. The constant voltage generating circuit according to claim 1, wherein a control electrode of said second output transistor is connected to an application terminal of said output voltage directly or via a resistive voltage dividing circuit.

9. The output circuit a first resistor connected between the control electrode and the second main electrode of the first output transistor; a second resistor connected to the second output transistor so that a current having the same value as the current flowing through the first resistor flows; further comprising 2. The constant voltage generating circuit according to claim 1, wherein the output voltage is a voltage obtained by adding together an inter-electrode voltage between the control electrode and the second main electrode of the second output transistor and a voltage across the second resistor, or a voltage corresponding thereto.

10. 10. The constant voltage generating circuit according to claim 1, further comprising a capacitor configured to smooth the output voltage.

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