Silicon carbide semiconductor device
Patent Information
- Application Number
- JP2024080146
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-05-16
- Publication Date
- 2025-11-28
Smart Images
Figure 2025174092000001_ABST
Abstract
Description
[Technical Field]
[0001] The present disclosure relates to silicon carbide semiconductor devices. [Background technology]
[0002] Conventionally, semiconductor devices having a superjunction structure have been disclosed. [Prior art documents] [Patent documents]
[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-273355 Summary of the Invention [Problem to be solved by the invention]
[0004] In conventional semiconductor devices, it is difficult to further improve the breakdown voltage.
[0005] An object of the present disclosure is to provide a silicon carbide semiconductor device that can improve breakdown voltage. [Means for solving the problem]
[0006] A silicon carbide semiconductor device according to the present disclosure comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and having, in a plan view perpendicular to the first main surface, an active region and a termination region surrounding the active region, the silicon carbide substrate having a first semiconductor region having a first conductivity type, a plurality of second semiconductor regions having a second conductivity type provided within the first semiconductor region, and a third semiconductor region having the second conductivity type provided within the active region, constituting the first main surface and having an annular shape in the plan view, The regions are aligned in the active region and the termination region along a first axis parallel to the first major surface and extend along a second axis parallel to the first major surface and perpendicular to the first axis, the second semiconductor region has at least two fourth semiconductor regions and a fifth semiconductor region between the fourth semiconductor regions, the fourth semiconductor regions are located at at least both ends of the second semiconductor region, and an effective concentration of the first impurity of the second conductivity type contained in the fourth semiconductor regions is lower than an effective concentration of the first impurity contained in the fifth semiconductor region. [Effects of the Invention]
[0007] According to the present disclosure, the breakdown voltage can be improved. [Brief explanation of the drawings]
[0008] [Figure 1] FIG. 1 is a schematic diagram showing an overview of a silicon carbide substrate in a silicon carbide semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing the configuration of an interlayer insulating film and a first main surface in an active region of the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view showing the configuration of the active region of the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 4] FIG. 4 is a diagram showing the configurations of the p-type region and the drift region in the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view showing a configuration in the vicinity of the boundary between the active region and the termination region of the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 6]FIG. 6 is a cross-sectional view (part 1) illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 2) illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 3) illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 4) illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a configuration in the vicinity of the boundary between the active region and the termination region of a silicon carbide semiconductor device according to a modification of the first embodiment. [Figure 11] FIG. 11 is a diagram showing the configurations of the p-type region and the drift region in the silicon carbide semiconductor device according to the second embodiment. [Figure 12] FIG. 12 is a diagram showing configurations of a p-type region and a drift region in a silicon carbide semiconductor device according to a modification of the second embodiment. In FIG. [Figure 13] FIG. 13 is a cross-sectional view showing a configuration in the vicinity of the boundary between the active region and the termination region of a silicon carbide semiconductor device according to a modification of the second embodiment. [Figure 14] FIG. 14 is a diagram showing the configurations of the p-type region and the drift region in the silicon carbide semiconductor device in accordance with the third embodiment. [Figure 15] FIG. 15 is a cross-sectional view showing a configuration in the vicinity of the boundary between the active region and the termination region of the silicon carbide semiconductor device in accordance with the third embodiment. [Figure 16] FIG. 16 is a diagram showing the configurations of the p-type region and the drift region in the silicon carbide semiconductor device according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION
[0009] The embodiments for carrying out the invention are described below.
[0010] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, identical or corresponding elements will be denoted by the same reference numerals, and the same description will not be repeated. In the crystallographic descriptions in this specification, individual orientations are represented by brackets [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. A negative index in crystallography is usually represented by placing a "-" (bar) above a number, but in this disclosure, a negative sign is placed before the number. In the following description, an XYZ Cartesian coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of the silicon carbide semiconductor device. An XY plane view is referred to as a planar view, and the +Z direction from an arbitrary point may be referred to as upward, upper side, or top, and the -Z direction may be referred to as downward, lower side, or bottom.
[0011] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and having, in a plan view perpendicular to the first main surface, an active region and a termination region surrounding the active region, the silicon carbide substrate including: a first semiconductor region having a first conductivity type; a plurality of second semiconductor regions having a second conductivity type provided in the first semiconductor region; and a third semiconductor region having the second conductivity type provided in the active region, constituting the first main surface and having an annular shape in the plan view; The conductor regions are aligned within the active region and the termination region along a first axis parallel to the first major surface and extend along a second axis parallel to the first major surface and perpendicular to the first axis, the second semiconductor region has at least two fourth semiconductor regions and a fifth semiconductor region between the fourth semiconductor regions, the fourth semiconductor regions are located at at least both ends of the second semiconductor region, and an effective concentration of the first impurity of the second conductivity type contained in the fourth semiconductor regions is lower than the effective concentration of the first impurity contained in the fifth semiconductor region.
[0012] Compared to when the effective concentration of the first impurity contained in the fourth semiconductor region is equal to the effective concentration of the first impurity contained in the fifth semiconductor region, depletion in the vicinity of the fourth semiconductor region is promoted and the electric field applied to the fourth semiconductor region is alleviated, thereby improving the breakdown voltage.
[0013] [2] In [1], the second semiconductor region may have four or more of the fourth semiconductor regions, and the fourth semiconductor regions and the fifth semiconductor regions may be arranged alternately along the second axis. In this case, depletion is more likely to be promoted.
[0014] [3] In [2], the dimension of the fourth semiconductor region in the direction along the second axis may increase as it approaches an end of the second semiconductor region. In this case, the change in the electric field becomes gentler, making it more difficult for electric field concentration to occur.
[0015] [4] In any one of [1] to [3], the first semiconductor region may have a sixth semiconductor region between the fourth semiconductor regions adjacent along the first axis and a seventh semiconductor region between the fifth semiconductor regions adjacent along the first axis, and an effective concentration of the second impurity of the first conductivity type contained in the sixth semiconductor region may be higher than an effective concentration of the second impurity contained in the seventh semiconductor region. In this case, the fourth semiconductor region may be easily formed by ion implantation of the first conductivity type impurity.
[0016] [5] In any one of [1] to [4], the fifth semiconductor region may include an eighth semiconductor region overlapping the third semiconductor region in a planar view and electrically connected to the third semiconductor region, a ninth semiconductor region in the termination region, and a tenth semiconductor region in the active region spaced apart from the third semiconductor region in a planar view, wherein the first width of the tenth semiconductor region is smaller than the second width of the ninth semiconductor region. In this case, the breakdown voltage in the active region is lower than the breakdown voltage in the termination region, and avalanche current is more likely to disperse within the active region when avalanche breakdown occurs. This improves avalanche resistance.
[0017] [6] In [5], the first width may be smaller than the third width of the eighth semiconductor region. In this case, the avalanche resistance can also be improved.
[0018] [7] In any one of [1] to [6], the second semiconductor regions may be provided at a constant pitch along the first axis, which makes it easier to obtain high uniformity in breakdown voltage within the silicon carbide semiconductor device.
[0019] [Embodiments of the present disclosure] (First embodiment) A first embodiment will be described. The first embodiment relates to a so-called vertical MOS (metal oxide semiconductor) field effect transistor (FET) using silicon carbide. This MOS FET is an example of a silicon carbide semiconductor device. FIG. 1 is a schematic diagram showing an overview of a silicon carbide substrate in the silicon carbide semiconductor device according to the first embodiment. FIG. 2 is a diagram showing the configuration of an interlayer insulating film and a first main surface in an active region of the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view showing the configuration of the active region of the silicon carbide semiconductor device according to the first embodiment. FIG. 4 is a diagram showing the configuration of a p-type region and a drift region in the silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view showing the configuration near the boundary between the active region and the termination region of the silicon carbide semiconductor device according to the first embodiment. FIG. 2 corresponds to region II in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. FIG. 4 corresponds to region IV in FIG. 1. FIG. 5 is a cross-sectional view taken along line VV in FIG. 4. A barrier metal film 84 is omitted in FIG. 5.
[0020] As shown in Figures 1 to 5, the silicon carbide semiconductor device 100 according to the first embodiment has a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, and a barrier metal film 84.
[0021] The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane, and the first main surface 1 is in the +Z direction when viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide epitaxial layer 40 forms the first main surface 1, and the silicon carbide single crystal substrate 50 forms the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, hexagonal silicon carbide of polytype 4H. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has an n-type conductivity (first conductivity type).
[0022] As shown in FIG. 1 , silicon carbide substrate 10 has active region 110 and termination region 120. Active region 110 has, for example, a square shape with rounded corners in a plan view perpendicular to first main surface 1. Active region 110 may also have a rectangular shape with rounded corners in a plan view. Termination region 120 surrounds active region 110 in a plan view. Termination region 120 is provided around active region 110 in a plan view. Termination region 120 has a first termination region 121 that contacts active region 110 in a direction parallel to the Y-axis, a second termination region 122 that contacts active region 110 in a direction parallel to the X-axis, and a third termination region 123 that contacts first termination region 121 and second termination region 122. First termination regions 121 are provided on the +Y and −Y sides of active region 110, second termination regions 122 are provided on the +X and −X sides of active region 110, and third termination regions 123 are provided at the four corners of silicon carbide substrate 10.
[0023] The first main surface 1 is a {0001} plane or a plane inclined at an off angle of 8° or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a plane inclined at an off angle of 8° or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.
[0024] The silicon carbide epitaxial layer 40 has a drift region 11, a body region 12, a source region 13, a p-type region 14 for a superjunction, a contact region 16, a junction termination extension (JTE) 17, and a contact region 18.
[0025] Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. Drift region 11 is provided on silicon carbide single crystal substrate 50.
[0026] The body region 12 contains p-type impurities such as aluminum (Al) and has p-type conductivity. The body region 12 is located within the active region 110. The body region 12 is provided on the drift region 11. The lower end surface of the body region 12 and the upper end surface of the drift region 11 are in contact with each other.
[0027] The source region 13 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity. The source region 13 is located within the active region 110. The source region 13 is provided on the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. The source region 13 constitutes the first main surface 1.
[0028] A plurality of gate trenches 5 defined by side surfaces 3 and bottom surfaces 4 are provided on the first main surface 1. The gate trenches 5 are formed in the active region 110. The gate trenches 5 extend, for example, along the Y axis. A plurality of gate trenches 5 are also provided along the X axis at regular intervals (first pitch P1). The side surfaces 3 penetrate the source region 13, the body region 12, and part of the drift region 11, and reach the drift region 11. The bottom surfaces 4 are continuous with the side surfaces 3. The bottom surfaces 4 are located in the drift region 11. For example, the bottom surfaces 4 are parallel to the first main surface 1 and the second main surface 2. In a cross-sectional view perpendicular to the Y axis, the angle θ1 of the side surfaces 3 with respect to an imaginary plane 30 including the bottom surfaces 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surfaces 3 preferably have a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility.
[0029] The contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 18 is located within the active region 110. The contact region 18 penetrates the source region 13 and is in contact with the body region 12. The contact region 18 constitutes the first main surface 1. In a plan view perpendicular to the first main surface 1, the contact region 18 is located between gate trenches 5 adjacent to each other along the X-axis. The contact regions 18 and the source regions 13 may be alternately provided along the Y-axis between two gate trenches 5 adjacent to each other along the X-axis. The contact regions 18 may be provided intermittently along the Y-axis between two gate trenches 5 adjacent to each other along the X-axis.
[0030] A plurality of gate trenches 5 may be arranged at regular intervals along the Y axis. When a plurality of gate trenches 5 are arranged at regular intervals along the Y axis, a part of the contact region 18 may be located between adjacent gate trenches 5 along the Y axis. A plurality of gate trenches 5 may be provided in an array.
[0031] The contact region 16 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 16 is located within the active region 110. The contact region 16 is formed simultaneously with the contact region 18, is made of the same material as the contact region 18, and has the same depth as the contact region 18. The contact region 16 also constitutes the first main surface 1. In a plan view, the contact region 16 is provided in an annular shape, and a plurality of gate trenches 5 and a gate electrode 82 (described below) are located inside the contact region 16. The outer edge of the contact region 16 is the boundary between the active region 110 and the termination region 120. In this disclosure, the term "annular" includes a shape that is a single closed curve other than a circular annular shape or an elliptical annular shape, such as a rounded rectangular shape. The contact region 16 is an example of a third semiconductor region.
[0032] JTE 17 contains p-type impurities such as aluminum at an effective concentration lower than that of contact region 16, and has p-type conductivity. JTE 17 is provided in an annular shape so as to be in contact with contact region 16. In a plan view, contact region 16 is located inside JTE 17. JTE 17 is located within termination region 120. JTE 17 also constitutes first main surface 1. JTE 17 is provided inside the outer edge of silicon carbide substrate 10, and first main surface 1 at the outer edge of silicon carbide substrate 10 is constituted by drift region 11.
[0033] P-type region 14 contains p-type impurities such as aluminum and has p-type conductivity. P-type region 14 is in active region 110 and termination region 120. P-type region 14 is provided within drift region 11. P-type region 14 may extend along the Y-axis. Multiple p-type regions 14 are aligned along the X-axis. Multiple p-type regions 14 may be provided at a regular pitch along the X-axis. Multiple p-type regions 14 may be provided in a stripe pattern. The X-axis is an example of a first axis, and the Y-axis is an example of a second axis.
[0034] As shown in FIG. 3 , a portion of the p-type region 14 is located between adjacent gate trenches 5 along the X-axis in a plan view perpendicular to the first main surface 1. A p-type region 142, which is part of the p-type region 14 and located between adjacent gate trenches 5 along the X-axis, is spaced apart from the gate trench 5. The body region 12 is exposed at the side surface 3 of the gate trench 5. The p-type region 142 is spaced apart from the gate trench 5 along the X-axis more than the body region 12 is. The p-type region 142 is located below the body region 12 and in contact with the body region 12. The p-type region 142 overlaps the contact region 18 and is located inside the contact region 16 in a plan view perpendicular to the first main surface 1. The contact region 18 may penetrate the body region 12, and the p-type region 142 may be in contact with the body region 12 and the contact region 18. The contact region 18, the body region 12, and the p-type region 142 are electrically connected to one another. The p-type region 142 is an example of a second semiconductor region. The p-type impurity is an example of the first impurity of the second conductivity type.
[0035] 4 and 5, p-type region 142 has two p-type regions 144 and p-type region 145 between p-type regions 144. P-type regions 144 are located at both ends of p-type region 142. P-type region 144 is located in first termination region 121 and is away from JTE 17. The effective concentration of p-type impurities contained in p-type region 144 is lower than the effective concentration of p-type impurities contained in p-type region 145. The effective concentration of p-type impurities contained in p-type region 144 is, for example, 5×10 15 cm -3 3x10 or more 17 cm -3 The effective concentration of the p-type impurity contained in the p-type region 145 is, for example, 1×10 16 cm -3 5x10 or more 17 cm -3 The effective concentration of the p-type impurity contained in p-type region 144 and the effective concentration of the p-type impurity contained in p-type region 145 do not need to be uniform. P-type region 144 is an example of a fourth semiconductor region, and p-type region 145 is an example of a fifth semiconductor region.
[0036] P-type region 145 has p-type regions 148, 149, and 1410. P-type region 148 overlaps contact region 16 in a plan view and is electrically connected to contact region 16. P-type region 148 may be in direct contact with contact region 16. P-type region 149 is located within termination region 120. P-type region 1410 is located within active region 110 and is spaced apart from contact region 16 in a plan view. A first width W1 of p-type region 1410, a second width W2 of p-type region 149, and a third width W3 of p-type region 148 may be equal to one another. P-type region 148 is an example of an eighth semiconductor region, p-type region 149 is an example of a ninth semiconductor region, and p-type region 1410 is an example of a tenth semiconductor region.
[0037] In the active region 110, the drift region 11 is exposed to the side surface 3 and is in contact with the body region 12 and the p-type region 142. In the termination region 120, the drift region 11 forms the first main surface 1 outside the JTE 17 in a plan view. The drift region 11 may be in contact with the silicon carbide single crystal substrate 50. The effective concentration of the n-type impurity in the drift region 11 is, for example, 1×10 16 cm -3 5x10 or more 17 cm -3 The drift region 11 may include a current spreading region having a particularly high effective concentration of n-type impurities within the active region 110. The drift region 11 is an example of a first semiconductor region.
[0038] Along the Z axis, silicon carbide single crystal substrate 50 and drift region 11 are present between bottom surface 4 and second main surface 2, and the conductivity type of silicon carbide substrate 10 between bottom surface 4 and second main surface 2 is n-type. Along the Z axis, no semiconductor with p-type conductivity exists between bottom surface 4 and second main surface 2.
[0039] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the drift region 11 at the bottom surface 4. The gate insulating film 81 contacts the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 may also contact the source region 13 at the first main surface 1.
[0040] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. The gate electrode 82 faces the side surface 3 and the bottom surface 4. A portion of the gate electrode 82 may face the first main surface 1. The gate electrode 82 extends along the Y-axis. In a plan view perpendicular to the first main surface 1, the gate electrode 82 may overlap multiple gate trenches 5.
[0041] A gate insulating film 81 is also provided on the contact region 16, and an electrode film 85 is formed thereon. The electrode film 85 is formed simultaneously with the gate electrode 82, and is made of the same material as the gate electrode 82.
[0042] The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other. A part of the interlayer insulating film 83 may be provided inside the gate trench 5. The upper surface of the interlayer insulating film 83 may be a curved surface whose curvature changes continuously. The upper surface of the interlayer insulating film 83 may be a curved surface that is convex in the +Z direction above the gate trench 5.
[0043] Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals along the X-axis. The contact holes 90 are arranged such that the gate trench 5 is located between adjacent contact holes 90 along the X-axis. The contact holes 90 extend along the Y-axis. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.
[0044] Above the contact region 16, an interlayer insulating film 83 is provided on the gate insulating film 81 and the electrode film 85. A contact hole 91 is formed in the interlayer insulating film 83, reaching the electrode film 85, and a contact hole 92 is formed in the interlayer insulating film 83 and the gate insulating film 81, reaching the contact region 16. The silicon carbide semiconductor device 100 has a gate runner 63 and a source runner 64. The gate runner 63 and the source runner 64 are formed simultaneously with the source electrode 60 and are made of the same material as the source electrode 60. The gate runner 63 is electrically connected to the gate electrode 82 and the electrode film 85. The source runner 64 is electrically connected to the source electrode 60 and the contact region 16. In a plan view, the source runner 64 is provided in an annular shape, and the outer edge of the source runner 64 may coincide with the outer edge of the contact region 16. The gate runner 63 is provided between the source electrode 60 and the source runner 64.
[0045] The barrier metal film 84 covers the upper surface of the interlayer insulating film 83 and the side surface of the gate insulating film 81. The barrier metal film 84 is in contact with the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).
[0046] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 provided in a contact hole 90 and a source wiring 62. The contact electrode 61 is in contact with the source region 13, the contact region 16, and the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), aluminum, and silicon. The contact electrode 61 forms an ohmic junction with the source region 13, the contact region 16, and the contact region 18. The source wiring 62 covers the upper surface and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the barrier metal film 84 and the contact electrode 61. The source wiring 62 is made of a material containing, for example, aluminum.
[0047] Silicon carbide semiconductor device 100 further has silicon nitride film 87 and polyimide film 88. Silicon nitride film 87 covers the upper surface and side surfaces of interlayer insulating film 83, and polyimide film 88 covers the upper surface and side surfaces of silicon nitride film 87. An opening exposing a portion of source electrode 60 is formed in silicon nitride film 87 and polyimide film 88, and a source plating film 86 is formed inside this opening. Silicon nitride film 87 and polyimide film 88 also have an opening (not shown) exposing a portion of a gate electrode (not shown) connected to gate runner 63, and a gate plating film (not shown) is formed inside this opening.
[0048] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing nickel silicide, for example. The drain electrode 70 may also be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 is in ohmic contact with the silicon carbide single crystal substrate 50.
[0049] A buffer layer containing n-type impurities such as nitrogen and having n-type conductivity may be provided between silicon carbide single crystal substrate 50 and drift region 11. Also, a passivation film covering a portion of source electrode 60 may be provided.
[0050] The effective concentration of p-type impurities in the contact regions 16 and 18 may be higher than the effective concentration of p-type impurities in the body region 12. For example, the effective concentration of p-type impurities in the contact regions 16 and 18 may be, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The effective concentration of p-type impurities in the body region 12 is 5×10 17 cm -3 More than 1×10 18 cm -3 The following is the result.
[0051] The effective concentration of n-type impurities in the source region 13 may be higher than the effective concentration of p-type impurities in the body region 12. The effective concentration of n-type impurities in the source region 13 may be, for example, 1×10 19 cm -3 That's about it.
[0052] In the present disclosure, the effective concentration of a first conductivity type impurity is the concentration obtained by subtracting the concentration of a second conductivity type impurity from the concentration of the first conductivity type impurity, and the effective concentration of a second conductivity type impurity is the concentration obtained by subtracting the concentration of the first conductivity type impurity from the concentration of the second conductivity type impurity. The effective concentrations can be measured using, for example, a scanning capacitance microscope (SCM). The effective concentration of an impurity contained in each region is the average value of the effective concentrations of the impurities contained in that region.
[0053] Drift region 11 has n-type conductivity, and body region 12 and p-type region 14 have p-type conductivity, so the boundary between drift region 11 and body region 12 and the boundary between drift region 11 and p-type region 14 are clear.
[0054] Next, a description will be given of a method for manufacturing silicon carbide semiconductor device 100. Figures 6 to 9 are cross-sectional views illustrating the method for manufacturing silicon carbide semiconductor device 100 according to the first embodiment.
[0055] First, as shown in Fig. 6, a silicon carbide single crystal substrate 50 is prepared. Next, a silicon carbide epitaxial layer 40 is formed on the silicon carbide single crystal substrate 50. For example, the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has n-type conductivity. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of n-type impurities such as nitrogen.
[0056] 7 , ions are implanted into silicon carbide epitaxial layer 40 to form p-type region 14. The ion implantation for forming p-type region 14 involves channeling implantation of p-type impurities such as aluminum. At this time, the upper end surface of p-type region 14 may be exposed from the upper surface of silicon carbide epitaxial layer 40.
[0057] Next, as shown in FIG. 8, ions are implanted into the silicon carbide epitaxial layer 40 to form the body region 12, the source region 13, the contact region 16, the JTE 17, and the contact region 18. As shown in FIG.
[0058] 9, ions of n-type impurities such as phosphorus (P) or nitrogen (N) are implanted into a portion of p-type region 14 to form p-type region 144. As a result of implanting the n-type impurities, the dimension of p-type region 144 along the X-axis may become larger than the dimension of p-type region 14 other than p-type region 144 (p-type region 145) along the X-axis.
[0059] Next, a plurality of gate trenches 5 are formed. Next, a gate insulating film 81, a gate electrode 82, an electrode film 85, an interlayer insulating film 83, a barrier metal film 84, a silicon nitride film 87, a polyimide film 88, and a plating film 86 are formed (see FIG. 5).
[0060] In this manner, silicon carbide semiconductor device 100 can be manufactured.
[0061] In silicon carbide semiconductor device 100, as described above, the effective concentration of the p-type impurity contained in p-type region 144 is lower than the effective concentration of the p-type impurity contained in p-type region 145. Therefore, compared to when the effective concentration of the p-type impurity contained in p-type region 144 is equal to the effective concentration of the p-type impurity contained in p-type region 145, depletion in the vicinity of p-type region 144 is promoted and the electric field applied to p-type region 144 is alleviated. Therefore, the breakdown voltage can be improved.
[0062] If the effective concentration of n-type impurities contained in the drift region 11 becomes low or the effective concentration of p-type impurities contained in the p-type region 142 becomes high due to manufacturing variations, etc., the electric field tends to concentrate near both ends of the p-type region 142, but even in such cases, an excellent breakdown voltage can be obtained.
[0063] Note that p-type region 14 provided in second termination region 122 may have p-type regions 144 and 145, similar to p-type region 142. When p-type region 14 provided in second termination region 122 and electrically connected to JTE 17 has p-type regions 144 and 145, depletion is also promoted in the vicinity of p-type region 144 of p-type region 14.
[0064] The first width W1 of p-type region 1410 may be smaller than the second width W2 of p-type region 149. If first width W1 is smaller than second width W2, the breakdown voltage in active region 110 will be lower than the breakdown voltage in first termination region 121, and the avalanche current generated when avalanche breakdown occurs will be more likely to disperse within active region 110. This improves the avalanche resistance. Similarly, the avalanche resistance can also be improved by making first width W1 smaller than third width W3 of p-type region 148.
[0065] When multiple p-type regions 14 are provided at a constant pitch along the X-axis, it is easy to obtain high uniformity in the breakdown voltage within silicon carbide semiconductor device 100. When multiple p-type regions 14 extend along the Y-axis, it is easy to form p-type regions 14 uniformly.
[0066] (Modification of the first embodiment) A modification of the first embodiment will be described. The modification of the first embodiment differs from the first embodiment mainly in the configurations of p-type region 14 and drift region 11. Fig. 10 is a cross-sectional view showing the configuration near the boundary between the active region and the termination region of a silicon carbide semiconductor device according to the modification of the first embodiment.
[0067] 10 , in silicon carbide semiconductor device 101 according to the modification of the first embodiment, p-type region 144 is formed shallower than in the first embodiment, and the lower end of p-type region 144 is higher than the lower end of p-type region 142. Drift region 11 may have n-type region 1111 between the upper end of p-type region 144 and first main surface 1. The effective concentration of n-type impurities contained in n-type region 1111 is higher than the effective concentration of n-type impurities contained in drift region 11 other than n-type region 1111.
[0068] Other configurations of silicon carbide semiconductor device 101 are the same as those of silicon carbide semiconductor device 100. The modified example of the first embodiment also achieves the same effects as those of the first embodiment. Furthermore, because the lower end of p-type region 144 is higher than the lower end of p-type region 142, depletion in the vicinity of p-type region 144 is promoted, but excessive depletion is unlikely to occur.
[0069] (Second embodiment) A second embodiment will now be described. The second embodiment differs from the first embodiment mainly in the configuration of drift region 11. Fig. 11 is a diagram showing the configurations of a p-type region and a drift region in a silicon carbide semiconductor device according to the second embodiment.
[0070] As shown in FIG. 11 , in the silicon carbide semiconductor device 200 according to the second embodiment, the drift region 11 includes an n-type region 116 located between adjacent p-type regions 144 along the X-axis and an n-type region 117 located between adjacent p-type regions 145 along the X-axis. The effective concentration of the n-type impurity contained in the n-type region 116 is higher than the effective concentration of the n-type impurity contained in the n-type region 117. For example, the effective concentration of the n-type impurity contained in the n-type region 117 is equal to the effective concentration of the n-type impurity contained in the drift region 11 in the first embodiment, and the effective concentration of the n-type impurity contained in the n-type region 116 is equal to the effective concentration of the n-type impurity contained in the n-type region 1111 in the modification of the first embodiment. The n-type region 116 is an example of a sixth semiconductor region, and the n-type region 117 is an example of a seventh semiconductor region. The n-type impurity is an example of an impurity of the first conductivity type.
[0071] Other configurations of silicon carbide semiconductor device 200 are the same as those of silicon carbide semiconductor device 100. As with the first embodiment, the second embodiment can also improve the breakdown voltage. Furthermore, the plurality of p-type regions 144 and the plurality of n-type regions 116 can be formed by ion implantation of n-type impurities through one opening in a mask.
[0072] Silicon carbide semiconductor device 200 may have n-type regions 1111 as in the modification of the first embodiment, and in this case, n-type regions 116 may also be located between n-type regions 1111 adjacent to each other along the X-axis.
[0073] (Modification of the second embodiment) A modification of the second embodiment will be described. The modification of the second embodiment differs from the second embodiment mainly in the configurations of the p-type region 14 and the drift region 11. FIG. 12 is a diagram showing the configuration of the p-type region and the drift region in a silicon carbide semiconductor device according to a modification of the second embodiment. FIG. 13 is a cross-sectional view showing the configuration near the boundary between the active region and the termination region of a silicon carbide semiconductor device according to a modification of the second embodiment. FIG. 13 corresponds to a cross-sectional view taken along line XIII-XIII in FIG. 12. Barrier metal film 84 is omitted in FIG. 13.
[0074] 12 and 13 , in a silicon carbide semiconductor device 201 according to a modification of the second embodiment, similar to silicon carbide semiconductor device 101, p-type region 144 is formed shallower than in the first embodiment, and drift region 11 has an n-type region 1111. In silicon carbide semiconductor device 201, drift region 11 further has an n-type region 1112. N-type region 1112 contacts p-type region 144 and n-type region 1111 on the +Y side of p-type region 144 and n-type region 1111. The effective concentration of n-type impurities contained in n-type region 1112 is equal to the effective concentration of n-type impurities contained in n-type region 1111.
[0075] Other configurations of silicon carbide semiconductor device 201 are the same as those of silicon carbide semiconductor device 200. The modified example of the second embodiment also provides the same effects as those of the second embodiment. Furthermore, multiple p-type regions 144, multiple n-type regions 116, multiple n-type regions 1111, and n-type region 1112 can be formed by ion implantation of n-type impurities through one opening in a mask, which provides a large tolerance (margin) when forming p-type region 144.
[0076] (Third embodiment) A third embodiment will be described. The third embodiment differs from the modified example of the first embodiment mainly in the configurations of the p-type region 14 and the drift region 11. FIG. 14 is a diagram showing the configuration of the p-type region and the drift region in a silicon carbide semiconductor device according to the third embodiment. FIG. 15 is a cross-sectional view showing the configuration near the boundary between the active region and the termination region of the silicon carbide semiconductor device according to the third embodiment. FIG. 15 corresponds to a cross-sectional view taken along line XV-XV in FIG. 14. A barrier metal film 84 is omitted in FIG. 15.
[0077] As shown in FIGS. 14 and 15 , in the silicon carbide semiconductor device 300 according to the third embodiment, the p-type region 142 has six p-type regions 144. Three p-type regions 144 are located at each end of the p-type region 142. The p-type regions 144 and p-type regions 145 are arranged alternately along the Y-axis. As in the silicon carbide semiconductor device 101, the p-type regions 144 are formed shallower than in the first embodiment, and the drift region 11 has an n-type region 1111. The n-type region 1111 is located between the top end of each of the p-type regions 144 and the first main surface 1. The dimension of the p-type regions 144 along the Y-axis increases as they approach the ends of the p-type region 142.
[0078] Other configurations of silicon carbide semiconductor device 300 are the same as those of silicon carbide semiconductor device 101. The third embodiment also achieves the same effects as the modified example of the first embodiment. Furthermore, since multiple p-type regions 144 are provided at both ends of p-type region 142, depletion is more likely to be promoted. Furthermore, the dimension of p-type region 144 in the direction along the Y-axis increases as it approaches the end of p-type region 142, which makes the change in the electric field more gradual and makes it less likely for electric field concentration to occur.
[0079] (Fourth embodiment) A fourth embodiment will be described. The fourth embodiment differs from the third embodiment mainly in the configuration of drift region 11. Fig. 16 is a diagram showing the configurations of the p-type region and drift region in a silicon carbide semiconductor device according to the fourth embodiment.
[0080] As shown in FIG. 16 , in the silicon carbide semiconductor device 400 according to the fourth embodiment, the drift region 11 has an n-type region 116 located between the p-type regions 144 adjacent to each other along the X-axis, and an n-type region 117 located between the p-type regions 145 adjacent to each other along the X-axis, similar to the second embodiment.
[0081] Other configurations of silicon carbide semiconductor device 400 are the same as those of silicon carbide semiconductor device 300. The fourth embodiment also provides the same effects as the third and second embodiments.
[0082] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]
[0083] 1 First main surface 2 Second main surface 3. Aspects 4 Bottom 5 Gate trench 10 Silicon carbide substrate 11 Drift Region 12 Body Region 13 Source Region 14, 142, 144, 145, 148, 149, 1410 p-type region 16 Contact Area 17 Junction termination structure 18 Contact Area 30 Virtual Plane 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 63 Gate Runner 64 Source Runner 70 drain electrode 81 Gate insulating film 82 gate electrode 83 Interlayer insulating film 84 Barrier metal film 85 Electrode membrane 86 Plating film 87 Silicon nitride film 88 Polyimide film 90, 91, 92 contact holes 100, 101, 200, 201, 300, 400 Silicon carbide semiconductor device 110 Active area 116, 117, 1111, 1112 n-type region 120 Termination area 121 1st termination area 122 Second termination area 123 Third terminal area P1 First pitch W1 1st width W2 Second width W3 3rd width θ1 angle
Claims
1. a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and having, in a plan view perpendicular to the first main surface, an active region and a termination region surrounding the active region; The silicon carbide substrate is a first semiconductor region having a first conductivity type; a plurality of second semiconductor regions provided within the first semiconductor region and having a second conductivity type; a third semiconductor region having the second conductivity type, being provided in the active region, constituting the first main surface, and having an annular shape in the plan view; and the second semiconductor regions are aligned in the active region and the termination region along a first axis parallel to the first major surface, and extend along a second axis parallel to the first major surface and perpendicular to the first axis; The second semiconductor region is at least two fourth semiconductor regions; a fifth semiconductor region between the fourth semiconductor regions; and the fourth semiconductor region is located at least on both ends of the second semiconductor region, an effective concentration of the first impurity of the second conductivity type contained in the fourth semiconductor region is lower than an effective concentration of the first impurity contained in the fifth semiconductor region;
2. the second semiconductor region has four or more of the fourth semiconductor regions, The silicon carbide semiconductor device according to claim 1 , wherein said fourth semiconductor regions and said fifth semiconductor regions are arranged alternately along said second axis.
3. The silicon carbide semiconductor device according to claim 2 , wherein a dimension of said fourth semiconductor region in a direction along said second axis increases with increasing proximity to an end of said second semiconductor region.
4. The first semiconductor region is a sixth semiconductor region located between the fourth semiconductor regions adjacent to each other along the first axis; a seventh semiconductor region located between the fifth semiconductor regions adjacent to each other along the first axis; and 4 . The silicon carbide semiconductor device according to claim 1 , wherein an effective concentration of the second impurity of the first conductivity type contained in the sixth semiconductor region is higher than an effective concentration of the second impurity contained in the seventh semiconductor region.
5. The fifth semiconductor region is an eighth semiconductor region overlapping the third semiconductor region in a plan view and electrically connected to the third semiconductor region; a ninth semiconductor region in the termination region; a tenth semiconductor region in the active region, the tenth semiconductor region being spaced apart from the third semiconductor region in a plan view; and The silicon carbide semiconductor device according to claim 1 , wherein a first width of said tenth semiconductor region is smaller than a second width of said ninth semiconductor region.
6. The silicon carbide semiconductor device according to claim 5 , wherein said first width is smaller than a third width of said eighth semiconductor region.
7. The silicon carbide semiconductor device according to claim 1 , wherein the plurality of second semiconductor regions are provided at a constant pitch along the first axis.