Nitride semiconductor device and method of manufacturing nitride semiconductor device

Abstract

To provide a nitride semiconductor device including a gate layer of a step structure in which step thickness dependency of on-resistance is reduced.SOLUTION: A nitride semiconductor device 10 includes an electron transit layer 16, an electron supply layer 18, a gate layer 22, a gate electrode 24, a source electrode 28, and a drain electrode 30. The gate layer 22 includes a main body part 40, a source-side extension part 42S, and a drain-side extension part 42D. The main body part 40 includes: a lower layer 44 which is undoped or includes an acceptor type impurity of a first acceptor concentration; an intermediate layer 46 which includes an acceptor type impurity of a second acceptor concentration which is higher than the first acceptor concentration; and an upper layer 48 in which the gate electrode 24 is positioned and which is undoped or includes an acceptor type impurity of a third acceptor concentration which is lower than the second acceptor concentration. The source-side extension part 42S and the drain-side extension part 42D are undoped or include an acceptor type impurity of a fourth acceptor concentration which is lower than the second acceptor concentration.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device. [Background technology]

[0002] Currently, high electron mobility transistors (HEMTs) using group III nitride semiconductors (hereinafter sometimes simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. HEMTs use a two-dimensional electron gas (2DEG) formed near the interface of a semiconductor heterojunction as a conductive path (channel) (see, for example, Patent Document 1). Power devices using HEMTs are recognized as devices that have lower on-resistance and are capable of high-speed, high-frequency operation compared to typical silicon (Si) power devices. In recent years, the adoption of a step structure in the gate layer of HEMTs has been proposed, for example, from the perspective of improving gate breakdown voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-73506

[0004] [overview] In a gate layer with a step structure, the on-resistance can increase significantly depending on the thickness of the lateral extensions (steps) of the gate layer. Therefore, there is still room for improvement in realizing a step structure that reduces the on-resistance dependency on the step thickness.

[0005] A nitride semiconductor device according to one aspect of the present disclosure includes an electron transit layer, an electron supply layer, a gate layer, a gate electrode, a source electrode, and a drain electrode. The electron supply layer is located on the electron transit layer and has a larger bandgap than the electron transit layer. The gate layer is located on the electron supply layer and contains acceptor-type impurities. The gate electrode is located on the gate layer. The source electrode includes a source contact portion in contact with the electron supply layer. The drain electrode includes a drain contact portion in contact with the electron supply layer. The gate layer includes a main body portion, a source-side extension portion extending from the main body portion toward the source contact portion, and a drain-side extension portion extending from the main body portion toward the drain contact portion. The body portion includes a lower layer that is undoped or contains the acceptor-type impurities at a first acceptor concentration, a middle layer that contains the acceptor-type impurities at a second acceptor concentration higher than the first acceptor concentration, and an upper layer in which the gate electrode is located and that is undoped or contains the acceptor-type impurities at a third acceptor concentration lower than the second acceptor concentration. The source-side extension and the drain-side extension are undoped or contain the acceptor-type impurities at a fourth acceptor concentration lower than the second acceptor concentration. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view of the nitride semiconductor device taken along line F2-F2 in FIG. [Figure 3] FIG. 3 is an enlarged view of the gate layer of FIG. [Figure 4] FIG. 4 is a diagram showing the relationship between the acceptor concentration and the on-resistance (sheet resistance) in the step structure of the gate layer. [Figure 5] FIG. 5 is a diagram showing the relationship between the acceptor concentration in the gate layer and the gate threshold voltage. [Figure 6]FIG. 6 is a diagram showing the change in band energy with respect to the distance from the gate electrode (bottom surface). [Figure 7] FIG. 7 is a graph showing the change in acceptor concentration and the change in band energy with respect to the distance from the gate electrode (bottom surface). [Figure 8] 8A to 8C are schematic cross-sectional views illustrating exemplary manufacturing steps for the nitride semiconductor device shown in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of FIG.

[0007] [Detailed explanation] Hereinafter, several embodiments of nitride semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0008] As used in this disclosure, terms such as "first," "second," "third," etc. are used merely to clearly distinguish objects and do not rank them. For example, a claim may refer to a "second" element without referring to a "first" element, or to a "second" sub-element of a "second" element without referring to the "first" sub-element of the "first" element.

[0009] As used in this disclosure, the phrase "at least one" means one or more of a desired number of options. As an example, if the number of options is two, the phrase "at least one" means only one option or both options. As another example, if the number of options is three or more, the phrase "at least one" means only one option or any combination of two or more options.

[0010] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0011] [1-1. Schematic structure of nitride semiconductor device] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device 10 according to one embodiment. FIG. 2 is a schematic cross-sectional view of the nitride semiconductor device 10 taken along line F2-F2 in FIG. 1. Note that, hereinafter, components of the nitride semiconductor device 10 may be described based on mutually orthogonal X, Y, and Z axes shown in the figure. As used herein, the term "plan view" refers to viewing the nitride semiconductor device 10 in the Z-axis direction, unless explicitly stated otherwise.

[0012] The nitride semiconductor device 10 may be configured as, for example, a HEMT using a nitride semiconductor. In one example, the nitride semiconductor device 10 is a GaN-HEMT using GaN. As shown in FIG. 2 , the nitride semiconductor device 10 may include a semiconductor substrate 12 and a buffer layer 14 located on the semiconductor substrate 12. The nitride semiconductor device 10 further includes an electron transit layer 16 and an electron supply layer 18 located on the electron transit layer 16.

[0013] The semiconductor substrate 12 may be formed of Si, silicon carbide (SiC), GaN, sapphire, or other substrate materials. In one example, the semiconductor substrate 12 is a conductive Si substrate. The semiconductor substrate 12 may have a thickness of, for example, 100 μm or more and 1500 μm or less. In one example, the thickness of the semiconductor substrate 12 is 250 μm.

[0014] The buffer layer 14 includes one or more nitride semiconductor layers. The electron transport layer 16 may be located on the buffer layer 14. The buffer layer 14 may be made of any material that can facilitate epitaxial growth of the electron transport layer 16.

[0015] For example, the buffer layer 14 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different Al compositions. For example, the buffer layer 14 may be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure. To suppress leakage current in the buffer layer 14, impurities may be introduced into a portion of the buffer layer 14 to make the buffer layer 14 semi-insulating. In this case, the impurity may be, for example, carbon (C) or iron (Fe), and the impurity concentration may be, for example, 4×10 16 cm -3 It can be more than that.

[0016] The electron transport layer 16 is composed of a nitride semiconductor. The electron transport layer 16 may be, for example, a GaN layer. The electron transport layer 16 may have a thickness of, for example, 0.5 μm or more and 2 μm or less. In order to suppress the leakage current in the electron transport layer 16, by introducing impurities into a part of the electron transport layer 16, the region other than the surface layer region of the electron transport layer 16 may be made semi-insulating. In this case, the impurity may be, for example, C, and the concentration of the impurity in the electron transport layer 16 may be, for example, 4×10 16 cm -3 or more.

[0017] The electron supply layer 18 is composed of a nitride semiconductor having a larger bandgap than the electron transport layer 16. The electron supply layer 18 may be, for example, an AlGaN layer. Since the larger the Al composition, the larger the bandgap, the electron supply layer 18 which is an AlGaN layer has a larger bandgap than the electron transport layer 16 which is a GaN layer. In one example, the electron supply layer 18 is composed of Al X Ga (1-X) N with an Al composition ratio X. The Al composition ratio X is, for example, 0.1 < X < 0.4, and more preferably 0.2 < X < 0.3. The electron supply layer 18 may have a thickness of, for example, 5 nm or more and 20 nm or less, and more preferably 10 nm or more and less than 20 nm. In one example, the thickness of the electron supply layer 18 is 8 nm or more. <000019;2> The electron transport layer 16 and the electron supply layer 18 are composed of nitride semiconductors having different lattice constants. Therefore, the nitride semiconductor (for example, GaN) constituting the electron transport layer 16 and the nitride semiconductor (for example, AlGaN) constituting the electron supply layer 18 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron transport layer 16 and the electron supply layer 18 and the piezo-polarization caused by the crystal strain near the hetero-junction interface, the energy level of the conduction band of the electron transport layer 16 near the hetero-junction interface becomes lower than the Fermi level. As a result, 2DEG20 spreads in the electron transport layer 16 at a position close to the hetero-junction interface between the electron transport layer 16 and the electron supply layer 18 (for example, within a range of about several nm from the interface).

[0019] The nitride semiconductor device 10 further includes a gate layer 22 located on the electron supply layer 18 and a gate electrode 24 located on the gate layer 22. The gate layer 22 may be provided on a portion of the electron supply layer 18. The gate electrode 24 may be provided on a portion of the gate layer 22.

[0020] The gate layer 22 is made of a nitride semiconductor containing acceptor-type impurities. For example, the gate layer 22 may be a gallium nitride layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities may include at least one of zinc (Zn), magnesium (Mg), iron (Fe), and carbon (C). In one example, the gate layer 22 is GaN doped with Mg as an acceptor-type impurity. Details of the gate layer 22 will be described later.

[0021] The gate electrode 24 includes one or more metal layers. In one example, the gate electrode 24 is a titanium nitride (TiN) layer. In another example, the gate electrode 24 includes a first metal layer made of Ti and a second metal layer formed of TiN on the first metal layer. The gate electrode 24 can form a Schottky junction with the gate layer 22. The gate electrode 24 can have a thickness of, for example, 50 nm to 200 nm.

[0022] The nitride semiconductor device 10 further includes a passivation layer 26. The passivation layer 26 covers the electron supply layer 18, the gate layer 22, and the gate electrode 24. The passivation layer 26 is formed of at least one of silicon nitride (SiN), silicon dioxide (SiO), silicon oxynitride (SiON), alumina (AlO), AlN, and aluminum oxynitride (AlON), for example. In one example, the passivation layer 26 is formed of a material containing SiN. The passivation layer 26 may have a thickness of, for example, 80 nm to 150 nm.

[0023] The passivation layer 26 includes a source opening 26S and a drain opening 26D spaced apart from each other in one direction (the X-axis direction in FIG. 1). In this specification, the direction in which the source opening 26S, the gate layer 22, and the drain opening 26D are aligned in one direction in a plan view (the X-axis direction in FIG. 1) is referred to as a first direction X, and the direction orthogonal to the first direction X in a plan view (the Y-axis direction in FIG. 1) is referred to as a second direction Y. The gate layer 22 is located between the source opening 26S and the drain opening 26D in the first direction X. The gate layer 22 is located closer to the source opening 26S than the drain opening 26D.

[0024] The nitride semiconductor device 10 includes a source electrode 28 in contact with the electron supply layer 18 through a source opening 26S and a drain electrode 30 in contact with the electron supply layer 18 through a drain opening 26D. The source electrode 28 and the drain electrode 30 include one or more metal layers. For example, the source electrode 28 and the drain electrode 30 may be formed by combining two or more metal layers selected from the group including a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. In one example, the source electrode 28 and the drain electrode 30 have a four-layer structure including, from the top surface side, a Ti layer, an AlCu layer, a Ti layer, and a TiN layer.

[0025] The source electrode 28 includes a source contact portion 28SC that fills the source opening 26S and contacts the electron supply layer 18. The source electrode 28 also optionally includes a source field plate portion 28SF that is located on the passivation layer 26. The source field plate portion 28SF may be formed integrally and continuously with the source contact portion 28SC. The source contact portion 28SC makes ohmic contact with the 2DEG 20 directly below the electron supply layer 18 through the source opening 26S.

[0026] The source field plate portion 28SF, for example, entirely covers the gate layer 22 and the gate electrode 24. The source field plate portion 28SF is spaced apart from the drain electrode 30. The source field plate portion 28SF includes an end portion 28E located between the drain electrode 30 and the gate layer 22 in a plan view. The source field plate portion 28SF plays a role in alleviating electric field concentration near the ends of the gate layer 22 and the gate electrode 24 when a drain voltage is applied to the drain electrode 30 in an off state in which the 2DEG 20 in the region of the electron transit layer 16 directly below the gate layer 22 has disappeared.

[0027] The drain electrode 30 includes a drain contact portion 30DC that fills the drain opening 26D and is in contact with the electron supply layer 18. The drain contact portion 30DC is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 through the drain opening 26D.

[0028] In the nitride semiconductor device 10, the gate layer 22 contains acceptor-type impurities, which raises the energy levels of the electron transit layer 16 and the electron supply layer 18. Therefore, in the region immediately below the gate layer 22, the energy level of the conduction band of the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 is approximately the same as or higher than the Fermi level. As a result, when a gate control voltage that turns off the transistor (HEMT) is applied to the gate electrode 24 (for example, when the gate-source voltage is 0 V or lower), a 2DEG 20 is not formed in the region of the electron transit layer 16 immediately below the gate layer 22. On the other hand, a 2DEG 20 is formed in the region of the electron transit layer 16 other than the region immediately below the gate layer 22.

[0029] In this way, by providing the gate layer 22 doped with acceptor-type impurities, the 2DEG 20 disappears in the region of the electron transit layer 16 directly below the gate layer 22, thereby achieving normally-off operation. When an appropriate gate control voltage (on voltage) is applied to the gate electrode 24, a channel is formed by the 2DEG 20 in the region of the electron transit layer 16 directly below the gate layer 22, thereby establishing conduction between the source and drain.

[0030] [1-2. Planar Layout of Nitride Semiconductor Devices] Next, an example of a planar layout of the nitride semiconductor device 10 will be described with reference to Fig. 1. In Fig. 1, the gate electrode 24, the source electrode 28, the drain electrode 30, and the source field plate portion 28SF are depicted by dashed lines. In addition, for the passivation layer 26, the source opening 26S and the drain opening 26D are depicted by solid lines, and the other portions are shown transparently.

[0031] 1, the gate layer 22 may be formed to surround the drain electrode 30 in a plan view. For example, the gate layer 22 includes a first portion 22A located in an active region that contributes to HEMT operation and extending in the second direction Y, and a second portion 22B located in an inactive region that does not directly contribute to HEMT operation, extending in the first direction X, and connecting two first portions 22A adjacent to each other in the first direction X. The first portion 22A is located between the source opening 26S and the drain opening 26D.

[0032] The gate electrode 24 is disposed so as to overlap the gate layer 22 in a planar view. Therefore, similar to the gate layer 22, the gate electrode 24 can be formed so as to surround the drain electrode 30 in a planar view. For example, the gate electrode 24 includes a first portion 24A located in the active region and extending in the second direction Y, and a second portion 24B located in the inactive region and extending in the first direction X to connect two first portions 24A adjacent to each other in the first direction X. The gate electrode 24 can have an area smaller than that of the gate layer 22 in a planar view.

[0033] The nitride semiconductor device 10 includes a gate wiring 32, a source wiring 34, and a drain wiring 36. In FIG. 1 , the gate wiring 32, the source wiring 34, and the drain wiring 36 are depicted by dashed lines. The gate wiring 32, the source wiring 34, and the drain wiring 36 are located above the source electrode 28 and the drain electrode 30 in the Z-axis direction (a direction perpendicular to both the first direction X and the second direction Y). For example, the gate wiring 32 extends in the first direction X and is disposed above the second portion 24B of the gate electrode 24. The source wiring 34 and the drain wiring 36 extend in the first direction X and are disposed so as to intersect with the source electrode 28 and the drain electrode 30, respectively, in a plan view.

[0034] The gate electrode 24 is electrically connected to the gate wiring 32 by a connecting conductor 32V arranged on the second portion 24B of the gate electrode 24. The source electrode 28 is electrically connected to the source wiring 34 by a connecting conductor 34V arranged on the source contact portion 28SC. The drain electrode 30 is electrically connected to the drain wiring 36 by a connecting conductor 36V arranged on the drain contact portion 30DC. The planar layout of the nitride semiconductor device 10 is not limited to the example shown in FIG. 1 . Any other planar layout can be applied to the nitride semiconductor device 10.

[0035] [1-3. Gate layer structure] Next, the structure of the gate layer 22 will be described with reference to Fig. 3. Fig. 3 is an enlarged view of the gate layer 22 in Fig. 2.

[0036] The gate layer 22 has a step structure including a main body portion 40 and two extension portions (steps) located on either side of the main body portion 40: a source-side extension portion 42S and a drain-side extension portion 42D. The source-side extension portion 42S extends from the main body portion 40 toward the source contact portion 28SC (see FIG. 2), and the drain-side extension portion 42D extends from the main body portion 40 toward the drain contact portion 30DC (see FIG. 2). The main body portion 40, the source-side extension portion 42S, and the drain-side extension portion 42D are all in contact with the electron supply layer 18.

[0037] The main body 40 is generally ridge-shaped and has a rectangular or trapezoidal cross section. The main body 40 includes a lower layer 44, an intermediate layer 46, and an upper layer 48, which are broadly classified based on whether or not they are doped with acceptor-type impurities or on the concentration of the acceptor-type impurities. The gate electrode 24 is located on the upper layer 48.

[0038] The main body 40 includes acceptor-type impurities in at least the intermediate layer 46 of the lower layer 44, intermediate layer 46, and upper layer 48. The lower layer 44 and the upper layer 48 may include acceptor-type impurities, but in that case, the acceptor-type impurities have a lower acceptor concentration than the intermediate layer 46. Thus, the lower layer 44 is undoped or includes acceptor-type impurities at a first acceptor concentration N1. The intermediate layer 46 includes acceptor-type impurities at a second acceptor concentration N2 higher than the first acceptor concentration N1. The upper layer 48 is undoped or includes acceptor-type impurities at a third acceptor concentration N3 lower than the second acceptor concentration N2.

[0039] Here, the first to third acceptor concentrations N1, N2, and N3 may be concentrations measured at any portion of the lower layer 44, the intermediate layer 46, and the upper layer 48, respectively. For example, the first to third acceptor concentrations N1, N2, and N3 may be concentrations measured at or below the intermediate positions of the lower layer 44, the intermediate layer 46, and the upper layer 48 in the thickness direction (i.e., the Z-axis direction) of the main body 40. For example, the first to third acceptor concentrations N1, N2, and N3 may be concentrations measured at the bottom portions of the lower layer 44, the intermediate layer 46, and the upper layer 48, respectively. The bottom portion refers to any portion included within a given thickness range above the bottom surface of the corresponding layer.

[0040] However, the first to third acceptor concentrations N1, N2, and N3 are not limited to concentrations measured in specific portions of each layer as described above. For example, the first to third acceptor concentrations N1, N2, and N3 may be the average acceptor concentration of the lower layer 44, the average acceptor concentration of the middle layer 46, and the average acceptor concentration of the upper layer 48, respectively.

[0041] 3, the lower layer 44 and the upper layer 48 are each an undoped layer, and the intermediate layer 46 is a layer doped with an acceptor-type impurity (e.g., Mg). The concentration of the acceptor-type impurity contained in the intermediate layer 46, i.e., the second acceptor concentration N2, is, for example, 2.0×10 17 cm -3 The second acceptor concentration N2 may be 2.0×10 or more. 17 cm -3 Over 3.0 x 10 20 cm -3 In one example, the intermediate layer 46 may have a second acceptor concentration N2 of 2.0×10 or less measured at a middle position of the intermediate layer 46. 17 cm -3 Over 3.0 x 10 20 cm -3 The acceptor-type impurities are doped as follows:

[0042] 3, the intermediate layer 46 of the gate layer 22 includes a first intermediate layer 52, a second intermediate layer 54, and a third intermediate layer 56, each having a different acceptor concentration. The first intermediate layer 52 is the layer having the highest acceptor concentration among the intermediate layers 46, and may have a uniform acceptor concentration throughout the first intermediate layer 52. For example, the first intermediate layer 52 has a second acceptor concentration N2.

[0043] The second intermediate layer 54 is located between the lower layer 44 and the intermediate layer 46 (first intermediate layer 52 in the example of FIG. 3), and is a transition layer in which the acceptor concentration increases from the acceptor concentration of the lower layer 44 (i.e., zero or the first acceptor concentration N1) to the second acceptor concentration N2. The second intermediate layer 54 corresponds to the lower intermediate layer.

[0044] The third intermediate layer 56 is located between the intermediate layer 46 (the first intermediate layer 52 in the example of FIG. 3) and the upper layer 48, and is a transition layer in which the acceptor concentration decreases from the second acceptor concentration N2 toward the acceptor concentration of the upper layer 48 (i.e., zero or the third acceptor concentration N3). The third intermediate layer 56 corresponds to the upper intermediate layer.

[0045] 3, the thickness T21 of the first intermediate layer 52 is set to be the largest among the first to third intermediate layers 52, 54, 56, and the thickness T22 of the second intermediate layer 54 (lower intermediate layer) is set to be the smallest. That is, the thickness T23 of the third intermediate layer 56 (upper intermediate layer) is set to be smaller than the thickness T21 of the first intermediate layer 52 and larger than the thickness T22 of the second intermediate layer 54.

[0046] Since the lower layer 44 and the upper layer 48 are provided as undoped layers, the acceptor concentration in the lower layer 44 and the upper layer 48 can be considered to be 0 (zero). Note that the term "undoped layer" used in this disclosure is defined as a layer into which acceptor-type impurities are not intentionally introduced. However, acceptor-type impurities may be unintentionally mixed into an "undoped layer" during the process of forming the nitride semiconductor device 10. Therefore, the term "undoped layer" refers not only to a layer that does not contain any acceptor-type impurities, but also to a layer that unintentionally contains a small amount of acceptor-type impurities but is not substantially doped.

[0047] 3, the lower layer 44 and the upper layer 48 are undoped layers, but as described above, the lower layer 44 may contain acceptor-type impurities at a first acceptor concentration N1, and the upper layer 48 may contain acceptor-type impurities at a third acceptor concentration N3. In this case, the first and third acceptor concentrations N1 and N3 are greater than 0 and less than 3.0×10 20 cm -3 The first and third acceptor concentrations N1, N3 may be set to a concentration lower than the second acceptor concentration N2 in a range of less than 1000 kJ / cm. Note that the first and third acceptor concentrations N1, N3 may be the same value or may be different values.

[0048] The main body 40 may have a thickness of, for example, 50 nm to 200 nm, more preferably 80 nm to 150 nm, and even more preferably 100 nm to 130 nm. The thickness of the main body 40 corresponds to the total thickness of the lower layer 44, the intermediate layer 46, and the upper layer 48. The thickness of the main body 40 can be determined taking into account various parameters, including the gate threshold voltage. In one example, the thickness of the main body 40 is 110 nm.

[0049] As shown in FIG. 3 , the upper layer 48 has a thickness T11. The intermediate layer 46 has a thickness T12 that is smaller than the thickness T11, and the lower layer 44 has a thickness T13 that is smaller than the thickness T12. The thickness T12 of the intermediate layer 46 may be, for example, 10 nm or more and 100 nm or less. The thickness T12 can be determined in consideration of the function of the intermediate layer 46 (described below). In one example, the thickness T12 is 30 nm. The thickness T13 of the lower layer 44 corresponds to the thickness of each of the source side extension portion 42S and the drain side extension portion 42D. The thickness T13 may be, for example, 5 nm or more and 50 nm or less, and more preferably 10 nm or more and 40 nm or less. The thickness T13 can be determined in consideration of the function of the source side extension portion 42S and the drain side extension portion 42D (described below). In one example, the thickness T13 is 15 nm. The thickness T11 of the upper layer 48 may be, for example, at least twice the thickness T12 of the intermediate layer 46. In one example, the thickness T11 is 70 nm.

[0050] The source-side extension 42S and the drain-side extension 42D are formed integrally with the main body 40 and have a thickness smaller than that of the main body 40. For example, the source-side extension 42S and the drain-side extension 42D are formed integrally with the lower layer 44 and have the same thickness T13 as the lower layer 44. The source-side extension 42S does not reach the source opening 26S, and a passivation layer 26 is disposed between the source contact portion 28SC and the source-side extension 42S. Similarly, the drain-side extension 42D does not reach the drain opening 26D, and a passivation layer 26 is disposed between the drain contact portion 30DC and the drain-side extension 42D.

[0051] The drain-side extension portion 42D may extend longer in the first direction X than the source-side extension portion 42S. That is, the drain-side extension portion 42D may have a larger dimension in the first direction X than the source-side extension portion 42S. The source-side extension portion 42S has a dimension in the first direction X of, for example, 0.05 μm to 0.3 μm, more preferably 0.2 μm to 0.3 μm. The drain-side extension portion 42D has a dimension in the first direction X of, for example, 0.05 μm to 0.6 μm, more preferably 0.2 μm to 0.6 μm. The source-side extension portion 42S and the drain-side extension portion 42D serve to reduce electric field concentration near the ends of the gate layer 22 and the gate electrode 24, thereby improving the gate breakdown voltage.

[0052] The source-side extension 42S and the drain-side extension 42D are undoped or contain acceptor-type impurities at a fourth acceptor concentration N4 lower than the second acceptor concentration N2. The fourth acceptor concentration N4 may be a concentration measured at any portion of the source-side extension 42S and the drain-side extension 42D. For example, the fourth acceptor concentration N4 may be a concentration measured at or below an intermediate position between the source-side extension 42S and the drain-side extension 42D in the thickness direction of the body 40. For example, the fourth acceptor concentration N4 may be a concentration measured at the bottom of the source-side extension 42S and the drain-side extension 42D.

[0053] However, the fourth acceptor concentration N4 is not limited to the concentration measured in specific portions of the source-side extension portion 42S and the drain-side extension portion 42D as described above. For example, the fourth acceptor concentration N4 may be the average acceptor concentration of each of the source-side extension portion 42S and the drain-side extension portion 42D.

[0054] 3, the source-side extension 42S and the drain-side extension 42D are each an undoped layer. Therefore, the acceptor concentration in the source-side extension 42S and the drain-side extension 42D can be considered to be 0 (zero). Note that, when the source-side extension 42S and the drain-side extension 42D contain acceptor-type impurities, the fourth acceptor concentration N4 is greater than 0 and is 3.0×10 20 cm -3 The fourth acceptor concentration N4 may be set to a concentration lower than the second acceptor concentration N2 in a range of less than 1000 .mu.m. The fourth acceptor concentration N4 may be the same as the first acceptor concentration N1 of the lower layer 44.

[0055] [1-4. Relationship between acceptor concentration and on-resistance in step structures] FIG. 4 is a diagram showing the relationship between the acceptor concentration and the on-resistance (sheet resistance) in the step structure of the gate layer 22. In the gate layer 22 including the source-side extension portion 42S and the drain-side extension portion 42D, the on-resistance can vary depending on the step thickness, i.e., the thickness of the source-side extension portion 42S and the drain-side extension portion 42D (thickness T13 in the example of FIG. 3). The present inventors have found that such step-thickness dependence of the on-resistance can be controlled by adjusting the acceptor concentration in the gate layer 22, particularly the acceptor concentration in the source-side extension portion 42S and the drain-side extension portion 42D. FIG. 4 shows the step-thickness dependence of the on-resistance depending on the difference in the acceptor concentration in the source-side extension portion 42S and the drain-side extension portion 42D.

[0056] In Figure 4, graph L1 shows the acceptor concentration at 0 cm -3 Graph L2 shows the case where the acceptor concentration is 5×10 17 cm -3 Graph L3 shows the case where the acceptor concentration is 1×10 18 cm -3 Graph L4 shows the case where the acceptor concentration is 2×10 18 cm -3 Graph L5 shows the case where the acceptor concentration is 3×10 18 cm -3 Graph L6 shows the case where the acceptor concentration is 5×1018 cm -3 This shows the case where

[0057] As shown by the graphs L1 to L6, it can be seen that the step thickness dependency of the on-resistance increases as the acceptor concentration increases. For example, as shown by the graph L6, when the acceptor concentration is 5×10 18 cm -3 In this case, when the step thickness is larger than about 17 nm, the on-resistance (sheet resistance) increases significantly. Also, as shown by graph L5, when the acceptor concentration is 3×10 18 cm -3 In this case, when the step thickness is greater than about 22 nm, the on-resistance (sheet resistance) increases significantly. In contrast, as shown by graphs L1 to L3, when the acceptor concentration is 0 cm -3 More than 1×10 18 cm -3 In the following cases, the step thickness dependency of the on-resistance (sheet resistance) is suppressed, and the on-resistance is robust against fluctuations in the step thickness. In particular, as shown by graph L1, when the acceptor concentration is 0 cm -3 In this case, almost no step thickness dependency is observed. From this viewpoint, in the example of Fig. 3, the source-side extension 42S and the drain-side extension 42D (together with the lower layer 44) are provided as undoped layers.

[0058] As shown in Figure 4, when the acceptor concentration is 2 × 10 18 cm -3 Even so, it can be said that the on-resistance is robust against fluctuations in step thickness within a given step thickness range. For example, as shown by graph L6, when the acceptor concentration is 5×10 18 cm -3 In this case, the step thickness dependence of the on-resistance is suppressed in the range of step thickness of approximately 17 nm or less. 20 cm -3In this case, the step thickness dependency of the on-resistance is suppressed within a step thickness range of approximately 5 nm or less. Therefore, the upper limit of the acceptor concentration (i.e., the fourth acceptor concentration N4) of the source-side extension portion 42S and the drain-side extension portion 42D may be set according to the step thickness to be realized.

[0059] [1-5. Relationship between acceptor concentration in the gate layer and gate threshold voltage] 5 is a diagram showing the relationship between the acceptor concentration and the gate threshold voltage Vth in the main body 40 of the gate layer 22. Note that FIG. 5 shows how the gate threshold voltage Vth varies depending on the acceptor concentration for four types of acceptor levels set in the main body 40.

[0060] In the example of Figure 5, the black circles indicate the acceptor level when Ev + 0.17 eV, the black triangles indicate the acceptor level when Ev + 0.9 eV, the black squares indicate the acceptor level when Ev + 1.5 eV, and the black diamonds indicate the acceptor level when Ev + 2.8 eV. For example, the acceptor level of Ev + 0.17 eV can be formed when Mg is used as the acceptor-type impurity. The acceptor levels of Ev + 0.9 eV, Ev + 1.5 eV, and Ev + 2.8 eV can be formed when Mg that has not been subjected to activation annealing is used as the acceptor-type impurity.

[0061] As shown in Figure 5, the gate threshold voltage Vth generally increases as the acceptor concentration increases, and it is found that it saturates or approaches a given voltage Vths, which is the target voltage. For example, when the acceptor level is Ev+0.17 eV, when the acceptor concentration is 1×10 17 cm -3 2×10 17 cm -3 At this time, a higher gate threshold voltage Vth is obtained, and the gate threshold voltage Vth reaches the voltage Vths. This means that even if the acceptor concentration doped in the gate layer 22 (main body 40) is increased above a certain level, there is no change in the effect of increasing the gate threshold voltage Vth.

[0062] 6 is a band diagram showing the change in the energy level Ev of the valence band and the energy level Ec of the conduction band in the gate layer 22, the electron supply layer 18, and the electron transit layer 16 with respect to the distance from the bottom surface of the gate electrode 24 (i.e., the top surface of the gate layer 22) for four different acceptor concentrations. In FIG. 6, the dotted lines indicate the change in the energy level Ev of the valence band and the energy level Ec of the conduction band in the gate layer 22, the electron supply layer 18, and the electron transit layer 16 with respect to the distance from the bottom surface of the gate electrode 24 (i.e., the top surface of the gate layer 22). 17 cm -3 The dashed line indicates the case where the acceptor concentration is 2×10 17 cm -3 The dashed double-dashed line indicates the case where the acceptor concentration is 1×10 18 cm -3 The solid line indicates the case where the acceptor concentration is 1×10 19 cm -3 1. The distance T0 indicates the position of the bottom surface of the gate layer 22.

[0063] As shown by the dotted line in the band diagram in Fig. 6, the acceptor concentration is 1 × 10 17 cm -3 In this case, the energy band rises gradually, and the depletion layer extends from the top surface to the bottom surface (distance T0) of the gate layer 22. In addition, in the region greater than distance T0, the energy levels Ev and Ec are lower in the electron supply layer 18 and the electron transit layer 16 due to a lack of acceptors, compared to the cases of other acceptor concentrations (band diagrams indicated by dashed-dotted lines, dashed-double-dotted lines, and solid lines). This indicates that the gate threshold voltage Vth is reduced.

[0064] On the other hand, when the acceptor concentration is 2×10 17 cm -3 In the above cases, as shown in the band diagrams of the dashed line, the two-dot dashed line, and the solid line, the energy band is raised as the acceptor concentration increases, thereby suppressing the formation of a depletion layer (the width of the depletion layer from the top surface of the gate layer 22) in the gate layer 22. In addition, the energy band is raised even in the region at a distance of T0 or more, so that the above-mentioned acceptor concentration becomes 1×10 17 cm -3It is shown that the gate threshold voltage Vth increases compared to the case of

[0065] However, when the acceptor concentration is 2×10 17 cm -3 In the above cases, the energy levels Ev and Ec are almost the same in the region of distance T0 or more (in FIG. 6, the band diagrams of the dashed-dotted line, the dashed-two-dotted line, and the solid line are shown overlapping each other.) This means that even if the acceptor concentration doped in the gate layer 22 (main body 40) is increased above a certain level, there is no change in the effect of increasing the gate threshold voltage Vth.

[0066] Considering the above, from the viewpoint of increasing the gate threshold voltage Vth, the second acceptor concentration N2 of the intermediate layer 46 is set to 2.0×10 17 cm -3 On the other hand, since an increase in the second acceptor concentration N2 of the intermediate layer 46 can also be a factor in increasing the on-resistance, it is more desirable to set an upper limit for the second acceptor concentration N2 of the intermediate layer 46. From this perspective, for example, taking into consideration the step thickness dependency of the on-resistance described above (in other words, the realized step thickness), the second acceptor concentration N2 of the intermediate layer 46 is set to 2.0×10 17 cm -3 Over 3.0 x 10 20 cm -3 It can be set to:

[0067] [1-6. Relationship between acceptor concentration in the gate layer and gate leakage current] Continuing with reference to FIG. 6, the relationship between the acceptor concentration in the gate layer 22 and the gate leakage current will be described. As described with reference to FIG. 6, the higher the acceptor concentration, the smaller the depletion layer width from the upper surface of the gate layer 22. Therefore, the higher the acceptor concentration, the greater the strength of the electric field applied to the depletion layer width when a gate voltage is applied, and the greater the gate leakage current. In other words, the gate leakage current can be reduced by lowering the acceptor concentration.

[0068] 3, the upper layer 48 of the main body 40 of the gate layer 22 is provided as an undoped layer. By making the upper layer 48 an undoped layer in this way, the acceptor density of the entire gate layer 22 can be reduced, and the width of the depletion layer formed in the gate layer 22 can be increased. This makes it possible to reduce the gate leakage current.

[0069] [1-7. Function of nitride semiconductor device] Next, the operation of the nitride semiconductor device 10 will be described with reference to Fig. 7. Fig. 7 is a diagram showing changes in the acceptor concentration and changes in the energy levels Ev and Ec in the gate layer 22 with respect to the distance from the bottom surface of the gate electrode 24 (i.e., the top surface of the gate layer 22). In Fig. 7, distance T1 indicates the position of the top surface of the intermediate layer 46 of the gate layer 22, distance T2 indicates the position of the bottom surface of the intermediate layer 46, and distance T3 indicates the position of the bottom surface of the lower layer 44 (i.e., the bottom surface of the gate layer 22).

[0070] As described with reference to Fig. 3, the upper layer 48 of the gate layer 22 is provided as an undoped layer. Therefore, the acceptor concentration is zero from the top surface of the gate layer 22 to a distance T1. By making the upper layer 48 an undoped layer in this way, the width of the depletion layer formed in the gate layer 22 increases, as described with reference to Fig. 6. This reduces the electric field strength when a gate voltage is applied to the gate layer 22, thereby reducing the gate leakage current.

[0071] On the other hand, the intermediate layer 46 of the gate layer 22 is provided as a doped layer doped with acceptor-type impurities at a second acceptor concentration N2. This second acceptor concentration N2 is, for example, the above-mentioned 2.0×10 17 cm -3 Over 3.0 x 10 20 cm -3 A given concentration Nt is set within the following range. Here, as an example, the concentration Nt is 5.0×10 17 cm -3As described above, the intermediate layer 46 may include an upper intermediate layer (third intermediate layer 56) as a transition layer in which the acceptor concentration increases, and an upper intermediate layer (second intermediate layer 54) as a transition layer in which the acceptor concentration decreases (see FIG. 3). Therefore, the gate layer 22 contains acceptor-type impurities with a relatively high acceptor concentration throughout the entire region of the intermediate layer 46 from the distance T1 to the distance T2. By providing the intermediate layer 46 as a highly doped layer in this way, the gate threshold voltage Vth can be increased, as described with reference to FIGS. 5 and 6.

[0072] In addition, in the gate layer 22, the source-side extension 42S and the drain-side extension 42D, together with the lower layer 44, are provided as undoped layers. Therefore, the acceptor concentration is zero throughout the region of the gate layer 22 from the distance T2 to the distance T3 (i.e., the lower layer 44, the source-side extension 42S, and the drain-side extension 42D). This reduces the step thickness dependency of the on-resistance as described with reference to FIG. 4, thereby suppressing the variation in on-resistance due to the variation in the step thickness.

[0073] [1-8. Manufacturing Method of Nitride Semiconductor Device] Next, an example of a method for manufacturing the nitride semiconductor device 10 shown in Fig. 2 will be described. Figs. 8 to 18 are schematic cross-sectional views showing exemplary manufacturing steps for the nitride semiconductor device 10. For ease of understanding, in Figs. 8 to 18, the same components as those in Fig. 2 are denoted by the same reference numerals.

[0074] 8, a method for manufacturing a nitride semiconductor device 10 includes sequentially forming a buffer layer 14, an electron transit layer 16, an electron supply layer 18, and a first layer 62 made of gallium nitride (GaN) on a semiconductor substrate 12, such as a Si substrate. The buffer layer 14, the electron transit layer 16, the electron supply layer 18, and the first layer 62 can be epitaxially grown using a metal organic chemical vapor deposition (MOCVD) method.

[0075] Although detailed illustration is omitted, in one example, the buffer layer 14 may be a multi-layer buffer layer. The multi-layer buffer layer may include an AlN layer (first buffer layer) formed on the semiconductor substrate 12 and a graded AlGaN layer (second buffer layer) formed on the AlN layer. The graded AlGaN layer may be formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25%, in that order from the side closest to the AlN layer.

[0076] The electron transit layer 16 formed on the buffer layer 14 may be a GaN layer. The electron supply layer 18 formed on the electron transit layer 16 may be an AlGaN layer. Therefore, the electron supply layer 18 is made of a nitride semiconductor having a larger band gap than the electron transit layer 16.

[0077] In this example, the first layer 62 formed on the electron supply layer 18 is an undoped layer that does not contain acceptor-type impurities. However, the first layer 62 may be a doped layer that contains acceptor-type impurities (e.g., Mg) at a first acceptor concentration N1. The first layer 62 corresponds to the lower layer 44, the source-side extension 42S, and the drain-side extension 42D described with reference to FIG. 3.

[0078] Fig. 9 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of Fig. 8. As shown in Fig. 9, the manufacturing method of the nitride semiconductor device 10 includes forming a second layer 64 by epitaxially growing GaN containing acceptor-type impurities at a second acceptor concentration N2 on a first layer 62. The second layer 64 corresponds to the intermediate layer 46 described with reference to Fig. 3. As described above, the second acceptor concentration N2 is higher than the first acceptor concentration N1.

[0079] The acceptor-type impurity contained in the second layer 64 may be, for example, Mg. The second layer 64 containing the acceptor-type impurity can be formed by doping the first layer 62 with Mg while growing the second layer 64. The amount of Mg doped into the second layer 64, i.e., the second acceptor concentration N2, can be adjusted by, for example, controlling the flow rate of a doping gas (e.g., biscyclopentadienyl magnesium (CpMg)) introduced into the growth chamber, the growth temperature, etc. In this case, by adjusting the amount of Mg, the second layer 64 can be formed as the intermediate layer 46 including the first to third intermediate layers 52, 54, and 56 described with reference to FIG. 3. Note that in FIG. 9, the first to third intermediate layers 52, 54, and 56 shown in FIG. 3 are not distinguished from each other to avoid ambiguity.

[0080] Fig. 10 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of Fig. 9. As shown in Fig. 10, the manufacturing method of nitride semiconductor device 10 includes forming a third layer 66 by epitaxially growing GaN on second layer 64. Note that third layer 66 is a layer corresponding to upper layer 48 described with reference to Fig. 3.

[0081] In this example, the third layer 66 is an undoped layer that does not contain acceptor-type impurities. However, the third layer 66 may also be a doped layer that contains acceptor-type impurities (e.g., Mg) at a third acceptor concentration N3. In this case, as described above, the third acceptor concentration N3 is lower than the second acceptor concentration N2.

[0082] Fig. 11 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of Fig. 10. As shown in Fig. 11, the manufacturing method of the nitride semiconductor device 10 includes forming a metal layer 68 on the third layer 66. The metal layer 68 can be formed on the third layer 66 by, for example, a sputtering method. The metal layer 68 may be, for example, a TiN layer. The metal layer 68 is a layer corresponding to the gate electrode 24 described with reference to Fig. 2.

[0083] FIG. 12 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of FIG. 11 . As shown in FIG. 12 , the manufacturing method of the nitride semiconductor device 10 further includes selectively removing the metal layer 68 (see FIG. 11 ) by lithography and etching to form the gate electrode 24. In this step, a mask 70 is formed on a portion of the metal layer 68 that is to become the gate electrode 24. The mask 70 can be formed, for example, by exposing a photoresist provided on the metal layer 68. In another example, the mask 70 may be a hard mask. Next, the metal layer 68 is etched using this mask 70, thereby removing the metal layer 68 in areas not covered by the mask 70. As a result, the metal layer 68 in areas covered by the mask 70 remains, thereby forming the gate electrode 24. The mask 70 is removed after etching.

[0084] 13 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of FIG. 12. As shown in FIG. 13, the manufacturing method for the nitride semiconductor device 10 further includes forming a mask 72 that covers the upper and side surfaces of the gate electrode 24 and a region of the third layer 66 around the gate electrode 24. The region of the third layer 66 around the gate electrode 24 that is covered by the mask 72 extends symmetrically in the first direction X with the gate electrode 24 as the center. In other words, the mask 72 is formed so that the center of the mask 72 is aligned with the center of the gate electrode 24 in the first direction X. The mask 72 may be a resist mask.

[0085] Fig. 14 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of Fig. 13. As shown in Fig. 14, the manufacturing method of the nitride semiconductor device 10 further includes etching the third layer 66 and the second layer 64 using a mask 72. As a result, the third layer 66 and the second layer 64 located under the mask 72 remain after etching, forming the upper layer 48 and the intermediate layer 46 described with reference to Fig. 2. The third layer 66 and the second layer 64 not covered by the mask 72 are removed by etching. The mask 72 is removed after etching.

[0086] Fig. 15 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of Fig. 14. As shown in Fig. 15, the manufacturing method of the nitride semiconductor device 10 further includes forming a mask 74 that covers the upper and side surfaces of the gate electrode 24, the upper layer 48, the intermediate layer 46, and a region of the first layer 62 (see Fig. 14) around the intermediate layer 46. The region of the first layer 62 around the intermediate layer 46 that is covered by the mask 74 extends asymmetrically in the first direction X with the intermediate layer 46 as the center. In other words, the mask 74 is formed so that the center of the mask 74 is offset from the center of the intermediate layer 46 (the center of the gate electrode 24) in the first direction X.

[0087] Next, the manufacturing method for the nitride semiconductor device 10 further includes etching the first layer 62 (see FIG. 14) using the mask 74. As a result, the first layer 62 located under the mask 74 remains after the etching, and the lower layer 44, the source-side extension portion 42S, and the drain-side extension portion 42D described with reference to FIG. 2 are formed. The first layer 62 not covered by the mask 74 is removed by the etching. The mask 74 is removed after the etching.

[0088] Fig. 16 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of Fig. 15. As shown in Fig. 16, the method for manufacturing the nitride semiconductor device 10 further includes forming a passivation layer 26 so as to cover the entire exposed surfaces of the electron supply layer 18, the gate layer 22, and the gate electrode 24. In one example, the passivation layer 26 may be a SiN layer formed by a low-pressure chemical vapor deposition (LPCVD) method.

[0089] FIG. 17 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 16 . As shown in FIG. 17 , the manufacturing method for the nitride semiconductor device 10 further includes selectively removing the passivation layer 26 by lithography and etching to form a source opening 26S and a drain opening 26D. In this step, a mask 76 is formed to cover the passivation layer 26 except for the regions where the source opening 26S and the drain opening 26D are to be formed. The passivation layer 26 is then patterned using the mask 76. As a result, the source opening 26S and the drain opening 26D are formed through the passivation layer 26 to expose the electron supply layer 18. The source opening 26S and the drain opening 26D are formed so that the gate layer 22 is located between the source opening 26S and the drain opening 26D. The gate layer 22 is located closer to the source opening 26S than the drain opening 26D. The mask 76 is removed after etching.

[0090] Fig. 18 is a schematic cross-sectional view showing a manufacturing step subsequent to the step of Fig. 17. As shown in Fig. 18, the method for manufacturing the nitride semiconductor device 10 further includes forming a metal layer 78 covering the passivation layer 26. The metal layer 78 is formed to fill the source opening 26S and the drain opening 26D and to be in contact with the electron supply layer 18 through the source opening 26S and the drain opening 26D. In one example, the metal layer 78 includes at least one of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer.

[0091] Next, the metal layer 78 is selectively removed by lithography and etching to form the source electrode 28 and the drain electrode 30 shown in Fig. 2. In this way, the nitride semiconductor device 10 shown in Fig. 2 can be obtained.

[0092] [1-9. Advantages of nitride semiconductor devices] The nitride semiconductor device 10 has the following advantages. (1-1) The gate layer 22 of the nitride semiconductor device 10 includes a main body portion 40, and a source-side extension portion 42S and a drain-side extension portion 42D located on either side of the main body portion 40. The main body portion 40 includes a lower layer 44 provided as an undoped layer, an intermediate layer 46 containing acceptor-type impurities at a second acceptor concentration N2, and an upper layer 48 provided as an undoped layer. The source-side extension portion 42S and the drain-side extension portion 42D are also provided as undoped layers.

[0093] In this configuration, the upper layer 48 is an undoped layer (or contains acceptor-type impurities at a first acceptor concentration N1), which weakens the strength of the electric field applied to the gate layer 22 and reduces the gate leakage current. Furthermore, the intermediate layer 46 contains acceptor-type impurities at a relatively high second acceptor concentration N2, which increases the gate threshold voltage Vth. Furthermore, the source-side extension 42S and the drain-side extension 42D, together with the lower layer 44, are undoped layers (or contain acceptor-type impurities at a third acceptor concentration N3), which reduces the step thickness dependence of the on-resistance and reduces the variation in the on-resistance with respect to the variation in the step thickness. As a result, strict control of the thicknesses of the source-side extension 42S and the drain-side extension 42D is not necessary. Therefore, the above-described configuration of the gate layer 22 not only reduces the step thickness dependence of the on-resistance, but also simultaneously reduces the gate leakage current and increases the gate threshold voltage Vth.

[0094] (1-2) In the main body 40 of the gate layer 22, the acceptor concentrations of the lower layer 44, the intermediate layer 46, and the upper layer 48 are determined as concentrations measured at or below the middle position of each layer. By determining the position for measuring the acceptor concentration in each layer, the functions of the lower layer 44, the intermediate layer 46, and the upper layer 48 can be suitably maintained.

[0095] (1-3) In the main body 40 of the gate layer 22, the thickness T12 of the intermediate layer 46 is set to be smaller than the thickness T11 of the upper layer 48. This makes it possible to make the thickness T11 of the upper layer 48, which is an undoped layer, relatively large in the gate layer 22, thereby enhancing the effect of reducing the gate leakage current described above.

[0096] (1-4) In the main body 40 of the gate layer 22, the second acceptor concentration N2 of the intermediate layer 46 is 2.0×10 17 cm -3 By setting the concentration in this manner, the effect of increasing the gate threshold voltage Vth can be preferably obtained.

[0097] (1-5) The second acceptor concentration N2 of the intermediate layer 46 is 3.0×10 20 cm -3 By setting the concentration in this manner, it is possible to prevent the acceptor concentration in the entire gate layer 22 from increasing within the range of the desired step thickness, and to prevent the on-resistance from becoming highly dependent on the step thickness.

[0098] (1-6) In the main body portion 40 of the gate layer 22, the lower layer 44 can be a doped layer doped with acceptor-type impurities at a first acceptor concentration N1 instead of an undoped layer. The source-side extension 42S and the drain-side extension 42D can also be doped layers doped with acceptor-type impurities at a fourth acceptor concentration N4 instead of an undoped layer. The first acceptor concentration N1 and the fourth acceptor concentration N4 may be the same. In this case, the first acceptor concentration N1 and the fourth acceptor concentration N4 are greater than 0 and less than 3.0×10. 20 cm -3 The second acceptor concentration N2 can be set to a value lower than the second acceptor concentration N2 in the range of less than 1000 kJ / cm. By setting the concentration in this manner, it is possible to obtain the effect of reducing the step thickness dependency of the on-resistance.

[0099] [Example of change] The above-described embodiments can be modified, for example, as follows: The above-described embodiments and the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts common to the above-described embodiments will be assigned the same reference numerals as in the above-described embodiments, and their description will be omitted.

[0100] In the main body 40 of the gate layer 22, the thickness relationships among the lower layer 44, intermediate layer 46, and upper layer 48 are not particularly limited to those described in the above embodiment. The intermediate layer 46 may be formed entirely as the first intermediate layer 52, and the second intermediate layer 54 (lower intermediate layer) and the third intermediate layer 56 (upper intermediate layer) may be omitted.

[0101] The nitride semiconductor device 10 is not limited to a GaN-HEMT, but may be a transistor using other nitride semiconductors. The term "on" as used in this disclosure includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0102] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described herein being "up" and "down" of the vertical direction. For example, the X axis direction may be the vertical direction, or the Y axis direction may be the vertical direction.

[0103] [Note] The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0104] [Appendix A1] an electron transit layer (16); an electron supply layer (18) located on the electron transit layer (16) and having a band gap larger than that of the electron transit layer (16); a gate layer (22) located on the electron supply layer (18) and containing acceptor-type impurities; a gate electrode (24) located on the gate layer (22); a source electrode (28) including a source contact portion (28SC) in contact with the electron supply layer (18); a drain electrode (30) including a drain contact portion (30DC) in contact with the electron supply layer (18), The gate layer (22) A main body (40); a source side extension portion (42S) extending from the main body portion (40) toward the source contact portion (28SC); a drain side extension portion (42D) extending from the main body portion (40) toward the drain contact portion (30DC), The main body portion (40) is a lower layer (44) that is undoped or contains the acceptor-type impurities at a first acceptor concentration; an intermediate layer (46) containing the acceptor-type impurities at a second acceptor concentration higher than the first acceptor concentration; an upper layer (48) in which the gate electrode (24) is located, the upper layer (48) being undoped or containing the acceptor-type impurities at a third acceptor concentration lower than the second acceptor concentration; The nitride semiconductor device (10) is configured such that the source-side extension (42S) and the drain-side extension (42D) are undoped or contain the acceptor-type impurities at a fourth acceptor concentration lower than the second acceptor concentration.

[0105] [Appendix 2] 2. The nitride semiconductor device (10) according to claim 1, wherein the source-side extension (42S), the drain-side extension (42D), and the lower layer (44) are undoped layers.

[0106] [Appendix 3] 3. The nitride semiconductor device (10) according to claim 1 or 2, wherein the upper layer (48) is an undoped layer.

[0107] [Appendix 4] the first acceptor concentration, the second acceptor concentration, and the third acceptor concentration are concentrations measured at or below intermediate positions between the lower layer (44), the intermediate layer (46), and the upper layer (48) in the thickness direction of the main body (40), respectively; The nitride semiconductor device (10) according to any one of Appendices 1 to 3, wherein the fourth acceptor concentration is a concentration measured at or below an intermediate position between the source-side extension portion (42S) and the drain-side extension portion (42D) in the thickness direction.

[0108] [Appendix 5] the first acceptor concentration, the second acceptor concentration, and the third acceptor concentration are concentrations measured at the bottom of the lower layer (44), the middle layer (46), and the upper layer (48), respectively; The nitride semiconductor device (10) according to appendix 4, wherein the fourth acceptor concentration is a concentration measured at the bottom of the source-side extension (42S) and the drain-side extension (42D).

[0109] [Appendix 6] the first acceptor concentration, the second acceptor concentration, and the third acceptor concentration are the average acceptor concentration of the lower layer (44), the average acceptor concentration of the middle layer (46), and the average acceptor concentration of the upper layer (48), respectively; 4. The nitride semiconductor device (10) according to any one of appendices 1 to 3, wherein the fourth acceptor concentration is an average acceptor concentration in each of the source-side extension (42S) and the drain-side extension (42D).

[0110] [Appendix 7] The nitride semiconductor device (10) according to any one of Appendices 1 to 6, wherein the main body portion (40) includes a lower intermediate layer (54) located between the lower layer (44) and the intermediate layer (46) and having an acceptor concentration that increases from zero or the first acceptor concentration toward the second acceptor concentration.

[0111] [Appendix 8] The nitride semiconductor device (10) according to any one of Appendices 1 to 7, wherein the main body portion (40) includes an upper intermediate layer (56) located between the intermediate layer (46) and the upper layer (48), the upper intermediate layer (56) having an acceptor concentration that decreases from the second acceptor concentration toward zero or the third acceptor concentration.

[0112] [Appendix 9] The main body portion (40) is a lower intermediate layer (54) located between the lower layer (44) and the intermediate layer (46), the lower intermediate layer (54) having an acceptor concentration that increases from zero or the first acceptor concentration toward the second acceptor concentration; an upper intermediate layer (56) located between the intermediate layer (46) and the upper layer (48), the upper intermediate layer having an acceptor concentration that decreases from the second acceptor concentration toward zero or the third acceptor concentration; 7. The nitride semiconductor device (10) according to any one of claims 1 to 6, wherein the upper intermediate layer (54) has a thickness different from that of the lower intermediate layer (56).

[0113] [Appendix 10] The second acceptor concentration is 2.0×10 17 cm -3 The nitride semiconductor device (10) according to any one of appendices 1 to 9 described above.

[0114] [Appendix 11] The second acceptor concentration is 3.0×10 20 cm -3 A nitride semiconductor device (10) according to appendix 10, which is as follows:

[0115] [Appendix 12] The first acceptor concentration, the third acceptor concentration, and the fourth acceptor concentration are greater than 0 and less than 3.0×10 20 cm -3 12. The nitride semiconductor device (10) according to any one of appendices 1 to 11, wherein the concentration of the second acceptor is set to a value lower than the second acceptor concentration in the range of less than 1.

[0116] [Appendix 13] 13. The nitride semiconductor device (10) according to any one of claims 1 to 12, wherein the intermediate layer (46) has a thickness smaller than that of the upper layer (48).

[0117] [Appendix 14] 14. The nitride semiconductor device (10) according to any one of appendices 1 to 13, wherein the intermediate layer (46) has a thickness of 10 nm or more and 100 nm or less.

[0118] [Appendix 15] The nitride semiconductor device (10) according to any one of appendices 1 to 14, wherein the acceptor-type impurity is at least one of Mg, Zn, Fe, and C.

[0119] [Appendix 16] the electron transit layer (16) is a GaN layer, the electron supply layer (18) is an AlGaN layer, 16. The nitride semiconductor device (10) according to any one of appendices 1 to 15, wherein the gate layer (22) is a GaN layer containing the acceptor-type impurities.

[0120] [Appendix 17] A method for manufacturing a nitride semiconductor device (10), comprising: forming an electron transit layer (16) using a first nitride semiconductor; forming an electron supply layer (18) on the electron transit layer (16) using a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor; forming a gate layer (22) on the electron supply layer (18) using a third nitride semiconductor containing an acceptor-type impurity; forming a gate electrode (24) on the gate layer (22); and forming a source electrode (28) including a source contact portion (28SC) in contact with the electron supply layer (18) and a drain electrode (30) including a drain contact portion (30DC) in contact with the electron supply layer (18); Forming the gate layer (22) from the third nitride semiconductor containing the acceptor-type impurity forming a first layer (62) from the third nitride semiconductor that is undoped or contains the acceptor-type impurities at a first acceptor concentration; forming a second layer (64) on the first layer (62) using the third nitride semiconductor containing the acceptor-type impurities at a second acceptor concentration higher than the first acceptor concentration; forming a third layer (66) on the second layer (64) using the third nitride semiconductor that is undoped or that contains the acceptor-type impurities at a third acceptor concentration lower than the second acceptor concentration; partially etching the third layer (66) and the second layer (64) down to the first layer (62) to form a body portion (40) of the gate layer (22) including a portion of the first layer (62), a portion of the second layer (64), and a portion of the third layer (66); and partially etching the first layer (62) to form a source-side extension portion (42S) extending from the body portion (40) toward the source contact portion (28SC) and a drain-side extension portion (42D) extending from the body portion (40) toward the drain contact portion (30DC); A method for manufacturing a nitride semiconductor device (10), comprising: [Explanation of symbols]

[0121] 10...Nitride semiconductor device 12...Semiconductor substrate 14...Buffer layer 16...Electron transit layer 18...electron supply layer 20...2DEG 22...Gate layer 24...Gate electrode 26...passivation layer 26S…Source opening 26D...Drain opening 28...Source electrode 28SC...Source contact part 28SF…Source Field Plate Section 28E…End 30...Drain electrode 30DC...Drain contact part 32...Gate wiring 32V...connecting conductor 34...Source wiring 34V...connecting conductor 36...Drain wiring 36V…connecting conductor 40...Main body 42S…Source side extension part 42D...Drain side extension 44...Lower layer 46...Middle class 48...upper layer 52...First middle class 54...Second middle class (lower middle class) 56...Third middle class (upper middle class) 62...First layer 64...Second layer 66...Third layer

Claims

1. an electron transit layer; an electron supply layer located on the electron transit layer and having a band gap larger than that of the electron transit layer; a gate layer located on the electron supply layer and containing an acceptor-type impurity; a gate electrode located on the gate layer; a source electrode including a source contact portion in contact with the electron supply layer; a drain electrode including a drain contact portion in contact with the electron supply layer, The gate layer a main body; a source side extension portion extending from the main body portion toward the source contact portion; a drain-side extension portion extending from the main body portion toward the drain contact portion, The main body portion is a lower layer that is undoped or contains said acceptor-type impurities at a first acceptor concentration; an intermediate layer containing the acceptor-type impurities at a second acceptor concentration higher than the first acceptor concentration; an upper layer in which the gate electrode is located and which is undoped or contains the acceptor-type impurities at a third acceptor concentration lower than the second acceptor concentration; the source-side extension and the drain-side extension are undoped or contain the acceptor-type impurity at a fourth acceptor concentration lower than the second acceptor concentration.

2. The nitride semiconductor device according to claim 1 , wherein said source-side extension, said drain-side extension, and said lower layer are undoped layers.

3. The nitride semiconductor device according to claim 1 , wherein said upper layer is an undoped layer.

4. the first acceptor concentration, the second acceptor concentration, and the third acceptor concentration are concentrations measured at or below intermediate positions between the lower layer, the intermediate layer, and the upper layer in a thickness direction of the main body portion, respectively; 2. The nitride semiconductor device according to claim 1, wherein said fourth acceptor concentration is a concentration measured at or below an intermediate position between said source-side extension and said drain-side extension in said thickness direction.

5. the first acceptor concentration, the second acceptor concentration, and the third acceptor concentration are concentrations measured at the bottom of the lower layer, the middle layer, and the upper layer, respectively; The nitride semiconductor device according to claim 4 , wherein said fourth acceptor concentration is a concentration measured at the bottom of said source-side extension and said drain-side extension.

6. the first acceptor concentration, the second acceptor concentration, and the third acceptor concentration are the average acceptor concentration of the lower layer, the average acceptor concentration of the middle layer, and the average acceptor concentration of the upper layer, respectively; The nitride semiconductor device according to claim 1 , wherein said fourth acceptor concentration is an average acceptor concentration in each of said source-side extension and said drain-side extension.

7. 2. The nitride semiconductor device according to claim 1, wherein the main body portion includes a lower intermediate layer located between the lower layer and the intermediate layer, the lower intermediate layer having an acceptor concentration that increases from zero or the first acceptor concentration toward the second acceptor concentration.

8. 2. The nitride semiconductor device according to claim 1, wherein the main body portion includes an upper intermediate layer located between the intermediate layer and the upper layer, the upper intermediate layer having an acceptor concentration that decreases from the second acceptor concentration toward zero or the third acceptor concentration.

9. The main body portion is a lower intermediate layer located between the lower layer and the intermediate layer, the lower intermediate layer having an acceptor concentration that increases from zero or the first acceptor concentration toward the second acceptor concentration; an upper intermediate layer located between the intermediate layer and the upper layer, the upper intermediate layer having an acceptor concentration that decreases from the second acceptor concentration toward zero or the third acceptor concentration; The nitride semiconductor device of claim 1 , wherein said upper intermediate layer has a thickness different from that of said lower intermediate layer.

10. The second acceptor concentration is 2.0×10 １７ cm －３ The nitride semiconductor device according to claim 1 .

11. The second acceptor concentration is 3.0×10 ２０ cm －３ The nitride semiconductor device according to claim 10 , wherein:

12. The first acceptor concentration, the third acceptor concentration, and the fourth acceptor concentration are greater than 0 and less than 3.0×10 ２０ cm －３ 2. The nitride semiconductor device according to claim 1, wherein the concentration of said second acceptor is set to a value lower than said second acceptor concentration in a range of less than 1000 .mu.m.

13. The nitride semiconductor device according to claim 1 , wherein said intermediate layer has a thickness smaller than that of said upper layer.

14. The nitride semiconductor device according to claim 1 , wherein said intermediate layer has a thickness of not less than 10 nm and not more than 100 nm.

15. 2. The nitride semiconductor device according to claim 1, wherein said acceptor-type impurity is at least one of Mg, Zn, Fe, and C.

16. the electron transit layer is a GaN layer, the electron supply layer is an AlGaN layer, 16. The nitride semiconductor device according to claim 1, wherein said gate layer is a GaN layer containing said acceptor-type impurities.

17. A method for manufacturing a nitride semiconductor device, comprising: forming an electron transit layer using a first nitride semiconductor; forming an electron supply layer on the electron transit layer, the electron supply layer being made of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor; forming a gate layer on the electron supply layer using a third nitride semiconductor containing an acceptor-type impurity; forming a gate electrode on the gate layer; and forming a source electrode including a source contact portion in contact with the electron supply layer and a drain electrode including a drain contact portion in contact with the electron supply layer; forming a gate layer using the third nitride semiconductor containing the acceptor-type impurity, forming a first layer from the third nitride semiconductor that is undoped or that contains the acceptor-type impurity at a first acceptor concentration; forming a second layer on the first layer, the second layer being made of the third nitride semiconductor containing the acceptor-type impurities at a second acceptor concentration higher than the first acceptor concentration; forming a third layer on the second layer using the third nitride semiconductor that is undoped or that contains the acceptor-type impurity at a third acceptor concentration lower than the second acceptor concentration; partially etching the third layer and the second layer down to the first layer to form a body portion of the gate layer including a portion of the first layer, a portion of the second layer, and a portion of the third layer; and partially etching the first layer to form a source-side extension portion extending from the body portion toward the source contact portion and a source-side extension portion extending from the body portion toward the source contact portion; A method for manufacturing a nitride semiconductor device, comprising:

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