Semiconductor integrated circuit

Abstract

To provide a semiconductor integrated circuit provided with an overcurrent protection circuit that reduces temperature dependency of threshold current of an overcurrent detection circuit.SOLUTION: A semiconductor integrated circuit 100 is provided with a high-side transistor 102 and an overcurrent detection circuit 130. The overcurrent detection circuit 130 includes a V / I conversion circuit 200, a replica transistor 132, a comparator 134 and a first switch SW1. The overcurrent detection circuit 130 compares a current that flows through the high-side transistor 102 with a threshold current. The V / I conversion circuit 200 converts a reference voltage VREF to a reference current IREF, and sinks from the replica transistor 132. The comparator 134 compares a drain voltage of the high-side transistor 102 and a drain voltage of the replica transistor 132. The V / I conversion circuit 200 is provided with a voltage dividing circuit 210 and a NMOS transistor MN1, and capable of adjusting gate voltage of the NMOS transistor MN1.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to overcurrent detection. [Background technology]

[0002] When an overcurrent flows through a transistor that constitutes a semiconductor integrated circuit, the reliability of the transistor and other elements connected to the transistor deteriorates. For this reason, an overcurrent protection circuit is provided in the semiconductor integrated circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-82754

[0004] [overview] An aspect of the present disclosure has been made in light of this situation, and one exemplary purpose of the aspect is to reduce the temperature dependency of the threshold current of an overcurrent detection circuit.

[0005] A semiconductor integrated circuit according to one embodiment of the present disclosure includes a high-side transistor that is a PMOS transistor and an overcurrent detection circuit that compares a current flowing through the high-side transistor with a threshold current. The overcurrent detection circuit includes a voltage-to-current conversion circuit that converts a reference voltage into a reference current, a replica transistor that is a PMOS transistor and has its source connected to the source of the high-side transistor, and a comparator that compares the drain voltage of the high-side transistor with the drain voltage of the replica transistor. The voltage-to-current conversion circuit includes an input terminal that receives the reference voltage, an NMOS transistor as a native element, a first resistor connected between the source of the NMOS transistor and ground, and a voltage divider circuit that includes second and third resistors connected in series between the input terminal and ground and divides the reference voltage and supplies a voltage to the gate of the NMOS transistor.

[0006] Any combination of the above components, or mutual substitution of the components or expressions of the present disclosure between methods, devices, systems, etc., are also valid aspects of the present disclosure. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram of a semiconductor integrated circuit including an overcurrent detection circuit according to a comparative technique. [Figure 3] FIG. 3 is a circuit diagram of a DC / DC converter including a controller IC according to an embodiment.

[0008] [Detailed explanation] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure will be provided. This summary is intended to provide a basic understanding of one or more embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0009] This summary is not an exhaustive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or delineate the scope of some or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

[0010] According to one embodiment, a semiconductor integrated circuit includes a high-side transistor (PMOS transistor) and an overcurrent detection circuit that compares a current flowing through the high-side transistor with a threshold current. The overcurrent detection circuit includes a voltage-to-current converter that converts a reference voltage into a reference current, a replica transistor (PMOS transistor) that is provided on a path of the reference current output from the voltage-to-current converter and has its source connected to the source of the high-side transistor, and a comparator that compares the drain voltage of the high-side transistor with the drain voltage of the replica transistor. The voltage-to-current converter includes an input terminal that receives the reference voltage, an NMOS transistor (native element), a first resistor connected between the source of the NMOS transistor and ground, and a voltage divider circuit that includes second and third resistors connected in series between the input terminal and ground and divides the reference voltage and supplies the divided voltage to the gate of the NMOS transistor.

[0011] With this configuration, by adjusting the voltage division ratio of the voltage divider circuit, the temperature characteristics of the reference current can be adjusted, and the difference in temperature characteristics between the high-side transistor and the replica transistor can be canceled out. This reduces the temperature dependency of the threshold current of the overcurrent detection circuit. In addition, by using native elements as NMOS transistors, fluctuations in the threshold current due to process variations can be reduced.

[0012] In one embodiment, the replica transistor may include multiple PMOS transistors stacked vertically, which allows the size parameter (W / L) of the replica transistor to be reduced, thereby reducing the amount of reference current.

[0013] In one embodiment, the overcurrent detection circuit may further include a first switch connected between the drain and source of the high-side transistor.

[0014] In one embodiment, the voltage divider circuit may further include a second switch connected in series with the second resistor and the third resistor.

[0015] In one embodiment, the V / I conversion circuit may further include a third switch connected in series with the replica transistor.

[0016] In one embodiment, the high-side transistor may be a switching element of a DC / DC converter, and the semiconductor integrated circuit may be a controller IC of the DC / DC converter.

[0017] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be designated by the same reference numerals, and redundant descriptions will be omitted where appropriate. Furthermore, the embodiments are merely examples and do not limit the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0018] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0019] Similarly, "a state in which component C is provided between component A and component B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the functions or effects achieved by their combination.

[0020] 1 is a circuit diagram of a semiconductor integrated circuit 100 according to an embodiment. The semiconductor integrated circuit 100 is a functional IC that includes a high-side transistor 102, a reference voltage source 110, a high-side driver 120, and an overcurrent detection circuit 130, and is integrated on a single semiconductor substrate.

[0021] The reference voltage source 110 supplies a reference voltage V REFThis reference voltage V REF is supplied to an overcurrent detection circuit 130 and other circuit blocks not shown.

[0022] The high-side transistor 102 is a P-channel MOSFET, and its source is connected to the input terminal PVIN and its drain is connected to the output terminal OUT. IN The output terminal OUT is connected to a load (not shown).

[0023] The high-side driver 120 controls the on / off of the high-side transistor 102 in response to the control signal HCTRL. Specifically, when the control signal HCTRL is at a first level (e.g., low), the high-side driver 120 supplies a low voltage, i.e., a ground voltage of 0 V, to the gate of the high-side transistor 102, turning the high-side transistor 102 on. When the control signal HCTRL is at a second level (e.g., high), the high-side driver 120 supplies a high voltage, i.e., an input voltage V IN , turning the high-side transistor 102 off.

[0024] The overcurrent detection circuit 130 is enabled when the high-side transistor 102 is in an on-state, and detects the current I OUT is the threshold current I OCP Compared to, I OUT >I OCP When this occurs, the overcurrent detection circuit 130 asserts the overcurrent detection signal OCPDET. In this embodiment, the overcurrent detection signal OCPDET is negative logic, and low is assigned to assert. The enable / disable state of the overcurrent detection circuit 130 is controlled according to an enable signal OCPEN generated by a controller (not shown). When the enable signal OCPEN is asserted (high), the overcurrent detection circuit 130 is enabled (on), and when the enable signal OCPEN is negated (low), the overcurrent detection circuit 130 is disabled (off).

[0025] The overcurrent detection circuit 130 includes a V / I conversion circuit 200, a replica transistor 132, a comparator 134, and a first switch SW1.

[0026] The V / I conversion circuit 200 converts a reference voltage V REF into a reference current I REF and outputs it. The replica transistor 132 is a replica of the same type as the high-side transistor 102 and is provided on the path of the reference current I REF generated by the V / I conversion circuit 200, that is, between the output node 201 of the V / I conversion circuit 200 and the input terminal PVIN. The source of the replica transistor 132 is connected to the source of the high-side transistor 102, that is, the input terminal PVIN.

[0027] The ratio of the size parameter (W / L) of the replica transistor 132 to the size parameter (W / L) of the high-side transistor 102 is set to 1:n. Here, W represents the gate width and L represents the gate length.

[0028] The gate of the replica transistor 132 is grounded. As described above, in the on state of the high-side transistor 102, a ground voltage is supplied to its gate. Therefore, in the on state of the high-side transistor 102, the gate-source voltage of each of the high-side transistor 102 and the replica transistor 132 is equal.

[0029] The comparator 134 compares the drain voltage of the high-side transistor 102 with the drain voltage of the replica transistor 132. When V1 < V2, it asserts (low) the overcurrent detection signal OCPDET, and when V1 > V2, it negates (high) the overcurrent detection signal OCPDET. The comparator 134 enters the enabled state when the enable signal OCPEN is asserted and stops operating when the enable signal OCPEN is negated. This can reduce power consumption.

[0030] In the replica transistor 132 and the high-side transistor 102, n×I REF =I OUTWhen this holds, the drain-source voltages between them become equal. That is, V1 = V2 holds. n×I REF >I OUT When this is the case, since V1 > V2, the overcurrent detection signal OCPDET is high (negated). An overcurrent state occurs, and n×I REF <I OUT When this is the case, since V1 < V2, the overcurrent detection signal OCPDET becomes low (asserted). That is, n×I REF becomes the threshold current I OCP for overcurrent detection.

[0031] The first switch SW1 is connected in parallel with the high-side transistor 102. The first switch SW1 is controlled in conjunction with the enable signal OCPEN of the overcurrent detection circuit 130. When the enable signal OCPEN is asserted (high), the first switch SW1 turns off, and when the enable signal OCPEN is negated (low), the first switch SW1 turns on. The switch SW1B is provided between the output terminal OUT and the input terminal of the comparator 134. The switch SW1B is controlled complementarily to the first switch SW1 in response to the inverted enable signal OCPENB.

[0032] The V / I conversion circuit 200 includes a voltage division circuit 210, an NMOS transistor MN1, a first resistor R1, and a third switch SW3.

[0033] The NMOS transistor MN1 is a native device. A native device is located between the enhancement mode and the depletion mode and has a threshold voltage close to 0. A native device is a transistor formed without performing doping for adjusting the threshold voltage within the channel region, and refers to one created without additional doping on a silicon substrate doped p-type from the beginning. The first resistor R1 is connected between the source of the NMOS transistor MN1 and the ground.

[0034] The voltage divider circuit 210 includes a second resistor R2 and a third resistor R3 connected in series between the input terminal IN and ground. REF The voltage Vg obtained by dividing the overcurrent detection circuit 130 is supplied to the gate of the NMOS transistor MN1. The voltage divider circuit 210 further includes a second switch SW2. The second switch SW2 is controlled in response to an inverted signal OCPENB of the enable signal OCPEN. The second switch SW2 is turned on when the inverted enable signal OCPENB is asserted (low), and is turned off when the inverted enable signal OCPENB is negated (high). This blocks the current path when the overcurrent detection circuit 130 is disabled, thereby reducing power consumption.

[0035] The third switch SW3 is connected in series with the NMOS transistor MN1 and is switched on and off in response to the enable signal OCPEN. When the overcurrent detection circuit 130 is in a disabled state, the third switch SW3 is turned off, and the reference current I REF The current path is cut off, reducing power consumption.

[0036] The above is the configuration of the V / I conversion circuit 200. Next, the operation of the V / I conversion circuit 200 will be described.

[0037] The gate voltage Vg of the NMOS transistor MN1 is expressed by the formula (1). Vg=V REF ×R3 / (R2+R3) …(1) As will be described later, in this embodiment, the voltage division ratio R3 / (R2+R3) of the voltage divider circuit 210 is used as a parameter that defines the temperature characteristics of the V / I conversion circuit 200.

[0038] The source voltage Vs of the NMOS transistor MN1 is expressed by the formula (2). Vs=Vg-V gs =V REF ×R3 / (R2+R3)-V gs …(2) V gs is the gate-source voltage of the NMOS transistor MN1.

[0039] The current I flowing through the first resistor R1 and the NMOS transistor MN1 REF is expressed by equation (3). I REF =Vs / R1=(V REF ×R3 / (R2+R3)-V gs ) / R1 …(3)

[0040] For accurate overcurrent detection, the high-side transistor 102 and the replica transistor 132 must have the same temperature characteristics. However, to reduce power consumption, the on-resistance of the replica transistor 132 must be increased to reduce the current flowing through the replica transistor 132. For this reason, the replica transistor 132 has a vertically stacked structure of multiple PMOS transistors. When such a configuration is adopted, the high-side transistor 102 and the replica transistor 132 have different temperature characteristics.

[0041] In the overcurrent detection circuit 130, the reference current I generated by the V / I conversion circuit 200 REF has temperature characteristics that can cancel the difference in temperature characteristics between the high-side transistor 102 and the replica transistor 132.

[0042] In the V / I conversion circuit 200, the reference current I REF The temperature characteristic of the reference current I can be set according to the gate voltage Vg of the NMOS transistor MN1. The gate voltage Vg is expressed by equation (1), so the reference current I REF The temperature characteristics are specified.

[0043] Gate voltage Vg and reference current I REF The relationship between the temperature characteristics will be explained.

[0044] The gate-source voltage V of the native NMOS transistor MN1 gsis 0.15V at room temperature. The temperature coefficient is k=-1.6mV / ℃. Since the temperature dependence of the gate voltage Vg in equation (1) can be ignored, the source voltage Vs is gs Therefore, the temperature dependence of the source voltage Vs is -(k / Vs)=1.6mV / Vs[ppm / ℃] Vs=Vg-V gs Therefore, the temperature dependence of the source voltage Vs is α=-k / (Vg-V gs )=1.6mV / (Vg-0.15V)[ppm / ℃] and is expressed as a function of the gate voltage Vg.

[0045] The reference current I generated by the V / I conversion circuit 200 REF The temperature dependence of is (1+α) / (1+β)-1 β is the temperature dependency of the first resistor R1, and is, for example, +1500 ppm / °C.

[0046] For example, if the temperature characteristic of the on-resistance of the high-side transistor 102 is 3000 ppm and the temperature characteristic of the on-resistance of the replica transistor 132 is 3500 ppm, the reference current I REF The temperature dependency Z is 500 ppm. Z=(1+α) / (1+β)-1 The voltage division ratio of the voltage divider circuit 210 should be determined so that the determined gate voltage Vg is obtained.

[0047] The overcurrent detection circuit 130 detects a threshold current I OCP It also has the advantage that the variation in the

[0048] In this embodiment, a native element is used as the NMOS transistor MN1. The native element is not affected by variations in doping to the channel region during the manufacturing process, so the gate-source voltage Vgs The variation of is smaller than that of non-native devices. Now, the gate-source voltage V gs The variation in the voltage is ±0.025V and the variation in the resistance value is ±10%. Because the pairing of resistors R2 and R3 can suppress the relative variation to a negligible level, R3 / (R2+R3) can be treated as a constant, and only the variation in resistor R1 needs to be considered.

[0049] Considering process variations, the reference current I REF I REF(TYP) The variation is small, with a range of 88.8% to 113.7%.

[0050] The advantages of the overcurrent detection circuit 130 become clear when compared with a comparative technique, which will now be described.

[0051] 2 is a circuit diagram of a semiconductor integrated circuit 100R including an overcurrent detection circuit 130R according to a comparative technique. The overcurrent detection circuit 130R differs from that shown in FIG. 1 in the configuration of a V / I conversion circuit 200R. The V / I conversion circuit 200R is a closed-loop type, omitting the voltage divider circuit 210 and providing an operational amplifier OA1.

[0052] The V / I conversion circuit 200R also includes an NMOS transistor MN2, which is a normal non-native element, instead of the NMOS transistor MN1, which is a native element. The current mirror circuits CM1 and CM2 mirror the current flowing through the NMOS transistor MN2 to generate a reference current I REF Sink.

[0053] Due to negative feedback control by the operational amplifier OA1, the gate voltage Vg of the NMOS transistor MN2 is equal to the source voltage Vs and the reference voltage V REF Therefore, the current flowing through the first resistor R1 is expressed by equation (7). I R1 =V REF / R1 …(7)

[0054] This current IR1 is reflected by the current mirror circuits CM1 and CM2, resulting in the reference current I REF When the current mirror ratio of the current mirror circuits CM1 and CM2 is 1, the reference current I REF is expressed by equation (8). I REF =V REF / R1 …(8)

[0055] The problem with the overcurrent detection circuit 130R in FIG. 2 will be described.

[0056] In order to cancel the difference in temperature characteristics between the high-side transistor 102 and the replica transistor 132, the comparison technique also uses a reference current I REF In the comparative technique, the reference current I REF To impart temperature dependence to the high-side transistor 102, a first resistor R1 having a temperature characteristic is used. For example, if the temperature characteristic of the on-resistance of the high-side transistor 102 is 3000 ppm and the temperature characteristic of the replica transistor 132 is 3500 ppm, the first resistor R1 only needs to have a temperature characteristic of -500 ppm. The first resistor R1 is configured by connecting a resistor R1p having a positive temperature characteristic and a resistor R1n having a negative temperature characteristic in series.

[0057] In this configuration, if the resistance values ​​of resistors R1p and R1n are affected by process variations, the temperature characteristics of the first resistor R1 may deviate from the design, causing the overcurrent detection threshold I OPC This will result in variations.

[0058] Furthermore, since the closed-loop V / I conversion circuit 200R has a long response time, in applications where the high-side transistor 102 is switched at high speed, the V / I conversion circuit 200R must be kept operating at all times, which increases power consumption.

[0059] Returning to FIG. 1, the advantages of the overcurrent detection circuit 130 will be described. As described above, the overcurrent detection circuit 130 has an overcurrent detection threshold IOCP In addition, because the V / I conversion circuit 200 is an open-loop type, it operates at high speed. Therefore, in applications where the high-side transistor 102 is switched at high speed, the V / I conversion circuit 200 can be enabled / disabled in conjunction with the switching of the high-side transistor 102, thereby reducing power consumption compared to the comparative technology.

[0060] Next, a specific example of the semiconductor integrated circuit 100 will be described.

[0061] 3 is a circuit diagram of a DC / DC converter 300 including a controller IC 100A according to an embodiment. The DC / DC converter 300A is a synchronous rectification step-down converter (Buck converter).

[0062] The controller IC100A has the features of the semiconductor integrated circuit 100 of Fig. 1. In addition to the components of the semiconductor integrated circuit 100 of Fig. 1, the controller IC100A includes a low-side transistor 104, a low-side driver 122, a controller 160, an error amplifier 150, and resistors R11 and R12.

[0063] An inductor L11 and a capacitor C11 are connected to an output terminal OUT, which together with a controller IC100A constitute a DC / DC converter 300.

[0064] DC / DC converter 300 output voltage V OUT is fed back to the feedback terminal FB. The voltage at the feedback terminal FB is divided by resistors R11 and R12. The resistors R11 and R12 may be chip components external to the controller IC 100A. The error amplifier 150 divides the feedback voltage V FB and the reference voltage V REF The controller 160 includes a pulse modulator such as a pulse width modulator or a pulse frequency modulator, and amplifies the output voltage V of the error amplifier 150. ERRThe high-side driver 120 and the low-side driver 122 are supplied with control signals HCTRL and LCTRL that are generated based on the pulse signal.

[0065] The overcurrent detection signal OCPDET generated by the overcurrent detection circuit 130 is supplied to the controller 160. The controller 160 applies overcurrent protection in response to assertion of the overcurrent detection signal OCPDET. For example, pulse-by-pulse overcurrent protection may be applied by turning off the high-side transistor 102 each time the overcurrent detection signal OCPDET is asserted. Alternatively, overcurrent protection may be applied by stopping switching of the high-side transistor 102 and the low-side transistor 104 in response to continuous assertion of the overcurrent detection signal OCPDET.

[0066] As described above, the V / I conversion circuit 200 is an open-loop type and can operate at high speed. Therefore, the controller 160 may generate the enable signal OCPEN for the overcurrent detection circuit 130 in synchronization with the switching of the high-side transistor 102. This cuts off the current flowing through the overcurrent detection circuit 130 while the high-side transistor 102 is off, thereby reducing power consumption.

[0067] The application of the technology disclosed herein is not limited to controller ICs for DC / DC converters. For example, the technology disclosed herein can also be used in audio ICs equipped with class-D amplifiers, motor driver circuits, and the like.

[0068] Furthermore, the high-side transistor is not limited to a switching transistor, but may be a switch that is constantly on, such as a simple switch.

[0069] In the embodiment, the replica transistor 132 is formed as a vertically stacked structure of a plurality of PMOS transistors, but the method for reducing the size parameter (W / L) of the replica transistor 132 is not limited to this.

[0070] The embodiments described using specific terms merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted in the embodiments as long as they do not deviate from the spirit of the present invention as defined in the claims.

[0071] (Addendum) One aspect of the technology disclosed in this specification can be understood as follows.

[0072] (Item 1) A high-side transistor is a PMOS transistor, and an overcurrent detection circuit that compares the current flowing through the high-side transistor with a threshold current; Equipped with The overcurrent detection circuit a voltage-current conversion circuit that converts a reference voltage into a reference current; a replica transistor which is a PMOS transistor provided on a path of the reference current output from the voltage-current conversion circuit and has a source connected to a source of the high-side transistor; a comparator that compares the drain voltage of the high-side transistor with the drain voltage of the replica transistor; Equipped with The voltage-current conversion circuit an input terminal for receiving the reference voltage; A native element NMOS transistor, a first resistor connected between the source of the NMOS transistor and ground; a voltage divider circuit including a second resistor and a third resistor connected in series between the input terminal and ground, which divides the reference voltage and supplies the divided voltage to the gate of the NMOS transistor; A semiconductor integrated circuit comprising:

[0073] (Item 2) Item 1. The semiconductor integrated circuit according to item 1, wherein the replica transistor includes a plurality of PMOS transistors stacked in series.

[0074] (Item 3) The overcurrent detection circuit further includes a first switch connected between the drain and source of the high-side transistor, the semiconductor integrated circuit according to Item 1 or 2.

[0075] (Item 4) The voltage dividing circuit further includes a second switch connected in series with the second resistor and the third resistor, the semiconductor integrated circuit according to any one of Items 1 to 3.

[0076] (Item 5) The voltage-current conversion circuit further includes a third switch connected in series with the replica transistor, the semiconductor integrated circuit according to any one of Items 1 to 4.

[0077] (Item 6) The high-side transistor is a switching element of a DC / DC converter, the semiconductor integrated circuit according to any one of Items 1 to 5.

Explanation of Signs

[0078] 100 Semiconductor integrated circuit 102 High-side transistor 104 Low-side transistor 110 Reference voltage source 120 High-side driver 122 Low-side driver 130 Overcurrent detection circuit 132 Replica transistor 134 Comparator 150 Error amplifier 160 Controller SW1 First switch 200 V / I conversion circuit MN1 NMOS transistor R1 First resistor R2 Second resistor R3 Third resistor 210 Voltage dividing circuit

Claims

1. a high-side transistor that is a PMOS transistor; an overcurrent detection circuit that compares the current flowing through the high-side transistor with a threshold current; Equipped with The overcurrent detection circuit a voltage-current conversion circuit that converts a reference voltage into a reference current; a replica transistor which is a PMOS transistor provided on a path of the reference current output from the voltage-current conversion circuit and has a source connected to a source of the high-side transistor; a comparator that compares the drain voltage of the high-side transistor with the drain voltage of the replica transistor; Equipped with The voltage-current conversion circuit an input terminal for receiving the reference voltage; a native element NMOS transistor; a first resistor connected between the source of the NMOS transistor and ground; a voltage divider circuit including a second resistor and a third resistor connected in series between the input terminal and ground, the voltage divider circuit dividing the reference voltage and supplying the resulting voltage to the gate of the NMOS transistor; A semiconductor integrated circuit comprising:

2. The semiconductor integrated circuit according to claim 1 , wherein the replica transistors include a plurality of PMOS transistors stacked in series.

3. 3. The semiconductor integrated circuit according to claim 1, wherein the overcurrent detection circuit further includes a first switch connected between a drain and a source of the high-side transistor.

4. 3. The semiconductor integrated circuit according to claim 1, wherein said voltage divider circuit further includes a second switch connected in series with said second resistor and said third resistor.

5. 3. The semiconductor integrated circuit according to claim 1, wherein said voltage-current converter circuit further includes a third switch connected in series with said replica transistor.

6. 3. The semiconductor integrated circuit according to claim 1, wherein the high-side transistor is a switching element of a DC / DC converter.

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