Semiconductor device, method for manufacturing the same, and electronic apparatus

Abstract

To provide a semiconductor device capable of suppressing performance deterioration due to decrease in a current amplification factor.SOLUTION: A semiconductor device includes a bipolar junction transistor having a substrate made of SiC and an emitter electrode, a collector electrode, and a base electrode formed on a main surface side of the substrate. The semiconductor device further includes an element isolation region surrounding the bipolar junction transistor. The element isolation region includes: a trench; an insulating layer formed on an inner surface of the trench; and a nitrogen passivation region that is formed on an interface side of the substrate exposed to the trench and into which nitrogen is introduced.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device. [Background technology]

[0002] Semiconductor devices made of silicon carbide (SiC) are used in sensors, measuring instruments, and various other devices that are used in radiation environments. Semiconductor devices made of SiC have higher resistance to temperature, power density, and radiation density than semiconductor devices made of Si. Furthermore, bipolar junction transistors (BJTs) made of SiC are used as a type of power semiconductor capable of operating at high currents and high voltages. A configuration including a base layer formed by epitaxial growth on a collector layer, a mesa-shaped emitter layer formed by epitaxial growth on the base layer, and a protective film formed on the emitter layer has been proposed for the BJT (see, for example, Patent Document 1). A semiconductor device having this configuration can increase the current gain h of the BJT by suppressing the generation of surface recombination current in the base layer due to damage to the SiC crystal caused by ion implantation or the like. FE This has curbed the decline in [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-173841 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device has multiple BJT elements formed on a substrate, and therefore requires element isolation regions between the elements, each of which is made up of a trench formed from the surface of the substrate in the depth direction and an insulating film buried inside the trench. However, in the isolation region of a semiconductor device, defects occur in the SiC crystal at the interface of the formed trench. These defects trap minority carriers at the interface of the SiC substrate, generating a surface recombination current. As a result, the surface recombination current increases the current gain h of the transistor. FE The current gain h FE The decrease in the capacitance causes a decrease in the performance of the semiconductor device and the electronic device incorporating the semiconductor device.

[0005] In order to solve the above-mentioned problems, the present invention provides a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device that can suppress a decrease in performance due to a decrease in current amplification factor.

[0006] The above and other objects of the present invention and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] The semiconductor device of the present invention comprises a substrate made of SiC, a bipolar junction transistor having an emitter electrode, a collector electrode, and a base electrode formed on the main surface of the substrate, and an element isolation region surrounding the bipolar junction transistor. The element isolation region has a trench, an insulating layer formed on the inner surface of the trench, and a nitrogen passivation region doped with nitrogen and formed on the interface of the substrate exposed to the trench.

[0008] A method for manufacturing a semiconductor device according to the present invention includes the steps of forming a bipolar junction transistor having an emitter electrode, a collector electrode, and a base electrode on a main surface of a substrate, forming a trench surrounding the bipolar junction transistor from the main surface of the substrate, forming an insulating layer covering the inner surface of the trench, and introducing nitrogen into the interface of the substrate exposed to the inner surface of the trench.

[0009] An electronic device according to the present invention includes an electronic circuit on which the semiconductor device is mounted. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device that can suppress performance degradation due to a decrease in current amplification factor.

[0011] Problems, configurations, and effects other than those described above will become clear from the following description of the embodiments. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment. [Figure 2] FIG. 10 is a diagram showing the configuration of a semiconductor device according to a second embodiment. [Figure 3] FIG. 10 is a diagram showing the configuration of a semiconductor device according to a third embodiment. [Figure 4] FIG. 10 is a diagram showing the configuration of a semiconductor device according to a fourth embodiment. [Figure 5] FIG. 10 is a diagram showing the configuration of a semiconductor device according to a fifth embodiment. [Figure 6] 1A to 1C are diagrams for explaining a method for manufacturing a semiconductor device. [Figure 7] 1A to 1C are diagrams for explaining a method for manufacturing a semiconductor device. [Figure 8] 1A to 1C are diagrams for explaining a method for manufacturing a semiconductor device. [Figure 9] 1A to 1C are diagrams for explaining a method for manufacturing a semiconductor device. [Figure 10] 1A to 1C are diagrams for explaining a method for manufacturing a semiconductor device. [Figure 11] 1A to 1C are diagrams for explaining a method for manufacturing a semiconductor device. [Figure 12] 1A to 1C are diagrams for explaining a method for manufacturing a semiconductor device. [Figure 13] 1A to 1C are diagrams for explaining a method for manufacturing a semiconductor device. [Figure 14] 1A to 1C are diagrams for explaining a method for manufacturing a semiconductor device. [Figure 15] 1A to 1C are diagrams for explaining a method for manufacturing a semiconductor device. [Figure 16] 1A to 1C are diagrams for explaining a method for manufacturing a semiconductor device. [Figure 17] 1A to 1C are diagrams for explaining a method for manufacturing a semiconductor device. [Figure 18] 1A to 1C are diagrams for explaining a method for manufacturing a semiconductor device. [Figure 19] 1A to 1C are diagrams for explaining a method for manufacturing a semiconductor device. [Figure 20] FIG. 1 is a diagram illustrating a configuration of an electronic device according to an embodiment. [Figure 21] FIG. 1 is a diagram illustrating a configuration of an electronic device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, examples of semiconductor devices, semiconductor device manufacturing methods, and electronic devices according to embodiments of the present invention will be described with reference to the drawings. Note that the present invention is not limited to the following examples. In the drawings described below, common components are given the same reference numerals. Furthermore, in the drawings used in this specification, identical or corresponding components are given the same reference numerals, and repeated explanations of these components may be omitted. The explanation will be given in the following order. 1. First embodiment of semiconductor device 2. Second embodiment of semiconductor device 3. Third embodiment of semiconductor device 4. Fourth embodiment of semiconductor device 5. Fifth embodiment of semiconductor device 6. Manufacturing method of semiconductor device 7. Electronic Devices

[0014] 1. First Embodiment of Semiconductor Device A first embodiment of a semiconductor device will be described. FIG. 1 shows the configuration of a semiconductor device according to the first embodiment. In FIG. 1, a top view of the semiconductor device is shown in the upper part of the drawing, and a cross-sectional view of the semiconductor device is shown in the lower part. Note that the top view of the semiconductor layer omits the configuration of a protective film and a sealing member formed on the semiconductor layer. The semiconductor device 100 shown in FIG. 1 has a lateral bipolar junction transistor (BJT) formed on a SiC substrate 1. Note that in the following embodiments, the first conductivity type will be described as p-type and the second conductivity type as n-type, but these conductivity types may be reversed in the semiconductor device.

[0015] As shown in FIG. 1, the semiconductor device 100 has a transistor region 101 and an element isolation region 102. In FIG. 1, the transistor region 101 and the element isolation region 102 are each indicated by a dashed line. A single lateral bipolar junction transistor element is formed in the transistor region 101. The transistor region 101 is surrounded by the element isolation region 102. The element isolation region 102 electrically isolates the multiple transistor regions 101 arranged on the SiC substrate 1 and the transistors formed in the transistor region 101 from one another.

[0016] The semiconductor device 100 is formed by a SiC substrate 1, a semiconductor layer stack consisting of semiconductor layers 2, 3, and 4 formed by epitaxial growth on the SiC substrate 1, and an emitter electrode 10, a collector electrode 11, and a base electrode 12 formed on the stack. In the following description, the semiconductor layer stack consisting of the SiC substrate 1 and the semiconductor layers 2, 3, and 4 will be simply referred to as a base 20.

[0017] The base 20 has a p-type semiconductor layer 2 (first semiconductor layer) formed on an n-type SiC substrate 1. An n-type semiconductor layer 3 (second semiconductor layer) is formed on the p-type semiconductor layer 2. A p-type semiconductor layer 4 (third semiconductor layer) is formed on the n-type semiconductor layer 3. The p-type semiconductor layer 4 forms the outermost surface of the base 20 that constitutes the semiconductor device 100. The p-type semiconductor layer 2, the n-type semiconductor layer 3, and the p-type semiconductor layer 4 are SiC semiconductor layers into which p-type or n-type impurities have been introduced, respectively.

[0018] The emitter electrode 10, the collector electrode 11, and the base electrode 12 are formed on a first main surface (surface) of the substrate 20. The collector electrode 11 and the base electrode 12 are formed on the side end sides of the transistor region 101. The emitter electrode 10 is disposed between the collector electrode 11 and the base electrode 12. A protective film 9 is formed on the surface of the substrate 20, except for the contact surfaces between the emitter electrode 10, the collector electrode 11, and the base electrode 12 and the substrate 20. The emitter electrode 10, the collector electrode 11, and the base electrode 12 are led out from different side ends of the transistor region 101 to the outside of the element isolation region 102 by wiring formed on the protective film 9. Furthermore, a sealing member 19 is formed on the emitter electrode 10, the collector electrode 11, the base electrode 12, and the protective film 9, and the entire surface of the SiC substrate 1 is sealed. A back surface electrode 13 is formed on the second main surface (back surface) of the SiC substrate 1. The back surface electrode 13 is an electrode for stabilizing the operation of a transistor (lateral BJT) that constitutes the semiconductor device 100.

[0019] The semiconductor device 100 has, on the surface side of the base 20, impurity diffusion layers including an emitter layer 5, a first collector layer 6, a second collector layer 8, and a base layer 7. These impurity diffusion layers are formed in the p-type semiconductor layer 4 or in a region extending from the p-type semiconductor layer 4 to the n-type semiconductor layer 3 in the depth direction from the surface side of the base 20.

[0020] The lower portion of the emitter electrode 10 is provided with an n-type semiconductor layer having a higher impurity concentration than the semiconductor layer 4. +An emitter layer 5 of a silicon nitride type is formed on the surface of the base body 20 within the region of the semiconductor layer 4. The emitter layer 5 is formed on the surface side of the semiconductor layer 4 in an area wider than the emitter electrode 10. The emitter layer 5 is connected to the emitter electrode 10 in an area including the central portion of the emitter layer 5.

[0021] Below the collector electrode 11, a first collector layer 6 of n-type and a second collector layer 8 of n-type with a higher impurity concentration than the first collector layer 6 are provided. + A second collector layer 8 of the n type is formed. + The n-type second collector layer 8 is formed on the surface of the base 20 directly below the collector electrode 11. The second collector layer 8 is formed in an area wider than the contact surface between the collector electrode 11 and the base 20. The second collector layer 8 is surrounded (side and bottom surfaces) by the first collector layer 6 except for the surface of the base 20. In other words, the second collector layer 8 is contained in the formation region of the first collector layer 6 except for the surface of the base 20. The first collector layer 6 is formed on the surface of the base 20 except for the formation region of the second collector layer 8, i.e., the contact surface between the collector electrode 11 and the base 20. The first collector layer 6 is formed to a position deeper than the thickness of the semiconductor layer 4, and is formed to a depth reaching the n-type semiconductor layer 3.

[0022] The lower part of the base electrode 12 is formed with a p + A p-type base layer 7 is formed on the surface of the substrate 20. The base layer 7 is formed on the surface of the substrate 20 so as to surround the emitter layer 5 via the p-type semiconductor layer 4. The base layer 7 may be formed only below the base electrode 12. The base layer 7 is formed so as to surround the emitter layer 5, and a p-type semiconductor layer 4 is formed between the emitter layer 5 and the first collector layer 6. +The presence of the n-type base layer 7 makes it easier to control the movement of carriers in the emitter layer 5 and the first and second collector layers 6 and 8, which is effective for improving switching characteristics and current amplification characteristics. The base layer 7 is formed to a position deeper than the thickness of the semiconductor layer 4, and is formed to a depth that reaches the n-type semiconductor layer 3. The base layer 7 is formed on the surface side of the semiconductor layer 4, in an area that is at least wider than the emitter electrode 10. The emitter electrode 10 is connected to a region of the emitter layer 5 that includes the center of the layer.

[0023] In the semiconductor device 100, a base current is supplied to the base electrode 12, and p + Holes are supplied to the p-type semiconductor layer 4 through the p-type base layer 7. When a collector current is supplied to the collector electrode 11, n + a second collector layer 8 of n-type, a first collector layer 6 of n-type, a semiconductor layer 3 of n-type, a semiconductor layer 4 of p-type, and + A current flows through the emitter layer 5 to the emitter electrode 10 .

[0024] The element isolation region 102 is arranged on the surface side of the SiC substrate 20 so as to surround the transistor region 101 in the planar direction. The element isolation region 102 includes a trench 21 formed in the depth direction from the surface of the substrate 20, an insulating layer 14 buried in the trench 21, and a conductor layer 15.

[0025] The trench 21 is formed from the surface of the base 20 to a depth that reaches the p-type semiconductor layer 2. The trench 21 is formed on the surface side of the base 20 in contact with the n-type first collector layer 6 and the p-type semiconductor layer 4. That is, on the surface of the base 20, the trench 21 is entirely in contact with the p-type semiconductor layer 4 except for the region in contact with the first collector layer 6. Note that the p-type semiconductor layer 4 may be interposed between the trench 21 and the first collector layer 6. Moreover, trench 21 penetrates p-type semiconductor layer 4 and n-type semiconductor layer 3, and is formed deeper than the interface between n-type semiconductor layer 3 and p-type semiconductor layer 2. By forming trench 21 up to p-type semiconductor layer 2, movement of carriers (electrons) between transistors can be captured by p-type semiconductor layer 2.

[0026] The insulating layer 14 includes, for example, a silicon oxide film (SiO) etc. The insulating layer 14 has a thickness that allows electrical isolation of the transistors formed in the transistor region 101, and is sufficiently thinner than the protective film 9 and the conductive layer 15. The conductive layer 15 fills the inside of the trench 21 covered with the thin insulating layer 14. The conductive layer 15 is not particularly limited as long as it has a conductive configuration, and may be formed using polysilicon, metal, or the like. The element isolation region 102 includes at least an insulating layer 14 for the purpose of electrically isolating the transistors formed in the transistor region 101. Therefore, the element isolation region 102 does not necessarily include the conductive layer 15.

[0027] In the element isolation region 102, the inner surface (sidewall and bottom surface) of the trench 21 has a nitrogen passivation region 16. That is, the surfaces of the p-type semiconductor layer 2, the n-type semiconductor layer 3, the p-type semiconductor layer 4, and the n-type first collector layer 6 exposed in the trench 21 have the nitrogen passivation region 16. The nitrogen passivation region 16 is a region in which nitrogen is introduced into each semiconductor layer. The nitrogen passivation region 16 is formed from the interface of the trench 21 toward the inside of the base 20 to a thickness of about 2 nm.

[0028] In the nitrogen passivation region 16, Si at the interface with the substrate 20 is nitrided by a method such as NO annealing. As a result, Si-N bonds are formed at the interface of the semiconductor layer in the trench 21, and a nitrided interface is formed in the substrate 20. In the nitrogen passivation region 16, the nitrogen concentration at the nitrided interface is 10 13 cm -2This concentration can suppress trapping of minority carriers at the interface of the substrate 20 and suppress the generation of surface recombination current. As a result, the current amplification factor h of the lateral BJT formed in the transistor region 101 due to the generation of surface recombination current can be reduced. FE This can suppress the deterioration of the performance of the semiconductor device 100.

[0029] In addition, in conjunction with the interfacial nitridation of the base 20, nitrogen is also introduced into the insulating layer 14. In particular, nitrogen is introduced into the inner surface of the trench 21 in the insulating layer 14. The nitrogen concentration in the insulating layer 14 is not particularly limited. For example, nitrogen is introduced into the SiO that constitutes the insulating layer 14, and nitrides such as SiN and SiON are formed in the insulating layer 14.

[0030] 2. Second Embodiment of Semiconductor Device Next, a second embodiment of the semiconductor device will be described. The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment described above only in the formation region of the nitrogen passivation region. Therefore, in the following, description of the same configuration as the semiconductor device of the first embodiment will be omitted.

[0031] The configuration of a semiconductor device according to the second embodiment is shown in Fig. 2. In Fig. 2, a top view of the semiconductor device 200 is shown in the upper part of the drawing, and a cross-sectional view of the semiconductor device 200 is shown in the lower part. The semiconductor device 200 shown in Fig. 2 is different from the semiconductor device 100 of the first embodiment shown in Fig. 1 described above in that an insulating layer 14a and a nitrogen passivation region 16a are added to the surface side of the base 20. The semiconductor device 200 has the same configuration as the semiconductor device 100 shown in Fig. 1 described above, except for the configurations of the insulating layer 14a and the nitrogen passivation region 16a.

[0032] The insulating layer 14a and the nitrogen passivation region 16a formed on the surface side of the substrate 20 are formed in the region in the transistor region 101 where the surface of the substrate 20 contacts the bottom surface of the protective film 9. That is, the insulating layer 14a and the nitrogen passivation region 16a are formed in the contact region between the base electrode 12 and the p-type base layer 7, the contact region between the emitter electrode 10 and the n-type base layer 7, and the +The contact area with the emitter layer 5 of the n-type, the collector electrode 11 and + The second collector layer 8 is formed in a region other than the contact region with the second collector layer 8 of the mold. The insulating layer 14a and the nitrogen passivation region 16a are formed in the element isolation region 102 except for the area on the conductive layer 15.

[0033] The nitrogen passivation region 16a forms Si-N bonds at the interface of the semiconductor layer on the surface of the substrate 20, forming a nitrided interface in the substrate 20. The nitrogen passivation region 16a has a nitrogen concentration of 10 13 cm -2 It is preferable that this is equal to or greater than this.

[0034] The generation of surface recombination current due to the trapping of minority carriers at the interface of the semiconductor layer occurs not only in the trench 21 but also on the surface of the substrate 20. For this reason, by providing the nitrogen passivation region 16 formed on the side surface of the trench 21 and the nitrogen passivation region 16a formed on the surface side of the substrate 20, interface defects between the surface of the semiconductor layer and the trench 21 are terminated. This makes it possible for the nitrogen passivation regions 16 and 16a to suppress the effects of interface defects in the semiconductor layer. As a result, the trapping of minority carriers at the interface of the semiconductor layer is suppressed, and the generation of surface recombination current can be suppressed.

[0035] The nitrogen passivation region 16a formed on the surface side of the substrate 20 is preferably continuous with the nitrogen passivation region 16 formed on the side surface of the trench 21. By connecting the nitrogen passivation region 16a and the nitrogen passivation region 16, it is possible to terminate interface defects in the semiconductor layer over a larger area, and it is possible to suppress the effects of interface defects in the semiconductor layer.

[0036] In addition, in conjunction with the interfacial nitriding of the base 20, nitrogen is also introduced into the insulating layer 14a formed on the surface side of the base 20. In particular, nitrogen is introduced into the bottom surface side of the insulating layer 14a that contacts the base 20. The nitrogen concentration in the insulating layer 14a is not particularly limited. For example, nitrogen is introduced into SiO that constitutes the insulating layer 14a, and nitrides such as SiN and SiON are formed in the insulating layer 14a.

[0037] 3. Third Embodiment of Semiconductor Device Next, a third embodiment of the semiconductor device will be described. The semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment described above only in that a configuration for controlling the potential of the element isolation region is added. Therefore, in the following, a description of the same configuration as the semiconductor device of the first embodiment will be omitted.

[0038] The configuration of a semiconductor device according to the third embodiment is shown in Fig. 3. In Fig. 3, a top view of the semiconductor device 300 is shown in the upper part of the drawing, and a cross-sectional view of the semiconductor device 300 is shown in the lower part. The semiconductor device 300 shown in Fig. 3 includes wiring 17 that electrically connects to the semiconductor device 100 of the first embodiment shown in Fig. 1 described above. Except for the wiring 17, the semiconductor device 300 has the same configuration as the semiconductor device 100 shown in Fig. 1 described above.

[0039] The wiring 17 electrically connects the conductive layer 15 formed in the trench 21 of the element isolation region 102 to the base electrode 12. By short-circuiting the conductive layer 15 and the base electrode 12 with the wiring 17, the potential of the conductive layer 15 can be made the same as that of the base electrode 12.

[0040] By setting the conductive layer 15 formed in the trench 21 and the base electrode 12 at the same potential, the same voltage as that of the base electrode 12 is also applied to the conductive layer 15 in the trench 21 when a base current is supplied to the base electrode 12. This makes it possible to suppress activation of interfacial defects in the semiconductor layer exposed from the trench 21 through the insulating layer 14 from the conductive layer 15.

[0041] The wiring 17 is an example of a means for electrically connecting the conductive layer 15 formed in the trench 21 and the base electrode 12. The configuration for electrically connecting the conductive layer 15 and the base electrode 12 is not limited to the wiring 17, and other configurations may be used. Furthermore, the configuration for making the conductive layer 15 formed in the trench 21 and the base electrode 12 at the same potential may be other methods than the above-described electrical connection between the conductive layer 15 and the base electrode 12.

[0042] 4. Fourth Embodiment of Semiconductor Device Next, a fourth embodiment of the semiconductor device will be described. The semiconductor device of the fourth embodiment differs from the semiconductor device of the first embodiment described above only in the configuration of the impurity diffusion layer formed on the surface of the semiconductor layer stack. Therefore, in the following, a description of the same configuration as the semiconductor device of the first embodiment will be omitted.

[0043] The configuration of a semiconductor device according to the fourth embodiment is shown in Fig. 4. In Fig. 4, a top view of the semiconductor device 400 is shown in the upper part of the drawing, and a cross-sectional view of the semiconductor device 400 is shown in the lower part. The semiconductor device 400 shown in Fig. 4 differs from the semiconductor device 100 of the first embodiment shown in Fig. 1 described above in that an n-type buffer layer 18 is formed between the p-type semiconductor layer 4 and the trench 21 of the element isolation region 102. The semiconductor device 400 has the same configuration as the semiconductor device 100 shown in Fig. 1 described above, except for the configuration of the n-type buffer layer 18.

[0044] The n-type buffer layer 18 is formed over the entire surface between the p-type semiconductor layer 4 and the trench 21 of the element isolation region 102, except for the region where the n-type first collector layer 6 is formed. The n-type buffer layer 18 is formed to prevent the p-type semiconductor layer 4 from contacting the trench 21. For this reason, the n-type buffer layer 18 is formed by an impurity diffusion layer of the opposite conductivity type to that of the p-type base layer 7 and the p-type semiconductor layer 4, to which current is supplied from the base electrode 12. Furthermore, the n-type buffer layer 18 is formed to a position deeper than the p-type semiconductor layer 4, and is formed to a depth reaching the n-type semiconductor layer 3. Furthermore, since it is sufficient for the n-type buffer layer 18 to prevent the p-type semiconductor layer 4 from contacting the trench 21, it is not necessary to cover the entire surface of the trench 21. The n-type buffer layer 18 can suppress the influence on the base current caused by the interface of the semiconductor layer exposed in the trench 21, for example, a decrease in the base current due to the trapping of base current carriers (holes) by dangling bonds.

[0045] 4, the n-type first collector layer 6 and the trench 21 are in contact with each other. However, in the semiconductor device 400, for example, when the p-type semiconductor layer 4 is interposed between the n-type first collector layer 6 and the trench 21, it is preferable to form an n-type buffer layer 18 between the p-type semiconductor layer 4 and the trench 21.

[0046] 5. Fifth Embodiment of Semiconductor Device Next, a fifth embodiment of the semiconductor device will be described. The semiconductor device of the fifth embodiment differs from the semiconductor device of the first embodiment described above only in the configuration of the isolation formed in the isolation region. Therefore, in the following, the description of the same configuration as the semiconductor device of the first embodiment will be omitted.

[0047] The configuration of a semiconductor device according to the fifth embodiment is shown in Fig. 5. Fig. 5 is a cross-sectional view of a semiconductor device 500. Note that the cross-sectional view of the semiconductor device 500 shown in Fig. 5 omits the emitter layer 5, the first collector layer 6, the second collector layer 8, and the impurity diffusion layers of the base layer 7 (Fig. 1). Furthermore, the cross-sectional view of the semiconductor device 500 shown in Fig. 5 omits the nitrogen passivation regions 16, 16a (Figs. 1 and 2).

[0048] 5 differs from the semiconductor device 100 of the first embodiment shown in FIG. 1 in that the semiconductor device 500 includes, in the isolation region 102, a plurality of isolations 22 each consisting of a trench 21, an insulating layer 14 buried in the trench 21, and a conductive layer 15. FIG. 5 shows three isolations 22 each consisting of a trench 21, an insulating layer 14, and a conductive layer 15. The number of isolations 22 is not particularly limited. The configurations of the trenches 21, the insulating layer 14, and the conductive layer 15 constituting each isolation 22 are the same as those of the first embodiment.

[0049] The plurality of isolation regions 22 preferably include nitrogen passivation regions 16, 16a (FIGS. 1 and 2). At least, in the trenches 21 formed on both ends of the isolation region 102 and in contact with the transistor region 101, the nitrogen passivation region 16 is provided on the sidewall of the trench on the side in contact with the transistor. In consideration of productivity, it is preferable that the nitrogen passivation region 16 is formed on the entire surface of all the trenches 21 of the plurality of isolation regions 22. The nitrogen passivation region 16a formed on the surface of the base body 20 is preferably formed in the same manner as in the semiconductor device 200 of the second embodiment shown in FIG.

[0050] 6. Manufacturing Method of Semiconductor Device Next, a method for manufacturing the semiconductor device described above will be described, which has a configuration in which the buffer layer of the fourth embodiment is added to the configuration of the semiconductor device of the second embodiment described above.

[0051] First, an n-type SiC substrate 1 is prepared. Then, as shown in FIG. 6 , a p-type semiconductor layer 2, an n-type semiconductor layer 3, and a p-type semiconductor layer 4 are formed on the SiC substrate 1. The p-type semiconductor layer 2, the n-type semiconductor layer 3, and the p-type semiconductor layer 4 are formed, for example, by epitaxial growth of SiC, which maintains the crystallinity of the SiC substrate 1. During the epitaxial growth, p-type or n-type impurities are introduced to form a p-type or n-type epitaxially grown layer. The impurity concentrations of the p-type semiconductor layer 2, the n-type semiconductor layer 3, and the p-type semiconductor layer 4 are not particularly limited, as long as they have the performance required for a lateral BJT. Furthermore, the thicknesses of the p-type semiconductor layer 2, the n-type semiconductor layer 3, and the p-type semiconductor layer 4 are not particularly limited, but as shown in FIG. 6, it is preferable that the outermost semiconductor layer 4 is the thinnest and the outermost semiconductor layer 3 is the thickest.

[0052] 7, a resist layer 30 is patterned on the semiconductor layer 4, excluding the regions where the first collector layer 6 and the buffer layer 18 are to be formed, and ions of impurities such as phosphorus (P) and arsenic (As) are implanted. The resist layer 30 can be patterned using conventional photolithography or the like. The ion implantation is performed to a depth that reaches from the surface of the semiconductor layer 4 to the n-type semiconductor layer 3. As a result, an n-type first collector layer 6 and a buffer layer 18 are formed.

[0053] 1 and 2, a resist layer 30 is also formed in the region where the buffer layer 18 is to be formed, and ion implantation is performed, as shown in Fig. 8. This allows only the n-type first collector layer 6 to be formed.

[0054] Next, after removing the resist layer 30, as shown in FIG. + A hard mask 31 is patterned and formed on the semiconductor layer 4, except for the region where the mold base layer 7 is to be formed, and ions of impurities such as boron (B) are implanted. The patterning of the hard mask 31 can be performed by forming an SiO2 layer using a conventionally known method, such as a CVD (Chemical Vapor Deposition) method, and then etching the SiO2 layer using a resist layer patterned using photolithography or the like as a mask. The ion implantation is performed from the surface of the semiconductor layer 4 to a depth reaching the n-type semiconductor layer 3. + A base layer 7 of the mold is formed.

[0055] Next, after removing the hard mask 31, as shown in FIG. 10, a resist layer 32 is patterned on the substrate 20 except for the regions where the emitter layer 5 and the second collector layer 8 are to be formed, and ions of impurities such as phosphorus (P) and arsenic (As) are implanted. The ion implantation is performed only inside the semiconductor layer 4. As a result, n + type emitter layer 5 and n + A second collector layer 8 of the same type is formed. Then, a heat treatment at about 1700° C. is performed to remove the activation anneal p formed on the surface of the substrate 20. + Mold base layer 7, n + n-type emitter layer 5, n-type first collector layer 6, n + The second collector layer 8 and the buffer layer 18 are subjected to activation annealing.

[0056] 11, trenches 21 are formed in the element isolation region 102 (FIG. 1) from the surface of the base 20, and insulating layers 14, 14a are formed on the surface of the base 20 and in the trenches 21. Furthermore, NO annealing is performed to form nitrogen passivation regions 16, 16a on the inner surface of the trenches 21 and in the insulating layer 14. The trench 21 is formed, for example, by forming a mask of a resist layer or the like in areas other than the area where the trench 21 is to be formed, and using reactive ion etching (RIE) or the like, which is capable of deep etching into the SiC substrate 20. The trench 21 is formed to a depth that reaches the p-type semiconductor layer 2 from the surface of the semiconductor layer 4. In forming the insulating layer 14, for example, the substrate 20 is heated in an oxygen atmosphere to form a thermal oxide film. The nitrogen passivation regions 16, 16a are formed, for example, by forming the insulating layer 14 and then performing NO annealing, which is a heat treatment at about 1200 to 1400°C in a nitrogen-based atmosphere. The nitrogen-based atmosphere may be NO, NO, N (mixed gas containing O), or the like. This forms the nitrogen passivation regions 16 in the trenches 21 of the base 20 and in the insulating layer 14. At the same time, the nitrogen passivation regions 16a are formed on the upper surface of the base 20 and in the insulating layer 14a.

[0057] 1, the insulating layer 14 is removed from the upper surface of the substrate 20 except for the inside of the trench 21, as shown in FIG. 12. For example, a resist layer is patterned on the trench 21, and the thermal oxide film is etched using this resist layer as a mask, thereby removing the insulating layer on the upper surface of the substrate 20. Then, a resist layer is patterned in the area excluding the area above the trench 21, and the above-mentioned NO annealing process is performed. This allows the nitrogen passivation region 16 to be formed only on the inner surface of the trench 21 and in the insulating layer 14.

[0058] 13, a conductive layer 15 is formed on the entire surface of the base 20. The conductive layer 15 is formed to a thickness that allows it to fill the trenches 21. The conductive layer 15 is formed by depositing polysilicon or a metal such as Cu or W on the base 20 using, for example, a CVD method or the like.

[0059] Next, as shown in Fig. 14, the conductive layer 15 is removed from areas other than within the trenches 21. The conductive layer 15 is removed by, for example, chemical mechanical polishing (CMP) or wet etching using a chemical solution, which processes the entire conductive layer 15 on the base 20. Furthermore, as shown in Fig. 14, a resist layer 33 is patterned on the trenches 21, and then dry etching such as wet etching or plasma etching is performed on the conductive layer 15 on the upper surface of the base 20. This completely removes the conductive layer 15 on the base 20 within the transistor region 101, excluding the element isolation region 102.

[0060] 15, a protective film 9 is formed on the entire surface of the base 20. The protective film 9 is formed by forming an insulating layer such as SiO2 in both the transistor region 101 and the element isolation region 102 of the base 20 using, for example, a CVD method.

[0061] Next, as shown in FIG. 16, the protective film 9 is removed from the regions where the emitter electrode 10, collector electrode 11, and base electrode 12 (FIG. 1) are to be formed. This forms openings 34 in the protective film 9 for forming the electrodes. Furthermore, the emitter layer 5, base layer 7, and second collector layer 8 of the substrate 20 exposed through the openings 34 are silicided. For silicidation, a metal layer made of, for example, Ti, W, or Ta is formed and heated. As a result, metal silicide is formed on the surfaces of the emitter layer 5, base layer 7, and second collector layer 8. Furthermore, by removing the formed metal layer, the silicided emitter layer 5, base layer 7, and second collector layer 8 are exposed through the openings 34 in the protective film 9, as shown in FIG. 16.

[0062] 17, a metal layer 35 for forming electrodes is formed on the entire surface of the base 20. The metal layer 35 is formed by using, for example, a CVD method, etc., using a metal such as Cu, W, or Ti to a thickness greater than or equal to that required to form the emitter electrode 10, the collector electrode 11, and the base electrode 12 (FIG. 1).

[0063] 18, the metal layer 35 is etched into the shapes of the emitter electrode 10, the collector electrode 11, and the base electrode 12. The metal layer 35 is etched by dry etching such as RIE using a patterned resist layer as a mask, for example. Furthermore, the protective film 9 on the trench 21 is removed. Then, the sealing member 19 is formed on the entire surface of the base body 20 to seal the semiconductor device. After the sealing member 19 is formed, the back electrode 13 is formed on the back surface side of the SiC substrate 1. The back electrode is formed by forming a metal layer of Cu, W, Ti, or the like using, for example, a CVD method. Through the above steps, the semiconductor device of this embodiment can be manufactured.

[0064] When forming a plurality of isolations 22 in the isolation region 102 as in the semiconductor device 500 of the fifth embodiment shown in Fig. 5 described above, a plurality of trenches 21 are formed in parallel in the isolation region 102 as shown in Fig. 19. Then, insulating layers 14, 14a are formed on the upper surface of the base 20 and on the inner surfaces of the trenches 21. The trenches 21 and insulating layers 14, 14a are formed by the method shown in Fig. 11 described above. The other steps are the same as those in the manufacturing method of the above embodiment.

[0065] 7. Electronic Device Embodiments Next, an embodiment of an electronic device will be described. The electronic device of this embodiment is equipped with a semiconductor device according to any one of the above-described embodiments 1 to 5. Below, as an example of an electronic device, a pressure transmitter equipped with a semiconductor device according to any one of the above-described embodiments will be described. Note that the electronic device is not limited to a pressure transmitter and may have other configurations as long as it is equipped with a semiconductor device according to any one of the above-described embodiments.

[0066] An overview of the pressure transmitter is shown in Fig. 20. The pressure transmitter 600 shown in Fig. 20 is connected to a tank 610 and functions as a so-called water level gauge that measures a water level 612 of water 611 stored in the tank 610. The pressure transmitter 600 is connected to a pressure diaphragm 613 connected to a flange 615 via a cable 614 filled with a medium such as oil. The flange 615 is attached to the top and bottom of the tank 610, penetrating the exterior of the tank 610.

[0067] 21 shows a schematic configuration of a pressure transmitter 600. The pressure transmitter 600 has a housing 604, a semiconductor sensor 603 built into the housing 604, and a printed circuit board 601. The printed circuit board 601 has an electronic circuit on which a plurality of electronic components 602 are mounted. The electronic component 602 is composed of a substrate, a plurality of semiconductor elements, wiring, etc. The electronic component 602 has a semiconductor device according to each of the above-described embodiments as a built-in transistor. The pressure transmitter 600 acquires the strain of a pressure diaphragm 613 connected to a tank 610 via a cable 614. The strain of the pressure diaphragm 613 fluctuates depending on the water level 612 in the tank 610. Therefore, the pressure transmitter 600 measures the pressure from the strain of the pressure diaphragm 613 using a semiconductor sensor 603. Furthermore, the pressure transmitter 600 converts the pressure measured by the semiconductor sensor 603 into a digital signal using a circuit formed on a printed circuit board 601 and outputs the digital signal.

[0068] The semiconductor device according to each of the above-described embodiments has a trench formed in the substrate of the semiconductor layer and a nitrogen passivation region on the surface of the substrate. The nitrogen passivation region terminates the interface defects in the trench and the surface, suppressing the surface recombination current and increasing the current amplification factor h FE Therefore, it is possible to suppress the performance degradation due to the reduction in the current amplification factor in the semiconductor device and the electronic device. In particular, the semiconductor device according to each embodiment and electronic equipment equipped with this semiconductor device are effective for use under the influence of radiation such as gamma rays. The influence of radiation easily activates interface defects in the trenches and surfaces of the semiconductor device. Therefore, under the influence of radiation, many minority carriers are trapped at the interface, which tends to increase the surface recombination current, and the current amplification factor h of the transistor FE In other words, by applying the semiconductor device of the above-described embodiment to semiconductor devices and electronic devices used under the influence of radiation, the nitrogen passivation region can suppress an increase in surface recombination current due to activation of interface defects caused by radiation. Therefore, it is possible to configure semiconductor devices and electronic devices that can suppress a decrease in current gain and suppress performance degradation due to a decrease in current gain even under the influence of radiation.

[0069] It should be noted that the present invention is not limited to the above-described embodiments and various modifications are possible. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to an embodiment including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment. It is also possible to add the configuration of another embodiment to the configuration of one embodiment. It is also possible to delete part of the configuration of each embodiment, or to add or replace other configurations. [Explanation of symbols]

[0070] 1 SiC substrate, 2, 3, 4 semiconductor layer, 5 emitter layer, 6 first collector layer, 7 base layer, 8 second collector layer, 9 protective film, 10 emitter electrode, 11 collector electrode, 12 base electrode, 13 back electrode, 14, 14a insulating layer, 15 conductor layer, 16, 16a nitrogen passivation region, 17 wiring, 18 buffer layer, 19 sealing member, 20 base, 21 trench, 22 element isolation, 30, 32, 33 resist layer, 31 hard mask, 34 opening, 35 metal layer, 100, 200, 300, 400, 500 semiconductor device, 101 transistor region, 102 element isolation region, 600 pressure transmitter, 601 printed circuit board, 602 electronic component, 603 semiconductor sensor, 604 housing, 610 tank, 611 Water, 612 Water level, 613 Pressure diaphragm, 614 Cable, 615 Flange

Claims

1. a substrate made of SiC; a bipolar junction transistor having an emitter electrode, a collector electrode, and a base electrode formed on a main surface side of the substrate; an isolation region surrounding the bipolar junction transistor; The element isolation region includes a trench and an insulating layer formed on the inner surface of the trench; a nitrogen passivation region into which nitrogen is introduced, formed on the interface side of the substrate exposed to the trench; Semiconductor device.

2. The nitrogen passivation region has nitrogen introduced into the insulating layer formed in the trench. The semiconductor device according to claim 1 .

3. The nitrogen passivation region is provided on the main surface of the substrate in a region where the bipolar junction transistor is formed, together with the element isolation region. The semiconductor device according to claim 1 .

4. The main surface of the substrate on which the nitrogen passivation region is formed is covered with an insulating layer having a nitrogen passivation region into which nitrogen is introduced. The semiconductor device according to claim 3 .

5. The nitrogen passivation region on the main surface of the substrate is formed in a region excluding a contact surface between the emitter electrode and the substrate, a contact surface between the collector electrode and the substrate, and a contact surface between the base electrode and the substrate. The semiconductor device according to claim 3 .

6. The nitrogen passivation region has a nitrogen concentration of 10 １３ cm －２ That's all The semiconductor device according to claim 1 .

7. a conductive layer filling the trench whose inner surface is covered with the insulating layer; The semiconductor device according to claim 1 .

8. The conductive layer is at the same potential as the base electrode. The semiconductor device according to claim 7 .

9. a buffer layer of a conductivity type opposite to that of a base layer to which the base electrode is provided, at least partially between the sidewall of the trench and the bipolar junction transistor; The semiconductor device according to claim 1 .

10. The element isolation region has a plurality of trenches surrounding the bipolar junction transistor. The semiconductor device according to claim 1 .

11. forming a bipolar junction transistor having an emitter electrode, a collector electrode, and a base electrode on the main surface side of a substrate; forming a trench surrounding the bipolar junction transistor from the main surface side of the substrate; forming an insulating layer covering the inner surface of the trench; and introducing nitrogen into the interface side of the substrate exposed to the inner surface of the trench. A method for manufacturing a semiconductor device.

12. a semiconductor device and an electronic circuit on which the semiconductor device is mounted, The semiconductor device includes: a substrate made of SiC; a bipolar junction transistor having an emitter electrode, a collector electrode, and a base electrode formed on a main surface of the substrate; an isolation region surrounding the bipolar junction transistor; The element isolation region includes a trench and an insulating layer formed on the inner surface of the trench; a nitrogen passivation region into which nitrogen is introduced, the nitrogen passivation region being formed on the interface side of the substrate exposed to the trench. electronic equipment.

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