Semiconductor device

Abstract

To provide a semiconductor device that can reduce noise.SOLUTION: A semiconductor device 1 of an embodiment comprises: a first switching element 13 provided with a first electrode DE1 and a second electrode SE1; a second switching element 14 provided with a third electrode SE2 and a fourth electrode DE2; a first capacitor 15 including a first wiring layer 25 connected to the third electrode, a second wiring layer 26 connected to the first electrode, and a first dielectric layer 51; a substrate 20; a third wiring layer 22 connected to the first wiring layer and applied with a first voltage VDC-; a fourth wiring layer 21 connected to the second wiring layer and applied with a second voltage VDC+; and a fifth wiring layer 23 connected to the second and fourth electrodes and applied with a third voltage VSW. The first capacitor is arranged between the first and second switching elements. The third electrode is arranged facing the first electrode. The fourth electrode is arranged facing the second electrode and connected in series to the second electrode.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices that convert and control power are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-343021 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-032507 [Patent Document 3] Patent No. 5447453 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of reducing noise is provided. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first switching element having a first electrode and a second electrode on its surface, a second switching element having a third electrode and a fourth electrode on its surface, a first capacitor including a first wiring layer connected to the third electrode, a second wiring layer connected to the first electrode, and a first dielectric layer disposed between the first and second wiring layers, a substrate incorporating the first switching element, the second switching element, and the first capacitor, a third wiring layer connected to the first wiring layer and to which a first voltage is applied, a fourth wiring layer connected to the second wiring layer and to which a second voltage higher than the first voltage is applied, and a fifth wiring layer connected to the second and fourth electrodes and to which a third voltage in the range from the first voltage to the second voltage is applied. The first capacitor is disposed between the first switching element and the second switching element. The third electrode is disposed opposite the first electrode in a first direction. The fourth electrode is disposed opposite the second electrode in the first direction and is connected in series to the second electrode. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a circuit diagram showing an example of a circuit configuration of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an application example of the semiconductor device according to the first embodiment. [Figure 3] FIG. 2 is a circuit diagram showing an example of the configuration of each switching element in the semiconductor device according to the first embodiment. [Figure 4] FIG. 1 is a perspective view showing an example of the structure of a semiconductor device according to a first embodiment. [Figure 5] 1 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to a first embodiment. [Figure 6] FIG. 3 is a cross-sectional view showing another example of the cross-sectional structure of the semiconductor device according to the first embodiment. [Figure 7] 7 is a plan view taken along line aa in FIGS. 5 and 6, showing an example of the planar structure of the semiconductor device according to the first embodiment. FIG. [Figure 8] 7 is a plan view taken along the line bb in FIGS. 5 and 6, showing an example of the planar structure of the semiconductor device according to the first embodiment. FIG. [Figure 9]7 is a plan view taken along line cc in FIGS. 5 and 6, showing an example of the planar structure of the semiconductor device according to the first embodiment. FIG. [Figure 10] 7 is a plan view taken along line dd in FIGS. 5 and 6, showing an example of the planar structure of the semiconductor device according to the first embodiment. FIG. [Figure 11] FIG. 2 is a diagram showing a high-frequency current path in the semiconductor device according to the first embodiment. [Figure 12] FIG. 10 is a circuit diagram showing an example of a circuit configuration of a semiconductor device according to a second embodiment. [Figure 13] FIG. 10 is a circuit diagram showing an example of the configuration of each switching element in the semiconductor device according to the second embodiment. [Figure 14] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to a second embodiment. [Figure 15] FIG. 10 is a cross-sectional view showing another example of the cross-sectional structure of the semiconductor device according to the second embodiment. [Figure 16] 16 is a plan view taken along line aa in FIGS. 14 and 15, showing an example of the planar structure of the semiconductor device according to the second embodiment. FIG. [Figure 17] 16 is a plan view taken along the line bb in FIGS. 14 and 15, showing an example of the planar structure of the semiconductor device according to the second embodiment. FIG. [Figure 18] 16 is a plan view taken along line cc in FIGS. 14 and 15, showing an example of the planar structure of the semiconductor device according to the second embodiment. FIG. [Figure 19] 16 is a plan view taken along line dd in FIGS. 14 and 15, showing an example of the planar structure of the semiconductor device according to the second embodiment. FIG. [Figure 20] 10 is a diagram showing a high-frequency current path in a semiconductor device according to a second embodiment and magnetic flux generated by the high-frequency current. [Figure 21] FIG. 10 is a circuit diagram showing an example of a circuit configuration of a semiconductor device according to a third embodiment. [Figure 22] FIG. 10 is a circuit diagram showing an example of the configuration of each switching element in the semiconductor device according to the third embodiment. [Figure 23] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to a third embodiment. [Figure 24]FIG. 10 is a cross-sectional view showing another example of the cross-sectional structure of the semiconductor device according to the third embodiment. [Figure 25] FIG. 10 is a diagram showing a high-frequency current path in the semiconductor device according to the third embodiment. [Figure 26] FIG. 10 is a circuit diagram showing an example of a circuit configuration of a semiconductor device according to a fourth embodiment. [Figure 27] FIG. 10 is a circuit diagram showing an example of the configuration of each switching element in the semiconductor device according to the fourth embodiment. [Figure 28] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to a fourth embodiment. [Figure 29] FIG. 10 is a cross-sectional view showing another example of the cross-sectional structure of the semiconductor device according to the fourth embodiment. [Figure 30] FIG. 10 is a diagram showing a high-frequency current path in a semiconductor device according to a fourth embodiment and magnetic flux generated by the high-frequency current. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. The dimensions and ratios of the drawings are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are given the same reference numerals, and repeated description may be omitted. When elements having similar configurations are particularly distinguished from one another, different letters or numbers may be added to the end of the same reference numerals. Furthermore, all descriptions of one embodiment also apply to descriptions of other embodiments, unless explicitly or obviously excluded.

[0008] 1. First embodiment A semiconductor device according to a first embodiment will be described. In the following, a semiconductor device that converts and controls power by alternately driving two switching elements will be described as an example. The semiconductor device according to this embodiment is applied to, for example, an AC-DC converter, a DC-AC inverter, and a DC-DC converter.

[0009] 1.1 Circuit configuration of semiconductor device The circuit configuration of the semiconductor device will be described with reference to Fig. 1. Fig. 1 is a circuit diagram showing an example of the circuit configuration of the semiconductor device.

[0010] The semiconductor device 1 is, for example, a power supply module, and includes control terminals T1 and T2, driver circuits 11 and 12, input / output terminals T3, T4, and T5, switching elements 13 and 14, and a capacitor 15.

[0011] The control terminal T1 is a terminal to which a control signal IH1 is input from the outside. The control signal IH1 is a signal for controlling the operation of the driver circuit 11. The control signal IH1 is, for example, a high (“H”) level signal or a low (“L”) level signal.

[0012] The control terminal T2 is a terminal to which a control signal IL1 is input from the outside. The control signal IL1 is a signal for controlling the operation of the driver circuit 12. The control signal IL1 is, for example, an "H" level signal or an "L" level signal.

[0013] The driver circuit 11 is a circuit that drives the switching element 13. The driver circuit 11 is connected to the control terminal T1 and the switching element 13. The driver circuit 11 turns the switching element 13 on or off based on a control signal IH1.

[0014] The driver circuit 11 turns on the switching element 13 in response to an ON request signal to the switching element 13 by the control signal IH1. The driver circuit 11 also turns off the switching element 13 in response to an OFF request signal to the switching element 13 by the control signal IH1.

[0015] The driver circuit 12 is a circuit that drives the switching element 14. The driver circuit 12 is connected to the control terminal T2 and the switching element 14. The driver circuit 12 turns the switching element 14 on or off based on a control signal IL1.

[0016] The driver circuit 12 turns on the switching element 14 in response to an ON request signal to the switching element 14 by the control signal IL1. The driver circuit 12 also turns off the switching element 14 in response to an OFF request signal to the switching element 14 by the control signal IL1.

[0017] The control signals IH1 and IL1 are controlled so that the switching elements 13 and 14 are alternately turned on or off. As a result, the driver circuits 11 and 12 alternately turn on or off the switching elements 13 and 14. In other words, when one of the switching elements 13 and 14 is in the on state, the other is in the off state.

[0018] The input / output terminals T3 to T5 are input terminals or output terminals. The input / output terminal T3 is connected to the node N1. The input / output terminal T4 is connected to the node N2. The input / output terminal T5 is connected to the node N3. The voltage VDC- is a DC voltage applied to the node N3, i.e., the input / output terminal T5. The voltage VDC- is, for example, a ground voltage GND. The voltage VDC+ is a DC voltage applied to the node N2, i.e., the input / output terminal T4. The voltage VDC+ is a voltage higher than the voltage VDC-. The voltage VSW is a voltage applied to the node N1, i.e., the input / output terminal T3. The voltage VSW is switched between the voltage VDC- and the voltage VDC+. The voltage VSW may exceed the voltage VDC+ due to a surge generated due to the parasitic inductance of the wiring when the switching elements 13 and 14 are switched. In a steady state, the voltage VSW is a voltage in the range of not less than the voltage VDC- and not more than the voltage VDC+.

[0019] The switching element 13 has a first terminal, a second terminal, and a third terminal. The first terminal of the switching element 13 is connected to the driver circuit 11. The second terminal of the switching element 13 is connected to a node N2. The third terminal of the switching element 13 is connected to a node N1. The switching element 14 has a first terminal, a second terminal, and a third terminal. The first terminal of the switching element 14 is connected to the driver circuit 12. The second terminal of the switching element 14 is connected to the node N1. The third terminal of the switching element 14 is connected to a node N3. The switching elements 13 and 14 include, for example, at least one of an n-channel metal oxide semiconductor field effect transistor (MOSFET), a p-channel MOSFET, a gallium nitride (GaN) transistor, a silicon carbide (SiC) transistor, an insulated gate bipolar transistor (IGBT), and a junction field effect transistor (JFET). The switching elements 13 and 14 are normally-off switching elements.

[0020] One electrode of capacitor 15 is connected to node N2. The other electrode of capacitor 15 is connected to node N3. In other words, capacitor 15 is connected to both ends of the series-connected switching elements 13 and 14. This allows capacitor 15 to function as a snubber capacitor for reducing surges that may occur due to parasitic inductance in the wiring when switching elements 13 and 14 are switched on or off.

[0021] The input / output terminals T3 to T5 function as input terminals or output terminals depending on the configuration of a circuit (not shown) connected to the input / output terminals T3 to T5.

[0022] For example, when a synchronous rectification boost converter is configured by the semiconductor device 1 and circuits connected to the input / output terminals T3 to T5, the input / output terminal T3 is an input terminal, and the input / output terminals T4 and T5 are output terminals.

[0023] Fig. 2 is a circuit diagram showing an application example (synchronous rectification boost converter) of the semiconductor device 1. As shown in Fig. 2, the synchronous rectification boost converter includes the semiconductor device 1, terminals Tin and Tout, a coil L1, and capacitors C1 and C2.

[0024] The terminal Tin is connected to the node N61, and the input voltage Vin is applied to the terminal Tin.

[0025] The terminal Tout is connected to the node N62, and outputs the output voltage Vout.

[0026] One end of the coil L1 is connected to the node N61, and the other end of the coil L1 is connected to the input / output terminal T3.

[0027] One electrode of the capacitor C1 is connected to the node N61, and the other electrode of the capacitor C1 is grounded.

[0028] The input / output terminal T4 is connected to a node N62.

[0029] One electrode of the capacitor C2 is connected to the node N62, and the other electrode of the capacitor C2 is grounded.

[0030] The input / output terminal T5 is grounded.

[0031] When switching element 13 is turned off and switching element 14 is turned on, input / output terminal T3 is grounded via switching element 14, and current flows from terminal Tin to coil L1, input / output terminal T3, switching element 14, and input / output terminal T5. At this time, magnetic energy is stored in coil L1.

[0032] Thereafter, when switching element 13 is turned on and switching element 14 is turned off, coil L1 releases magnetic energy, causing current to flow from input / output terminal T3 to input / output terminal T4 via switching element 13. This causes charge to accumulate in capacitor C2, increasing the voltage at node N62. The increased voltage is output from terminal Tout as voltage Vout.

[0033] Furthermore, for example, when a half-bridge converter, a full-bridge converter, a half-bridge LLC converter, a phase-shift full-bridge converter, or the like is configured by the semiconductor device 1 and circuits connected to the input / output terminals T3 to T5, the input / output terminal T3 is an output terminal, and the input / output terminals T4 and T5 are input terminals. When a DC-AC inverter is configured by the semiconductor device 1 and circuits connected to the input / output terminals T3 to T5, the input / output terminal T3 is an output terminal, and the input / output terminals T4 and T5 are input terminals.

[0034] In the following, as an example, a case where the switching elements 13 and 14 are n-channel MOSFETs will be described.

[0035] FIG. 3 is a circuit diagram showing an example of the configuration of each switching element in the semiconductor device 1. As shown in FIG.

[0036] 3, the switching element 13 is a transistor TR1. The switching element 14 is a transistor TR2. The transistors TR1 and TR2 are n-channel MOSFETs. The transistors TR1 and TR2 are normally-off transistors.

[0037] A gate electrode (control electrode) of switching element 13 is connected to driver circuit 11. A drain electrode of switching element 13 is connected to node N2. A source electrode of switching element 13 is connected to node N1. A gate electrode (control electrode) of switching element 14 is connected to driver circuit 12. A drain electrode of switching element 14 is connected to node N1. A source electrode of switching element 14 is connected to node N3. A source electrode of switching element 13 and a drain electrode of switching element 14 are connected in series.

[0038] 1.2 Structure of semiconductor device The structure of the semiconductor device 1 will be described.

[0039] Fig. 4 is a perspective view showing an example of the structure of the semiconductor device 1. As shown in Fig. 4, the semiconductor device 1 includes a substrate 20 incorporating driver circuits 11 and 12, switching elements 13 and 14, and a capacitor 15. In other words, the substrate 20 is a component-embedded substrate. The substrate 20 is, for example, a glass epoxy substrate. Note that control terminals T1 and T2 are not shown in Fig. 4.

[0040] Hereinafter, a plane parallel to the surface of the substrate 20 is referred to as the XY plane. Directions that intersect perpendicularly with each other in the XY plane are referred to as the X direction and the Y direction. A direction that intersects with the XY plane is referred to as the Z direction. Within the Z direction, the direction from the substrate 20 toward the wiring layer 30, which will be described later, is also referred to as the upward direction, and the direction from the substrate 20 toward the wiring layers 21, 22, and 23, which will be described later, is also referred to as the downward direction. Additionally, the upper surface of the substrate 20 is also referred to as the "surface of the substrate 20," and the lower surface of the substrate 20 is also referred to as the "rear surface of the substrate 20."

[0041] Wiring layers 21 to 23 are provided on the back surface of substrate 20. Wiring layers 21 to 23 are arranged spaced apart from one another in the X direction. Wiring layer 21 corresponds to input / output terminal T4. A voltage VDC+ is applied to wiring layer 21. Wiring layer 22 corresponds to input / output terminal T5. A voltage VDC- is applied to wiring layer 22. Wiring layer 23 corresponds to input / output terminal T3. A voltage VSW is applied to wiring layer 23. Hereinafter, the surface of wiring layer 22 that contacts substrate 20 will also be referred to as the "surface of wiring layer 22," and the surface of wiring layer 23 that contacts substrate 20 will also be referred to as the "surface of wiring layer 23."

[0042] The switching element 14 is provided above the wiring layer 22. The switching element 14 and the wiring layer 22 are connected to each other through a plurality of vias 41.

[0043] Wiring layers 24, 25, and 28 are provided above the switching element 14. The wiring layers 24 and 25 are arranged spaced apart from each other in the Y direction. The wiring layers 25 and 28 are arranged spaced apart from each other in the X direction. The wiring layer 24 and the switching element 14 are connected via a via 41. The wiring layer 25 and the switching element 14 are connected via a plurality of vias 41. The wiring layer 28 and the switching element 14 are connected via a plurality of vias 41.

[0044] The driver circuit 12 is provided below the wiring layer 24. The driver circuit 12 and the switching elements 14 are arranged spaced apart from each other in the X direction. The driver circuit 12 and the wiring layer 24 are connected through vias 41. The driver circuit 12 does not have to be built into the substrate 20.

[0045] A dielectric layer 51 is provided on the wiring layer 25. A wiring layer 26 is provided on the dielectric layer 51. The wiring layer 25, the dielectric layer 51, and the wiring layer 26 form a capacitor 15. The capacitor 15 is disposed between the switching element 13 and the switching element 14.

[0046] A wiring layer 29 is provided above the wiring layer 28. The wiring layers 29 and 26 are spaced apart from each other in the X direction. The wiring layer 29 and the wiring layer 28 are connected to each other through a plurality of vias 41.

[0047] The switching element 13 is provided above the wiring layers 26 and 29. The switching element 13 and the wiring layer 26 are connected to each other through a plurality of vias 41. The switching element 13 and the wiring layer 29 are connected to each other through a plurality of vias 41.

[0048] A wiring layer 27 is provided below the switching element 13. The wiring layer 27 and the switching element 13 are connected through a via 41.

[0049] The driver circuit 11 is provided above the wiring layer 27. The driver circuit 11 and the switching elements 13 are arranged spaced apart from each other in the X direction. The driver circuit 11 and the wiring layer 27 are connected through vias 41. The driver circuit 11 does not have to be built into the substrate 20.

[0050] A wiring layer 30 is provided on the surface of the substrate 20. The wiring layer 30 and the wiring layer 21 are connected to each other through a plurality of vias 41. The wiring layer 30 and the wiring layer 26 are connected to each other through a plurality of vias 41. The wiring layer 30 and the switching element 13 are connected to each other through a plurality of vias 41.

[0051] The wiring layers 21 to 30 are made of a conductive material. The wiring layers 21 to 30 include, for example, copper (copper foil). The via 41 is made of a conductive material. The via 41 includes, for example, copper (copper plating). The dielectric layer 51 includes, for example, silicon or barium titanate. The dielectric layer 51 may include, for example, a nitride.

[0052] FIG. 5 is a cross-sectional view taken along line II in FIG. 4, showing an example of the cross-sectional structure of the semiconductor device 1. As shown in FIG.

[0053] 5, the switching element 13 has a surface S1 and a surface S2 opposite to the surface S1. Hereinafter, the surface S1 will also be referred to as the "surface of the switching element 13," and the surface S2 will also be referred to as the "rear surface of the switching element 13." A drain electrode DE1 and a source electrode SE1 are provided on the surface of the switching element 13. A plurality of vias 41 are provided between the switching element 13 and the wiring layer 30.

[0054] The switching element 14 has a surface S3 and a surface S4 opposite to surface S3. Hereinafter, surface S3 will also be referred to as the "front surface of the switching element 14," and surface S4 will also be referred to as the "rear surface of the switching element 14." A source electrode SE2 and a drain electrode DE2 are provided on the front surface of the switching element 14. A plurality of vias 41 are provided between the switching element 14 and the wiring layer 22.

[0055] The wiring layer 25 is provided above the switching element 14. A plurality of vias 41 are provided between the end of the lower surface of the wiring layer 25 on the switching element 14 side and the source electrode SE2 of the switching element 14. In other words, the end of the lower surface of the wiring layer 25 on the switching element 14 side is in contact with the plurality of vias 41. The source electrode SE2 of the switching element 14 is in contact with the plurality of vias 41. That is, the wiring layer 25 is connected to the source electrode SE2 of the switching element 14 through the plurality of vias 41. A plurality of vias 41 are provided between the wiring layer 25 and the wiring layer 22. The wiring layer 25 functions as a wiring that supplies the voltage VDC-. The wiring layer 25 also functions as the other electrode of the capacitor 15. Hereinafter, the lower surface of the wiring layer 25 will also be referred to as the "surface of the wiring layer 25."

[0056] The dielectric layer 51 is provided on the wiring layer 25 .

[0057] The wiring layer 26 is provided on the dielectric layer 51 and below the switching element 13. A plurality of vias 41 are provided between the end of the upper surface of the wiring layer 26 facing the switching element 13 and the drain electrode DE1 of the switching element 13. In other words, the end of the upper surface of the wiring layer 26 facing the switching element 13 is in contact with the plurality of vias 41. The drain electrode DE1 of the switching element 13 is in contact with the plurality of vias 41. That is, the wiring layer 26 is connected to the drain electrode DE1 of the switching element 13 through the plurality of vias 41. A plurality of vias 41 are provided between the wiring layer 26 and the wiring layer 30. The wiring layer 26 functions as a wiring that supplies the voltage VDC+. The wiring layer 26 also functions as one electrode of the capacitor 15. Hereinafter, the upper surface of the wiring layer 26 will also be referred to as the "surface of the wiring layer 26."

[0058] The wiring layer 28 is provided above the switching element 14. The wiring layer 28 is provided in the same layer as the wiring layer 25. A plurality of vias 41 are provided between the end of the lower surface of the wiring layer 28 on the switching element 14 side and the drain electrode DE2 of the switching element 14. In other words, the end of the lower surface of the wiring layer 28 on the switching element 14 side is in contact with the plurality of vias 41. The drain electrode DE2 of the switching element 14 is in contact with the plurality of vias 41. A plurality of vias 41 are provided between the wiring layer 28 and the wiring layer 23. The wiring layer 28 functions as a wiring that supplies the voltage VSW.

[0059] The wiring layer 29 is provided above the wiring layer 28 and below the switching element 13. The wiring layer 29 is provided in the same layer as the wiring layer 26. A plurality of vias 41 are provided between the wiring layer 29 and the wiring layer 28. A plurality of vias 41 are provided between the end of the upper surface of the wiring layer 29 on the switching element 13 side and the source electrode SE1 of the switching element 13. In other words, the end of the upper surface of the wiring layer 29 on the switching element 13 side is in contact with the plurality of vias 41. The source electrode SE1 of the switching element 13 is in contact with the plurality of vias 41. The wiring layer 29 functions as a wiring that supplies the voltage VSW.

[0060] A plurality of vias 41 are provided between the wiring layer 21 and the wiring layer 30. The wiring layer 30 functions as a wiring that supplies the voltage VDC+.

[0061] The wiring layer 21 is connected to the wiring layer 26 via a plurality of vias 41, the wiring layer 30, and a plurality of vias 41. The wiring layer 22 is connected to the wiring layer 25 via a plurality of vias 41. The wiring layer 23 is connected to the source electrode SE1 of the switching element 13 via a plurality of vias 41, the wiring layer 28, a plurality of vias 41, the wiring layer 29, and a plurality of vias 41. The wiring layer 23 is also connected to the drain electrode DE2 of the switching element 14 via a plurality of vias 41, the wiring layer 28, and a plurality of vias 41.

[0062] FIG. 6 is a cross-sectional view taken along line II-II in FIG. 4, showing an example of the cross-sectional structure of the semiconductor device 1. As shown in FIG.

[0063] 6, a gate electrode GE1 is provided on the surface of the switching element 13. A gate electrode GE2 is provided on the surface of the switching element .

[0064] The wiring layer 24 is provided above the switching element 14. A via 41 is provided between an end of the lower surface of the wiring layer 24 on the switching element 14 side and the gate electrode GE2 of the switching element 14. A via 41 is provided between an end of the lower surface of the wiring layer 24 opposite the switching element 14 and the driver circuit 12.

[0065] The wiring layer 27 is provided below the switching element 13. A via 41 is provided between the end of the upper surface of the wiring layer 27 on the switching element 13 side and the gate electrode GE1 of the switching element 13. A via 41 is provided between the end of the upper surface of the wiring layer 27 opposite to the switching element 13 and the driver circuit 11.

[0066] FIG. 7 is a plan view showing an example of the planar structure of the semiconductor device 1, viewed downward from the position of line aa in FIGS.

[0067] 7, a plurality of vias 41 are provided on the wiring layer 21. The wiring layer 21 functions as an external connection terminal for the voltage VDC+.

[0068] A plurality of vias 41 are provided on the wiring layer 22. The wiring layer 22 functions as an external connection terminal for the voltage VDC-. The switching element 14 is provided above the wiring layer 22. Note that FIG. 7 shows the back surface of the switching element 14. The plurality of vias 41 provided between the wiring layer 22 and the switching element 14 are provided to release heat from the switching element 14. In other words, the wiring layer 22 also functions as a heat release surface for the switching element 14.

[0069] A plurality of vias 41 are provided on the wiring layer 23. The wiring layer 23 functions as an external connection terminal for the voltage VSW.

[0070] FIG. 8 is a plan view showing an example of the planar structure of the semiconductor device 1, viewed downward from the position of line bb in FIGS.

[0071] As shown in Fig. 8, the switching element 14 is provided above the wiring layer 22. Fig. 8 also shows the surface of the switching element 14. A drain electrode DE2, a source electrode SE2, and two gate electrodes GE2 are provided on the surface of the switching element 14.

[0072] The drain electrode DE2 is provided at an end of the surface of the switching element 14 on the wiring layer 23 side. The source electrode SE2 and the two gate electrodes GE2 are provided at an end of the surface of the switching element 14 on the wiring layer 21 side. In other words, the drain electrode DE2, the source electrode SE2, and the two gate electrodes GE2 are spaced apart from each other in the X direction.

[0073] The two gate electrodes GE2 are provided at both ends of the surface of the switching element 14 in the Y direction. The source electrode SE2 is provided between the two gate electrodes GE2 in the Y direction. In other words, the source electrode SE2 and the two gate electrodes GE2 are arranged in the order of gate electrode GE2, source electrode SE2, gate electrode GE2 in the Y direction, and are spaced apart from each other. The number of gate electrodes GE2 may be one, or three or more.

[0074] The driver circuit 12 is provided above the wiring layer 22. The wiring layer 24 is provided above the driver circuit 12 and the switching elements 14. A via 41 is provided between the wiring layer 24 and the driver circuit 12. A via 41 is provided between the wiring layer 24 and the switching elements 14.

[0075] A dielectric layer 51 is provided above the wiring layer 22 and above the switching element 14. A plurality of vias 41 are provided below the dielectric layer 51 and on the wiring layer 22. A plurality of vias 41 are provided below the dielectric layer 51 and on the switching element 14. More specifically, a plurality of vias 41 are provided below the dielectric layer 51 and on the source electrode SE2 on the surface of the switching element 14.

[0076] A wiring layer is provided above the wiring layer 23 and above the switching element 14. A plurality of vias 41 are provided on the wiring layer .

[0077] FIG. 9 is a plan view showing an example of the planar structure of the semiconductor device 1, viewed downward from the position of line cc in FIGS.

[0078] 9, a wiring layer is provided above the wiring layer 22. A plurality of vias 41 are provided on the wiring layer .

[0079] A wiring layer 29 is provided above the wiring layer 23. Below the wiring layer 29, a plurality of vias 41 are provided.

[0080] The switching element 13 is provided above the wiring layers 26 and 29. Note that Fig. 9 shows the surface of the switching element 13. A drain electrode DE1, a source electrode SE1, and two gate electrodes GE1 are provided on the surface of the switching element 13.

[0081] The drain electrode DE1 is provided at an end of the surface of the switching element 13 on the wiring layer 21 side. The source electrode SE1 and the two gate electrodes GE1 are provided at an end of the surface of the switching element 13 on the wiring layer 23 side. In other words, the drain electrode DE1, the source electrode SE1, and the two gate electrodes GE1 are arranged to be spaced apart from each other in the X direction.

[0082] The two gate electrodes GE1 are provided at both ends of the surface of the switching element 13 in the Y direction. The source electrode SE1 is provided between the two gate electrodes GE1 in the Y direction. In other words, the source electrode SE1 and the two gate electrodes GE1 are arranged in the order of gate electrode GE1, source electrode SE1, gate electrode GE1 in the Y direction, and are spaced apart from each other. The number of gate electrodes GE1 may be one, or three or more.

[0083] A plurality of vias 41 are provided between the switching element 13 and the wiring layer 26. More specifically, a plurality of vias 41 are provided between the drain electrode DE1 on the surface of the switching element 13 and the wiring layer 26. A plurality of vias 41 are provided between the switching element 13 and the wiring layer 29. More specifically, a plurality of vias 41 are provided between the source electrode SE1 on the surface of the switching element 13 and the wiring layer 29.

[0084] The driver circuit 11 is provided above the wiring layer 23. The wiring layer 27 is provided below the driver circuit 11 and the switching elements 13. A via 41 is provided between the wiring layer 27 and the driver circuit 11. A via 41 is provided between the wiring layer 27 and the switching elements 13.

[0085] FIG. 10 is a plan view showing an example of the planar structure of the semiconductor device 1, viewed downward from the position of line dd in FIGS.

[0086] As shown in FIG. 10 , a plurality of vias 41 are provided between the wiring layer 30 and the wiring layer 21. A plurality of vias 41 are provided between the wiring layer 30 and the wiring layer 26. The wiring layer 30 functions as a wiring that supplies the voltage VDC+. The switching element 13 is provided below the wiring layer 30. Note that FIG. 10 shows the back surface of the switching element 13. The plurality of vias 41 provided between the wiring layer 30 and the switching element 13 are provided to release heat from the switching element 13. In other words, the wiring layer 30 also functions as a heat release surface for the switching element 13.

[0087] According to the semiconductor device 1 of this embodiment, noise can be reduced.

[0088] In a power supply module configured with a snubber capacitor placed across two switching elements connected in series, high-frequency current flows through a loop consisting of the snubber capacitor and the two switching elements when the two switching elements are switched on or off. This high-frequency current can be a source of noise. The longer the wiring connecting the snubber capacitor and the two switching elements, the longer the loop path becomes, and the larger the parasitic inductance of the loop becomes. Therefore, in order to reduce noise caused by high-frequency current, it is desirable to shorten the loop path.

[0089] FIG. 11 is a diagram showing a high-frequency current path in the semiconductor device 1. As shown in FIG.

[0090] As shown in Figure 11, the high-frequency current path RT1 of the semiconductor device 1 is a path from the wiring layer 26, through the via 41 on the wiring layer 26, the drain electrode DE1, the source electrode SE1, the via 41 below the source electrode SE1, the wiring layer 29, the via 41 below the wiring layer 29, the wiring layer 28, the via 41 below the wiring layer 28, the drain electrode DE2, the source electrode SE2, and the via 41 above the source electrode SE2, to the wiring layer 25.

[0091] The semiconductor device 1 of this embodiment includes a substrate 20 incorporating a switching element 13 having a drain electrode DE1 and a source electrode SE1 on its surface, a switching element 14 having a source electrode SE2 and a drain electrode DE2 on its surface, and a capacitor 15.

[0092] The capacitor 15 includes a wiring layer 25 connected to the source electrode SE2, a wiring layer 26 connected to the drain electrode DE1, and a dielectric layer 51 disposed between the wiring layer 25 and the wiring layer 26. The capacitor 15 is formed between a layer in which the switching element 13 is provided and a layer in which the switching element 14 is provided. The source electrode SE2 is disposed opposite the drain electrode DE1 in the Z direction. The drain electrode DE2 is disposed opposite the source electrode SE1 in the Z direction. The drain electrode DE2 is also connected in series to the source electrode SE1.

[0093] Due to the above configuration, in this embodiment, the path between the wiring layer 26 and the drain electrode DE1 is shorter than when the capacitor 15 is not formed between the switching elements 13 and 14, the drain electrode DE1 and the source electrode SE2 do not face each other, and the source electrode SE1 and the drain electrode DE2 do not face each other. The path between the source electrode SE1 and the drain electrode DE2 and the path between the source electrode SE2 and the wiring layer 25 are similarly short. As a result, the high-frequency current path RT1 is shorter than when the capacitor 15 is not formed between the switching elements 13 and 14, the drain electrode DE1 and the source electrode SE2 do not face each other, and the source electrode SE1 and the drain electrode DE2 do not face each other. Therefore, the parasitic inductance of the loop formed by the capacitor 15 and the switching elements 13 and 14 can be reduced. As a result, according to this embodiment, noise can be reduced. Furthermore, the reduced noise can improve power conversion efficiency.

[0094] The drain electrode DE1 and the source electrode SE1 are arranged opposite to each other in the X direction. The source electrode SE2 and the drain electrode DE2 are arranged opposite to each other in the X direction. Therefore, in this embodiment, the path between the drain electrode DE1 and the source electrode SE1 and the path between the drain electrode DE2 and the source electrode SE2 are relatively short. This makes the high-frequency current path RT1 relatively short.

[0095] The thickness of the dielectric layer 51 is thinner than the thickness of the switching element 13. The thickness of the dielectric layer 51 is also thinner than the thickness of the switching element 14. That is, the thickness of the capacitor 15 is relatively thin. Therefore, in this embodiment, the path between the wiring layer 26 and the drain electrode DE1, the path between the source electrode SE2 and the wiring layer 25, and the path between the source electrode SE1 and the drain electrode DE2 are relatively short. Furthermore, the thicknesses of the switching elements 13 and 14 are not involved in the high-frequency current path RT1. As a result, the high-frequency current path RT1 becomes relatively short.

[0096] The dielectric layer 51 includes, for example, silicon or barium titanate. That is, the capacitor 15 is, for example, a silicon capacitor or a barium titanate capacitor. A relatively thin capacitor, such as a silicon capacitor or a barium titanate capacitor, can be formed between the layer on the substrate 20 where the switching element 13 is provided and the layer on which the switching element 14 is provided. This allows the thickness of the capacitor 15 to be relatively thin. Therefore, in this embodiment, the path between the wiring layer 26 and the drain electrode DE1, the path between the source electrode SE2 and the wiring layer 25, and the path between the source electrode SE1 and the drain electrode DE2 are relatively short. This makes the high-frequency current path RT1 relatively short.

[0097] The surface area of ​​the wiring layer 26 is larger than the surface area of ​​the switching element 13. The surface area of ​​the wiring layer 25 is larger than the surface area of ​​the switching element 14. This makes the capacitance of the capacitor 15 relatively large.

[0098] The wiring layer 26 protrudes in the X direction toward the wiring layer 21 further than the switching element 13. The wiring layer 25 protrudes in the X direction toward the wiring layer 21 further than the switching element 14. This makes the area of ​​the switching element 13 and the area of ​​the switching element 14 relatively large. Therefore, the capacitance of the capacitor 15 becomes relatively large.

[0099] The back surface of the switching element 13 is connected to the wiring layer 30 through a plurality of vias 41. As a result, heat from the switching element 13 is transmitted through the plurality of vias 41 and the wiring layer 30 and released to the outside of the semiconductor device 1. The back surface of the switching element 14 is connected to the wiring layer 22 through a plurality of vias 41. As a result, heat from the switching element 14 is transmitted through the plurality of vias 41 and the wiring layer 22 and released to the outside of the semiconductor device 1.

[0100] The surface area of ​​the wiring layer 23 is smaller than the surface area of ​​the wiring layer 22. This is because the wiring layer 22 functions as a heat dissipation surface for the switching element 14, and therefore the wiring layer 23 does not need to function as a heat dissipation surface. The wiring layer 23 is connected to the wiring layers 28 and 29 included in the high-frequency current path RT1, and therefore can be a noise source. However, because the surface area of ​​the wiring layer 23 is relatively small, the noise source can be reduced.

[0101] When the switching elements 13 and 14 are GaN transistors, the switching operation of the switching elements 13 and 14 can be made faster.

[0102] 2. Second embodiment A semiconductor device according to the second embodiment will now be described. The semiconductor device 1A according to the second embodiment includes two semiconductor devices 1, and has a configuration in which the input / output terminal T3 is shared by the two semiconductor devices 1. The following describes the differences from the first embodiment.

[0103] 2.1 Circuit configuration of semiconductor device The circuit configuration of the semiconductor device 1A will be described with reference to Fig. 12. Fig. 12 is a circuit diagram showing an example of the circuit configuration of the semiconductor device 1A.

[0104] The semiconductor device 1A includes control terminals T1 and T2, driver circuits 11 and 12, input / output terminals T3 to T5, switching elements 13 and 14, a capacitor 15, control terminals T6 and T7, driver circuits 61 and 62, input / output terminals T8 and T9, switching elements 63 and 64, and a capacitor 65.

[0105] The control terminals T1 and T2, the driver circuits 11 and 12, the input / output terminals T4 and T5, the switching elements 13 and 14, and the capacitor 15 are the same as those shown in FIG. 1 in the first embodiment.

[0106] The control terminal T6 is a terminal to which a control signal IH2 is input from the outside. The control signal IH2 is a signal for controlling the operation of the driver circuit 61. The control signal IH2 is, for example, an "H" level signal or an "L" level signal.

[0107] The control terminal T7 is a terminal to which a control signal IL2 is input from the outside. The control signal IL2 is a signal for controlling the operation of the driver circuit 62. The control signal IL2 is, for example, an "H" level signal or an "L" level signal.

[0108] The driver circuit 61 is a circuit that drives the switching element 63. The driver circuit 61 is connected to the control terminal T6 and the switching element 63. The driver circuit 61 turns the switching element 63 on or off based on a control signal IH2.

[0109] The driver circuit 62 is a circuit that drives the switching element 64. The driver circuit 62 is connected to the control terminal T7 and the switching element 64. The driver circuit 62 turns the switching element 64 on or off based on a control signal IL2.

[0110] The control signal IH2 is the same signal as the control signal IH1. The control signal IL2 is the same signal as the control signal IL1. Therefore, the driver circuit 61 operates in synchronization with the driver circuit 11. The driver circuit 62 operates in synchronization with the driver circuit 12. As a result, the driver circuits 11, 12, 61, and 62 alternately turn on or off the switching elements 13 and 63 and the switching elements 14 and 64. In other words, when one of the switching elements 13 and 63 and the switching elements 14 and 64 is in the on state, the other is in the off state.

[0111] Input / output terminals T3, T8, and T9 are input terminals or output terminals. Input / output terminal T3 is connected to nodes N1 and N4. Input / output terminal T8 is connected to node N5. Input / output terminal T9 is connected to node N6. Node N4, i.e., input / output terminal T3, is applied with voltage VSW. Node N5, i.e., input / output terminal T8, is applied with voltage VDC+. Node N6, i.e., input / output terminal T9, is applied with voltage VDC-.

[0112] The switching element 63 has a first end, a second end, and a third end. The first end of the switching element 63 is connected to the driver circuit 61. The second end of the switching element 63 is connected to a node N5. The third end of the switching element 63 is connected to a node N4. The switching element 64 has a first end, a second end, and a third end. The first end of the switching element 64 is connected to the driver circuit 62. The second end of the switching element 64 is connected to a node N4. The third end of the switching element 64 is connected to a node N6. The switching elements 63 and 64 include, for example, at least one of an n-channel MOSFET, a p-channel MOSFET, a GaN transistor, a SiC transistor, an IGBT, and a JFET.

[0113] One electrode of capacitor 65 is connected to node N5. The other electrode of capacitor 65 is connected to node N6. In other words, capacitor 65 is connected across switching elements 63 and 64 connected in series. This allows capacitor 65 to function as a snubber capacitor.

[0114] In addition, in the semiconductor device 1A, the driver circuits 61 and 62 and the control terminals T6 and T7 may not be mounted, and the driver circuits 11 and 12 and the control terminals T1 and T2 may be shared. In this case, the control electrode of the switching element 63 is connected to the driver circuit 11. The control electrode of the switching element 64 is connected to the driver circuit 12.

[0115] The input / output terminals T3, T8, and T9 function as input terminals or output terminals, similarly to the first embodiment, depending on the configuration of the circuit (not shown) connected to the input / output terminals T3, T8, and T9.

[0116] In the following, as an example, a case where the switching elements 63 and 64 are n-channel MOSFETs will be described.

[0117] FIG. 13 is a circuit diagram showing an example of the configuration of each switching element in the semiconductor device 1. As shown in FIG.

[0118] 13, the switching element 63 is a transistor TR3. The switching element 64 is a transistor TR4. The transistors TR3 and TR4 are n-channel MOSFETs. The transistors TR3 and TR4 are normally-off transistors.

[0119] A gate electrode (control electrode) of switching element 63 is connected to driver circuit 61. A drain electrode of switching element 63 is connected to node N5. A source electrode of switching element 63 is connected to node N4. A gate electrode (control electrode) of switching element 64 is connected to driver circuit 62. A drain electrode of switching element 64 is connected to node N4. A source electrode of switching element 64 is connected to node N6. A source electrode of switching element 63 and a drain electrode of switching element 64 are connected in series.

[0120] 2.2 Structure of semiconductor device The structure of the semiconductor device 1A will be described. The semiconductor device 1A has a structure in which two semiconductor devices 1 are combined. Figure 14 is a cross-sectional view taken along the same line as line II in Figure 4 shown in the first embodiment, showing an example of the cross-sectional structure of the semiconductor device 1A.

[0121] As shown in FIG. 14 , in semiconductor device 1A, with a line (hereinafter referred to as "line AA") extending from the center of the surface of wiring layer 23 in the Z direction as the boundary, the structure on the left side along the X axis has the same structure as semiconductor device 1, and the structure on the right side along the X axis has a structure obtained by rotating semiconductor device 1 by 180 degrees around line AA as the rotation axis. Wiring layer 71 corresponds to wiring layer 21. Wiring layer 72 corresponds to wiring layer 22. Switching element 63 corresponds to switching element 13. Switching element 64 corresponds to switching element 14. Wiring layer 74 corresponds to wiring layer 25. Dielectric layer 81 corresponds to dielectric layer 51. Wiring layer 75 corresponds to wiring layer 26. Capacitor 65 corresponds to capacitor 15.

[0122] Wiring layers 71 and 72 are provided on the back surface of the substrate 20. The wiring layers 23, 71, and 72 are spaced apart from each other in the X direction. The wiring layer 71 corresponds to the input / output terminal T8. A voltage VDC+ is applied to the wiring layer 71. The wiring layer 72 corresponds to the input / output terminal T9. A voltage VDC- is applied to the wiring layer 72.

[0123] The switching element 63 has a surface S5 and a surface S6 opposite to surface S5. Hereinafter, surface S5 will also be referred to as the "front surface of the switching element 63," and surface S6 will also be referred to as the "rear surface of the switching element 63." A drain electrode DE3 and a source electrode SE3 are provided on the front surface of the switching element 63. A plurality of vias 41 are provided between the switching element 63 and the wiring layer 30.

[0124] The switching element 64 has a surface S7 and a surface S8 facing the surface S7. Hereinafter, the surface S7 will also be referred to as the "surface of the switching element 64," and the surface S8 will also be referred to as the "back surface of the switching element 64." A source electrode SE4 and a drain electrode DE4 are provided on the surface of the switching element 64. A plurality of vias 41 are provided between the switching element 64 and the wiring layer 72.

[0125] The wiring layer 74 is provided above the switching element 64. A plurality of vias 41 are provided between the end of the lower surface of the wiring layer 74 on the switching element 64 side and the source electrode SE4 of the switching element 64. In other words, the end of the lower surface of the wiring layer 74 on the switching element 64 side is in contact with the plurality of vias 41. The source electrode SE4 of the switching element 64 is in contact with the plurality of vias 41. That is, the wiring layer 74 is connected to the source electrode SE4 of the switching element 64 through the plurality of vias 41. A plurality of vias 41 are provided between the wiring layer 74 and the wiring layer 72. The wiring layer 74 functions as a wiring that supplies the voltage VDC−. The wiring layer 74 also functions as the other electrode of the capacitor 65.

[0126] The dielectric layer 81 is provided on the wiring layer 74 .

[0127] The wiring layer 75 is provided on the dielectric layer 81 and below the switching element 63. A plurality of vias 41 are provided between the end of the upper surface of the wiring layer 75 on the switching element 63 side and the drain electrode DE3 of the switching element 63. In other words, the end of the upper surface of the wiring layer 75 on the switching element 63 side is in contact with the plurality of vias 41. The drain electrode DE3 of the switching element 63 is in contact with the plurality of vias 41. That is, the wiring layer 75 is connected to the drain electrode DE3 of the switching element 63 through the plurality of vias 41. A plurality of vias 41 are provided between the wiring layer 75 and the wiring layer 30. The wiring layer 75 functions as a wiring that supplies the voltage VDC+. The wiring layer 75 also functions as one electrode of the capacitor 65.

[0128] A plurality of vias 41 are provided between the wiring layer 71 and the wiring layer 30 .

[0129] The wiring layer 71 is connected to the wiring layer 75 via a plurality of vias 41, the wiring layer 30, and a plurality of vias 41. The wiring layer 72 is connected to the wiring layer 74 via a plurality of vias 41. The wiring layer 23 is connected to the source electrode SE3 of the switching element 63 via a plurality of vias 41, the wiring layer 28, a plurality of vias 41, the wiring layer 29, and a plurality of vias 41. The wiring layer 23 is also connected to the drain electrode DE4 of the switching element 64 via a plurality of vias 41, the wiring layer 28, and a plurality of vias 41.

[0130] FIG. 15 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor device 1, taken along the same line as line II-II in FIG. 4 shown in the first embodiment.

[0131] As shown in FIG. 15, in the semiconductor device 1A, the cross-sectional structure along the same line as line II-II in FIG. 4 differs between the structure on the left side along the X axis and the structure on the right side along the X axis, with line AA as the boundary.

[0132] A gate electrode GE3 is provided on the surface of the switching element 63. A gate electrode GE4 is provided on the surface of the switching element 64.

[0133] FIG. 16 is a plan view showing an example of the planar structure of the semiconductor device 1, viewed downward from the position of line aa in FIGS.

[0134] 16, a plurality of vias 41 are provided on the wiring layer 71. The wiring layer 71 functions as an external connection terminal for the voltage VDC+.

[0135] A plurality of vias 41 are provided on the wiring layer 72. The wiring layer 72 functions as an external connection terminal for a voltage VDC-. A switching element 64 is provided above the wiring layer 72. Note that FIG. 16 shows the back surface of the switching element 64. The plurality of vias 41 provided between the wiring layer 72 and the switching element 64 are provided to release heat from the switching element 64. In other words, the wiring layer 72 also functions as a heat release surface for the switching element 64.

[0136] FIG. 17 is a plan view showing an example of the planar structure of the semiconductor device 1, viewed downward from the position of line bb in FIGS.

[0137] 17, a switching element 64 is provided above the wiring layer 72. Note that Fig. 17 shows the surface of the switching element 64. A drain electrode DE4, a source electrode SE4, and two gate electrodes GE4 are provided on the surface of the switching element 64.

[0138] The drain electrode DE4 is provided at an end of the surface of the switching element 64 on the wiring layer 23 side. The source electrode SE4 and the two gate electrodes GE4 are provided at an end of the surface of the switching element 64 on the wiring layer 71 side. In other words, the drain electrode DE4, the source electrode SE4, and the two gate electrodes GE4 are spaced apart from each other in the X direction.

[0139] The two gate electrodes GE4 are provided at both ends of the surface of the switching element 64 in the Y direction. The source electrode SE4 is provided between the two gate electrodes GE4 in the Y direction. In other words, the source electrode SE4 and the two gate electrodes GE4 are arranged in the order of gate electrode GE4, source electrode SE4, gate electrode GE4 in the Y direction, and are spaced apart from each other. The number of gate electrodes GE4 may be one, or three or more.

[0140] A driver circuit 62 is provided above the wiring layer 72. The driver circuit 62 corresponds to the driver circuit 12. A wiring layer 73 is provided above the driver circuit 62 and the switching element 64. The wiring layer 73 corresponds to the wiring layer 24. A via 41 is provided between the wiring layer 73 and the driver circuit 62. A via 41 is provided between the wiring layer 73 and the switching element 64.

[0141] A dielectric layer 81 is provided above the wiring layer 72 and above the switching element 64. A plurality of vias 41 are provided below the dielectric layer 81 and on the wiring layer 72. A plurality of vias 41 are provided below the dielectric layer 81 and on the switching element 64. More specifically, a plurality of vias 41 are provided below the dielectric layer 81 and on the source electrode SE4 on the surface of the switching element 64.

[0142] A wiring layer is provided above the wiring layer 23 and above the switching element 64. A plurality of vias 41 are provided on the wiring layer .

[0143] FIG. 18 is a plan view showing an example of the planar structure of the semiconductor device 1, viewed downward from the position of line cc in FIGS.

[0144] 18, a wiring layer 75 is provided above the wiring layer 72. On the wiring layer 75, a plurality of vias 41 are provided.

[0145] A wiring layer 29 is provided above the wiring layer 23. Below the wiring layer 29, a plurality of vias 41 are provided.

[0146] A switching element 63 is provided above the wiring layers 75 and 29. Fig. 18 shows the surface of the switching element 63. A drain electrode DE3, a source electrode SE3, and two gate electrodes GE3 are provided on the surface of the switching element 63.

[0147] The drain electrode DE3 is provided at an end of the surface of the switching element 63 on the wiring layer 71 side. The source electrode SE3 and the two gate electrodes GE3 are provided at an end of the surface of the switching element 63 on the wiring layer 23 side. In other words, the drain electrode DE3 is spaced apart from the source electrode SE3 and the two gate electrodes GE3 in the X direction.

[0148] The two gate electrodes GE3 are provided at both ends of the surface of the switching element 63 in the Y direction. The source electrode SE3 is provided between the two gate electrodes GE3 in the Y direction. In other words, the source electrode SE3 and the two gate electrodes GE3 are arranged in the order of gate electrode GE3, source electrode SE3, gate electrode GE3 in the Y direction, and are spaced apart from each other. The number of gate electrodes GE3 may be one, or three or more.

[0149] A plurality of vias 41 are provided between the switching element 63 and the wiring layer 75. More specifically, a plurality of vias 41 are provided between the wiring layer 75 and a drain electrode DE3 on the surface of the switching element 63. A plurality of vias 41 are provided between the switching element 63 and the wiring layer 29. More specifically, a plurality of vias 41 are provided between the wiring layer 29 and a source electrode SE3 on the surface of the switching element 63.

[0150] A driver circuit 61 is provided above the wiring layer 23. The driver circuit 61 corresponds to the driver circuit 11. A wiring layer 76 is provided below the driver circuit 61 and the switching elements 63. The wiring layer 76 corresponds to the wiring layer 27. A via 41 is provided between the wiring layer 76 and the driver circuit 61. A via 41 is provided between the wiring layer 76 and the switching elements 63.

[0151] FIG. 19 is a plan view showing an example of the planar structure of the semiconductor device 1, viewed downward from the position of line dd in FIGS.

[0152] As shown in FIG. 19 , a plurality of vias 41 are provided between the wiring layer 30 and the wiring layer 71. A plurality of vias 41 are provided between the wiring layer 30 and the wiring layer 75. A switching element 63 is provided below the wiring layer 30. Note that FIG. 19 shows the back surface of the switching element 63. The plurality of vias 41 provided between the wiring layer 30 and the switching element 63 are provided to release heat from the switching element 63. In other words, the wiring layer 30 also functions as a heat release surface for the switching element 63.

[0153] According to the semiconductor device 1A of this embodiment, noise can be reduced.

[0154] FIG. 20 is a diagram showing a high-frequency current path in the semiconductor device 1A and magnetic flux generated by the high-frequency current.

[0155] As shown in FIG. 20, the high-frequency current path of the semiconductor device 1A includes the path of FIG. 11 shown in the first embodiment (hereinafter referred to as "first path RT1").

[0156] The semiconductor device 1A also includes a path (hereinafter referred to as the "second path RT2") from the wiring layer 75 through a via 41 above the wiring layer 75, a drain electrode DE3, a source electrode SE3, a via 41 below the source electrode SE3, the wiring layer 29, a via 41 below the wiring layer 29, the wiring layer 28, a via 41 below the wiring layer 28, the drain electrode DE4, the source electrode SE4, and a via 41 above the source electrode SE4 to the wiring layer 74.

[0157] A semiconductor device 1A according to this embodiment includes the semiconductor device 1 shown in the first embodiment.

[0158] The substrate 20 has built-in a switching element 63 having a drain electrode DE3 and a source electrode SE3 on its surface, a switching element 64 having a source electrode SE4 and a drain electrode DE4 on its surface, and a capacitor 65.

[0159] The capacitor 65 includes a wiring layer 74 connected to the source electrode SE4, a wiring layer 75 connected to the drain electrode DE3, and a dielectric layer 81 disposed between the wiring layer 74 and the wiring layer 75. The capacitor 65 is formed between a layer in which the switching element 63 is provided and a layer in which the switching element 64 is provided. The source electrode SE4 is disposed opposite the drain electrode DE3 in the Z direction. The drain electrode DE4 is disposed opposite the source electrode SE3 in the Z direction. The drain electrode DE4 is also connected in series to the source electrode SE3.

[0160] With the above configuration, in this embodiment, the high-frequency current paths are short in the first path RT1 and the second path RT2, similar to the first embodiment, and therefore, according to this embodiment, the same effects as the first embodiment can be achieved.

[0161] Furthermore, wiring layer 25 is connected to wiring layer 22, which supplies voltage VDC-. Wiring layer 26 is connected to wiring layer 21, which supplies voltage VDC+. Source electrode SE1 and drain electrode DE2 are connected to wiring layer 23, which supplies voltage VSW in the range of voltage VDC- or more and voltage VDC+ or less. Wiring layer 74 is connected to wiring layer 72, which supplies voltage VDC-. Wiring layer 75 is connected to wiring layer 71, which supplies voltage VDC+. Source electrode SE3 and drain electrode DE4 are connected to wiring layer 23.

[0162] The switching elements 63 and 64 and the capacitor 65 (wiring layers 74 and 75 and dielectric layer 81) are arranged at positions obtained by rotating the switching elements 13 and 14 and the capacitor 15 (wiring layers 25 and 26 and dielectric layer 51) by 180 degrees around the AA line. The wiring layers 71 and 72 are arranged at positions obtained by rotating the wiring layers 21 and 22 by 180 degrees around the AA line.

[0163] Due to the above configuration, in this embodiment, as shown in FIG. 20, the direction of the magnetic flux Φ1 generated by the high-frequency current flowing through the first path RT1 (direction from the front to the back of the page) is opposite to the direction of the magnetic flux Φ2 generated by the high-frequency current flowing through the second path RT2 (direction from the back to the front of the page). Therefore, the magnetic fluxes generated in the two paths RT1 and RT2 cancel each other out. Therefore, noise emitted to the outside due to the generation of magnetic flux can be suppressed. As a result, according to this embodiment, noise can be reduced. Furthermore, the reduction in noise can improve power conversion efficiency.

[0164] 3. Third embodiment A semiconductor device according to a third embodiment will now be described. In the semiconductor device 1B according to the third embodiment, the switching elements 13 and 14 of the semiconductor device 1 are replaced with normally-on switching elements, and a normally-off switching element and a driver circuit for realizing a pseudo-normally-off state (hereinafter referred to as a "QN-off driver circuit") are added to the semiconductor device 1. The following describes the differences from the first embodiment.

[0165] 3.1 Circuit configuration of semiconductor device The circuit configuration of the semiconductor device 1B will be described with reference to Fig. 21. Fig. 21 is a circuit diagram showing an example of the circuit configuration of the semiconductor device 1B.

[0166] The semiconductor device 1B includes control terminals T1 and T2, driver circuits 11 and 12, input / output terminals T3 to T5, switching elements 13 and 14, and a capacitor 15. The semiconductor device 1B also includes control terminals T10 and T11, QN-off driver circuits 91 and 92, and switching elements 93 and 94.

[0167] The control terminals T1 and T2, the input / output terminals T3 to T5, and the capacitor 15 are the same as those shown in FIG. 1 in the first embodiment.

[0168] A third terminal of switching element 13 is connected to node N7. A third terminal of switching element 14 is connected to node N8. Switching elements 13 and 14 include, for example, at least one of an n-channel MOSFET, a p-channel MOSFET, a GaN transistor, a SiC transistor, an IGBT, and a JFET. Switching elements 13 and 14 are normally-on switching elements.

[0169] The control terminal T10 is a terminal to which a control signal IH3 is input from outside. The control signal IH3 is a signal for controlling the operation of the QN-off driver circuit 91. The control signal IH3 is, for example, an "H" level signal or an "L" level signal.

[0170] The control terminal T11 is a terminal to which a control signal IL3 is input from the outside. The control signal IL3 is a signal for controlling the operation of the QN-off driver circuit 92. The control signal IL3 is, for example, an “H” level signal or an “L” level signal.

[0171] The QN-off driver circuit 91 is a circuit that drives the switching element 93. The QN-off driver circuit 91 is connected to a control terminal T10 and the switching element 93. The QN-off driver circuit 91 turns the switching element 93 on or off based on a control signal IH3.

[0172] The QN-off driver circuit 92 is a circuit that drives the switching element 94. The QN-off driver circuit 92 is connected to the control terminal T11 and the switching element 94. The QN-off driver circuit 92 turns the switching element 94 on or off based on a control signal IL3.

[0173] The driver circuit 11 turns on the switching element 13 in response to an ON request signal to the switching element 13 by the control signal IH1. The driver circuit 11 also turns off the switching element 13 in response to an OFF request signal to the switching element 13 by the control signal IH1.

[0174] The driver circuit 12 turns on the switching element 14 in response to an ON request signal to the switching element 14 by the control signal IL1. The driver circuit 12 also turns off the switching element 14 in response to an OFF request signal to the switching element 14 by the control signal IL1.

[0175] However, when the entire system including the semiconductor device 1B is powered on or off, that is, when the power supply is in an unstable state, the switching elements 13 and 14 may be unintentionally turned on.

[0176] Therefore, when the power supply is in an unstable state, the control signals IH3 and IL3 are controlled to turn off the switching elements 93 and 94. As a result, both the high-side switching elements, including the switching elements 13 and 93, and the low-side switching elements, including the switching elements 14 and 94, are turned off. On the other hand, when the power supply is in a steady state, the control signals IH3 and IL3 are controlled to turn on the switching elements 93 and 94. The control signals IH1 and IL1 are controlled to alternately turn on and off the switching elements 13 and 14. As a result, the high-side switching elements, including the switching elements 13 and 93, and the low-side switching elements, including the switching elements 14 and 94, are alternately turned on and off. In this way, a "quasi-normally off" state is realized. As a result, power conversion and control are performed by alternately driving the high-side switching elements and the low-side switching elements.

[0177] The switching element 93 has a first terminal, a second terminal, and a third terminal. The first terminal of the switching element 93 is connected to the QN-off driver circuit 91. The second terminal of the switching element 93 is connected to a node N7. The third terminal of the switching element 93 is connected to a node N1. The switching element 94 has a first terminal, a second terminal, and a third terminal. The first terminal of the switching element 94 is connected to the QN-off driver circuit 92. The second terminal of the switching element 94 is connected to a node N8. The third terminal of the switching element 94 is connected to a node N3. The switching elements 93 and 94 include, for example, at least one of an n-channel MOSFET and a p-channel MOSFET. The switching elements 93 and 94 are normally-off switching elements.

[0178] In the following, as an example, a case will be described in which the switching elements 13 and 14 are n-channel MOSFETs and the switching elements 93 and 94 are p-channel MOSFETs.

[0179] FIG. 22 is a circuit diagram showing an example of the configuration of each switching element in the semiconductor device 1B.

[0180] 22, the switching element 13 is a transistor TR1. The switching element 14 is a transistor TR2. The transistors TR1 and TR2 are n-channel MOSFETs. The transistors TR1 and TR2 are normally-on transistors.

[0181] The source electrode of switching element 13 is connected to node N7, and the source electrode of switching element 14 is connected to node N8.

[0182] The switching element 93 is a transistor TR5. The switching element 94 is a transistor TR6. The transistors TR5 and TR6 are p-channel MOSFETs. The transistors TR5 and TR6 are normally-off transistors.

[0183] A gate electrode (control electrode) of the switching element 93 is connected to the QN-off driver circuit 91. A drain electrode of the switching element 93 is connected to a node N1. A source electrode of the switching element 93 is connected to a node N7. A gate electrode (control electrode) of the switching element 94 is connected to the QN-off driver circuit 92. A drain electrode of the switching element 94 is connected to a node N3. A source electrode of the switching element 94 is connected to a node N8.

[0184] The source electrode of switching element 13 and the source electrode of switching element 93 are connected in series. The drain electrode of switching element 93 and the drain electrode of switching element 14 are connected in series. The source electrode of switching element 14 and the source electrode of switching element 94 are connected in series.

[0185] 3.2 Structure of semiconductor device The structure of semiconductor device 1B will be described. Semiconductor device 1B has a structure in which a switching element 93 is provided between wiring layer 29 of semiconductor device 1 and switching element 13, and a QN-off driver circuit 91 connected to switching element 93 is provided. Semiconductor device 1B also has a structure in which a switching element 94 is provided between wiring layer 25 of semiconductor device 1 and switching element 14, and a QN-off driver circuit 92 connected to switching element 94 is provided. Figure 23 is a cross-sectional view taken along the same line as line II in Figure 4 shown in the first embodiment, showing an example of the cross-sectional structure of semiconductor device 1B.

[0186] A switching element 93 is provided above the wiring layer 29. A drain electrode (not shown) of the switching element 93 is connected to the wiring layer 29 through a plurality of vias 41. A switching element 13 is provided above the switching element 93. A source electrode (not shown) of the switching element 93 is connected to a source electrode SE1 of the switching element 13 through a plurality of vias 41. The drain electrode of the switching element 93 is provided, for example, on a surface of the switching element 93 (a surface facing the wiring layer 29 in the Z direction). The source electrode of the switching element 93 is provided, for example, on a surface of the switching element 93 (a surface facing the source electrode SE1 in the Z direction). A drain electrode DE2 of the switching element 14 is connected in series to the switching element 93.

[0187] A switching element 94 is provided below the wiring layer 25. A drain electrode (not shown) of the switching element 94 is connected to the wiring layer 25 through a plurality of vias 41. A switching element 14 is provided below the switching element 94. A source electrode (not shown) of the switching element 94 is connected to a source electrode SE2 of the switching element 14 through a plurality of vias 41. The drain electrode of the switching element 94 is provided, for example, on a surface of the switching element 94 (a surface facing the wiring layer 25 in the Z direction). The source electrode of the switching element 94 is provided, for example, on a surface of the switching element 94 (a surface facing the source electrode SE2 in the Z direction).

[0188] FIG. 24 is a cross-sectional view taken along the same line as line II-II in FIG. 4, showing an example of the cross-sectional structure of the semiconductor device 1B.

[0189] 24, a gate electrode GE1 is provided on the surface of the switching element 13. A gate electrode GE2 is provided on the surface of the switching element .

[0190] A wiring layer 95 is provided below the switching element 93. The switching element 93 is connected to the wiring layer 95 through a via 41. A QN-off driver circuit 91 is provided above the wiring layer 95 and below the switching element 13. The QN-off driver circuit 91 is connected to the wiring layer 95 through the via 41.

[0191] A wiring layer 96 is provided above the switching element 94. The switching element 94 is connected to the wiring layer 96 through a via 41. A QN-off driver circuit 92 is provided below the wiring layer 96 and above the switching element 14. The QN-off driver circuit 92 is connected to the wiring layer 96 through a via 41.

[0192] FIG. 25 is a diagram showing a high-frequency current path in the semiconductor device 1B.

[0193] As shown in FIG. 25, the high-frequency current path RT3 of the semiconductor device 1B is a path from the wiring layer 26 through the via 41 on the wiring layer 26, the drain electrode DE1, the source electrode SE1, the via 41 below the source electrode SE1, the switching element 93, the via 41 below the switching element 93, the wiring layer 29, the via 41 below the wiring layer 29, the wiring layer 28, the via 41 below the wiring layer 28, the drain electrode DE2, the source electrode SE2, the via 41 above the source electrode SE2, the switching element 94, and the via 41 above the switching element 94, to the wiring layer 25.

[0194] The semiconductor device 1B of this embodiment includes a substrate 20 incorporating a switching element 13 having a drain electrode DE1 and a source electrode SE1 on its surface, a switching element 14 having a source electrode SE2 and a drain electrode DE2 on its surface, switching elements 93 and 94, and a capacitor 15.

[0195] The switching element 93 is provided between the source electrode SE1 and the drain electrode DE2. The switching element 94 is provided between the drain electrode DE1 and the source electrode SE2. More specifically, the switching element 93 is provided between the wiring layer 29 and the switching element 13. The switching element 94 is provided between the wiring layer 25 and the switching element 14.

[0196] With the above configuration, in this embodiment, the length of the high-frequency current path RT3 can be made equal to the length of the high-frequency current path RT1 shown in the first embodiment. Therefore, it is possible to reduce the parasitic inductance of the loop formed by the capacitor 15 and the switching elements 13, 14, 93, and 94. As a result, according to this embodiment, noise can be reduced and power conversion efficiency can be improved, similar to the first embodiment.

[0197] 4. Fourth embodiment A semiconductor device according to the fourth embodiment will now be described. In the semiconductor device 1C according to the fourth embodiment, the switching elements 13, 14, 63, and 64 of the semiconductor device 1A are replaced with normally-on switching elements, and a normally-off switching element and a QN-off driver circuit are added to the semiconductor device 1A. The differences from the second embodiment will be described below.

[0198] 4.1 Circuit configuration of semiconductor device The circuit configuration of the semiconductor device 1C will be described with reference to Fig. 26. Fig. 26 is a circuit diagram showing an example of the circuit configuration of the semiconductor device 1C.

[0199] The semiconductor device 1C includes control terminals T1 and T2, driver circuits 11 and 12, input / output terminals T3 to T5, switching elements 13 and 14, a capacitor 15, control terminals T6 and T7, driver circuits 61 and 62, input / output terminals T8 and T9, switching elements 63 and 64, and a capacitor 65. The semiconductor device 1C also includes control terminals T10 and T11, QN-off driver circuits 91 and 92, switching elements 93 and 94, control terminals T12 and T13, QN-off driver circuits 101 and 102, and switching elements 103 and 104.

[0200] The control terminals T1 and T2, the input / output terminals T3 to T5, the capacitor 15, the control terminals T6 and T7, the input / output terminals T8 and T9, and the capacitor 65 are the same as those shown in FIG. 12 in the second embodiment.

[0201] The driver circuits 11 and 12, switching elements 13 and 14, control terminals T10 and T11, QN-off driver circuits 91 and 92, and switching elements 93 and 94 are the same as those shown in FIG. 21 in the third embodiment.

[0202] A third terminal of the switching element 63 is connected to a node N9. A third terminal of the switching element 64 is connected to a node N10. The switching elements 63 and 64 include, for example, at least one of an n-channel MOSFET, a p-channel MOSFET, a GaN transistor, a SiC transistor, an IGBT, and a JFET. The switching elements 63 and 64 are normally-on switching elements.

[0203] The control terminal T12 is a terminal to which a control signal IH4 is input from the outside. The control signal IH4 is a signal for controlling the operation of the QN-off driver circuit 101. The control signal IH4 is, for example, an “H” level signal or an “L” level signal.

[0204] The control terminal T13 is a terminal to which a control signal IL4 is input from the outside. The control signal IL4 is a signal for controlling the operation of the QN-off driver circuit 102. The control signal IL4 is, for example, an “H” level signal or an “L” level signal.

[0205] The QN-off driver circuit 101 is a circuit that drives the switching element 103. The QN-off driver circuit 101 is connected to a control terminal T12 and the switching element 103. The QN-off driver circuit 101 turns the switching element 103 on or off based on a control signal IH4.

[0206] The QN-off driver circuit 102 is a circuit that drives the switching element 104. The QN-off driver circuit 102 is connected to a control terminal T13 and the switching element 104. The QN-off driver circuit 102 turns the switching element 104 on or off based on a control signal IL4.

[0207] Driver circuit 61 operates in the same manner as driver circuit 11. Driver circuit 62 operates in the same manner as driver circuit 12. QN-off driver circuit 101 operates in the same manner as QN-off driver circuit 91. QN-off driver circuit 102 operates in the same manner as QN-off driver circuit 92. As a result, when the power supply is in an unstable state, both the high-side switching elements including switching elements 63 and 103 and the low-side switching elements including switching elements 64 and 104 are turned off. On the other hand, when the power supply is in a steady state, the high-side switching elements including switching elements 63 and 103 and the low-side switching elements including switching elements 64 and 104 are alternately turned on or off.

[0208] The control signal IH2 is the same signal as the control signal IH1. The control signal IL2 is the same signal as the control signal IL1. Therefore, the driver circuit 61 operates in synchronization with the driver circuit 11. The driver circuit 62 operates in synchronization with the driver circuit 12.

[0209] The control signal IH4 is the same signal as the control signal IH3. The control signal IL4 is the same signal as the control signal IL3. Therefore, the QN-off driver circuit 101 operates in synchronization with the QN-off driver circuit 91. The QN-off driver circuit 102 operates in synchronization with the QN-off driver circuit 92.

[0210] The switching element 103 has a first terminal, a second terminal, and a third terminal. The first terminal of the switching element 103 is connected to the QN-off driver circuit 101. The second terminal of the switching element 103 is connected to a node N9. The third terminal of the switching element 103 is connected to a node N4. The switching element 104 has a first terminal, a second terminal, and a third terminal. The first terminal of the switching element 104 is connected to the QN-off driver circuit 102. The second terminal of the switching element 104 is connected to a node N10. The third terminal of the switching element 104 is connected to a node N6. The switching elements 103 and 104 include, for example, at least one of an n-channel MOSFET and a p-channel MOSFET. The switching elements 103 and 104 are normally-off switching elements.

[0211] In addition, in semiconductor device 1C, driver circuits 61 and 62 and control terminals T6 and T7 may not be mounted, and driver circuits 11 and 12 and control terminals T1 and T2 may be shared, as in the second embodiment. Also, in semiconductor device 1C, QN-off driver circuits 101 and 102 and control terminals T12 and T13 may not be mounted, and QN-off driver circuits 91 and 92 and control terminals T10 and T11 may be shared. In this case, the control electrode of switching element 103 is connected to QN-off driver circuit 91. The control electrode of switching element 104 is connected to QN-off driver circuit 92.

[0212] In the following, as an example, a case will be described in which the switching elements 13, 14, 63, and 64 are n-channel MOSFETs, and the switching elements 93, 94, 103, and 104 are p-channel MOSFETs.

[0213] FIG. 27 is a circuit diagram showing an example of the configuration of each switching element in the semiconductor device 1C.

[0214] 27, the switching element 63 is a transistor TR3. The switching element 64 is a transistor TR4. The transistors TR3 and TR4 are n-channel MOSFETs. The transistors TR3 and TR4 are normally-on transistors.

[0215] The source electrode of switching element 63 is connected to node N9, and the source electrode of switching element 64 is connected to node N10.

[0216] The switching element 103 is a transistor TR7. The switching element 104 is a transistor TR8. The transistors TR7 and TR8 are p-channel MOSFETs. The transistors TR7 and TR8 are normally-off transistors.

[0217] The switching elements 13, 14, 93, and 94 are the same as those shown in FIG. 22 in the third embodiment.

[0218] A gate electrode (control electrode) of the switching element 103 is connected to the QN-off driver circuit 101. A drain electrode of the switching element 103 is connected to a node N4. A source electrode of the switching element 103 is connected to a node N9. A gate electrode (control electrode) of the switching element 104 is connected to the QN-off driver circuit 102. A drain electrode of the switching element 104 is connected to a node N6. A source electrode of the switching element 104 is connected to a node N10.

[0219] The source electrode of switching element 63 is connected in series to the source electrode of switching element 103. The drain electrode of switching element 103 is connected in series to the drain electrode of switching element 64. The source electrode of switching element 64 is connected in series to the source electrode of switching element 104.

[0220] 4.2 Structure of semiconductor device The structure of the semiconductor device 1C will be described. The semiconductor device 1C has a structure in which two semiconductor devices 1B are combined. Figure 28 is a cross-sectional view taken along the same line as line II in Figure 4 shown in the first embodiment, showing an example of the cross-sectional structure of the semiconductor device 1C.

[0221] 28, in semiconductor device 1C, with line AA as the boundary, the structure on the left side along the X axis has the same structure as semiconductor device 1B, and the structure on the right side along the X axis has a structure obtained by rotating semiconductor device 1B by 180 degrees around line AA as the rotation axis. Switching element 103 corresponds to switching element 93. Switching element 104 corresponds to switching element 94.

[0222] A switching element 103 is provided above the wiring layer 29. A drain electrode (not shown) of the switching element 103 is connected to the wiring layer 29 through a plurality of vias 41. A switching element 63 is provided above the switching element 103. A source electrode (not shown) of the switching element 103 is connected to a source electrode SE3 of the switching element 63 through a plurality of vias 41. The drain electrode of the switching element 103 is provided, for example, on a surface of the switching element 103 (a surface facing the wiring layer 29 in the Z direction). The source electrode of the switching element 103 is provided, for example, on a surface of the switching element 103 (a surface facing the source electrode SE3 of the switching element 63 in the Z direction).

[0223] A switching element 104 is provided below the wiring layer 74. A drain electrode (not shown) of the switching element 104 is connected to the wiring layer 74 through a plurality of vias 41. A switching element 64 is provided below the switching element 104. A source electrode (not shown) of the switching element 104 is connected to a source electrode SE4 of the switching element 64 through a plurality of vias 41. The drain electrode of the switching element 104 is provided, for example, on a surface of the switching element 104 (a surface facing the wiring layer 74 in the Z direction). The source electrode of the switching element 104 is provided, for example, on a surface of the switching element 104 (a surface facing the source electrode SE4 of the switching element 64 in the Z direction).

[0224] FIG. 29 is a cross-sectional view taken along the same line as line II-II in FIG. 4, showing an example of the cross-sectional structure of the semiconductor device 1C.

[0225] As shown in FIG. 29, in the semiconductor device 1C, the cross-sectional structure along the same line as line II-II in FIG. 4 differs between the structure on the left side along the X axis and the structure on the right side along the X axis, with line AA as the boundary.

[0226] A gate electrode GE3 is provided on the surface of the switching element 63. A gate electrode GE4 is provided on the surface of the switching element 64.

[0227] FIG. 30 is a diagram showing a high-frequency current path in the semiconductor device 1C and magnetic flux generated by the high-frequency current.

[0228] As shown in FIG. 30, the high-frequency current path of the semiconductor device 1C includes the path of FIG. 25 shown in the third embodiment (hereinafter referred to as "third path RT3").

[0229] The semiconductor device 1C also includes a path (hereinafter referred to as the "fourth path RT4") from the wiring layer 75 through a via 41 above the wiring layer 75, a drain electrode DE3, a source electrode SE3, a via 41 below the source electrode SE3, a switching element 103, a via 41 below the switching element 103, a wiring layer 29, a via 41 below the wiring layer 29, a wiring layer 28, a via 41 below the wiring layer 28, a drain electrode DE4, a source electrode SE4, a via 41 above the source electrode SE4, a switching element 104, and a via 41 above the switching element 104 to the wiring layer 74.

[0230] Due to the above configuration, in this embodiment, the high-frequency current paths are short in the third path RT3 and the fourth path RT4, as in the first embodiment. Therefore, it is possible to reduce the parasitic inductance of the loop formed by the capacitor 15 and the switching elements 13, 14, 93, and 94. It is also possible to reduce the parasitic inductance of the loop formed by the capacitor 65 and the switching elements 63, 64, 103, and 104. As a result, this embodiment provides the same effects as the first embodiment.

[0231] 30, in this embodiment, the direction of the magnetic flux Φ3 generated by the high-frequency current flowing through the third path RT3 (direction from the front to the back of the page) is opposite to the direction of the magnetic flux Φ4 generated by the high-frequency current flowing through the fourth path RT4 (direction from the back to the front of the page). Therefore, the magnetic fluxes generated in the two paths RT3 and RT4 cancel each other out. Therefore, noise emitted to the outside due to the generation of magnetic flux can be suppressed. As a result, this embodiment achieves the same effects as the second embodiment.

[0232] 5. Modifications, etc. As described above, the semiconductor device (1) according to the embodiment includes a first switching element (13) having a first electrode (DE1) and a second electrode (SE1) provided on a surface (S1), a second switching element (14) having a third electrode (SE2) and a fourth electrode (DE2) provided on a surface (S3), a first capacitor (15) including a first wiring layer (25) connected to the third electrode (SE2), a second wiring layer (26) connected to the first electrode (DE1), and a first dielectric layer (51) arranged between the first wiring layer and the second wiring layer, and a first capacitor (15) including a first switching element (13), a second wiring layer (26) connected to the third electrode (SE2), a second wiring layer (26) connected to the first electrode (DE1), and a first dielectric layer (51) arranged between the first wiring layer and the second wiring layer. The semiconductor device includes a substrate (20) incorporating a second switching element (14) and a first capacitor (15), a third wiring layer (22(T5)) connected to the first wiring layer (25) and receiving a first voltage (VDC-), a fourth wiring layer (21(T4)) connected to the second wiring layer (26) and receiving a second voltage (VDC+) higher than the first voltage (VDC-), and a fifth wiring layer (23(T3)) connected to the second electrode (SE1) and the fourth electrode (DE2) and receiving a third voltage (VSW) in the range of equal to or greater than the first voltage (VDC-) and equal to or less than the second voltage (VDC+). The first capacitor (15) is disposed between the first switching element (13) and the second switching element (14). The third electrode (SE2) is disposed opposite the first electrode (DE1) in the first direction (Z). The fourth electrode (DE2) is disposed opposite the second electrode (SE1) in the first direction (Z) and is connected in series to the second electrode (SE1).

[0233] The embodiment is not limited to the above-described embodiment, and various modifications are possible.

[0234] In this specification, the term "connected" refers to being electrically connected, and does not exclude, for example, the presence of another element therebetween.

[0235] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0236] 1, 1A, 1B, 1C... semiconductor device, 11, 12... driver circuit, 13, 14... switching element, 15... capacitor, 20... substrate, 21 to 30... wiring layer, 41... via, 51... dielectric layer, 61, 62... driver circuit, 63, 64... switching element, 65... capacitor, 71 to 76... wiring layer, 81... dielectric layer, 91, 92... QN-off driver circuit, 93, 94... switching element, 101, 102... QN-off driver circuit, 103, 104... switching element, T1, T2, T6, T7, T10, T11, T12, T13... control terminal, T3, T4, T5, T8, T9... input / output terminal

Claims

1. a first switching element having a first electrode and a second electrode provided on a surface thereof; a second switching element having a third electrode and a fourth electrode provided on a surface thereof; a first capacitor including a first wiring layer connected to the third electrode, a second wiring layer connected to the first electrode, and a first dielectric layer disposed between the first wiring layer and the second wiring layer; a substrate incorporating the first switching element, the second switching element, and the first capacitor; a third wiring layer connected to the first wiring layer and to which a first voltage is applied; a fourth wiring layer connected to the second wiring layer and to which a second voltage higher than the first voltage is applied; a fifth wiring layer connected to the second electrode and the fourth electrode, to which a third voltage in a range equal to or greater than the first voltage and equal to or less than the second voltage is applied; Equipped with the first capacitor is disposed between the first switching element and the second switching element; the third electrode is disposed opposite the first electrode in a first direction; the fourth electrode is disposed opposite the second electrode in the first direction and is connected in series to the second electrode; Semiconductor device.

2. the first electrode and the second electrode are arranged opposite to each other in a second direction intersecting the first direction, the third electrode and the fourth electrode are disposed opposite to each other in the second direction. The semiconductor device according to claim 1.

3. a thickness of the first dielectric layer is thinner than a thickness of the first switching element and thinner than a thickness of the second switching element; The semiconductor device according to claim 1.

4. the first dielectric layer comprises silicon or barium titanate; The semiconductor device according to claim 1.

5. the area of ​​the surface of the second wiring layer is larger than the area of ​​the surface of the first switching element; the area of ​​the surface of the first wiring layer is larger than the area of ​​the surface of the second switching element; The semiconductor device according to claim 1.

6. the second wiring layer protrudes further than the second switching element along a second direction intersecting the first direction, the first wiring layer protrudes in the second direction beyond the first switching element; The semiconductor device according to claim 1.

7. a sixth wiring layer connected to the second wiring layer and the fourth wiring layer; Further provided with a back surface of the first switching element is connected to the sixth wiring layer through at least one first via; a back surface of the second switching element is connected to the third wiring layer through at least one second via; The semiconductor device according to claim 1.

8. a third switching element having a fifth electrode and a sixth electrode provided on a surface thereof; a fourth switching element having a seventh electrode and an eighth electrode provided on a surface thereof; a second capacitor including a seventh wiring layer connected to the seventh electrode, an eighth wiring layer connected to the fifth electrode, and a second dielectric layer disposed between the seventh wiring layer and the eighth wiring layer; a ninth wiring layer connected to the seventh wiring layer and to which the first voltage is applied; a tenth wiring layer connected to the eighth wiring layer and to which the second voltage is applied; Further provided with the third switching element, the fourth switching element, and the second capacitor are built into the substrate; the fifth wiring layer is connected to the sixth electrode and the eighth electrode, the second capacitor is disposed between the third switching element and the fourth switching element; the seventh electrode is disposed opposite the fifth electrode in the first direction; the eighth electrode is disposed opposite the sixth electrode in the first direction and is connected in series to the sixth electrode; The semiconductor device according to claim 1.

9. the surface area of ​​the fifth wiring layer is smaller than the surface area of ​​the third wiring layer; The semiconductor device according to claim 1.

10. The first switching element and the second switching element include at least one of an n-channel MOSFET, a p-channel MOSFET, a GaN transistor, a SiC (silicon carbide) transistor, an IGBT (Insulated Gate Bipolar Transistor), and a JFET. The semiconductor device according to claim 1.

11. a first switching element having a first electrode and a second electrode provided on a surface thereof; a second switching element having a third electrode and a fourth electrode provided on a surface thereof; a third switching element; a fourth switching element; a first capacitor connected to the fourth switching element and including a first wiring layer connected to the third electrode via the fourth switching element, a second wiring layer connected to the first electrode, and a first dielectric layer disposed between the first wiring layer and the second wiring layer; a substrate on which the first switching element, the second switching element, the third switching element, the fourth switching element, and the first capacitor are built; a third wiring layer connected to the first wiring layer and to which a first voltage is applied; a fourth wiring layer connected to the second wiring layer and to which a second voltage higher than the first voltage is applied; a fifth wiring layer connected to the third switching element and the fourth electrode, connected to the second electrode via the third switching element, and to which a third voltage in a range equal to or greater than the first voltage and equal to or less than the second voltage is applied; Equipped with the first capacitor is disposed between the first switching element and the second switching element; the third electrode is disposed opposite the first electrode in a first direction; the fourth electrode is disposed to face the second electrode in the first direction and is connected in series to the third switching element; the third switching element is provided between the second electrode and the fourth electrode, the fourth switching element is provided between the first electrode and the third electrode; Semiconductor device.

12. a fifth switching element having a fifth electrode and a sixth electrode provided on a surface thereof; a sixth switching element having a seventh electrode and an eighth electrode provided on a surface thereof; a seventh switching element; an eighth switching element; a second capacitor connected to the eighth switching element, the second capacitor including a sixth wiring layer connected to the seventh electrode via the eighth switching element, a seventh wiring layer connected to the fifth electrode, and a second dielectric layer disposed between the sixth wiring layer and the seventh wiring layer; an eighth wiring layer connected to the sixth wiring layer and to which the first voltage is applied; a ninth wiring layer connected to the seventh wiring layer and to which the second voltage is applied; Further provided with the fifth switching element, the sixth switching element, the seventh switching element, the eighth switching element, and the second capacitor are built into the substrate, the fifth wiring layer is connected to the seventh switching element and the seventh electrode, and is connected to the sixth electrode via the seventh switching element; the second capacitor is disposed between the fifth switching element and the sixth switching element; the seventh electrode is disposed opposite the fifth electrode in the first direction; the eighth electrode is disposed to face the sixth electrode in the first direction and is connected in series to the seventh switching element; the seventh switching element is provided between the sixth electrode and the eighth electrode, the eighth switching element is provided between the fifth electrode and the seventh electrode; The semiconductor device according to claim 11.

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