Photoelectric conversion device, photoelectric conversion system, mobile object, and apparatus

Abstract

To provide a photoelectric conversion device achieving both wide dynamic range and high-speed AD conversion operation.SOLUTION: A photoelectric conversion device includes an AD conversion part for performing analog to digital conversion for obtaining a digital value corresponding to a pixel signal using a pixel for outputting the pixel signal and a ramp signal whose signal voltage changes at a predetermined voltage change rate with respect to time. The AD conversion part includes: an amplification circuit for controlling the gain for the pixel signal; a gain changeover circuit for changing over the gain; a ramp signal changeover circuit for changing over the voltage change rate of the ramp signal; a comparator circuit for outputting a comparison result signal generated from an amplified pixel signal outputted from the amplification circuit and the ramp signal; and a memory part for storing a plurality of determined values according to the comparison result signal, in which the analog to digital conversion is performed with the voltage change rate of the ramp signal and the gain of the amplification circuit which are selected using a predetermined determination value.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device, a photoelectric conversion system, a mobile object, and an apparatus. [Background technology]

[0002] As performance requirements for photoelectric conversion devices, an expanded dynamic range, high-speed readout, etc. Patent Document 1 discloses a technology for expanding the detection dynamic range by switching pixel signal detection sensitivity based on the result of analog-to-digital conversion (hereinafter referred to as AD conversion) of pixel signals output from pixels, performing AD conversion again, and forming an image. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-68318 Summary of the Invention [Problem to be solved by the invention]

[0004] However, conventional photoelectric conversion devices require a long AD conversion period, making it difficult to achieve high-speed readout.

[0005] An object of the present invention is to provide a photoelectric conversion device that achieves both a wide dynamic range and high-speed AD conversion operation. [Means for solving the problem]

[0006] A first aspect of the present invention provides an AD conversion unit that performs analog-to-digital conversion to obtain a digital value corresponding to a pixel signal using a pixel that outputs a pixel signal and a ramp signal whose signal voltage changes at a predetermined voltage change rate over time, the AD conversion unit including an amplifier circuit that controls an amplification rate of the pixel signal, an amplification rate switching circuit that switches the amplification rate, a ramp signal switching circuit that switches the voltage change rate of the ramp signal, a comparison circuit that outputs a comparison result signal generated from the amplified pixel signal output from the amplifier circuit and the ramp signal, and a memory unit that holds a plurality of determination values ​​corresponding to the comparison result signal, wherein a first signal is generated by comparing the amplified pixel signal with any one first threshold voltage value selected from M-1 (M>1) threshold voltages, and the ramp signal switching circuit determines the first determination value based on the first determination value corresponding to the first signal. a second signal is generated by comparing the amplified pixel signal with one second threshold voltage value selected from N-1 (N>1) threshold voltages generated from the ramp signal; the amplification factor switching circuit is capable of switching the amplification factor of the amplifier circuit among N values ​​based on a second determination value corresponding to the second signal; and the AD conversion unit performs analog-to-digital conversion using the voltage change rate of the ramp signal and the amplification factor of the amplifier circuit, the voltage change rate of the ramp signal being selected using the first determination value and the second determination value from among M×N combinations of switching the voltage change rate of the ramp signal and switching the amplification factor of the amplifier circuit, where the M×N combinations are three or more combinations that are less than M×N.

[0007] A second aspect of the present invention is a photoelectric conversion system comprising the above-described photoelectric conversion device and a signal processing unit that generates an image using a signal output from the photoelectric conversion device.

[0008] A third aspect of the present invention is a moving body including the above-described photoelectric conversion device, characterized in that the moving body further includes a control unit that controls movement of the moving body using a signal output from the photoelectric conversion device. It is a mobile object.

[0009] A fourth aspect of the present invention is an apparatus characterized by having the above-mentioned photoelectric conversion device and at least one of an optical device corresponding to the photoelectric conversion device, a control device that controls the photoelectric conversion device, a processing device that processes signals output from the photoelectric conversion device, a display device that displays information obtained by the photoelectric conversion device, a memory device that stores information obtained by the photoelectric conversion device, and a mechanical device that operates based on information obtained by the photoelectric conversion device. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a photoelectric conversion device that achieves both a wide dynamic range and high-speed AD conversion operation. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram of a photoelectric conversion device according to a first embodiment. [Figure 2] FIG. 2 is a diagram illustrating a circuit operation of a pixel according to the first embodiment. [Figure 3] FIG. 2 is a block diagram of a column circuit according to the first embodiment. [Figure 4] 4 is a timing chart illustrating AD conversion in the first embodiment. [Figure 5] 4 is a flowchart illustrating S conversion sensitivity setting in the first embodiment. [Figure 6] 5A to 5C are diagrams illustrating magnification correction of the signal processing circuit in the first embodiment. [Figure 7] FIG. 4 is a diagram illustrating S signal error correction in the first embodiment. [Figure 8] 5A to 5C are diagrams illustrating a method for outputting correction values ​​in the first embodiment. [Figure 9] 10 is a timing chart illustrating AD conversion in the second embodiment. [Figure 10] 10 is a flowchart illustrating S conversion sensitivity setting in the second embodiment. [Figure 11]10 is a timing chart illustrating AD conversion in the third embodiment. [Figure 12] 10 is a flowchart illustrating S conversion sensitivity setting in the third embodiment. [Figure 13] 10A and 10B are diagrams illustrating magnification correction of a signal processing circuit in the third embodiment. [Figure 14] FIG. 10 is a block diagram of a column circuit according to a fourth embodiment. [Figure 15] 10 is a timing chart illustrating AD conversion in the fourth embodiment. [Figure 16] 10 is a flowchart illustrating S conversion sensitivity setting in the fourth embodiment. [Figure 17] 10A and 10B are diagrams illustrating a correction process of a photoelectric conversion device according to a fourth embodiment. [Figure 18] 10A and 10B are diagrams illustrating a correction process of a photoelectric conversion device according to a fourth embodiment. [Figure 19] 10A and 10B are diagrams illustrating a method for obtaining correction values ​​in the fourth embodiment. [Figure 20] FIG. 10 is a diagram illustrating a photoelectric conversion system according to a fifth embodiment. [Figure 21] FIG. 10 is a diagram illustrating a photoelectric conversion system and a moving object according to a sixth embodiment. [Figure 22] 13A and 13B are diagrams illustrating a range image sensor according to a seventh embodiment. [Figure 23] 13A and 13B are diagrams illustrating an endoscopic surgery system according to an eighth embodiment. [Figure 24] FIG. 13 is a diagram illustrating smart glasses according to a ninth embodiment. [Figure 25] FIG. 19 is a diagram illustrating an electronic device according to a tenth embodiment. [Figure 26] FIG. 20 is a diagram illustrating a device according to an eleventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] An outline of each embodiment will be described below. In the photoelectric conversion device of the present invention, pixel signal detection sensitivity is adjusted based on a selection operation of the column amplifier amplification factor and a selection operation of the ramp signal during a determination period. The first embodiment is an example in which the selection operation of the ramp signal is performed first during the determination period. The second and third embodiments are examples in which the selection operation of the column amplifier amplification factor is performed first during the determination period. The fourth embodiment is an example in which the AD conversion sensitivity is switched in multiple stages by the selection operation, as compared to the other embodiments. The AD conversion sensitivity will be described later.

[0013] Hereinafter, each embodiment will be described with reference to the drawings. First Embodiment A photoelectric conversion device according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 8. First, the configuration of the photoelectric conversion device according to this embodiment will be described. FIG. 1 is a block diagram of the photoelectric conversion device. As shown in FIG. 1, the photoelectric conversion device is provided with a plurality of pixels 101 arranged in a matrix. In an actual photoelectric conversion device, tens of millions of pixels 101 are arranged, but FIG. 1 shows an example in which a portion of these pixels, 16 pixels 101, are arranged in 4 rows and 4 columns. This photoelectric conversion device is a so-called CMOS image sensor.

[0014] Each pixel 101 generates a pixel signal according to the amount of light received through photoelectric conversion. The pixel signal is output to a vertical output line 102. A current source 103 that supplies a current is connected to the vertical output line 102. The pixel signal is input via the vertical output line 102 to a column circuit 104 that is individually provided for each vertical output line 102.

[0015] The column circuit 104 functions as an AD conversion unit that amplifies pixel signals and performs analog-to-digital conversion (hereinafter referred to as AD conversion). In addition to pixel signals, a ramp signal and a count signal used for AD conversion are input to the column circuit 104. The ramp signal is generated by a ramp signal output circuit 105. The ramp signal is a signal voltage whose output voltage changes at a predetermined rate of change over time. In addition, the ramp signal output circuit 105 inputs a plurality of ramp signals with different rates of change to the column circuit 104.

[0016] The count signal is generated by a counter circuit 106. The counter circuit 106 starts counting the number of pulses supplied from a clock pulse supply unit (not shown) in synchronization with a change in the output of the ramp signal. The count signal is a signal indicating the count value measured by the counter circuit 106.

[0017] The column circuits 104 perform AD conversion on the pixel signals in the row direction all at once within the same period. The signals AD converted by the column circuits 104 are sequentially output by a horizontal scanning circuit 107 to the outside of the photoelectric conversion device via a horizontal output line 108 and a signal processing circuit 109.

[0018] The vertical scanning circuit 110 switches pixel rows to be AD converted by the column circuit 104, and repeats the operation of sequentially outputting the AD converted results to the signal processing circuit 109, until all pixels are AD converted.

[0019] A timing generation unit 111 supplies drive signals to the vertical scanning circuit 110, the horizontal scanning circuit 107, the column circuit 104, the ramp signal output circuit 105, and the counter circuit 106. The above is the configuration of the photoelectric conversion device in this embodiment.

[0020] Next, the operation of the pixel 101 will be described with reference to the circuit diagram of the pixel 101 in FIG. The photoelectric conversion unit 201 converts incident light into electric charges. The electric charges generated in the photoelectric conversion unit 201 are transferred to a floating diffusion (hereinafter referred to as FD) 203 via a transfer MOS transistor 202. The FD 203 temporarily holds the transferred electric charges and functions as a charge-voltage converter that converts the held electric charges into a voltage signal.

[0021] When the selection MOS transistor 205 is turned on, the amplification MOS transistor 204 outputs the voltage signal generated in the FD 203 to the vertical output line 102. Thereafter, the reset MOS transistor 206 resets the voltage of the FD 203 and the voltage of the photoelectric conversion unit (photodiode) 201 to the pixel voltage SVDD.

[0022] The transfer MOS transistor 202, the reset MOS transistor 206, and the selection MOS transistor 205 receive a transfer pulse PTX and a reset pulse PTX from the vertical scanning circuit 110, respectively. The pixel is controlled by the select pulse PRES and the select pulse PSEL.

[0023] Next, the column circuit 104 that performs AD conversion will be described. FIG. 3 is a block diagram of the column circuit 104 in this embodiment. The pixel signals are input to a column amplifier 301 via the vertical output line 102. The column amplifier 301 functions as an amplifier circuit and includes an input capacitor C0, an amplifier AMP, feedback capacitors Cf1, Cf2, Cf3, and Cf4, and switches SW1, SW2, SW3, SW4, and SW5.

[0024] The gain of the column amplifier 301 is determined by the ratio of the combined capacitance of active feedback capacitors Cf1, Cf2, Cf3, and Cf4 arranged on the feedback path of the amplifier AMP to the capacitance of the input capacitor C0. A control signal from the gain switching circuit 302 switches the switches SW1, SW2, SW3, and SW4 to change the combined capacitance of the feedback path. The switch SW5 is controlled by a C0 reset pulse PC0R from the timing generator 111. The gain of the column amplifier 301 may be either amplification or attenuation.

[0025] The amplified pixel signal output from the column amplifier 301 after being amplified at a predetermined amplification factor is input to one input terminal of the comparator 303. A ramp signal is input to the other input terminal of the comparator 303 from a ramp signal switching circuit 304. The ramp signal switching circuit 304 selects a ramp signal to be input to the comparator 303 from the multiple ramp signals input from the ramp signal output circuit 105. The comparator 303 functions as a comparison circuit.

[0026] The ramp signal output circuit 105 inputs ramp signals VRAMP_H, VRAMP_L, and VRAMP_J to the ramp signal switching circuit 304. In this embodiment, the ramp signal VRAMP_L is a signal whose voltage change rate is 1 / 4 of that of the ramp signal VRAMP_H (the AD conversion sensitivity during AD conversion is four times higher). The ramp signal VRAMP_J is a signal used during a determination period, which will be described later.

[0027] In this way, the comparator 303 compares the amplified pixel signal input from the column amplifier 301 with the ramp signal supplied from the ramp signal switching circuit 304, and outputs a comparison result signal. When the ramp signal is smaller than the amplified pixel signal, the comparator 303 outputs a low level comparison result signal, and when the magnitude relationship is reversed, it outputs a high level comparison result signal. The comparison result signal is output to an output node. To this node, an N memory 305A, an S memory 305B, a judgment value memory 305C, and a selection circuit 306 are connected.

[0028] Next, the N memory 305A, the S memory 305B, and the judgment value memory 305C will be described. The count signal CNT from the counter circuit 106 is connected to the N memory 305A and the S memory 305B. The N memory 305A and the S memory 305B hold the value of the count signal CNT at the time when the polarity of the comparison result signal changes during their respective operation periods. The value held by the N memory 305A is the N signal, and the signal held by the S memory 305B is the S signal. The judgment value memory 305C holds a judgment value that is the judgment result of the comparator 303.

[0029] The selection circuit 306 outputs control signals to the amplification factor switching circuit 302 and the ramp signal switching circuit 304 based on the judgment value held in the judgment value memory 305C. The amplification factor switching circuit 302 switches the amplification factor of the column amplifier 301 based on the control signal. Furthermore, the ramp signal switching circuit 304 switches the ramp signal to be input to the comparator 303 based on the control signal. The S signal, N signal, and judgment value are output to the signal processing circuit 109 via the horizontal output line 108 by control signals from the horizontal scanning circuit 107. This concludes the description of the operation of the column circuit 104.

[0030] Next, a method for acquiring an N signal, a judgment value, and an S signal by AD conversion will be described. FIG. 4 is a timing chart illustrating AD conversion. The period from time t400 to time t406 is an N signal acquisition period. At time t400, the vertical scanning circuit 110 sets the selection pulse PSEL to a high level to select the pixel 101 that is to output a pixel signal PIXOUT. At the same time, the reset pulse PRES is at a high level, and the voltage of the FD 203 is reset.

[0031] At time t401, the vertical scanning circuit 110 sets the reset pulse PRES to low level. At this time, the pixel signal PIXOUT output to the vertical output line 102 is set as a pixel reference signal. The pixel reference signal is a signal that includes noise components possessed by the pixel 101.

[0032] At time t402, the horizontal scanning circuit 107 sets the C0 reset pulse PC0R to low level, releasing the reset state of the amplifier AMP and input capacitor C0 of the column amplifier 301. A charge based on the voltage of the pixel reference signal when the C0 reset pulse PC0R is set to low level is held in the input capacitor C0, and the column amplifier 301 outputs the amplified pixel signal AMPOUT.

[0033] Here, a supplementary explanation will be given regarding the amplification factor of the column amplifier 301 in this embodiment. As described above, the amplification factor of the column amplifier 301 is determined by the ratio of the combined capacitance of the feedback path of the amplifier AMP to the input capacitance. In this embodiment, the capacitance values ​​of the feedback capacitances Cf1, Cf2, Cf3, and Cf4 are 1 / 8, 1 / 8, 1 / 4, and 1 / 2 times the capacitance value of the input capacitance C0, respectively. When only the feedback capacitances Cf1 and Cf2 are used, the amplification factor of the column amplifier 301 is 1 / (1 / 8+1 / 8)=4, which is defined as the first amplification factor. When all of the feedback capacitances Cf1, Cf2, Cf3, and Cf4 are used, the amplification factor of the column amplifier 301 is 1 / (1 / 8+1 / 8+1 / 4+1 / 2)=1, which is defined as the second amplification factor.

[0034] At time t402, the switches SW3 and SW4 are turned off, and the feedback capacitors Cf1 and Cf2 are used, so that the amplification factor of the column amplifier 301 becomes four times, which is the first amplification factor.

[0035] At time t403, the horizontal scanning circuit 107 sets the comparator reset pulse COMPRES to high level for a predetermined period of time, thereby initializing the comparator 303.

[0036] During the period from time t404 to time t406, AD conversion of the pixel reference signal is performed. A signal obtained from the pixel reference signal is output as an amplified image signal from the column amplifier 301. At this time, the ramp signal switching circuit 304 inputs a ramp signal VRAMP_L to the comparator 303. In addition, in synchronization with the output change of the ramp signal VRAMP_L, the counter circuit 106 starts counting.

[0037] At time t405, when the ramp signal VRAMP_L exceeds the amplified pixel signal AMPOUT, the signal polarity of the comparison result signal COMPOUT changes. At time t405, the N memory 305A holds the count value indicated by the count signal CNT input to the N memory 305A as the N signal.

[0038] After time t406, the ramp signal VRAMP and the count signal CNT are reset and initialized.

[0039] The period from time t407 to time t414 is a determination period and is a period for acquiring a determination value. In this embodiment, the determination value is 2-bit information. First, a first determination value J1 is acquired during the period from time t407 to time t411.

[0040] From time t407 to time t408, the transfer pulse PTX is set to the high level. Photoelectric The charge photoelectrically converted upon entering the photoelectric conversion unit 201 is transferred to the FD203 and output as the pixel signal PIXOUT. The pixel signal PIXOUT at this time is used as the pixel output signal. The pixel output signal passes through the vertical output line 102 and the column amplifier 301 of the column circuit 104 and becomes an amplified pixel signal and is input to the comparator 303. At this time, the amplified pixel signal from the column amplifier 301 is an output obtained by inverting and amplifying the voltage difference between the pixel reference signal and the pixel output signal.

[0041] At time t409, the lamp signal switching circuit 304 inputs the lamp signal VRAMP_J to the comparator 303. The lamp signal VRAMP_J performs an operation of increasing the voltage value during the period from time t409 to time t410 and holding the voltage value for a certain period from time t410 to time t411. At this time, the voltage value of the lamp signal VRAMP_J held between time t410 and time t411 is set as the first threshold voltage value VREF1, and the same period is set as the determination period 1.

[0042] During the determination period 1, the comparator 303 compares the first threshold voltage value VREF1 with the amplified pixel signal AMPOUT and outputs a comparison result signal. The comparison result signal at this time is used as the first comparison result signal and serves as the first determination value J1. When the amplified pixel signal AMPOUT is lower than the first threshold voltage value VREF1 (AMPOUT < VREF1), the comparator output COMPOUT changes in polarity from the low level to the high level. Therefore, the first determination value J1 becomes "1".

[0043] On the one hand, when the voltage value of the amplified pixel signal AMPOUT is greater than or equal to the first threshold voltage value VREF1 (AMPOUT ≥ VREF1), the comparator output COMPOUT maintains a low level. At this time, the first determination value J1 becomes "0".

[0044] The first determination value J1 is input to and held in the first bit of the determination value memory 305C. After time t411, the ramp signal VRAMP is reset. In the case of FIG. 4, since the amplified pixel signal AMPOUT is greater than the first threshold voltage value VREF1, the first determination value J1 becomes "0", and "0" is held in the first bit of the determination value memory 305C.

[0045] During the period from time t412 to time t414, the second determination value J2 is obtained. At time t412, the ramp signal switching circuit 304 inputs the ramp signal VRAMP_J to the comparator 303 again. The ramp signal VRAMP_J increases the voltage value during the period from time t_{412} to time t_{413} and holds the voltage value when the increase stops for a certain period. The voltage value of the ramp signal VRAMP_J from time t413 to time t414 is set as the second threshold voltage value VREF2, and this period is set as determination period 2.

[0046] During determination period 2, the comparator 303 compares the second threshold voltage value VREF2 with the amplified pixel signal AMPOUT and outputs a comparison result signal. The comparison result signal at this time is used as the second comparison result signal and becomes the second determination value J2. When the amplified pixel signal AMPOUT is lower than the second threshold voltage value VREF2 (AMPOUT < VREF2), the comparator output COMPOUT changes its polarity from a low level to a high level. At this time, the second determination value J2 becomes "1".

[0047] On the other hand, when the amplified pixel signal AMPOUT is higher than the second threshold voltage value VREF2 (AMPOUT≧VREF2), the comparator output COMPOUT remains low. At this time, the second decision value J2 becomes “0.” The second decision value J2 is stored in the second bit of the decision value memory 305C. After time t414, the ramp signal VRAMP is reset. In the case of FIG. 4, since the amplified pixel signal AMPOUT is higher than the second threshold voltage value VREF2, the first decision value J1 becomes “0,” and “0” is stored in the second bit of the decision value memory 305C.

[0048] The period from time t414 to time t417 is an S signal acquisition period. During the period from time t414 to time t415, the selection circuit 306 sends a control signal to the gain switching circuit 302 based on the second determination value J2. During this period, the gain switching circuit 302 switches the switches SW1, SW2, SW3, and SW4 of the column amplifier 301 based on the control signal.

[0049] 4, the selection circuit 306 has a second determination value J2 of "0," and sends a control signal to the amplification factor switching circuit 302 to change the amplification factor of the column amplifier 301 from 4 times (first amplification factor) to 1 time (second amplification factor). The amplification factor switching circuit 302 turns on the switches SW3 and SW4 based on the control signal. The amplification factor of the column amplifier 301 changes from 4 times to 1 time, and the signal level of the amplified pixel signal AMPOUT decreases.

[0050] On the other hand, if the second judgment value held in the judgment value memory 305C is "1", the selection circuit 306 does not output a control signal to the column amplifier 301 for the amplification factor switching circuit 302. Subsequently, during the same period, the selection circuit 306 sends a control signal to the ramp signal switching circuit 304 based on the first judgment value J1 held in the judgment value memory 305C. Based on the control signal, the ramp signal switching circuit 304 selects a ramp signal to be input to the comparator 303 at time t415.

[0051] 4, the first judgment value J1 held in the judgment value memory 305C is "0." Therefore, the selection circuit 306 transmits a control signal to the ramp signal switching circuit 304 so that the ramp signal VRAMP_H is input to the comparator 303. On the other hand, when the first judgment value J1 held in the judgment value memory 305C is "1," the selection circuit 306 inputs the ramp signal VRAMP_L to the comparator 303.

[0052] At time t415, the ramp signal starts to change in output at a constant rate. The counter circuit 106 synchronizes with the change in output of the ramp signal and starts counting the clock pulse signal.

[0053] In this embodiment, at time t415, the ramp signal VRAMP_H is input to the comparator 303. At time t416, when the voltage of the ramp signal VRAMP_H exceeds the amplified pixel signal AMPOUT, the signal polarity of the comparison result signal COMPOUT output by the comparator 303 changes. The S memory 305B holds the value of the count signal CNT at time t416 as an S signal.

[0054] After time t417, the ramp signal VRAMP and count signal CNT are reset and initialized. In the case of Figure 4, when the pixel captures a high-brightness object and the output of the amplified pixel signal AMPOUT is large, the amplification factor of the column amplifier 301 and the voltage change rate of the ramp signal are switched to reduce the S conversion sensitivity, which is defined by the integrated value, enabling appropriate AD conversion.

[0055] On the other hand, in contrast to this embodiment, if the output of the amplified pixel signal is too small, the amplification factor of the column amplifier 301 can be increased, the voltage change rate of the ramp signal can be reduced, and the S conversion sensitivity can be increased, thereby enabling high-resolution signal detection even under weak light conditions, thereby achieving a wide detection dynamic range.

[0056] Here, a supplementary explanation will be given regarding AD conversion sensitivity. In this embodiment, during the AD conversion period of the S signal from time t415 to time t417, the voltage change rate of the ramp signal VRAMP_H is four times that of the ramp signal VRAMP_L. As described above, the AD conversion value is the value of the count signal CNT output by the counter circuit 106 at the time when the magnitude relationship between the ramp signal and the amplified pixel signal is inverted. The earlier the magnitude relationship between the ramp signal and the amplified pixel signal is inverted, the smaller the value of the count signal CNT, and the smaller the AD conversion value.

[0057] As shown in the period from time t415 to time t417 in Figure 4, the ramp signal VRAMP_H, which has a large voltage change rate, reverses the above-mentioned magnitude relationship more quickly than the ramp signal VRAMP_L, which has a small voltage change rate. In other words, the ramp signal VRAMP_H obtains a small value as the AD converted value, so its AD conversion sensitivity is low. On the other hand, the ramp signal VRAML_L, which has a small voltage change rate, reverses the above-mentioned magnitude relationship more slowly and obtains a large value as the AD converted value, so its AD conversion sensitivity is high. The ratio of the voltage change rates of the ramp signals produces a difference in the counter values ​​that is its reciprocal.

[0058] Here, we will provide additional information on the relationship between the first threshold voltage value VREF1 and the second threshold voltage value VREF2 in this embodiment. If the amplified pixel signal input to the comparator 303 is always greater than the ramp signal during the S signal acquisition period, the polarity of the comparison signal COMPOUT will not be inverted, and a correct count signal CNT will not be obtained. Therefore, during the S signal acquisition period, there must always be an inversion period in which the amplified pixel signal is smaller than the ramp signal.

[0059] The first threshold voltage value VREF1 is a threshold voltage for switching the ramp signal input to the comparator 303 when acquiring the S signal. If the first threshold voltage value VREF1 is smaller than the ramp signal VRAMP_L at time t417, an inversion period occurs when acquiring the S signal using the ramp signal VRAMP_L. Therefore, it is desirable to set the first threshold voltage value VREF1 to be equal to or lower than the signal level of VRAMP_L at time t417, as shown in the following (Equation 1). VREF1 ≤ VRAMP_L(t417) (Equation - 1) When the amplified pixel signal is greater than VREF1, it switches to the ramp signal VRAMP_H during S signal acquisition.

[0060] The second threshold voltage value VREF2 is a threshold voltage for switching the amplification factor of the column amplifier 301 during S signal acquisition. When the amplified pixel signal is greater than the ramp signal VRAMP_H at time t417, the second threshold voltage value VREF2 serves as a reference signal to reduce the amplification factor of the column amplifier 301 so that an inversion period occurs. Therefore, it is desirable to set the second threshold voltage value VREF2 to be equal to or less than the ramp signal VRAMP_H at time t417 as shown in the following (Equation - 2). VREF2 ≤ VRAMP_H(t417) (Equation - 2)

[0061] Also, from the ratio of the voltage change rates of the ramp signal VRAMP_L and the ramp signal VRAMP_H, the following Equation - 3 is obtained. VREF1 < VREF2 (Equation - 3) Here, the maximum threshold voltage value included in the first threshold voltage value is smaller than the minimum threshold voltage value included in the second threshold voltage value. The reason for excluding the equal sign in the relationship between the first threshold voltage value VREF1 and the second threshold voltage value VREF2 is for the purpose of S signal correction, which will be described later.

[0062] Next, in this embodiment, the amplification factor of the column amplifier 301 during S signal acquisition and the method of selecting the ramp signal input to the comparator 303 according to the signal level of the amplified pixel signal AMPOUT input to the comparator 303 during the determination period will be described.

[0063] FIG. 5 is a flowchart for explaining the amplification factor of the column amplifier 301 and the selection of the ramp signal input to the comparator 303 when the S signal of the photoelectric conversion device according to the present embodiment is acquired. There are three patterns of combinations of the amplification factor of the column amplifier 301 and the ramp signal input to the comparator 303 in the present embodiment, namely, "Setting A", "Setting B", and "Setting C", which will be described respectively. First, the amplification factor of the column amplifier 301 is set to 4 times, which is the first amplification factor. Also, a ramp signal VRAMP_L is input from the ramp signal switching circuit 304 to the comparator 303. . Under this condition, the N signal is acquired. The above is common to each setting.

[0064] Hereinafter, each setting will be described respectively. First, "Setting A" will be described. "Setting A" shows an example in which the signal level of the amplified pixel signal AMPOUT is low and the pixel is irradiated with low-intensity light. In determination period 1, the amplified pixel signal AMPOUT is compared with the first threshold voltage value VREF1. In "Setting A", AMPOUT < VREF1, and the first determination value J1 becomes "1". "1" is held in the first bit of the determination value memory 305C.

[0065] In determination period 2, the amplified pixel signal AMPOUT is compared with the second threshold voltage value VREF2. Since VREF1 < VREF2, AMPOUT < VREF2. Therefore, the second determination value J2 becomes "1", and "1" is held in the second bit of the determination value memory 305C.

[0066] The amplification factor of the column amplifier is maintained at four times the second amplification factor. At time t415, based on the first determination value J1 = 1 held in the determination value memory 305C, the selection circuit 306 sends a control signal to the lamp signal switching circuit 304. The lamp signal switching circuit 304 inputs the lamp signal VRAMP_L to the comparator 303, and the AD conversion sensitivity becomes four times. Thus, in "Setting A", the amplification factor of the column amplifier 301 is four times the first amplification factor, and the lamp signal VRAMP_L with an AD conversion sensitivity also four times is input to the comparator 303. At this time, the S signal is acquired in a state where the S conversion sensitivity defined by the integrated value of the aforementioned column amplifier 301 amplification factor and the AD conversion sensitivity due to the voltage change rate of the lamp signal is 4×4 = 16 times.

[0067] Next, "Setting B" will be described. "Setting B" shows an example where the signal level of the amplified pixel signal AMPOUT is medium and the pixel is irradiated with medium-intensity light. In determination period 1, the amplified pixel signal AMPOUT and the first threshold voltage value VREF1 are compared. In "Setting B", AMPOUT≥VREF1, and J1 of the first determination value becomes "0". In the first bit of the determination value memory 305C, "0" is held.

[0068] Next, in determination period 2, the amplified pixel signal AMPOUT and the second threshold voltage value VREF2 are compared. In "Setting B", AMPOUT < VREF2, and the second determination value J2 becomes "1". "1" is held in the second bit of the determination value memory 305C. Together, the amplification factor of the column amplifier switches to the second amplification factor and becomes from four times to one time. At time t415, based on the first determination value J1 = 0 held in the determination value memory 305C, the selection circuit 306 sends a control signal to the lamp signal switching circuit 304.

[0069] The lamp signal switching circuit 304 inputs the lamp signal VRAMP_H to the comparator 303, and the AD conversion sensitivity becomes one time. Thus, in "Setting B", the amplification factor of the column amplifier 301 is four times the first amplification factor, and the lamp signal VRAMP_L with an AD conversion sensitivity of one time is input to the comparator 303. At this time, the S signal is acquired with an S conversion sensitivity of 4×1 = 4 times.

[0070] Finally, we will explain "Setting C." "Setting C" shows an example in which the signal level of the amplified pixel signal AMPOUT is high and the pixel is illuminated with high-intensity light. During decision period 1, the amplified pixel signal AMPOUT, which includes an image signal, is compared with the first threshold voltage value VREF1. In "Setting C," AMPOUT≧VREF1, and the first decision value J1 becomes "0." A "0" is held in the first bit of decision value memory 305C.

[0071] Next, in the determination period 2, the amplified pixel signal AMPOUT including the image signal is compared with the second threshold voltage value VREF2. In "setting C", AMPOUT≧VREF2, and the second determination value J2 becomes "0". "0" is held in the second bit of the determination value memory 305C. At the same time, the gain of the column amplifier is switched to a second gain, changing from 4x to 1x. At time t415, based on the first judgment value "0" stored in the judgment value memory 305C, the selection circuit 306 sends a control signal to the ramp signal switching circuit 304. The ramp signal switching circuit 304 inputs the ramp signal VRAMP_H to the comparator 303, and the AD conversion sensitivity becomes 1x. Thus, in "setting C," the ramp signal VRAMP_L, which makes the AD conversion sensitivity 1x, is input to the comparator 303 at the first gain, which makes the gain of the column amplifier 301 1x. At this time, the S signal is acquired with an S conversion sensitivity of 1x (1x = 1x).

[0072] As described above, the S conversion sensitivity can be switched between 16 times, 4 times, and 1 time based on the result of determining the amplified image signal AMPOUT from the column amplifier 301 during the determination period, and an S signal value can be obtained.

[0073] The column amplifier gain can be set to two values, 4x and 1x, and the ramp signal AD conversion sensitivity can also be set to two values, 4x and 1x. This results in 2 x 2 = 4 possible combinations. In this embodiment, S signal conversion is performed using three of the four settings. By doing so, when switching from "Setting A" to "Setting B" or from "Setting B" to "Setting C," only one of the gain of the column amplifier 301 and the voltage change rate of the ramp signal is changed. Note that while an example of 2 x 2 = 4 possible combinations is shown here, this embodiment is not limited to this. For example, if N gains are selectable and M AD conversion sensitivities of the ramp signal are settable, there are M x N possible combinations of AD conversion sensitivity and gain of the column amplifier. In this case, S signal conversion is performed using less than M x N possible combinations. In this case, the first threshold voltage value is composed of M-1 (M > 1) threshold voltages, and the second threshold voltage value is composed of N-1 (N > 1) threshold voltages.

[0074] When the settings are switched, a correction process (described later) is required for the S signal. However, if only one of the settings is changed, correction errors due to the complicated correction process can be prevented, and good signal characteristics can be obtained. Furthermore, as shown in (Equation 3), the relationship between the first threshold voltage value VREF1 and the second threshold voltage value VREF2 must be such that VREF1≠VREF2. If these are equal, then when the pattern is switched, the gain of the column amplifier 301 and the ramp signal are switched simultaneously.

[0075] Next, the magnification correction process for the S signal in the signal processing circuit 109 in this embodiment will be described with reference to FIG. The horizontal axis represents the signal level (in voltage V) of the pixel signal PIXOUT that correlates with the amount of light incident on the pixel 101. The vertical axis represents the output value (in LSB) corrected by the signal processing circuit 109.

[0076] First, using FIG. 6(a), we will explain the difference in the correction magnification of the S signal due to the difference in the second judgment value J2 stored in the judgment value memory 305C when the S signal was acquired. The pixel signal PIXOUT changes in amplitude up to a maximum voltage value VA2 [V] depending on the amount of light incident on the pixel 101. When the gain of the column amplifier 301 is 4x, the AD-converted value DA1 [LSB] is obtained when the pixel signal PIXOUT is at a voltage value VA1 [V] that is 1 / 4 of the voltage value VA2 [V]. When the gain of the column amplifier 301 is 1x, the AD-converted value DA1 [LSB] is also obtained when the pixel signal PIXOUT is at a voltage value VA2 [V].

[0077] The signal processing circuit 109 is sent an N signal, an S signal, and a judgment value, and it is possible to detect from the judgment value which setting, A / B / C, the S signal obtained by AD conversion was obtained from. In other words, the magnification correction of the S signal is performed based on the judgment value. The amplification factor of the column amplifier 301 when the S signal is obtained is stored as a second judgment value J2 in the judgment value memory 305C. When the second judgment value J2 is J2=0, the S signal input to the signal processing circuit 109 is not corrected. On the other hand, If the judgment value J2 of step 2 is J2=1, the S signal is multiplied by four through the magnification correction process.

[0078] Furthermore, the voltage value VA1 [V] is a voltage value that is a boundary for switching the amplification factor of the column amplifier 301 when the S signal is acquired. When converted into the pixel signal AMPOUT amplified by the column amplifier 301 at the first amplification factor (×4), the voltage value VA1 [V] corresponds to the second threshold voltage value VREF2. When the pixel signal PIXOUT is in the range (bold line) from the voltage value 0 [V] to the voltage value VA1 [V], the amplification factor of the column amplifier 301 when the S signal is acquired is the first amplification factor (×4). At this time, the S signal is not subjected to magnification correction processing by the signal processing circuit 109.

[0079] On the other hand, when the pixel signal PIXOUT is in the range from voltage value VA1 [V] to voltage value VA2 [V] (dash-dotted line), the amplification factor of the column amplifier 301 when acquiring the S signal is a second amplification factor (×1). At this time, the S signal undergoes magnification correction processing in the signal processing circuit, where its value is multiplied by four (thick dash-dotted line). The output resolution of the magnification-corrected S signal becomes coarser by the correction magnification factor, but the output bits are expanded. In this way, the signal processing circuit 109 corrects the S signal, providing high resolution at low luminance and reducing the resolution at high luminance to widen the light detection range, thereby expanding the dynamic range.

[0080] Next, the correction magnification factor that takes into account the difference in the voltage change rate of the ramp signal in addition to the difference in the amplification factor of the column amplifier 301 when acquiring the S signal will be described with reference to FIG. 6(b).

[0081] In this embodiment, the column amplifier 301 shown in FIG. 6A performs AD conversion with an amplification factor of 4. The voltage ranges from 0 [V] to VA1 [V], and the voltage range is 1 / 4 of that, VR1 [V]. V], the ramp signal VRAMP_L is input to the comparator 303. The comparator 303 receives the ramp signal VRAMP_H.

[0082] When the pixel signal PIXOUT has a voltage value VR1 [V] and the condition of setting A is set, an AD-converted value DR1 [LSB] is obtained. The AD-converted value DR1 [LSB] is the maximum value of the count value counted by the counter circuit 106 during the period from time t415 to time t417. On the other hand, when the pixel signal PIXOUT has a voltage value VA1 [V] that is four times the voltage value VR1 [V] and the condition of setting B is set, an AD-converted value DR1 [LSB] is also obtained. When the pixel signal PIXOUT has a voltage value VA2 [V] that is 4 × 4 = 16 times the voltage value VR1 [V] and the condition of setting C is set, an AD-converted value DR1 [LSB] is also obtained. The AD-converted values, which are S signals obtained under these different settings, are subjected to magnification correction based on the first judgment value J1 and the second judgment value J2 stored in the judgment value memory 305C.

[0083] When the first judgment value J1 and the second judgment value J2 stored in the judgment value memory 305C are J1="1" and J2="1", respectively, the S signal is not corrected. This applies to the pixel signal PIXOUT voltage range from 0 [V] to VR1 [V] (bold line). When the first judgment value J1 and the second judgment value J2 stored in the judgment value memory 305C are J1="0" and J2="1", respectively, the S signal is subjected to a four-fold magnification correction. This applies to the pixel signal PIXOUT voltage range from VR1 [V] to VA1 [V], and the uncorrected S signal (dash-dotted line) is magnified and becomes a four-fold S signal (bold dash-dotted line). Here, the pixel signal PIXOUT switches between "Setting A" and "Setting B" at the voltage value VR1 [V].

[0084] The voltage value VR1 [V] corresponds to the first threshold voltage value VREF1 when converted to the amplified pixel signal AMPOUT at the first amplification factor. Furthermore, the pixel signal PIXOUT switches between "Setting B" and "Setting C" at the voltage value VA1 [V]. The pixel signal PIXOUT output at the voltage value VA1 [V] corresponds to the second threshold voltage value VREF2 when converted to the amplified pixel signal AMPOUT at the first amplification factor. When the first and second judgment values ​​J1 and J2 stored in the judgment value memory 305C are J1="0" and J2="0", respectively, the S signal is subjected to a 16-fold magnification correction. The pixel signal PIXOUT falls within the range from the voltage value VA1 [V] to the voltage value VA2 [V], and the S signal before correction (two-dot chain line) is converted to the S signal multiplied by 16 (thick two-dot chain line). This becomes:

[0085] In this way, the combination of the gain of the column amplifier 301 when acquiring the S signal and the ramp signal is subjected to magnification correction processing based on the judgment value. This makes it possible to achieve both a dynamic range exceeding the number of output bits that can be acquired as an S signal and high resolution at low brightness with a single AD conversion. However, in reality, errors in the ratio of the gain of the column amplifier 301 that can be set and errors in the ratio of the voltage change rate between the selected ramp signals can occur. These ratio errors can cause offsets in the digital signal at the boundary points where the above-mentioned settings are switched. Furthermore, if there is a difference in the linearity of the signals output between "Setting A," "Setting B," and "Setting C," offsets can also occur at the boundary points.

[0086] An error correction processing method for reducing such offset and linearity errors will be described below. FIG. 7 is a diagram illustrating S signal error correction in this embodiment. In the error correction processing, a correction value used in the error correction processing is obtained by a dedicated correction value acquisition operation. In the correction value acquisition operation, the signals input to the column circuit 104 are not pixel signals from the pixels, but correction operation input values ​​V1, V2, and V3 from a reference voltage source (not shown) connected to the vertical output line 102. The correction values ​​are obtained by AD converting the correction operation input values ​​in each of the settings "Setting A," "Setting B," and "Setting C" used during the S signal acquisition period.

[0087] The correction value obtained by inputting the correction operation input value V1 to the column circuit 104 will be described below. AD conversion is performed using "setting A", and the obtained value will be referred to as correction value D1. AD conversion is performed using "setting B", and the obtained value will be referred to as correction value D3. AD conversion is performed using "setting C", and the obtained value will be referred to as correction value D6. Next, the correction value obtained by inputting the correction operation input value V2 to the column circuit 104 will be described below.

[0088] AD conversion is performed with "setting A", and the obtained value is set as correction value D2. AD conversion is performed with "setting B", and the obtained value is set as correction value D4. Next, the correction value obtained by inputting the correction operation input value V3 to the column circuit 104 will be explained. AD conversion is performed with "setting B", and the obtained value is set as correction value D5. AD conversion is performed with "setting C", and the obtained value is set as correction value D7.

[0089] The following describes a method for calculating the ratio error of the amplification factor of the column amplifier 301 and the ratio error of the voltage change rate of the ramp signal using the obtained correction values. First, the ratio error of the voltage change rate of the ramp signal is obtained from the ratio of the slope (or difference value) of each line obtained by connecting the correction value D2 and the correction value D1 obtained in "Setting A" and the correction value D4 and the correction value D3 obtained in "Setting B". This is called the linearity correction value α1. α1=(D2-D1) / (D4-D3) / 4 (Equation 4)

[0090] The linearity correction value α1 is multiplied by the S signal obtained with "Setting B," and the linearity of the S signal obtained with "Setting B" is corrected to match the linearity of the signal obtained with "Setting A." In other words, the linearity standard is the linearity of the signal obtained with "Setting A." Similarly, the ratio error of the amplification factor of the column amplifier 301 is obtained from the ratio of the slopes (or difference values) of the lines obtained by connecting the correction value D5 and correction value D3 obtained with "Setting B," and the correction value D7 and correction value D6 obtained with "Setting C." This is called the linearity correction value α2. α2=(D5-D3) / (D7-D6) / 4 (Equation 5)

[0091] The linearity correction value α2 corrects the linearity of the S signal obtained with "Setting C" to match the linearity of the S signal obtained with "Setting B." However, the S signal obtained with "Setting B" is multiplied by the linearity correction value α1 to match the linearity of "Setting A." Therefore, the signal obtained with "Setting C" is corrected by multiplying it by α1 in addition to α2. As a result, the linearity of the signal obtained with "Setting C" is corrected to match the linearity of the signal obtained with "Setting A."

[0092] Next, a method for calculating the amount of offset between patterns that may occur at a boundary point where the setting is switched, and an output value output from the signal processing circuit 109 after correcting the linearity and offset will be described.

[0093] First, we will explain how to calculate the offset correction value β1 that occurs when switching from "Setting A" to "Setting B." The correction value D4 obtained with "Setting B" in the correction value acquisition operation becomes the corrected output 4×α1×D4 through magnification correction and linearity correction. If this corrected output is equal to the correction value D2, no offset occurs. In other words, the difference between D2 and 4×α1×D4 is the offset correction value β1. β1=D2-4×α1×D4 (Formula-6) Therefore, the S signal obtained by "setting B" is corrected by the signal processing circuit 109 and output as a signal SB as follows: SB=4×α1×S+β1-N (Equation 7) N is the N signal.

[0094] Next, we will explain how to calculate the offset correction value β2 that occurs when switching from "Setting B" to "Setting C." The correction value D7 obtained with "Setting C" in the correction value acquisition operation becomes the corrected output 16×α1×α2×D7 through magnification correction and linearity correction. If this corrected output is equal to the corrected output 4×α1×D5 obtained by applying magnification correction and linearity correction to correction value D5, no offset occurs. In other words, the difference between the corrected outputs becomes the offset correction value β2. β2=4×α1×D5-16×α1×α2×D7 (Formula-8) Therefore, the signal S obtained by "setting C" is corrected by the signal processing circuit 109, and the signal SC outputted is obtained by subtracting the N signal as follows: SC=16×α1×α2×S+β2-N (Formula-9)

[0095] The S signal obtained under "setting A" is not subjected to correction processing in the signal processing circuit 109, and the output from the signal processing circuit 109 is as follows: SA=SN (Equation 10)

[0096] In this way, by correcting the S signal using the linearity correction values ​​α1 and α2 and the offset correction values ​​β1 and β2 obtained through the correction operation, a signal exhibiting good linearity characteristics relative to the amount of incident light can be obtained. In this embodiment, the relationship between the first threshold voltage value VREF1 and the second threshold voltage value VREF2 is defined by (Equation 3), so that when switching settings, only one of the voltage change rate of the ramp signal or the amplification factor of the column amplifier is changed. This simplifies the correction and reduces the occurrence of correction errors due to the complexity of the correction process. Here, it is desirable that the correction operation input values ​​V2 and V3 be the same value as the pixel signal PIXOUT when the pattern is switched. When the output characteristics include nonlinearity, offset errors can be reduced.

[0097] Next, a method for obtaining correction values ​​during imaging operation will be described. FIG. 8 is a diagram illustrating a method for outputting correction values ​​in a photoelectric conversion device according to this embodiment. Here, the time required to read out one row of pixels 101 arranged in a matrix is ​​defined as 1H. FIG. 8 shows the settings of the correction operation input value, the voltage change rate of the ramp signal, and the amplification factor of the column amplifier input to the column circuit 104 in chronological order in 1H units. Using a readout time of eight rows (1H to 8H), the correction operation input value, the amplification factor of the column amplifier, and the voltage change rate of the ramp signal are sequentially switched to output correction values ​​D1, D2, D3, D4, D5, D6, and D7 for each row. This operation may be performed using rows of pixels that are not photosensitive and are not used for imaging, such as optical black rows.

[0098] In the correction value acquisition operation, the correction value D1 is acquired from time 0 to time 1H. During this period, the correction operation input value V1 is input, and the column circuit 104 performs AD conversion with "setting A." The S signal of the row output during this period becomes the correction value D1.

[0099] During the period from time 1H to time 2H, the correction value D3 is acquired. During this period, the correction operation input value V1 is input, and the column circuit 104 performs AD conversion with "setting B." The S signal of the row output during this period becomes the correction value D3.

[0100] During the period from time 2H to time 3H, the correction value D2 is acquired. During this period, the correction operation input value V2 is input, and the column circuit 104 performs AD conversion with "setting A." The S signal of the row output during this period becomes the correction value D2.

[0101] During the period from time 3H to time 4H, the correction value D4 is acquired. During this period, the correction operation input value V2 is input, and the column circuit 104 performs AD conversion using "setting B." The S signal of the row output during this period becomes the correction value D4.

[0102] The period from time 4H to time 5H is the same as the period from time 1H to time 2H, and correction value D3 is output. Measurement is performed taking into consideration symmetry in the time series.

[0103] During the period from time 5H to time 6H, the correction value D6 is acquired. During this period, the correction operation input value V1 is input, and the column circuit 104 performs AD conversion with "setting C." The S signal of the row output during this period becomes the correction value D6.

[0104] During the period from time 6H to time 7H, the correction value D5 is acquired. During this period, the correction operation input value V3 is input, and the column circuit 104 performs AD conversion with "setting B." The S signal of the row output during this period becomes the correction value D5.

[0105] During the period from time 7H to time 8H, a correction value D7 is acquired. During this period, a correction operation input value V3 is input, and the column circuit 104 performs AD conversion with "setting C." The S signal of the row output during this period becomes the correction value D7. The correction values ​​D1, D2, D3, D4, D5, D6, and D7 thus obtained over 8H are input to the signal processing circuit 109 and used for correction processing.

[0106] As described above, by setting the first threshold voltage for determining the voltage change rate of the ramp signal lower than the second threshold voltage for determining the amplification factor of the column amplifier, a wider dynamic range and faster speed can be achieved by performing a single S signal conversion without performing complex correction processing. While the above example shows the generation of the first comparison result signal followed by the second comparison result signal, the first comparison result signal and the second comparison result signal may also be generated in that order. In this case, it is preferable that the maximum threshold voltage value included in the second threshold voltage values ​​is lower than the minimum threshold voltage value included in the first threshold voltage values.

[0107] In this embodiment, the amplification factor of the column amplifier 301 and the voltage change rate of the ramp signal are set to 4x, but are not limited to this. Furthermore, the method of acquiring the correction value, the magnification correction, the linearity error correction, and the offset error correction are not limited to the above, and the settings used as the correction reference may be changed arbitrarily. The combination of input capacitance and feedback capacitance of the column amplifier, and the number of capacitors installed, are also examples. The signal amplification factor of the ramp signal is also an example, and can be changed arbitrarily. Furthermore, in this embodiment, the determination value is set to 2-bit information, but is not limited to this, and may be set to more than 2 bits.

[0108] Second Embodiment A photoelectric conversion device according to the second embodiment will be described with reference to Figures 9 and 10. In the second embodiment, the selection operation of the amplification factor of the column amplifier during the S signal acquisition period is performed first during the determination period. The configuration of the photoelectric conversion device, pixel circuit, and column circuit are the same as those of the first embodiment, so their description will be omitted.

[0109] 9 shows a timing chart of AD conversion in this embodiment. Here, the operation during the determination period, which is a characteristic feature of this embodiment, will be described.

[0110] During the determination period 1, the comparator 303 compares the amplified pixel signal with a first threshold voltage value VREF1, and outputs a comparison result signal as a first determination value J1. The first determination value J1 is input to the first bit of the determination value memory 305C and stored therein. At time t411, the selection circuit 306 sends a control signal to the amplification factor switching circuit 302 based on the first determination value J1. The amplification factor switching circuit 302 switches its switch based on the control signal.

[0111] In the case of amplified pixel signal 1 (dashed line) in FIG. 9, since the amplified pixel signal is greater than the first threshold voltage value VREF1 during decision period 1, switches SW3 and SW4 are set to high level (solid line). The amplification factor of column amplifier 301 decreases, and the signal level of amplified pixel signal 1 becomes smaller than VREF2 during decision period 2, and comparator output COMPOUT becomes high level (solid line). On the other hand, in the case of amplified pixel signal 2 (dashed line) in FIG. 9, since the amplified pixel signal is smaller than the first threshold voltage value VREF1 during decision period 1, comparator output COMPOUT becomes high level (dashed line). Switches SW3 and SW4 do not switch (dashed line), and the amplification factor of the column amplifier does not change. The signal level of the amplified pixel signal does not change, and becomes greater than VREF2 during decision period 2.

[0112] Next, a method for obtaining the second judgment value J2 will be described. The comparator 303 compares the second threshold voltage value VREF2 with the amplified pixel signal during judgment period 2. The comparison result signal from the comparator 303 is set as the second judgment value J2. The second judgment value J2 is held in the second bit of the judgment value memory 305C.

[0113] In the example of amplified pixel signal 1 (dashed line) in FIG. 9, the signal is smaller than the second threshold voltage value VREF2, so the second decision value J2 is J2=1, and a "1" is stored in the second bit of decision value memory 305C. The comparator output COMPOUT becomes high level (solid line). On the other hand, in the example of amplified pixel signal 2 (dashed line) in FIG. 9, the signal is larger than the second threshold voltage value VREF2, so the first decision value J1 is J1=0, and a "0" is stored in the second bit of decision value memory 305C. The comparator output COMPOUT remains low level (dashed line).

[0114] The ramp signal input to the comparator 303 at time t415 during the S signal acquisition period is set based on the second judgment value J2 in the judgment value memory 305C. The selection circuit 306 sends a control signal to the ramp signal switching circuit 304 based on the value of the second judgment value J2. When the second judgment value J2 is "1", the ramp signal switching circuit 304 inputs the ramp signal VRAMP_L to the comparator 303 from time t415. When the second judgment value J2 is "0", the ramp signal switching circuit 304 inputs the ramp signal VRAMP_H to the comparator 303 from time t415. The subsequent processing during the S signal acquisition period is the same as in the first embodiment, and therefore will not be described.

[0115] 9, during the S signal acquisition period, the amplification factor of the column amplifier 301 is 1, and the ramp signal VRAMP_L is input to the comparator 303. This combination is defined as "setting D." At time t416A when the polarity of the comparator output COMPOUT (solid line) changes, The value of the count signal CNT is stored in the S memory as the S signal. On the other hand, for the amplified pixel signal 2, during the S signal acquisition period, the amplification factor of the column amplifier 301 is 4, and the ramp signal VRAMP_H is input to the comparator 303. This combination corresponds to "setting B" defined in the first embodiment. At time t416B when the polarity of the comparator output COMPOUT (dashed line) changes, the value of the count signal CNT is stored in the S memory as the S signal. More specifically, if the amplified pixel signal is smaller than both the first threshold voltage value VREF1 and the second threshold voltage value VREF2, the S signal is acquired using "setting A" defined in the first embodiment. Furthermore, if the amplified pixel signal is larger than both the first threshold voltage value VREF1 and the second threshold voltage value VREF2, the S signal is acquired using "setting C" defined in the first embodiment.

[0116] That is, in this embodiment, as the signal level of the amplified pixel signal increases, the setting during S signal acquisition switches in the following order: "Setting A" → "Setting B" → "Setting D" → "Setting C." At this time, when switching between "Setting B" and "Setting D," both the amplification factor of the column amplifier 301 and the ramp signal input to the comparator 303 switch. As described in the first embodiment, when these two switch simultaneously, a correction error in the output value offset is likely to occur at the boundary point. Therefore, in this embodiment, the amplification factor of the column amplifier 301 during the S signal acquisition period and the selection of the ramp signal input to the comparator 303 are controlled based on the result of the judgment value. Here, by performing an operation that does not generate "Setting D," a signal output similar to that of the first embodiment is realized.

[0117] Next, the operation of "setting C" that skips "setting D" based on the judgment value stored in judgment value memory 305C will be described.

[0118] 10 is a flowchart for explaining the selection of the amplification factor of the column amplifier 301 when acquiring the S signal and the ramp signal to be input to the comparator 303. In this embodiment, too, a control method for setting three settings, "setting A", "setting B", and "setting C", will be described.

[0119] First, the amplification factor of the column amplifier 301 is set to 4 times the first amplification factor. The ramp signal VRAMP_L is input from the ramp signal switching circuit 304 to the comparator 303. Under this condition, N signal acquisition is performed.

[0120] Subsequently, the differences in the three "settings" will be described respectively. First, "Setting A" will be described. "Setting A" shows an example where the signal level of the amplified pixel signal AMPOUT is low and the pixel is irradiated with low-intensity light. In determination period 1, the amplified pixel signal AMPOUT and the first threshold voltage value VREF1 are compared. In "Setting A", AMPOUT < VREF1, and the first determination value J1 is held as "1" in the first bit of the determination value memory 305C.

[0121] Next, in determination period 2, the amplified pixel signal AMPOUT including the image signal and the second threshold voltage value VREF2 are compared. In "Setting A", AMPOUT < VREF2, and the second determination value J2 is held as "1" in the first bit of the determination value memory 305C. The amplification factor of the column amplifier 301 remains the first amplification factor and becomes 4 times. Then, at time t415 in the S signal acquisition period, based on the second determination value J2 = 1 held in the second bit of the determination value memory 305C, the selection circuit 306 sends a control signal to the ramp signal switching circuit 304. The ramp signal switching circuit 304 inputs the ramp signal VRAMP_L to the comparator 303, and the AD conversion sensitivity becomes 4 times.

[0122] Thus, in "Setting A", with the first amplification factor where the amplification factor of the column amplifier 301 becomes 4 times, the ramp signal VRAMP_L with an AD conversion sensitivity of 4 times is input to the comparator 303. That is, S signal acquisition is performed with an S conversion sensitivity of 4 × 4 = 16 times.

[0123] Subsequently, "Setting B" will be described. "Setting B" shows an example where the signal level of the amplified pixel signal AMPOUT is medium, that is, the pixel is irradiated with medium-intensity light.

[0124] During determination period 1, the amplified pixel signal AMPOUT is compared with the first threshold voltage value VREF1. In "Setting B", AMPOUT < VREF1, and the first determination value J1 is held as "1" in the first bit of the determination value memory 305C.

[0125] Next, during determination period 2, the amplified pixel signal AMPOUT including the image signal is compared with the second threshold voltage value VREF2. In "Setting B", AMPOUT ≥ VREF2, and the second determination value J2 is held as "0" in the second bit of the determination value J in the determination value memory 305C. Then, at time t415 in the S signal acquisition period, based on the first determination value "0" held in the second bit of the determination value J in the determination value memory 305C, the selection circuit 306 sends a control signal to the ramp signal switching circuit 304. The ramp signal switching circuit 304 inputs the ramp signal VRAMP_H to the comparator 303, and the AD conversion sensitivity becomes 1 times.

[0126] Thus, in "Setting B", the ramp signal VRAMP_H with an AD conversion sensitivity of 1 times is input to the comparator 303 at the first amplification factor where the amplification factor of the column amplifier 301 becomes 4 times. That is, the S signal is acquired at an AD conversion sensitivity of 4×1 = 4 times defined by the integrated value.

[0127] Finally, "Setting C" will be described. "Setting C" shows an example where the pixel is irradiated with high-intensity light with a high signal level of the amplified pixel signal AMPOUT.

[0128] The amplified pixel signal AMPOUT including the image signal is compared with the first threshold voltage value VREF1. In "Setting C", AMPOUT ≥ VREF1, and "0" is held as the first determination value J1 in the second bit of the determination value memory 305C. Next, during determination period 2, when the first determination value J1 becomes "0", the logic is such that the second determination value J2 is also forced to be "0".

[0129] For example, as shown in the following formula, the second determination value is the integrated value of the first determination value and the determination value obtained in determination period 2. The first determination value J1 = the determination result in determination period 1 (Equation - 11) Second judgment value J2 = First judgment value J1 × Judgment result of judgment period 2 (Equation 12)

[0130] As a result, when the first judgment value is 1, the judgment value for judgment period 2 is valid, and when the first judgment value is 0, the second judgment value is set to 0 regardless of the judgment result. In other words, the second judgment value J2 is determined in combination with the first judgment value. As a result, even if the first judgment value J1 becomes J1=0, the amplification factor of the column amplifier 301 is reduced, and the amplified pixel signal falls below the second threshold voltage value VREF2, the "Setting D" state does not occur. Therefore, the same method as in the first embodiment can be used to perform everything from AD conversion to S signal correction processing. Since the subsequent methods for correcting the magnification of the S signal and the ratio error of the amplification factor are common, a description thereof will be omitted.

[0131] As described above in the second embodiment, even when the amplification factor of the column amplifier 301 is determined first during the determination period, it is possible to perform processing similar to that of the first embodiment.

[0132] In this embodiment, the second determination value J2 is calculated by multiplying it by the first determination value J1, but the present invention is not limited to this.

[0133] Third Embodiment A photoelectric conversion device according to a third embodiment of the present invention will be described with reference to Figures 11 to 14. In the third embodiment, similar to the second embodiment, the selection operation of the amplification factor of the column amplifier in the S signal acquisition period is performed first in the determination period.

[0134] In this embodiment, the relationship between the first threshold voltage value VREF1 and the second threshold voltage value VREF2 is defined to suppress unnecessary transitions to settings. This transition is suppressed by defining the relationship between the first threshold voltage value VREF1 and the second threshold voltage value VREF2 as follows: VREF1≦VREF2 (Formula-13)

[0135] In this embodiment, for the sake of convenience, instead of the ramp signal VRAMP_L, a ramp signal VRAMP_M whose rate of change is twice (AD conversion sensitivity 1 / 2 times) that of the ramp signal VRAMP_L is used. In the description, the configurations of the photoelectric conversion device, pixel circuit, and column circuit are the same as those in the first embodiment, and thus the description thereof is omitted.

[0136] FIG. 11 is a timing chart for explaining the AD conversion operation in this embodiment. As shown in the determination period in FIG. 11, here VREF1 = VREF2 is set so that the magnitude relationship between the first threshold voltage value VREF1 and the second threshold voltage value VREF2 satisfies the relationship shown in (Equation - 8). Since the acquisition methods of the N signal, determination value, and S signal are the same as those in the second embodiment, the description thereof is omitted.

[0137] The combination setting of the amplification factor of the column amplifier 301 and the ramp signal input to the comparator 303 in this embodiment will be described. FIG. 12 is a flowchart for explaining the setting of the S conversion sensitivity in this embodiment.

[0138] The following is common to the three settings. First, the amplification factor of the column amplifier 301 is set to 4 times, which is the first amplification factor. Also, the ramp signal VRAMP_M is input from the ramp signal switching circuit 304 to the comparator 303. Under this condition, the N signal acquisition is performed.

[0139] Hereinafter, the differences between the three "settings" will be described separately. First, "Setting E" will be described. "Setting E" shows an example where the signal level of the amplified pixel signal AMPOUT is low, that is, the pixel is irradiated with low - intensity light.

[0140] In determination period 1, the amplified pixel signal AMPOUT and the first threshold voltage value VREF1 are compared. In "Setting E", AMPOUT < VREF1, and the first determination value J1 is held as "1" in the first bit of the determination value memory 305C. The amplification factor of the column amplifier 301 remains the first amplification factor and becomes 4 times.

[0141] Next, in determination period 2, an amplified pixel signal AMPOUT including an image signal is compared with a second threshold voltage value VREF2. As described above, since the relationship between the first voltage value and the second voltage value is VREF1 < VREF2, inevitably AMPOUT < VREF2. The second determination value J2 is held as "1" in the first bit of the determination value memory 305C.

[0142] Then, at time t415 in the S signal acquisition period, based on the second determination value J2 = 1 held in the second bit of the determination value memory 305C, the selection circuit 306 sends a control signal to the lamp signal switching circuit 304. The lamp signal switching circuit 304 inputs a lamp signal VRAMP_M to the comparator 303, and the AD conversion sensitivity becomes twice.

[0143] In this way, "in setting E, the amplification factor of the column amplifier 301 is the first amplification factor of 4 times, and a lamp signal VRAMP_M with an AD conversion sensitivity of 2 times is input to the comparator 303. That is, S signal acquisition is performed with an S conversion sensitivity of 4 × 2 = 8 times.

[0144] Next, an explanation will be given about "setting F". "Setting F" shows an example where the signal level of the amplified pixel signal AMPOUT is medium, that is, the pixel is irradiated with medium-intensity light. In determination period 1 , the amplified pixel signal AMPOUT is compared with the first threshold voltage value VREF1. In "setting F", AMPOUT > VREF1, and the first determination value J1 is held as "0" in the first bit of the determination value memory 305C. The amplification factor of the column amplifier 301 switches to the second amplification factor and becomes 1 time.

[0145] Next, in determination period 2, the amplified pixel signal AMPOUT including the image signal is compared with the second threshold voltage value VREF2.

[0146] In "Setting F", AMPOUT < VREF2, and the second determination value J2 is held as "1" in the second bit of the determination value J in the determination value memory 305C. Then, at time t415 during the S signal acquisition period, based on the first determination value "1" held in the second bit of the determination value J in the determination value memory 305C, the selection circuit 306 sends a control signal to the lamp signal switching circuit 304. The lamp signal switching circuit 304 inputs the lamp signal VRAMP_M to the comparator 303, and the AD conversion sensitivity becomes twice as high.

[0147] Thus, in "Setting F", the lamp signal VRAMP_H with an AD conversion sensitivity twice as high is input to the comparator 303 at the first amplification factor where the amplification factor of the column amplifier 301 is 1 times. That is, S signal acquisition is performed with an S conversion sensitivity of 1×2 = 2 times.

[0148] Finally, regarding "Setting C", since it is the same as the Setting C described in the first embodiment, the description is omitted.

[0149] Next, the magnification correction of the S signal in this embodiment will be described using FIG. 13. The pixel signal PIXOUT varies in amplitude up to a maximum voltage value VR2' V] according to the amount of light incident on the pixel 101. During the S signal acquisition period, the pixel signal PIXOU T is AD-converted by the lamp signal VRAMP_M up to the voltage value VR1' which is 1 / 2 of the voltage value VR2'[V], and above that, it is AD-converted by the lamp signal VRAMP_H. Also, up to the voltage value VA1'[V] which is 1 / 4 of the voltage value VR1'[V], the pixel signal PIXOUT is AD-converted at the first amplification factor by the column amplifier 301, and at pixel signal levels above that, it is AD-converted at the second amplification factor.

[0150] The pixel signal PIXOUT has a voltage value VA1' [V], and an AD-converted value DA1' [LSB] is obtained under "setting E." The AD-converted value DA1' [LSB] is the maximum value of the count value counted by the counter circuit 106 during the period from time t415 to time t417. Meanwhile, the pixel signal PIXOUT has a voltage value VR1' [V] that is four times the voltage value VR1 [V], and an AD-converted value DA1' [LSB] is also obtained under "setting F." Furthermore, the pixel signal PIXOUT has a voltage value VR2' [V] that is 4 × 2 = 8 times the voltage value VA1' [V], and an AD-converted value DA1' [LSB] is also obtained under "setting C." The S signals acquired under these different settings are subjected to magnification correction based on the first judgment value J1 and the second judgment value J2 stored in the judgment value memory 305C.

[0151] When the first judgment value J1 and the second judgment value J2 stored in the judgment value memory 305C are J1="1" and J2="1", respectively, the S signal is not corrected. This applies when the pixel signal PIXOUT has a voltage range from 0 [V] to VA1' [V] (bold line).

[0152] When the first judgment value J1 and the second judgment value J2 stored in the judgment value memory 305C are J1="0" and J2="1", respectively, the S signal undergoes a four-fold magnification correction. This applies to the pixel signal PIXOUT in the range from voltage value VA1' [V] to voltage value VR1' [V], and the S signal before correction (dash-dotted line) is magnified and becomes a four-fold S signal (thick dash-dotted line). Here, the pixel signal PIXOUT switches between "Setting E" and "Setting F" at the voltage value VA1' [V]. The voltage value VA1' [V] corresponds to the first threshold voltage value VREF1 when converted into an amplified pixel signal AMPOUT from the column amplifier 301 at a first amplification factor (×4). Furthermore, the pixel signal PIXOUT switches between "Setting F" and "Setting C" at the voltage value VR1' [V]. The output at which the pixel signal PIXOUT has a voltage value VR1' [V] corresponds to the second threshold voltage value VREF2 when converted into an amplified pixel signal AMPOUT at a second amplification factor (×1).

[0153] When the first judgment value J1 and the second judgment value J2 stored in the judgment value memory 305C are J1="0" and J2="0", respectively, the S signal undergoes a magnification correction of 8 times. This applies to the pixel signal PIXOUT in the range from the voltage value VR1' [V] to the voltage value VR2' [V], and the S signal before correction (two-dot chain line) becomes the S signal multiplied by 8 (thick two-dot chain line). In this way, the S signal obtained for each setting is subjected to magnification correction processing based on the judgment value. The calculation of the amplification factor of the column amplifier 301 and the ratio error of the voltage change rate of the ramp signal and the method of obtaining the correction value are omitted because they are the same as in other embodiments.

[0154] As described above, even if the column amplifier gain selection operation is performed first during the S signal acquisition period during the determination period, by setting the first threshold voltage VREF1 to be equal to or lower than the second threshold voltage VREF2, it is possible to suppress transition to an unnecessary setting. This makes it possible to achieve an expanded dynamic range, high speed, and good signal characteristics.

[0155] <Fourth embodiment> A photoelectric conversion device according to the fourth embodiment will be described with reference to Fig. 14 to Fig. 19. In this embodiment, four ramp signals are input to a ramp signal switching circuit 304, and three of the ramp signals are used to set the gain of AD conversion.

[0156] There are three ramp signal settings for acquiring the S signal and two column amplifier amplification factor settings, resulting in 3 x 2 = 6 possible combinations. However, as explained in other embodiments, in this example, four settings are used to perform AD conversion of the amplified pixel signal so that these two settings are not switched simultaneously when switching settings. This suppresses output errors at the setting switching point and achieves good output characteristics.

[0157] First, the configuration of the photoelectric conversion device of this embodiment will be described. FIG. 14 is a block diagram of the column circuit 104 of the photoelectric conversion device of this embodiment. As shown in FIG. 14, four ramp signals, namely, ramp signals VRAMP_L, VRAMP_M, VRAMP_H, and VRAMP_J, are input to the ramp signal switching circuit 304. The voltage change rates of the respective ramp signals are the same as those of the ramp signals of the same names described in the first to third embodiments. That is, compared to the ramp signal VRAMP_L, the ramp signal VRAMP_M has a voltage change rate that is twice as high, and the ramp signal VRAMP_H has a voltage change rate that is four times as high. Furthermore, the judgment value memory 305C is 3 bits and can hold three judgment result values. The other components are the same as those of the first embodiment, and therefore description thereof will be omitted.

[0158] Next, a method for acquiring the N signal, the decision value, and the S signal by AD conversion in the column circuit 104 will be described. Fig. 15 is a timing chart illustrating the AD conversion operation in the column amplifier. The operation during the N signal acquisition period is omitted because it is the same as in other embodiments.

[0159] A method for acquiring a judgment value during the judgment period will be described below: The period from time t407 to time t414 is the judgment period, during which a judgment value is acquired.

[0160] First, during the period from time t407 to time t411A, the first judgment value J1 is acquired, but since the method is the same as in the first embodiment, the description will be omitted. The first judgment value J1 becomes J1=0, and “0” is held in the first bit of the judgment value memory 305C.

[0161] Furthermore, during the period from time t412 to time t414, a second judgment value J2 is acquired, but since the method is the same as in the first embodiment, the description will be omitted. The second judgment value J2 becomes "0", and "0" is held in the second bit of the judgment value memory 305C.

[0162] A method for obtaining a third determination value J3, which is a characteristic part of this embodiment, will be described. The third determination value J3 is obtained during the period from time t411A to time t411B.

[0163] The lamp signal VRAMP_J further increases the voltage value during the period from time t411A to time t410B, and performs an operation of maintaining the voltage value for a certain period from time t410B to time t411B at this time, and the voltage value maintained between time t410B and time t411B at this time is set as the third threshold voltage value VREF3, and the same period is set as determination period 3. At this time, the first threshold voltage value VREF1 and the third threshold voltage value VREF3 satisfy the following relationship. VREF1 < VREF3 (Equation - 14)

[0164] Also, for the purpose of ensuring the comparison signal COMPRES inversion period for obtaining a correct AD conversion value during the S signal acquisition period described in the first embodiment, the third threshold voltage value VREF3 and the second voltage value satisfy the following relationship. VREF3 < VREF2 (Equation - 15)

[0165] The threshold voltage value for determining the amplification factor of the column amplifier 301 is larger than the maximum value of the plurality of threshold voltages for determining the voltage change rate of the lamp signal. During determination period 3, the comparator 303 compares the third threshold voltage value VREF3 with the amplified pixel signal AMPOUT, and the output comparison result signal becomes the third determination value J3. The third determination value J3 is input to and held in the 3rd bit of the determination value memory 305C. After time t411B, the lamp signal VRAMP is reset. In the case of FIG. 15, since the amplified pixel signal AMPOUT is larger than the third threshold voltage value VREF3, the third determination value J3 becomes "0", and "0" is held in the 3rd bit of the determination value memory 305C.

[0166] The period from time t414 to time t417 is the S signal acquisition period. The setting of the amplification factor of the column amplifier is the same as in the first embodiment, so a description thereof will be omitted. The selection of the ramp signal to be input to the comparator 303 will be described. The selection circuit 306 selects the ramp signal based on the first judgment value J1 and the third judgment value J3 stored in the judgment value memory 305C. A control signal is sent to the ramp signal switching circuit 304. Based on the control signal, the ramp signal switching circuit 304 selects the ramp signal to be input to the comparator 303 at time t415.

[0167] In the case of FIG. 15, the first judgment value J1 stored in the judgment value memory 305C is "0" and the third judgment value J3 is "0". At this time, the selection circuit 306 selects the lamp signal J1 from the comparator 303. On the other hand, if the first judgment value J1 stored in the judgment value memory 305C is "0" and the third judgment value J3 is "1", the selection circuit 306 sends a control signal to the ramp signal switching circuit 304 so that the ramp signal VRAMP_M is input to the comparator 303. Alternatively, if the first judgment value J1 stored in the judgment value memory 305C is "1" and the third judgment value J3 is "1", the selection circuit 306 outputs the ramp signal VR to the comparator 303. AMP_L is input. A state in which the first judgment value J1 is "0" and the third judgment value J3 is "1" is not taken into consideration because it cannot occur.

[0168] At time t415, the ramp signal input to the comparator 303 starts to change in output at a constant rate. The counter circuit 106 synchronizes with the change in the ramp signal output and starts counting the clock pulse signal. In the example of FIG. 15, the ramp signal VRAMP_H is input to the comparator 303 at time t415. At time t416, the voltage of the ramp signal VRAMP_H is amplified. When the pixel signal AMPOUT is exceeded, the signal polarity of the comparison result signal COMPOUT output by the comparator 303 changes. The S memory 305B holds the value of the count signal CNT at time t416 as the S signal. After time t417, the ramp signal VRAMP and the count signal CNT are reset and initialized.

[0169] The above is the AD conversion in the column circuit 104 in this embodiment. Subsequently, the setting of the combination of the amplification factor of the column amplifier and the signal change rate of the ramp signal in this embodiment will be described. FIG. 16 is a flowchart for explaining the S conversion sensitivity in this embodiment.

[0170] There are three types of ramp signal settings and two types of amplification factor settings for the column amplifier. Therefore, there can be 3×2 = 6 types of combinations as settings. However, as described in other embodiments, in this example, four settings are used to perform AD conversion of the amplified pixel signal so that these two settings do not switch simultaneously when the settings are switched.

[0171] The following is common to the four configurable settings. First, the amplification factor of the column amplifier 301 is set to four times the first amplification factor. Also, the ramp signal VRAMP_L is input from the ramp signal switching circuit 304 to the comparator 303. Under this condition, N signal acquisition is performed. Hereinafter, the differences between the four settings will be described respectively.

[0172] First, "Setting A" will be described. "Setting A" shows an example where the signal level of the amplified pixel signal AMPOUT is low, that is, the pixel is irradiated with low-intensity light. In determination period 1, the amplified pixel signal AMPOUT and the first threshold voltage value VREF1 are compared. In "Setting A", AMPOUT < VREF1, and the first determination value J1 is held as "1" in the first bit of the determination value memory 305C. Next, in determination period 3, the amplified pixel signal AMPOUT including the image signal and the third threshold voltage value VREF3 are compared. At this time, since the relationship between the first threshold voltage value VREF1 and the third threshold voltage value VREF3 is VREF1 < VREF3, inevitably AMPOUT < VREF3. The third determination value J3 is held as "1" in the third bit of the determination value memory 305C. The second determination value is also held as "l" in the same manner. The amplification factor of the column amplifier 301 is not changed. It is held. The amplification factor of the column amplifier 301 is not changed.

[0173] Then, at time t415 during the S signal acquisition period, based on the first determination value J1 (= 1) and the third determination value J3 (= 1) in the determination value memory 305C, the selection circuit 306 sends a control signal to the lamp signal switching circuit 304. The lamp signal switching circuit 304 inputs the lamp signal VRAMP_L to the comparator 303, and the AD conversion sensitivity becomes 4 times. Thus, in "Setting A", the lamp signal VRAMP_M with an AD conversion sensitivity 4 times and an amplification factor 4 times that of the column amplifier 301 is input to the comparator 303 at the first amplification factor. That is, the S signal is acquired with an S conversion sensitivity of 4×4 = 16 times.

[0174] Next, "Setting E" will be described. "Setting E" shows an example where the signal level of the amplified pixel signal AMPOUT is at a relatively low medium level, that is, the pixels are irradiated with medium-level light close to low brightness. In determination period 1, the amplified pixel signal AMPOUT is compared with the first threshold voltage value VREF1. In "Setting E", AMPOUT ≥ VREF1, and the first determination value J1 is held as "0" in the first bit of the determination value memory 305C.

[0175] Next, in determination period 3, in "Setting E", AMPOUT < VREF3. The third determination value J3 is held as "1" in the third bit of the determination value memory 305C. The second determination value is similarly held as "1". The amplification factor of the column amplifier 301 is not changed. Then, at time t415 during the S signal acquisition period, based on the first determination value J1 (= 0) and the third determination value J3 (= 1) in the determination value memory 305C, the selection circuit 306 sends a control signal to the lamp signal switching circuit 304. The lamp signal switching circuit 304 inputs the lamp signal VRAMP_M to the comparator 303, and the AD conversion sensitivity becomes 2 times. Thus, in "Setting E", the lamp signal VRAMP_M with an AD conversion sensitivity 2 times and an amplification factor 4 times that of the column amplifier 301 is input to the comparator 303 at the first amplification factor. That is, the S signal is acquired with an S conversion sensitivity of 4×2 = 8 times.

[0176] Next, "Setting B" will be described. "Setting B" shows an example where the signal level of the amplified pixel signal AMPOUT is at a relatively high medium level, that is, the pixels are irradiated with medium-level light close to high brightness.

[0177] In determination period 1, the amplified pixel signal AMPOUT is compared with the first threshold voltage value VREF1. In "Setting B", AMPOUT ≥ VREF1, and the first determination value J1 is held as "0" in the first bit of the determination value memory [0000661].

[0178] Next, in determination period 3, in "Setting B", AMPOUT ≥ VREF3. The third determination value J3 is held as "0" in the third bit of the determination value memory [0000661].

[0179] Next, in determination period 2, in "Setting B", AMPOUT < VREF2. The second determination value "1" is held. The amplification factor of the column amplifier [0000661] is not changed. At time t415 in the S signal acquisition period, based on the first determination value J1 (= 0) and the third determination value J3 (= 0) in the determination value memory [0000661], the selection circuit [000066... sends a control signal to the lamp signal switching circuit [000066... The lamp signal switching circuit [000066... inputs the lamp signal VRAMP_H to the comparator [000066... and the AD conversion sensitivity becomes double. Thus, in "Setting B", the lamp signal VRAMP_H with an AD conversion sensitivity of double is input to the comparator [000066... at the first amplification factor where the amplification factor of the column amplifier [0000661] becomes quadruple. That is, the S signal is acquired with an S conversion sensitivity of 4 × 1 = 4 times.

[0180] Finally, "Setting C" will be described. "Setting C" shows an example where the signal level of the amplified pixel signal AMPOUT is high, that is, the pixels are irradiated with high-brightness light.

[0181] In determination period [0000670], the amplified pixel signal AMPOUT is compared with the first threshold voltage value VREF1. In "Setting C", AMPOUT ≥ VREF1, and the first determination value J1 is held as "0" in the first bit of the determination value memory .

[0182] Next, in the determination period 3, AMPOUT≧VREF3 is established under "setting C." The third determination value J3 is held as "0" in the third bit of the determination value memory 305C.

[0183] Next, in the determination period 2, under "setting C," AMPOUT≧VREF2 holds. The second determination value is held at "0." The gain of the column amplifier 301 switches from the first gain to the second gain, becoming 1x. Then, at time t415 during the S signal acquisition period, the selection circuit 306 sends a control signal to the ramp signal switching circuit 304 based on the first determination value J1 (=0) and the third determination value J3 (=0) in the determination value memory 305C. The ramp signal switching circuit 304 inputs the ramp signal VRAMP_H to the comparator 303, and the AD conversion sensitivity becomes 1x. Thus, under "setting C," the ramp signal VRAMP_H, which makes the AD conversion sensitivity 1x, is input to the comparator 303 at the second gain, which makes the gain of the column amplifier 301 1x. In other words, the S signal is acquired with an S conversion sensitivity of 1x=4x.

[0184] The above is the state set in the S signal acquisition period in this embodiment. Next, the correction magnification of the S signal will be described with reference to FIG. 17. In this embodiment, a setting E is added to the first embodiment. The pixel signal PIXOUT is subjected to a magnification correction of 2x in the range from the voltage value VR1 [V] to the voltage value VR2 [V]. What has been added to the first embodiment is the existence of a boundary between "Setting A" and "Setting E" at the point where PIXOUT reaches a voltage value VR1 [V], and a boundary between "Setting E" and "Setting B" at the point where pixel signal PIXOUT reaches a voltage value VR2 [V]. Other magnification corrections of the S signal obtained with the patterns shown in the first embodiment are similar processes and will not be described.

[0185] FIG. 18 is a diagram illustrating the correction values ​​obtained by the correction value acquisition operation of the photoelectric conversion device according to this embodiment. Except for the acquisition of the correction value in "setting E", the process is the same as in the first embodiment, so duplicated explanations will be omitted. The correction value obtained by inputting the correction operation input value V1 to the column circuit 104 will be described. The value obtained by AD conversion in "setting E" will be referred to as correction value D8. Next, the correction value obtained by inputting the correction operation input value V2 to the column circuit 104 will be described. The value obtained by AD conversion in "setting E" will be referred to as correction value D9.

[0186] Below, a method for calculating the ratio error of the amplification factor of the column amplifier 301 and the ratio error of the voltage change rate of the ramp signal in this embodiment will be described using the correction values ​​D1, D2, D3, D4, D5, D6, D7, D8, and D9.

[0187] First, the ratio error of the voltage change rates of the ramp signals VRAMP_L and VRAMP_M is obtained from the ratio of the slope (or difference value) of the straight line obtained by connecting the correction value D2 obtained in "Setting A" to the correction value D1, and the correction value D9 obtained in "Setting E" to the correction value D8. This is called the linearity correction value α1. α1=(D2-D1) / (D9-D8) / 2 (Formula-16)

[0188] The linearity of the S signal obtained with "Setting E" is corrected to match the linearity of the signal obtained with "Setting A." In other words, the linearity standard is the linearity of the signal obtained with "Setting A."

[0189] Next, the ratio error of the voltage change rates of the ramp signals VRAMP_M and VRAMP_H is obtained from the ratio of the slope (or difference value) of each line obtained by connecting the correction value D9 and the correction value D8 obtained in "Setting E" and the correction value D4 and the correction value D3 obtained in "Setting B." This is defined as the linearity correction value α2. α2=(D9-D8) / (D4-D3) / 2 (Formula-17)

[0190] The linearity correction value α2 is multiplied by the S signal obtained with "Setting B," correcting the linearity of the S signal obtained with "Setting B" to match the linearity of the signal obtained with "Setting E." In addition, the S signal is further multiplied by α2 so that it matches the linearity of "Setting A."

[0191] Similarly, the ratio error of the amplification factor of the column amplifier 301 is obtained from the ratio of the slopes (or difference values) of the straight lines obtained by connecting the correction value D5 and the correction value D3 obtained in "Setting B" and the correction value D7 and the correction value D6 obtained in "Setting C." This is defined as the linearity correction value α3. α3=(D5-D3) / (D7-D6) / 4 (Formula-18)

[0192] The linearity correction value α3 corrects the linearity of the S signal obtained under "Setting C" to match the linearity of the S signal obtained under "Setting B." However, since it is necessary to match the linearity of "Setting A," the S signal under "Setting C" must also be multiplied by the linearity correction values ​​α1·α2.

[0193] Next, a method for calculating the amount of offset caused by a setting difference that may occur at a boundary point where the setting is switched, and an output value output from the signal processing circuit 109 after correcting the linearity and offset will be described.

[0194] First, we will explain how to calculate the offset correction value β1 that occurs when switching from "setting A" to "setting E." The correction value D9 obtained with "setting E" in the correction value acquisition operation becomes the corrected output 2×α1×D9 through magnification correction and linearity correction. If this corrected output is equal to the correction value D2, no offset occurs. In other words, the difference between D2 and 2×α1×D9 is the offset correction value β1. β1=D2-2×α1×D9 (Formula-19)

[0195] Therefore, the S signal obtained by "setting E" is corrected by the signal processing circuit 109 and output as the signal SB as follows: SB=2×α1×S+β1-N (Equation-20)

[0196] N is the digital value of the N signal. Next, we will explain how to calculate the offset correction value β2 that occurs when switching from "setting E" to "setting B." The correction value D9 obtained with "setting C" in the correction value acquisition operation becomes the corrected output 4×α1×α2×D4 through magnification correction and linearity correction. If this corrected output is equal to the corrected output 2×α1×D9 obtained by adding magnification correction and linearity correction to correction value D9, no offset occurs. In other words, the difference between the corrected outputs becomes the offset correction value β2. β2=2×α1×D9 - 4×α1×α2×D4 (Formula-21)

[0197] Therefore, the signal S obtained in "setting B" is corrected by the signal processing circuit 109, and the signal SC outputted is obtained by subtracting the N signal as follows: SC=4×α1×α2×S+β2-N (Formula-22)

[0198] Finally, we will explain the calculation of the offset correction value β3 that occurs when switching from "setting B" to "setting C." The correction value D7 obtained with "setting C" in the correction value acquisition operation becomes the corrected output 16×α1×α2×α3×D7 through magnification correction and linearity correction. If this corrected output is equal to the corrected output 4×α1×α2×D5 obtained by applying magnification correction and linearity correction to correction value D5, then no offset occurs. In other words, the difference between the corrected outputs becomes the offset correction value β2. β2=4×α1×α2×D5-16×α1×α2×α3×D7 (Formula-23)

[0199] Therefore, the signal S obtained by "setting C" is corrected by the signal processing circuit 109, and the signal SD outputted is obtained by subtracting the N signal as follows: SD=16×α1×α2×α3×S+β2-N (Formula-24)

[0200] The S signal obtained under "setting A" is not subjected to correction processing in the signal processing circuit 109, and the output from the signal processing circuit 109 is as follows: SA=SN (Eq.-25)

[0201] In this way, by correcting the S signal using the linearity correction values ​​α1, α2, and α3 obtained by the correction operation and the offset correction values ​​β1, β2, and β3, it is possible to obtain a signal that exhibits good linearity characteristics with respect to the amount of incident light.

[0202] Next, a method for obtaining correction values ​​during imaging operation will be described. FIG. 19 is a diagram illustrating a method for outputting correction values ​​of the photoelectric conversion device according to this embodiment. Here, the time required to read out one row of pixels 101 arranged in a matrix is ​​set to 1H. FIG. 19 shows, in chronological order in 1H time units, the setting states of the correction operation input value input to the column circuit 104, the voltage change rate of the ramp signal, and the amplification factor of the column amplifier. For positive values, the readout time for 10 rows from 1H to 10H is used, and the correction operation input value, the column amplifier amplification factor, and the voltage change rate of the ramp signal are sequentially switched to output correction values ​​D1, D2, D3, D4, D5, D6, D7, D8, and D9 for each row. This operation is preferably performed using rows consisting of pixels that are not used for imaging and that are non-photosensitive, such as optical black rows.

[0203] The correction value acquisition operation up to time 6H shown in FIG. 19(a) will be described below. In the correction value acquisition operation, the correction value D1 is acquired from time 0 to time 1H. During this period, the correction operation input value V1 is input, and the column circuit 104 performs AD conversion with the setting of "setting A." The S signal of the row output during this period becomes the correction value D1.

[0204] During the period from time 1H to time 2H, the correction value D8 is acquired. During this period, the correction operation input value V1 is input, and the column circuit 104 performs AD conversion with the setting of "setting E." The S signal of the row output during this period becomes the correction value D8.

[0205] During the period from time 2H to time 3H, the correction value D3 is acquired. During this period, the correction operation input value V2 is input, and the column circuit 104 performs AD conversion using the setting "setting B." The S signal of the row output during this period becomes the correction value D3.

[0206] During the period from time 3H to time 4H, the correction value D2 is acquired. During this period, the correction operation input value V2 is input, and the column circuit 104 performs AD conversion using the "setting A" setting. The S signal of the row output during this period becomes the correction value D2.

[0207] During the period from time 4H to time 5H, the correction value D9 is acquired. During this period, the correction operation input value V2 is input, and the column circuit 104 performs AD conversion with the setting of "setting E." The S signal of the row output during this period becomes the correction value D9.

[0208] During the period from time 5H to time 6H, the correction value D4 is acquired. During this period, the correction operation input value V2 is input, and the column circuit 104 performs AD conversion using the setting "setting B." The S signal of the row output during this period becomes the correction value D4.

[0209] The correction value acquisition operation from time 6H to time 10H shown in FIG. 19(b) will be described below.

[0210] The period from time 6H to time 7H is the same as the period from time 2H to time 3H, and correction value D3 is output. Measurement is performed taking into account symmetry in the time series. The period from time 7H to time 8H is where correction value D6 is acquired. During this period, correction operation input value V1 is input, and column circuit 104 performs AD conversion with the setting "Setting C." The S signal of the row output during this period is correction value D6.

[0211] During the period from time 8H to time 9H, the correction value D5 is acquired. During this period, the correction operation input value V3 is input, and the column circuit 104 performs AD conversion using the setting "setting B." The S signal of the row output during this period becomes the correction value D5.

[0212] During the period from time 9H to time 10H, a correction value D7 is acquired. During this period, a correction operation input value V3 is input, and the column circuit 104 performs AD conversion using the "setting C" setting. The S signal of the row output during this period becomes the correction value D7. The correction values ​​D1, D2, D3, D4, D5, D6, D7, D8, and D9 obtained over the 10H period are input to the signal processing circuit 109 and used in the correction process described with reference to FIG. 7.

[0213] In this embodiment, the threshold voltage value that determines the voltage change rate of the ramp signal during the determination period is set to multiple values. In this example, the AD conversion sensitivity is set in multiple stages. However, the gain of the column amplifier may be set in multiple stages. The threshold voltage that determines the voltage change rate of the ramp signal is also set in a stepped manner, but the ramp signal may be reset and set each time.

[0214] In each of the above-described embodiments, the comparison of the pixel signal with the threshold voltage value that determines the voltage change rate of the ramp signal and the comparison of the pixel signal with the threshold voltage value that determines the setting state of the amplification factor of the column amplifier are performed by the comparator 303, which is a comparison circuit. However, this is not limited to this configuration, and these comparisons may be performed by a determination circuit that is provided separately from the comparator 303. This determination circuit may be provided with a comparison circuit that compares the pixel signal with the threshold voltage value and outputs a determination value corresponding to a first signal and a second signal that indicate the comparison result.

[0215] In addition, in the above-described embodiments, the ramp signal has been described as changing in signal voltage in a slope-like manner, but is not limited to this. For example, the signal voltage may change in a step-like manner, and such a form is also included in the ramp signal that changes at a predetermined voltage change rate. Furthermore, the voltage change rate of the ramp signal does not need to be constant. For example, the signal voltage of the ramp signal may change at a relatively small voltage change rate when the signal voltage change of the ramp signal starts, and after a predetermined period has elapsed, the signal voltage of the ramp signal may change at a relatively large voltage change rate.

[0216] In addition, in each of the above-described embodiments, a column circuit 104 is provided for one column of pixels 101, but this correspondence is not limiting. That is, a plurality of column circuits 104 may be provided for one column of pixels 101, or one column circuit 104 may be provided for multiple columns of pixels 101.

[0217] The photoelectric conversion devices of the above-described embodiments can be applied to a stacked sensor in which multiple substrates are stacked, or a single-layer sensor in which the components shown in FIG. 1 are arranged on a single substrate. In the case of a stacked sensor, the arrangement of the components shown in FIG. 1 on the multiple substrates can be designed as appropriate. For example, when two substrates are stacked, an array of pixels 101 arranged in multiple rows and columns can be arranged on the first substrate, and the components shown in FIG. 1 other than the array can be arranged on the second substrate. When three substrates are stacked, the photodiode 201 and transfer MOS transistor 202 of the pixel 101 configuration can be arranged on the first substrate, and the other components of the pixel 101 can be arranged on the second substrate. Furthermore, the components shown in FIG. 1 other than the array of pixels 101 arranged in multiple rows and columns can be arranged on a third substrate. This arrangement is merely an example and can be modified as appropriate. For example, an array of pixels 101 arranged in multiple rows and multiple columns may be disposed on a first substrate, and components other than the array may be disposed on a second substrate among the components shown in Fig. 1. A memory array (e.g., DRAM) for storing signals and a computing unit (which may have machine learning functions) for processing signals may be disposed on a third substrate. Note that the stacked sensor may also be a sensor in which even more substrates are stacked.

[0218] The photoelectric conversion system, the mobile object, and the device according to the embodiment will be described below.

[0219] Fifth Embodiment The photoelectric conversion system according to this embodiment will be described with reference to Fig. 20. Fig. 20 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0220] The photoelectric conversion devices described in the first to fourth embodiments can be applied to various photoelectric conversion systems. A photoelectric conversion system includes at least the photoelectric conversion device according to the above embodiments and a signal processing unit that processes signals output from the photoelectric conversion device. Examples of devices to which such photoelectric conversion systems can be applied include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, sensors, and measuring instruments. Furthermore, a camera module equipped with an optical system such as a lens and a photoelectric conversion device is also included in the equipment to which the photoelectric conversion system is applied. Figure 9 shows a block diagram of a digital still camera as an example of such equipment.

[0221] 9 includes an imaging device 2504 to which the photoelectric conversion device of any of the above-described embodiments is applied, and a lens 2502 that forms an optical image of a subject on the imaging device 2504. The photoelectric conversion system also includes an aperture 2503 that adjusts the amount of light passing through the lens 2502, and a barrier 2501 that protects the lens 2502. The lens 2502 and aperture 2503 form an optical system that focuses light on the imaging device 2504. The imaging device 2504 is a photoelectric conversion device of any of the above-described embodiments, and converts the optical image formed by the lens 2502 into an electrical signal.

[0222] The photoelectric conversion system also includes a signal processing unit 2507, which is an image generation unit that generates an image by processing an output signal output from the imaging device 2504. The signal processing unit 2507 performs various corrections and compressions as necessary to output image data. The signal processing unit 2507 may be formed on the same semiconductor substrate on which the imaging device 2504 is provided, or may be formed on a semiconductor substrate separate from the imaging device 2504. Furthermore, the imaging device 2504 and the signal processing unit 2507 may be formed on the same semiconductor substrate.

[0223] The photoelectric conversion system further includes a memory unit 2510 for temporarily storing image data, and an external interface unit (external I / F unit) 2513 for communicating with an external computer or the like. The photoelectric conversion system further includes a recording medium 2512 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 2511 for recording or reading out data from the recording medium 2512. The recording medium 2512 may be built into the photoelectric conversion system or may be detachable.

[0224] The photoelectric conversion system further includes an overall control / calculation unit 2509 that performs various calculations and controls the entire digital still camera, and a timing generation unit 2508 that outputs various timing signals to the image capture device 2504 and signal processing unit 2507. Here, timing signals and the like may be input from outside, and the photoelectric conversion system only needs to include at least the image capture device 2504 and the signal processing unit 2507 that processes the output signal output from the image capture device 2504.

[0225] The imaging device 2504 outputs an imaging signal to the signal processing unit 2507. The signal processing unit 2507 performs predetermined signal processing on the imaging signal output from the imaging device 2504 and outputs image data. The signal processing unit 2507 generates an image using the imaging signal.

[0226] As described above, according to this embodiment, a photoelectric conversion system can be realized to which the photoelectric conversion device according to any one of the first to fourth embodiments is applied.

[0227] <Fourth embodiment> The photoelectric conversion system and the mobile object of this embodiment will be described with reference to Figures 21(A) and 21(B). Figure 21(A) is a diagram showing the configuration of the photoelectric conversion system of this embodiment, and Figure 21(B) is a diagram showing the configuration of the mobile object of this embodiment.

[0228] FIG. 21(A) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 2600 has an image pickup device 2610. The image pickup device 2610 is the photoelectric conversion device described in any one of the first to fourth embodiments. The photoelectric conversion system 2600 has an image processing unit 2612 that performs image processing on a plurality of image data acquired by the image pickup device 2610. The photoelectric conversion system 2600 also calculates the distance to an object. The vehicle speed control system includes a distance acquisition unit 2616 and a collision determination unit 2618 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the distance acquisition unit 2616 may acquire distance information to the object using ToF (Time Of Flight) or may acquire distance information using parallax information, etc. In other words, the distance information is information related to parallax, defocus amount, distance to the object, etc. The collision determination unit 2618 may determine the possibility of collision using any of these pieces of distance information. The distance information acquisition unit may be realized by dedicated hardware or a software module. Furthermore, it may be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), etc., or a combination thereof.

[0229] The photoelectric conversion system 2600 is connected to a vehicle information acquisition device 2620 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 2600 is also connected to an ECU 2630, which is a control device (control unit) that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 2618. The photoelectric conversion system 2600 is also connected to an alarm device 2640 that issues an alarm to the driver based on the determination result of the collision determination unit 2618. For example, if the determination result of the collision determination unit 2618 indicates a high possibility of a collision, the ECU 2630 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 2640 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0230] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 2600. Fig. 21(B) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 2650). A vehicle information acquisition device 2620 sends instructions to the photoelectric conversion system 2600 or the imaging device 2610. This configuration can further improve the accuracy of distance measurement.

[0231] While the above describes an example of control to prevent collisions with other vehicles, the present invention can also be applied to other applications, such as autonomous driving control to follow other vehicles and autonomous driving control to prevent vehicles from drifting out of their lanes. Furthermore, the photoelectric conversion system can be applied not only to automobiles and other vehicles, but also to moving bodies (mobile devices) such as ships, aircraft, and industrial robots. The moving body includes one or both of a driving force generator that generates a driving force primarily used to move the moving body and a rotating body primarily used to move the moving body. The driving force generator can be an engine, a motor, or the like. The rotating body can be a tire, a wheel, a ship's screw, an aircraft's propeller, or the like. In addition to moving bodies, the present invention can be applied to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0232] Seventh Embodiment The photoelectric conversion system of this embodiment will be described with reference to Fig. 22. Fig. 22 is a block diagram showing an example of the configuration of a range image sensor which is the photoelectric conversion system of this embodiment.

[0233] 22, the distance image sensor 2701 is configured to include an optical system 2707, a photoelectric conversion device 2708, an image processing circuit 2704, a monitor 2705, and a memory 2706. The distance image sensor 2701 can obtain a distance image according to the distance to the subject by receiving light (modulated light or pulsed light) that is projected toward the subject from a light source device 2709 and reflected from the surface of the subject.

[0234] The optical system 2707 is configured with one or more lenses, and guides image light (incident light) from the subject to the photoelectric conversion device 2708, and transmits the light to the light receiving surface (sensor section) of the photoelectric conversion device 2708. Form an image.

[0235] The photoelectric conversion device 2708 is any of the photoelectric conversion devices of the first to fourth embodiments described above, and a distance signal indicating the distance determined from the light receiving signal output from the photoelectric conversion device 2708 is supplied to the image processing circuit 2704.

[0236] The image processing circuit 2704 performs image processing to construct a distance image based on the distance signal supplied from the photoelectric conversion device 2708. The distance image (image data) obtained by this image processing is then supplied to a monitor 2705 for display, or supplied to a memory 2706 for storage (recording).

[0237] In the range image sensor 2701 configured in this way, by applying the above-described photoelectric conversion device, it is possible to obtain, for example, a more accurate range image as the pixel characteristics improve.

[0238] (Eighth embodiment) The photoelectric conversion system of this embodiment will be described with reference to Fig. 23. Fig. 23 is a diagram showing an example of the schematic configuration of an endoscopic surgery system, which is the photoelectric conversion system of this embodiment.

[0239] 23 shows a state in which an operator (doctor) 2831 is performing surgery on a patient 2832 on a patient bed 2833 using an endoscopic surgery system 2850. As shown in the figure, the endoscopic surgery system 2850 is composed of an endoscope 2800, a surgical tool 2810, and a cart 2834 on which various devices for endoscopic surgery are mounted.

[0240] The endoscope 2800 is composed of a lens barrel 2801, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 2832, and a camera head 2802 connected to the base end of the lens barrel 2801. In the example shown in the figure, the endoscope 2800 is configured as a so-called rigid lens barrel having a rigid lens barrel 2801, but the endoscope 2800 may also be configured as a so-called flexible lens barrel having a flexible lens barrel.

[0241] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 2801. A light source device 2803 is connected to the endoscope 2800. Light generated by the light source device 2803 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 2801, and is irradiated via the objective lens towards an observation target inside the body cavity of the patient 2832. Note that the endoscope 2800 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0242] An optical system and a photoelectric conversion device are provided inside the camera head 2802, and light reflected from the observation object (observation light) is focused onto the photoelectric conversion device by the optical system. The observation light is captured by the photoelectric conversion device, and an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observation image, is generated. The photoelectric conversion device may be any of the photoelectric conversion devices described in the above-described embodiments. The image signal is transmitted as RAW data to a camera control unit (CCU) 2835.

[0243] The CCU 2835 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 2800 and the display device 2836. Furthermore, the CCU 2835 receives an image signal from the camera head 2802 and performs various image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal. To apply reason.

[0244] The display device 2836, under the control of the CCU 2835, displays an image based on the image signal that has been subjected to image processing by the CCU 2835.

[0245] The light source device 2803 is configured from a light source such as an LED (Light Emitting Diode), and supplies the endoscope 2800 with irradiation light when photographing an operation site or the like.

[0246] The input device 2837 is an input interface for the endoscopic surgery system 2850. A user can input various information and instructions to the endoscopic surgery system 2850 via the input device 2837.

[0247] The treatment tool control device 2838 controls the driving of the energy treatment tool 2812 for cauterizing tissue, incising, sealing blood vessels, or the like.

[0248] The light source device 2803 that supplies illumination light to the endoscope 2800 when photographing the surgical site can be configured from a white light source configured from, for example, an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, making it possible to adjust the white balance of the captured image in the light source device 2803. In this case, it is also possible to capture images corresponding to each RGB in a time-division manner by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 2802 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0249] Furthermore, the driving of the light source device 2803 may be controlled so as to change the intensity of the light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 2802 in synchronization with the timing of the change in the light intensity to acquire images in a time-division manner and combining these images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0250] The light source device 2803 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation utilizes, for example, the wavelength dependency of light absorption in body tissue. Specifically, by irradiating light with a narrower band than the light (i.e., white light) used in normal observation, a specific tissue, such as blood vessels on the surface of a mucous membrane, can be photographed with high contrast. Alternatively, special light observation may involve fluorescence observation, in which an image is obtained using fluorescence generated by irradiating excitation light. Fluorescence observation can involve irradiating excitation light onto a body tissue and observing the fluorescence from the body tissue, or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 2803 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0251] Ninth Embodiment The photoelectric conversion system of this embodiment will be described with reference to FIGS. 24(A) and 24(B). FIG. 24(A) describes glasses 2900 (smart glasses) which are the photoelectric conversion system of this embodiment. The glasses 2900 have a photoelectric conversion device 2902. The photoelectric conversion device 2902 is the photoelectric conversion device described in the first to fourth embodiments. A display device including a light-emitting device such as an OLED or LED may be provided on the rear side of the lens 2901. The photoelectric conversion device 2902 may be one or more. A combination of multiple types of photoelectric conversion devices may also be used. The arrangement position of the photoelectric conversion device 2902 is not limited to that shown in FIG. 24(A). do not have.

[0252] The glasses 2900 further include a control device 2903. The control device 2903 functions as a power source that supplies power to the photoelectric conversion device 2902 and the display device. The control device 2903 also controls the operations of the photoelectric conversion device 2902 and the display device. The lens 2901 is formed with an optical system for focusing light onto the photoelectric conversion device 2902.

[0253] FIG. 24(B) illustrates glasses 2910 (smart glasses) according to one application example. The glasses 2910 include a control device 2912, which includes a photoelectric conversion device corresponding to the photoelectric conversion device 2902 and a display device. A lens 2911 includes an optical system for projecting light emitted from the photoelectric conversion device and the display device, and an image is projected onto the lens 2911. The control device 2912 functions as a power source for supplying power to the photoelectric conversion device and the display device, and controls the operation of the photoelectric conversion device and the display device. The control device may include a gaze detection unit for detecting the gaze of the wearer. Infrared light may be used for gaze detection. The infrared light emitter emits infrared light toward the eyeball of a user gazing at a displayed image. An imaging unit with a light receiving element detects the reflected light of the emitted infrared light from the eyeball, thereby obtaining an image of the eyeball. A reduction unit for reducing light from the infrared light emitter to the display unit in a planar view reduces degradation of image quality.

[0254] The gaze of the user relative to the displayed image is detected from an image of the eyeball obtained by capturing infrared light. Any known method can be used for gaze detection using an image of the eyeball. One example is a gaze detection method based on the Purkinje image formed by reflection of irradiated light on the cornea.

[0255] More specifically, gaze detection processing is performed based on the pupil-corneal reflex method, which calculates a gaze vector representing the direction (rotation angle) of the eyeball based on the pupil image and Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0256] The display device of this embodiment may have a photoelectric conversion device having a light receiving element, and may control the image displayed on the display device based on information about the user's line of sight from the photoelectric conversion device.

[0257] Specifically, the display device determines a first field of view area where the user gazes and a second field of view area other than the first field of view area based on the line-of-sight information. The first field of view area and the second field of view area may be determined by a control device of the display device, or may be determined by an external control device and received. In the display area of ​​the display device, the display resolution of the first field of view area may be controlled to be higher than the display resolution of the second field of view area. In other words, the resolution of the second field of view area may be lower than that of the first field of view area.

[0258] The display area may also include a first display area and a second display area different from the first display area, and a high-priority area may be determined from the first display area and the second display area based on line-of-sight information. The first display area and the second display area may be determined by a control device of the display device, or may be determined by an external control device and received. The resolution of the high-priority area may be controlled to be higher than the resolution of areas other than the high-priority area. In other words, the resolution of an area with a relatively low priority may be lowered.

[0259] Note that AI may be used to determine the first field of view area and areas with high priority. The AI ​​may be a model configured to estimate the angle of gaze and the distance to an object in the line of sight from an image of the eyeball, using as training data an image of the eyeball and the direction in which the eyeball in the image was actually looking. The AI ​​program may be included in the display device, the photoelectric conversion device, or an external device. If included in an external device, it is transmitted to the display device via communication.

[0260] When display control is performed based on visual recognition detection, the present invention is preferably applied to smart glasses that further include a photoelectric conversion device for capturing images of the outside world. The smart glasses can display captured external information in real time.

[0261] Tenth Embodiment The above-described photoelectric conversion device and photoelectric conversion system may be applied to electronic devices such as so-called smartphones and tablets.

[0262] 25(A) and 25(B) are diagrams showing an example of an electronic device 3000 equipped with a photoelectric conversion device. Fig. 25(A) shows the front side of the electronic device 3000, and Fig. 25(B) shows the back side of the electronic device 3000.

[0263] 25(A), a display 3010 for displaying an image is disposed in the center of the surface of electronic device 3000. Further, along the upper side of the surface of electronic device 3000, front cameras 3021 and 3022 using photoelectric conversion devices, an IR light source 3030 for emitting infrared light, and a visible light source 3040 for emitting visible light are disposed.

[0264] Also, as shown in Figure 25(B), rear cameras 3051 and 3052 using photoelectric conversion devices, an IR light source 3060 that emits infrared light, and a visible light source 3070 that emits visible light are arranged along the upper edge of the back of the electronic device 3000.

[0265] In the electronic device 3000 configured as described above, by applying the photoelectric conversion device according to any one of the first to fourth embodiments described above, it is possible to capture, for example, higher quality images. Note that the photoelectric conversion device can also be applied to other electronic devices such as infrared sensors, distance measuring sensors using active infrared light sources, security cameras, and personal or biometric authentication cameras. This can improve the accuracy and performance of these electronic devices.

[0266] Eleventh Embodiment A photoelectric conversion system according to the eleventh embodiment will be described with reference to Fig. 26. Fig. 26 is a block diagram showing a schematic configuration of a photoelectric conversion system SYS, which is a photoelectric conversion system according to the eleventh embodiment. The photoelectric conversion system SYS includes at least a photoelectric conversion device according to any one of the first to fourth embodiments described above, and a signal processing unit that processes a signal output from the photoelectric conversion device.

[0267] The photoelectric conversion system SYS is an information terminal having a camera or a photographing function. The photoelectric conversion system SYS is constructed using a photoelectric conversion device IS. The photoelectric conversion device IS may further include a package PKG that houses an imaging device IC. The package PKG may include a base to which the imaging device IC is fixed and a lid that faces the imaging device IC. The package PKG may include a connecting member (a member that connects terminals provided on the base with terminals provided on the imaging device IC). The photoelectric conversion device IS may also mount multiple imaging device ICs side by side in a common package PKG. Furthermore, the photoelectric conversion device IS may also mount an imaging device IC and other semiconductor device ICs stacked on top of each other in a common package PKG.

[0268] The photoelectric conversion system SYS may include an optical system OU (optical device) that forms an image on the photoelectric conversion device IS. The photoelectric conversion system SYS may also include at least one of a control device CU, a processing device PU, a display device DU, and a storage device MU. The control device CU controls the photoelectric conversion device IS, and the processing device PU processes signals obtained from the photoelectric conversion device IS. The display device The device DU displays the image obtained from the photoelectric conversion device IS, and the memory device MU stores the image obtained from the photoelectric conversion device IS.

[0269] (others) Although various devices have been described in the above embodiments, a mechanical device may also be included. The mechanical device in the camera can drive optical components for zooming, focusing, and shutter operation. Alternatively, the mechanical device in the camera can move a photoelectric conversion device for vibration reduction.

[0270] The equipment may also be transportation equipment such as a vehicle, a ship, or an aircraft. A mechanical device in the transportation equipment category may be used as a moving device. Equipment serving as transportation equipment is suitable for transporting a photoelectric conversion device or for assisting and / or automating driving (piloting) using a photographing function. A processing device for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device as a moving device based on information obtained by the photoelectric conversion device.

[0271] The embodiments described above can be modified as appropriate within the scope of the technical concept. The disclosure of this specification includes not only what is described in this specification, but also all matters that can be understood from this specification and the drawings attached hereto.

[0272] The disclosure of this embodiment includes the following configuration. (Configuration 1) an AD conversion unit that performs analog-to-digital conversion to obtain a digital value corresponding to the pixel signal using a pixel that outputs a pixel signal and a ramp signal whose signal voltage changes at a predetermined voltage change rate over time; the AD conversion unit includes an amplifier circuit that controls an amplification factor of the pixel signal, an amplification factor switching circuit that switches the amplification factor, a ramp signal switching circuit that switches the voltage change rate of the ramp signal, a comparison circuit that outputs a comparison result signal generated from the amplified pixel signal output from the amplifier circuit and the ramp signal, and a memory unit that holds a plurality of determination values ​​corresponding to the comparison result signal, a first signal is generated by comparing the amplified pixel signal with one first threshold voltage value selected from M-1 (M>1) threshold voltages, and the ramp signal switching circuit is capable of switching the voltage change rate of the ramp signal in M ​​ways based on a first determination value corresponding to the first signal; a second signal is generated by comparing the amplified pixel signal with one second threshold voltage value selected from N-1 (N>1) threshold voltages generated by the ramp signal, and the amplification factor switching circuit is capable of switching the amplification factor of the amplifier circuit among N different values ​​based on a second determination value corresponding to the second signal; the AD conversion unit performs analog-to-digital conversion using the voltage change rate of the ramp signal and the amplification factor of the amplifier circuit, which are selected from three or more combinations of less than M×N combinations of switching the voltage change rate of the ramp signal and switching the amplification factor of the amplifier circuit using the first determination value and the second determination value, out of M×N combinations resulting from combinations of switching the voltage change rate of the ramp signal and switching the amplification factor of the amplifier circuit. (Configuration 2) The photoelectric conversion device described in configuration 1, characterized in that the first signal and the second signal are generated in that order, and the maximum threshold voltage value included in the first threshold voltage value is smaller than the minimum threshold voltage value included in the second threshold voltage value. (Configuration 3) The photoelectric conversion device according to configuration 1, wherein the second signal and the first signal are generated in that order, and the first determination value is a value set in combination with the second determination value. Place. (Configuration 4) The photoelectric conversion device described in configuration 1, characterized in that the second signal and the first signal are generated in that order, and the maximum threshold voltage value included in the second threshold voltage values ​​is smaller than the minimum threshold voltage value included in the first threshold voltage values. (Configuration 5) 5. The photoelectric conversion device according to any one of configurations 1 to 4, wherein the memory section holds information of 2 or more bits. (Configuration 6) The pixels are arranged in multiple rows and multiple columns, each of the AD conversion units includes a plurality of AD conversion units arranged in a corresponding one of the plurality of columns; the pixel signals are output row by row from the pixels in the plurality of rows to corresponding AD conversion units among the plurality of AD conversion units; 6. The photoelectric conversion device according to any one of configurations 1 to 5, wherein during a period from when the pixel signals output from pixels in a predetermined row are input to the plurality of AD conversion units until the pixel signals output from pixels in another row are subsequently input to the plurality of AD conversion units, each of the plurality of AD conversion units performs analog-to-digital conversion on the pixel signals output from the pixels in the predetermined row using the voltage change rate of the ramp signal and the amplification factor of the amplifier circuit that are selected from three or more combinations using the first determination value and the second determination value, with the combination being less than M×N. (Configuration 7) The photoelectric conversion device according to any one of configurations 1 to 6, a signal processing unit that generates an image using a signal output from the photoelectric conversion device; A photoelectric conversion system comprising: (Configuration 8) A moving object including the photoelectric conversion device according to any one of configurations 1 to 6, a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device; A moving object characterized by: (Configuration 9) The photoelectric conversion device according to any one of configurations 1 to 6, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and a mechanical device that operates based on information obtained by the photoelectric conversion device; At least one of An apparatus characterized by having: [Explanation of symbols]

[0273] 101 pixels 104 column circuit 301 Column Amplifier 302 Amplification rate switching circuit 303 Comparison circuit 304 Lamp signal switching circuit 305A N Memory 305B S memory 305C Judgment value memory

Claims

1. an AD conversion unit that performs analog-to-digital conversion to obtain a digital value corresponding to the pixel signal using a pixel that outputs a pixel signal and a ramp signal whose signal voltage changes at a predetermined voltage change rate over time; the AD conversion unit includes an amplifier circuit that controls an amplification factor of the pixel signal, an amplification factor switching circuit that switches the amplification factor, a ramp signal switching circuit that switches the voltage change rate of the ramp signal, a comparison circuit that outputs a comparison result signal generated from the amplified pixel signal output from the amplifier circuit and the ramp signal, and a memory unit that holds a plurality of determination values ​​corresponding to the comparison result signal, a first signal is generated by comparing the amplified pixel signal with one first threshold voltage value selected from M−1 (M>1) threshold voltages, and the ramp signal switching circuit is capable of switching the voltage change rate of the ramp signal in M ​​ways based on a first determination value corresponding to the first signal; a second signal is generated by comparing the amplified pixel signal with one second threshold voltage value selected from N-1 (N>1) threshold voltages generated by the ramp signal, and the amplification factor switching circuit is capable of switching the amplification factor of the amplifier circuit among N different values ​​based on a second determination value corresponding to the second signal; the AD conversion unit performs analog-to-digital conversion using the voltage change rate of the ramp signal and the amplification factor of the amplifier circuit, which are selected from less than M×N combinations of switching the voltage change rate of the ramp signal and switching the amplification factor of the amplifier circuit using the first determination value and the second determination value, among M×N combinations of combinations of switching the voltage change rate of the ramp signal and switching the amplification factor of the amplifier circuit.

2. 2. The photoelectric conversion device according to claim 1, wherein the first signal and the second signal are generated in that order, and the maximum threshold voltage value included in the first threshold voltage value is smaller than the minimum threshold voltage value included in the second threshold voltage value.

3. 2. The photoelectric conversion device according to claim 1, wherein the second signal and the first signal are generated in that order, and the first determination value is a value set in combination with the second determination value.

4. 2. The photoelectric conversion device according to claim 1, wherein the second signal and the first signal are generated in that order, and the maximum threshold voltage value included in the second threshold voltage value is smaller than the minimum threshold voltage value included in the first threshold voltage value.

5. 2. The photoelectric conversion device according to claim 1, wherein the memory section holds information of 2 bits or more.

6. The pixels are arranged in multiple rows and multiple columns, each of the AD conversion units includes a plurality of AD conversion units arranged in a corresponding one of the plurality of columns; the pixel signals are output row by row from the plurality of rows of pixels to corresponding AD conversion units among the plurality of AD conversion units; During a period from when the pixel signals output from pixels in a predetermined row are input to the plurality of AD conversion units until the pixel signals output from pixels in another row are input to the plurality of AD conversion units, each of the plurality of AD conversion units performs analog-to-digital conversion on the pixel signals output from the pixels in the predetermined row using the voltage change rate of the ramp signal and the amplification factor of the amplifier circuit, which are selected from three or more combinations using the first determination value and the second determination value, with the number of combinations being less than M×N. The photoelectric conversion device according to claim 1 .

7. The photoelectric conversion device according to any one of claims 1 to 6, a signal processing unit that generates an image using a signal output from the photoelectric conversion device; A photoelectric conversion system comprising:

8. A moving object comprising the photoelectric conversion device according to any one of claims 1 to 6, a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device; A moving object characterized by:

9. The photoelectric conversion device according to any one of claims 1 to 6, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and a mechanical device that operates based on information obtained by the photoelectric conversion device; At least one of An apparatus characterized by having:

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