Semiconductor package

Abstract

To provide a semiconductor package with reliability improved.SOLUTION: A semiconductor package according to the present invention includes: a package substrate; an interposer die disposed on the package substrate and including a re-wiring structure, in which the re-wiring structure includes an insulating layer containing an organic substance and a re-wiring layer in the insulating layer; a passive element disposed in the interposer die, connected to the re-wiring layer, and including a first electrode and a dielectric film on the first electrode, and a second electrode on the dielectric film; and semiconductor chips disposed apart from each other in a direction parallel to an upper surface of the insulating layer on the interposer die and electrically connected to the package substrate through the re-wiring layer. The thickness of the passive element is 50 μm or less and at least a part of the dielectric film of the passive element has a crystalline structure.SELECTED DRAWING: Figure 1a

Description

[Technical Field]

[0001] The present invention relates to a semiconductor package, and more particularly to a semiconductor package with improved reliability. [Background technology]

[0002] 2. Description of the Related Art With the development of the electronics industry and user demands, electronic devices are becoming smaller and lighter, and semiconductor packages used in electronic devices are being required to be smaller and lighter, as well as have higher performance and larger capacity. 2. Description of the Related Art In order to achieve high performance and large capacity together with miniaturization and weight reduction, research and development of semiconductor packages including passive elements such as capacitors for improving the performance of semiconductor chips is being continuously carried out. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made in view of the above-mentioned problems with conventional semiconductor packages, and an object of the present invention is to provide a semiconductor package with improved reliability. [Means for solving the problem]

[0004] In order to achieve the above object, the semiconductor package according to the present invention comprises a package substrate, an interposer die disposed on the package substrate and including a redistribution structure, wherein the redistribution structure includes an insulating layer containing an organic material and a redistribution layer in the insulating layer, a passive element disposed in the interposer die and connected to the redistribution layer, the passive element including a first electrode, a dielectric film on the first electrode, and a second electrode on the dielectric film, and a semiconductor chip disposed on the interposer die and spaced apart in a direction horizontal to an upper surface of the insulating layer, and electrically connected to the package substrate via the redistribution layer, wherein the thickness of the passive element is 50 μm or less, and at least a portion of the dielectric film of the passive element has a crystalline structure.

[0005] In addition, the semiconductor package according to the present invention, which has been made to achieve the above-mentioned object, comprises a redistribution structure including a passive element, an insulating layer containing an organic material and covering the side and top surfaces of the passive element, and a redistribution layer disposed within the insulating layer and connected to the passive element, a first semiconductor chip and a second semiconductor chip disposed spaced apart from each other on the redistribution structure and connected to the redistribution layer, and a lower connection pad disposed below the redistribution structure, wherein a portion of the lower connection pad contacts the lower surface of the passive element.

[0006] In addition, the semiconductor package according to the present invention, which has been made to achieve the above-mentioned object, comprises a package substrate, an interposer die which includes a support layer disposed on the package substrate and which includes a cavity, an insulating layer disposed on the support layer, and a rewiring layer disposed within the insulating layer, a passive element disposed within the cavity of the support layer and connected to the rewiring layer, and a semiconductor chip disposed on the interposer die and electrically connected to the package substrate via the rewiring layer, wherein the upper surface of the passive element is in contact with the lower surface of the insulating layer. [Effects of the Invention]

[0007] According to the semiconductor package of the present invention, a semiconductor package with improved reliability can be provided by introducing a semiconductor package having a structure including thin passive elements having a certain thickness or less inside an interposer including a rewiring structure. [Brief explanation of the drawings]

[0008] [Figure 1a] 1 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 1b] 1 is a plan view showing a semiconductor package according to an embodiment of the present invention; [Figure 2] 1 is a cross-sectional view showing a passive element according to an embodiment of the present invention. [Figure 3]1 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 4] 1 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 5] 1 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 6] 1 is a plan view showing a semiconductor package according to an embodiment of the present invention; [Figure 7] 1 is a plan view showing a semiconductor package according to an embodiment of the present invention; [Figure 8] 1 is a plan view showing a semiconductor package according to an embodiment of the present invention; [Figure 9] 1 is a plan view showing a semiconductor package according to an embodiment of the present invention; [Figure 10a] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 10b] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 10c] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11a] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11b] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11c] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11d] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11e] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11f] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11g] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 12a] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 12b] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 12c] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] Next, specific examples of embodiments for carrying out a semiconductor package according to the present invention will be described with reference to the drawings.

[0010] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Hereinafter, terms such as "top," "upper portion," "upper surface," "bottom," "lower portion," "lower surface," and "side surface" are used as reference numerals, and unless otherwise specified, they may be understood to be referred to based on the drawings.

[0011] FIG. 1a is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention, and FIG. 1b is a plan view showing the semiconductor package according to the embodiment of the present invention. For ease of explanation, only some of the components are shown in FIG. 1b. FIG. 2 is a cross-sectional view showing a passive element according to an embodiment of the present invention.

[0012] 1a to 2, a semiconductor package 10 includes a package substrate 100, an interposer die 200, a passive component 300, and a semiconductor chip 400. The interposer die 200 includes a redistribution structure 220, and the semiconductor chip 400 includes a first semiconductor chip 400A and a second semiconductor chip 400B.

[0013] The package substrate 100 is a support substrate on which the interposer die 200 and the semiconductor chip 400 are mounted, and may be a semiconductor package substrate including a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape wiring substrate, or the like. The package substrate 100 includes a substrate body 110 , upper pads 120 , lower pads 160 , a wiring circuit 130 that electrically connects the upper pads 120 and the lower pads 160 , and external connection terminals 170 .

[0014] The substrate body 110 may include different materials depending on the type. For example, when the package substrate 100 is a printed circuit board, it may be a copper clad laminate of the main body or a copper clad laminate having wiring layers laminated on its cross section or both sides. The substrate body 110 may include an insulating material that electrically and physically protects the wiring circuit 130, for example, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a prepreg containing inorganic filler and / or glass fiber (glass cloth, glass fabric), ABF (Ajinomoto Build-up Film), FR4 (Frame Retardant 4), etc.

[0015] The upper pads 120 , the lower pads 160 , and the wiring circuit 130 form an electrical path connecting the lower surface and the upper surface of the package substrate 100 . The wiring circuit 130 may include at least one metal or an alloy composed of two or more metals selected from copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C). On the lower surface of the substrate body 110, external connection terminals 170 connected to the lower pads 160 are arranged. The external connection terminals 170 include, for example, solder balls. The solder balls may include tin (Sn), bismuth (Bi), lead (Pb), silver (Ag), or alloys thereof.

[0016] The interposer die 200 is disposed on the package substrate 100 . The interposer die 200 may be a support substrate on which the semiconductor chip 400 is mounted, and is disposed between the package substrate 100 and the semiconductor chip 400 . The interposer die 200 includes redistribution structures 220 , bottom connection pads 260 , and connection conductors 270 . The redistribution structure 220 includes an insulating layer 221 , an upper connection pad 222 , a redistribution layer 223 , and a redistribution via 224 .

[0017] The insulating layer 221 has opposing upper and lower surfaces. The semiconductor chip 400 is mounted on the upper surface of the insulating layer 221 , and the lower surface of the insulating layer 221 faces the package substrate 100 . The insulating layer 221 covers the top and side surfaces of the passive element 300 . The insulating layer 221 may include an organic material. For example, the insulating layer 221 includes a photosensitive polymer. The photosensitive polymer may include, for example, at least one of a photosensitive polyimide, a polybenzoxazole, a phenolic polymer, and a benzocyclobutene-based polymer. In one embodiment, the insulating layer 221 includes multiple insulating layers (not shown) stacked in a vertical direction (eg, the Z direction). In some processes, the boundaries between multiple insulating layers (not shown) may be unclear.

[0018] The upper connection pads 222 are disposed on the insulating layer 221 . The upper connection pads 222 electrically connect the semiconductor chip 400 to the redistribution layer via the connection pillars 460 and the connection solder 470 . The upper connection pad 222 may include a metal including, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The upper connection pads 222 may include more or fewer than those shown in the figure.

[0019] The redistribution layer 223 is disposed within the insulating layer 221 . In one embodiment, the redistribution layer 223 is disposed at the same level as or higher than the top surface of the passive components 300 . The upper surface of the lower redistribution layer 223 a , which is located at the lowest level among the redistribution layers 223 , is located at the same level as or higher than the upper surface of the passive element 300 . A part of the lower rewiring layer 223 a is connected to the passive element 300 through a rewiring via 224 . In one embodiment, unlike the one shown in the figure, a portion of the lower redistribution layer 223a may be in direct contact with and connected to the top surface of the passive element 300. In one embodiment, unlike what is shown in the figure, the upper surface of the lower redistribution layer 223a may be positioned at a higher level than the upper surface of the passive element 300, and the lower surface of the lower redistribution layer 223a may be positioned at a lower level than the upper surface of the passive element 300.

[0020] Redistribution layers 223 may include more or fewer than those shown in the figure. The redistribution layer 223 performs various functions depending on the design. For example, the redistribution layer 223 may include a ground (GND) pattern, a power (PWR) pattern, and a signal (S) pattern. Here, the signal (S) pattern can be defined as a transmission path for various signals, such as data signals, excluding the ground (GND) pattern, power (PWR) pattern, and the like. The redistribution layer 223 may include metals including, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof.

[0021] The redistribution vias 224 extend vertically within the insulating layer 221 and connect the redistribution layer 223, the upper connection pads 222, the lower connection pads 260, and the passive elements 300, which are arranged at different levels. The redistribution vias 224 may include signal vias, ground vias, and power vias. The redistribution vias 224 may include metallic materials including, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution via 224 may be a filled via in which a metal material is filled inside a via hole, or a conformal via in which a metal material extends along the inner wall of a via hole. In one embodiment, redistribution vias 224 may have sloped sides, unlike those shown in the figures. For example, the redistribution via 224 may have a side surface that is inclined so that its width increases toward the upper surface of the insulating layer 221, or conversely, may have a side surface that is inclined so that its width increases toward the lower surface of the insulating layer 221.

[0022] The lower connection pads 260 are disposed below the lower surface of the insulating layer 221 . The lower connection pads 260 include a first lower connection pad 260 a that contacts the passive element 300 and a second lower connection pad 260 b that contacts the insulating layer 221 . The first lower connection pad 260 a contacts the lower surface of the passive element 300 . The first lower connection pads 260a may include more or fewer than those shown in the figure. Unlike the one shown in the figure, in one embodiment, the first lower connection pad 260a can contact the lower surface of the passive element 300 and the lower surface of the insulating layer 221 simultaneously. The second lower connection pad 260b contacts the lower surface of the insulating layer 221 and electrically connects the rewiring via 224 and the connection conductor 270. The second lower connection pads 260b may include more or fewer than those shown in the figure. The lower contact pad 260 may comprise a metallic material including, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof.

[0023] The connecting conductors 270 are disposed below the lower connection pads 260 and connect the lower connection pads 260 to the upper pads 120 of the package substrate 100 . The connecting conductors 270 may include, for example, solder balls, which may include tin (Sn), bismuth (Bi), lead (Pb), silver (Ag), or alloys thereof.

[0024] The passive element 300 is disposed within the insulating layer 221 . The passive element 300 is disposed closer to the lower surface of the insulating layer 221 than to the upper surface of the insulating layer 221 . In one embodiment, the bottom surface of the passive element 300 is exposed and not covered by the insulating layer 221 . The passive element 300 is located at a level lower than the lower wiring layer 223a. The passive element 300 contacts a portion of the lower connection pad 260 . The lower surface of the passive element 300 contacts the upper surface of the first lower connection pad 260 . The upper and lower surfaces of the passive element 300 have the same planar area, but are not limited to this. The planar shape of the passive element 300 may be, but is not limited to, a quadrilateral shape.

[0025] The passive element 300 is disposed so as to overlap the semiconductor chip 400 . In this specification, "overlapping" means overlapping in a direction perpendicular to the top surface of insulating layer 221. In one embodiment, a portion of the passive element 300 may overlap with the first semiconductor chip 400A, another portion may overlap with the second semiconductor chip 400B, and the remaining portion may not overlap with the semiconductor chip 400A. In one embodiment, the passive component 300 has a larger area overlapping with the first semiconductor chip 400A, which is a logic chip, than with the second semiconductor chip 400B, which is a memory chip. The semiconductor package 10 may include a plurality of passive elements 300, different from those shown in the figure.

[0026] The passive element 300 may be a capacitor. In one embodiment, the passive element 300 may be a thin film capacitor (TFC). The thickness T of the passive element 300 may be 50 μm or less. In this specification, the term "thickness" refers to the thickness in a direction perpendicular to the top surface of the insulating layer 221 (for example, the Z direction). The passive element 300 includes a first electrode 311 , a dielectric film 320 on the first electrode 311 , and a second electrode 312 on the dielectric film 320 . The first electrode 311 and the second electrode 312 include a conductive material. For example, the first electrode 311 and the second electrode 312 include a metal material. In one embodiment, the first electrode 311 and the second electrode 312 may include different metal materials. For example, if the first electrode 311 includes nickel (Ni), the second electrode includes copper (Cu).

[0027] In one embodiment, at least a portion of the dielectric film 320 has a crystalline structure. In one embodiment, the dielectric film 320 includes both a portion having a crystalline structure and a portion having an amorphous structure, but the specific gravity of the portion having the crystalline structure is greater than the specific gravity of the portion having the amorphous structure. The dielectric film 320 includes a material having a crystalline structure. In one embodiment, the dielectric film 320 comprises a conductive polymer or a metal oxide. In one embodiment, the dielectric film 320 may be free of silicon (Si). In one embodiment, the dielectric film 320 may include barium titanate (BaTiO3).

[0028] The first electrode 311 has a first thickness T1, the second electrode 312 has a second thickness T2, and the dielectric film 320 has a third thickness T3. The first thickness T1, the second thickness T2, and the third thickness T3 may be different from each other. In one embodiment, the third thickness T3 is less than the first thickness T1 and the second thickness T2. In one embodiment, the first thickness T1 is less than or equal to 30 μm. In one embodiment, the second thickness T2 is less than or equal to 25 μm. In one embodiment, the third thickness T3 may be less than or equal to 10 μm, less than or equal to 5 μm, or less than or equal to 1 μm. In one embodiment, the third thickness T3 is less than the second thickness T2, which is less than the first thickness T1. The passive element 300 is disposed within the interposer die 200 such that the first electrode 311 faces downward and the second electrode 312 faces upward. In this case, the lower surface of the first electrode 311 constitutes the lower surface of the passive element 300 , and the upper surface of the second electrode 312 constitutes the upper surface of the passive element 300 . Conversely, in one embodiment, passive component 300 may be positioned within interposer die 200 with first electrode 311 facing upward and second electrode 312 facing downward.

[0029] By placing a thin film-like passive element 300 within the interposer die 200, the present invention can further secure the area on the top surface of the interposer die 200 on which the semiconductor chip 400 is mounted, thereby improving the power integrity (PI) of the semiconductor chip 400.

[0030] The semiconductor chip 400 is mounted on the interposer die 200 and is electrically connected to the package substrate 100 via the interposer die 200 . The semiconductor chip 400 may include multiple semiconductor chips 400 disposed on the interposer die 200 . For example, the semiconductor chip 400 includes a first semiconductor chip 400A and a second semiconductor chip 400B arranged in parallel on the interposer die 200. The first semiconductor chip 400A and the second semiconductor chip 400B may include different types of semiconductor chips. For example, in one embodiment, the first semiconductor chip 400A includes a logic chip and the second semiconductor chip 400B includes a memory chip. In this case, the second semiconductor chip 400B is provided as a high-capacity memory device such as a High Bandwidth Memory (HBM). The number of semiconductor chips 400 may be greater than that shown in the figure. In one embodiment, the passive components 300 may be placed closer to the first semiconductor chip 400A that includes a logic chip than to the second semiconductor chip 400B that includes a memory chip in order to improve the functionality of the first semiconductor chip 400A. Although not specifically shown, depending on the embodiment, a separate chiplet, a heat dissipation structure, or an encapsulant that encapsulates at least a portion of these may be arranged around the semiconductor chip 400 on the interposer die 200.

[0031] In the following description, the same description as that given with reference to FIGS. 1a to 2 will be omitted. FIG. 3 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention.

[0032] 3, a semiconductor package 10A differs from the semiconductor package 10 of FIGS. 1a and 1b in that the redistribution layer 223 is disposed at a level lower than the upper surface of the passive element 300. In the semiconductor package 10A of FIG. That is, the lower rewiring layer 223 a located at the lowest level among the rewiring layers 223 is located at a level lower than the upper surface of the passive element 300 . The relative level of the lower redistribution layer 223 and the passive element 300 may vary depending on the thickness of the passive element 300 or the process method of the redistribution structure 220 .

[0033] FIG. 4 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. 4, a semiconductor package 10B differs from the semiconductor package 10 of FIGS. 1a-1b in that the interposer die 200 further includes a support layer 210 that includes a cavity 215. Interposer die 200 further includes through vias 230 and connecting vias 235 . The interposer die 200 further includes an encapsulant 240 and a protective layer 250 .

[0034] Support layer 210 is the substrate on which redistribution structure 220 is placed. The support layer 210 can be formed of any one of silicon, organic, plastic, and glass substrates. The thickness of the support layer 210 is greater than the thickness of the passive element 300 . The insulating layer 221 is disposed on the support layer 210 . The support layer 210 includes a cavity 215 in the center. The cavity 215 is a space that passes through the support layer 210 in the vertical direction (for example, the Z direction), in which the passive element 300 is disposed and in which the sealing material 240 is filled.

[0035] The lower surface of the lower redistribution layer 223 a , which is located at the lowest level among the redistribution layers 223 , is coplanar with the lower surface of the insulating layer 221 and is in contact with the support layer 210 . The lower connection pads 260 and connection conductors 270 are disposed below the support layer 210 .

[0036] The encapsulant 240 fills the cavity 215 and surrounds the passive components 300 . The encapsulant 240 encapsulates the passive element 300 within the cavity 215 . The encapsulant 240 protects and secures the passive element 300 within the cavity 215 . The top surface of the encapsulant 240 is coplanar with the top surfaces of the passive elements 300 and the support layer 210 and is in contact with the insulating layer 221 . The encapsulant 240 may include an insulating material, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a prepreg, ABF, FR-4, BT, or EMC (Epoxy Molding Compound) in which inorganic fillers are impregnated into these resins. For example, the encapsulant 140 includes an EMC.

[0037] The protective layer 250 covers the lower surface of the encapsulant 240 and the lower surface of the support layer 210 . The protective layer 250 surrounds the sides of the through vias 230 and the connecting vias 235 at a level lower than the lower surface of the encapsulant 240 and the lower surface of the support layer 210 . The protective layer 250 includes an insulating material. For example, the protective layer 250 includes an insulating polymer. In one embodiment, the protective layer 250 may comprise the same material as the encapsulant 240 . In this case, unlike the one shown in the figure, the sealing material 240 and the protective layer 250 may be an integral single structure. The protective layer 250 provides physical and chemical protection to the support layer 210 and the encapsulant 240 . In one embodiment, interposer die 200 may not include protective layer 250 .

[0038] The through via 230 is a through silicon via (TSV) that penetrates the support layer 210 and the protective layer 250 in the vertical direction (for example, the Z direction). The through vias 230 provide an electrical path connecting the redistribution layer 233 and the lower connection pads 260 . The lower connection pad 260 in contact with the through via 230 may be a second lower connection pad 260b. The through via 230 includes a conductive plug and a barrier film surrounding it. The conductive plug includes a metal material, such as tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu). The conductive plugs can be formed by a plating process, a PVD process, or a CVD process.

[0039] The barrier film includes an insulating barrier film and / or a conductive barrier film. The insulating barrier film may be made of an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof. The conductive barrier film may include, for example, a metal compound such as tungsten nitride (WN), titanium nitride (TiN), or tantalum nitride (TaN). The barrier film can be formed by a PVD process or a CVD process. Through vias 230 may include more or fewer than those shown in the figure. Depending on the embodiment, unlike the one shown in the figure, multiple through vias 230 may be connected to one second lower connection pad 260b. For example, one second lower connection pad 260b can be connected to two through vias 230. In one embodiment, unlike that shown in the figure, the through via 230 may have sloped sides. For example, the through via 230 may have a side surface that slopes so that its width increases toward the upper surface of the support layer 210 , or conversely, may have a side surface that slopes so that its width increases toward the lower surface of the support layer 210 .

[0040] The connection via 235 penetrates the encapsulant 240 and the protective layer 250 in the vertical direction (eg, Z direction) in the area overlapping the passive element 300 to provide an electrical path connecting the passive element 300 and the first lower connection pad 260a. The connection via 235 is located between the passive element 300 and the first lower connection pad 260a, and contacts the lower surface of the passive element 300 and the upper surface of the first lower connection pad 260a. The connection via 235 has sloping sides that narrow towards the passive element 300 . The connection via 235 includes a conductive plug and a barrier film surrounding it. The conductive plugs may include a metallic material, such as tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu). The conductive plugs can be formed by a plating process, a PVD process, or a CVD process. The barrier film includes an insulating barrier film and / or a conductive barrier film. The insulating barrier film may be made of an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof. The conductive barrier film may include, for example, a metal compound such as tungsten nitride (WN), titanium nitride (TiN), or tantalum nitride (TaN). The barrier film can be formed by a PVD process or a CVD process. Connection vias 235 may include more or fewer than those shown in the figure.

[0041] In the following description of FIG. 5, the description that overlaps with the description made with reference to FIG. 4 will be omitted. FIG. 5 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. 5, the semiconductor package 10C differs from the semiconductor package 10B of FIG. 4 in that the thickness of the passive element 300 and the thickness of the support layer 210 may be the same, and the connection via 235 and the protective layer 250 may not be present.

[0042] The upper surface of the support layer 210, the upper surface of the passive element 300, and the upper surface of the encapsulant 240 are coplanar. The lower surface of the support layer 210, the lower surface of the passive element 300, and the lower surface of the encapsulant 240 are coplanar. The passive element 300 contacts the first lower connection pad 260a. In one embodiment, the semiconductor package 10B of FIG. 4 includes a protective layer 250 different from that shown. In this case, the connection via 235 in Figure 5 is arranged to penetrate the protective layer 250 and connect the passive element 300 to the first lower connection pad 260a, and the through via 230 penetrates the support layer 210 and the protective layer 250 and connects to the second lower connection pad 260b.

[0043] FIG. 6 is a plan view showing a semiconductor package according to an embodiment of the present invention. 6, a semiconductor package 10D differs from the semiconductor package 10 of FIG. 1b in that the passive element 300 is arranged to overlap the first semiconductor chip 400A.

[0044] The first semiconductor chip 400A includes a logic chip, and the passive element 300 is arranged to completely overlap the first semiconductor chip 400A, which can further improve the power integrity (PI) of the first semiconductor chip 400A, which is a logic chip. In this case, the passive element 300 does not need to overlap with the second semiconductor chip 400B, which is a memory chip. When a plurality of passive elements 300 are arranged, the arrangement of the passive elements 300 of the semiconductor package 10 in FIG. 1b and the arrangement of the passive elements 300 of the semiconductor package 10D in FIG. 6 are simultaneously realized. The number, size, and placement of the passive elements 300 may be varied in various ways within the range in which they can be placed within the interposer die 200 .

[0045] Here, "the size of the passive element 300" means the area on the XY plane. Depending on the embodiment, the semiconductor package 10D may or may not include a support layer 210. In one embodiment, when the semiconductor package 10D includes the support layer 210, it has a structure similar to the semiconductor package 10B of FIG. 4 or the semiconductor package 10C of FIG. In one embodiment, if the semiconductor package 10D does not include the support layer 210, it has a structure similar to the semiconductor package 10 of FIG. 1a or the semiconductor package 10A of FIG. In the following description of FIGS. 7 to 9, the description that overlaps with the description made with reference to FIG. 6 will be omitted.

[0046] 7 and 8 are plan views showing semiconductor packages according to embodiments of the present invention. 7, a semiconductor package 10E differs from the semiconductor package 10 of FIG. 1b in that the planar shape of the passive element 300 does not have to be rectangular. In one embodiment, the top surface of the passive element 300 may be cross-shaped. In the present invention, the passive element 300 manufactured separately can be placed and manufactured during the process of forming the interposer die 200, so the shape of the passive element 300 can be varied in various ways during the manufacturing process of the passive element 300.

[0047] 8, a semiconductor package 10F differs from the semiconductor package 10 of FIG. 1b in that the upper surface of the passive component 300 may be circular or elliptical. Passive element 300 can be manufactured and positioned so that the top surface of passive element 300 has a circular or elliptical shape rather than a polygonal shape, if necessary, taking into account the placement relationship with other components within interposer die 200.

[0048] FIG. 9 is a plan view showing a semiconductor package according to an embodiment of the present invention. 9, a semiconductor package 10G differs from the semiconductor package 10 of FIG. 1b in that the passive element 300 has an annular or ring-like shape of a rectangular parallelepiped having an inner surface 300S1 and an outer surface 300S2. The outer surface 300S2 of the passive element 300 extends opposite to the side surface of the interposer die 200.

[0049] The passive element 300 is arranged so as to overlap a part of the side surface of the semiconductor chip 400 . A part of the inner surface 300S1 of the passive element 300 may overlap with the semiconductor chip 400, and the outer surface 300S2 of the passive element 300 may not overlap with the semiconductor chip 400. The distance between the outer surface 300S2 and the inner surface 300S1 of the passive element 300, that is, the width of the passive element 300, may vary depending on the embodiment. In one embodiment, unlike the one shown in the figure, the outer surface 300S2 of the passive element 300 may partially overlap the semiconductor chip 400. In one embodiment, unlike the one shown in the figure, the passive element 300 is disposed adjacent to the first semiconductor chip 400A, which is a logic chip, so as to overlap the entire side surface of the first semiconductor chip 400A. The shape, position, width, etc. of the passive element 300 may be variously changed within the range in which the passive element 300 includes an inner surface 300S1 and an outer surface 300S2.

[0050] 10a to 10c are cross-sectional views showing a process sequence for explaining a method for manufacturing a semiconductor package according to an embodiment of the present invention. 10a-10c illustrate one embodiment of a method for fabricating the redistribution structure 220 of the semiconductor package 10 of FIG. 1a.

[0051] Referring to FIG. 10a, a passive element 300 is disposed on a carrier CA, and an insulating layer 221 is partially formed. The carrier CA is formed by sequentially coating, for example, a polymer layer containing a curable resin and a metal layer containing nickel (Ni), titanium (Ti), or the like on a copper clad laminate (CCL). The insulating layer 221 is formed by applying and curing a photosensitive material, for example, PID. In one embodiment, the passive element 300 is first placed on the carrier CA, and then the insulating layer 221 is formed on the carrier CA to cover the top and side surfaces of the passive element 300 . In another embodiment, the insulating layer 221 may be formed first, and then the area where the passive element 300 is to be disposed may be partially removed, and then the passive element 300 may be disposed, and the insulating layer 221 may be applied again.

[0052] Referring to FIG. 10b, the insulating layer 221 is subjected to an exposure process and a development process to form a redistribution via 224 and a lower redistribution layer 223a. The redistribution via 224 and the lower redistribution layer 223a are formed by forming a via hole penetrating the insulating layer 221 and patterning a metal material on the insulating layer 221 using a plating process. Although the lower redistribution layer 223a is shown as being formed at a higher level than the passive elements 300, it is not limited to this. In one embodiment, the insulating layer 221 is removed from the top surface to expose the top surface of the passive element 300a, and then the lower redistribution layer 223a is formed to form the lower redistribution layer 223a at a level lower than the top surface of the passive element 300a. In this case, the semiconductor package 10A of FIG. 3 can be manufactured according to the embodiment.

[0053] Referring to FIG. 10c, the process of applying an insulating layer 221 on the lower redistribution layer 223a, forming a redistribution via 224 and a redistribution layer 223, and then forming an upper connection pad 222 on the insulating layer 221 forms a redistribution structure 220. 1a, the carrier CA is then removed, and the lower connection pads 260 and connection conductors 270 are formed under the redistribution structure 220 to form the interposer die 200. Thereafter, the semiconductor package 10 shown in FIG. 1a is manufactured by placing the semiconductor package 10 on a package substrate 100. Thereafter, a semiconductor chip 400 is mounted on the rewiring structure 220 to be connected to the upper connection pads 222 . Depending on the embodiment, the order of the steps of forming the lower connection pads 260 and the connection conductors 270 and mounting the semiconductor chip 400 may be changed. For example, the lower connection pads 260 and the connection conductors 270 may be formed after the semiconductor chip 400 is mounted.

[0054] 11a to 11g are cross-sectional views showing a process sequence for explaining a method for manufacturing a semiconductor package according to an embodiment of the present invention. 11a-11g illustrate one embodiment of a method for fabricating a portion of the interposer die 200 of the semiconductor package 10B of FIG.

[0055] Referring to FIG. 11a, a support layer 210 containing a cavity 215 is placed on the bonding layer TA. Through vias 230 may be included in the support layer 210 . The through vias 230 extend vertically (eg, in the Z direction) within the support layer 210 and are coplanar with the lower surface of the support layer 210 and spaced apart from the upper surface of the support layer 210 . The cavity 215 is formed through the support layer 210 containing the through via 230 in a vertical direction (eg, Z direction). In one embodiment, through vias 230 are also located where cavity 215 is formed, but may be removed during the process of forming cavity 215 . In one embodiment, through vias 230 form cavities 215 without being located at the locations where cavities 215 are formed. The support layer 210 is disposed on the bonding layer TA so that the lower surface of the through via 230 faces the bonding layer TA.

[0056] Referring to FIG. 11 b, a passive element 300 is placed within the cavity 215 . The passive element 300 is disposed on the bonding layer TA and is fixed in the cavity 215 by the bonding layer TA. In one embodiment, if the thickness of the support layer 210 and the passive component 300 is the same, unlike the one shown in the figure, the semiconductor package 10C of FIG. 5 can be manufactured by a subsequent process.

[0057] Referring to FIG. 11 c, the cavity 215 in the support layer 210 is filled to form an encapsulant 240 that covers the passive element 300 . The sealing material 240 is formed by applying and curing EMC, for example. The upper surface of the encapsulant 240 is located at substantially the same level as the upper surface of the support layer 210, but is not limited to this. For example, the top surface of the encapsulant 240 can be located at a lower or higher level than the top surface of the support layer 210 .

[0058] Referring to FIG. 11d, the support layer 210 is partially removed from the top surface so that the through vias 230 are exposed. The sealing material 240 is partially removed so that the upper surface thereof is positioned at the same level as the upper surface of the support layer 210 . The support layer 210 and the encapsulant 240 are removed by a CMP (Chemical Mechanical Polishing) process, an etch-back process, or a combination thereof.

[0059] Referring to FIG. 11e, a protective layer 250 and a connecting via 235 are formed. The protective layer 250 is formed by forming an insulating material layer on the upper surface of the support layer 210 so as to cover the through vias 230, and then removing a portion of the insulating material layer so as to expose the through vias 230. The insulating material layer can be formed by, for example, a spin coating process or a spray process. The connection via 235 is formed by forming a hole penetrating the protective layer 250 and the encapsulant 240 so that a portion of the top surface of the passive element 300 is exposed, and then filling the hole with a conductive material. After forming the protective layer 250 and the connection vias 235, a CMP process is further performed so that the top surfaces of the protective layer 250, the connection vias 235 and the through vias 230 are coplanar.

[0060] Referring to FIG. 11f, a lower connection pad 260 is formed on the protective layer 250. The lower connection pads 260 are formed using a plating process or a photo process. The first lower connection pad 260 a is formed to contact the connection via 235 , and the second lower connection pad 260 b is formed to contact the through via 230 .

[0061] Referring to FIG. 11g, after removing the adhesive layer TA, the support layer 210 is placed on a carrier CA with the lower connection pads 260 facing downward, and then the redistribution structure 220 is formed on the support layer 210. In Figure 11g, for ease of understanding, the entire structure is shown as rotated or inverted in the form of a mirror image of the structure shown in Figures 11a-11f. Then, referring also to FIG. 4, the semiconductor chip 400 is mounted and the connecting conductors 270 are formed to manufacture the semiconductor package 10B of FIG.

[0062] In the following description with reference to FIGS. 12a to 12c, the contents that overlap with the description with reference to FIGS. 11a to 11g will be omitted. 12a to 12c are cross-sectional views showing a process sequence for explaining a method for manufacturing a semiconductor package according to an embodiment of the present invention. 12a-12c illustrate one embodiment of a method for fabricating a portion of the interposer die 200 of the semiconductor package 10B of FIG.

[0063] Referring to FIG. 12a, unlike FIG. 11a, a redistribution structure 220 is first formed on a support layer 210. In FIG. This is done before the support layer 210 has any cavities 215 formed therein.

[0064] Referring to FIG. 12b, the above structure is turned upside down and placed on a carrier CA, and then a cavity 215 is formed through the support layer 210 to expose the insulating layer 221, and a passive element 300 is placed in the cavity 215. In Figure 12b, for ease of understanding, the entire structure is shown as rotated or inverted in the form of a mirror image of the structure shown in Figure 12a.

[0065] Referring to FIG. 12c, an encapsulant 240, a protective layer 250, a connection via 235, a through via 230, and a bottom connection pad 260 are formed. Then, referring also to FIG. 4, the connecting conductors 270 are formed, and the semiconductor chip 400 is mounted to manufacture the semiconductor package 10B of FIG. As mentioned above, content that overlaps with the explanation referring to Figures 11a to 11g will be omitted, and compatible content in the explanation regarding the manufacturing method of Figures 11a to 11g can also be applied to the manufacturing method described referring to Figures 12a to 12c.

[0066] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0067] 10, 10A~G Semiconductor Package 100 Package Substrate 110 Board body 120 Upper Pad 130 Wiring circuit 160 Lower Pad 170 External connection terminal 200 interposer dies 210 Supporter layer 215 Cavity 220 Rewiring Structure 221 Insulating layer 222 upper connection pad 223 Redistribution layer 224 Rerouting Vias 230 through vias 235 Connection Vias 240 Encapsulating material 260 Bottom Connection Pad 260a First bottom connection pad 260b Second bottom connection pad 270 Connecting Conductors 300 Passive Elements 311 1st electrode 312 2nd electrode 320 Dielectric film 400 semiconductor chips 400A First Semiconductor Chip 400B Second semiconductor chip

Claims

1. A package substrate; an interposer die disposed on the package substrate and including a redistribution structure; wherein the redistribution structure includes an insulating layer containing an organic material and a redistribution layer in the insulating layer; a passive element disposed within the interposer die and connected to the redistribution layer, the passive element including a first electrode, a dielectric film on the first electrode, and a second electrode on the dielectric film; semiconductor chips arranged on the interposer die at a distance from each other in a direction horizontal to the upper surface of the insulating layer, and electrically connected to the package substrate via the redistribution layer; The thickness of the passive element is 50 μm or less, A semiconductor package, wherein at least a portion of the dielectric film of the passive element has a crystalline structure.

2. 2. The semiconductor package of claim 1, wherein the dielectric film of the passive element comprises a conductive polymer material or a metal oxide.

3. 2. The semiconductor package of claim 1, wherein the dielectric film has a third thickness that is smaller than the first thickness of the first electrode and the second thickness of the second electrode.

4. the semiconductor chip includes a first semiconductor chip and a second semiconductor chip; the first semiconductor chip includes a logic chip; the second semiconductor chip includes a memory chip; The semiconductor package according to claim 1 , wherein the passive element overlaps at least a portion of the first semiconductor chip in a direction perpendicular to the top surface of the insulating layer.

5. 2. The semiconductor package of claim 1, wherein a lower surface of the passive element is coplanar with a lower surface of the insulating layer.

6. the interposer die includes a support layer disposed below a lower surface of the insulating layer and including a cavity; The semiconductor package according to claim 1 , wherein the passive element is disposed within the cavity of the support layer.

7. a passive element; a rewiring structure including an insulating layer containing an organic material and covering a side surface and an upper surface of the passive element; and a rewiring layer disposed in the insulating layer and connected to the passive element; a first semiconductor chip and a second semiconductor chip spaced apart from each other on the redistribution structure and connected to the redistribution layer; a lower connection pad disposed below the redistribution structure; A semiconductor package, wherein a portion of the lower connection pad contacts the lower surface of the passive element.

8. A package substrate; an interposer die including: a support layer disposed on the package substrate and including a cavity; an insulating layer disposed on the support layer; and a redistribution layer disposed within the insulating layer; a passive element disposed in the cavity of the support layer and connected to the redistribution layer; a semiconductor chip disposed on the interposer die and electrically connected to the package substrate via the rewiring layer; A semiconductor package, wherein an upper surface of the passive element is in contact with a lower surface of the insulating layer.

9. The interposer die includes: an encapsulant that fills the cavity and covers the passive element; a protective layer covering a lower surface of the sealing material and a lower surface of the support layer; first and second lower connection pads disposed under the protective layer; a connection via that penetrates the encapsulant and connects the passive element and the first lower connection pad; a through via that penetrates the support layer and the protection layer and connects the redistribution layer and the second lower connection pad; 9. The semiconductor package according to claim 8, wherein the thickness of the passive element is smaller than the thickness of the support layer.

10. the interposer die further includes a bottom connection pad disposed below the support layer; the thickness of the passive element is the same as the thickness of the support layer; The semiconductor package of claim 8 , wherein a portion of the lower connection pad contacts the passive element.

Images