Power amplifier circuit, power amplifier, and transmitter

Abstract

To provide a power amplifier circuit, a power amplifier, and a transmitter that provide a highly linear power amplifier circuit.SOLUTION: A power amplifier circuit 1 includes a power amplifier unit 01 and a compensation unit 02. The power amplifier unit includes a first MOS field effect transistor M1. The compensation unit includes a third MOS field effect transistor M3. The gate electrode of the third MOS field effect transistor is connected to a first bias voltage terminal Vb1. The source electrode of the third MOS field effect transistor is connected to the drain electrode of the first MOS field effect transistor. The conductivity type of the third MOS field effect transistor is opposite to that of the first MOS field effect transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This application relates to the field of electronic technology, and in particular to power amplification circuits, power amplifiers, and transmitters. [Background technology]

[0002] Complementary metal oxide semiconductor (CMOS), as a mainstream semiconductor technology, is widely used to implement various digital / analog signal processing chips, such as general communication baseband and analog transceivers. Power amplifiers (PAs) are the final-stage modules in transmitters. PAs developed based on CMOS technology are primarily used in narrowband, low-power scenarios such as Bluetooth, Zigbee, and NB-IoT, and may also be used in early Wi-Fi systems. However, as the quadrature amplitude modulation (QAM) order of the modulated signal increases, the requirements for the signal-to-noise ratio of the communication link also increase accordingly to ensure lossless signal transmission. Therefore, transmitting high-order QAM signals requires the PA to have higher linearity, e.g., lower amplitude modulation-amplitude modulation (AM-AM) distortion and lower amplitude modulation-phase modulation (AM-Phase Modulation) distortion. Therefore, how to design a high linearity PA to satisfy the transmission of high bandwidth and high order QAM signals is a technical problem that needs to be urgently solved by those skilled in the art. Summary of the Invention

[0003] The present application provides a power amplification circuit, a power amplifier, and a transmitter to provide a highly linear power amplification circuit.

[0004] According to a first aspect, an embodiment of the present application provides a power amplifier circuit including a power amplifier unit and a compensation unit, wherein the power amplifier unit may include a first MOS field effect transistor, the gate electrode of which is connected to the input signal terminal of the power amplifier circuit, the drain electrode of which is connected to the output signal terminal of the power amplifier circuit, and the source electrode of which is grounded. The compensation unit may include a third MOS field effect transistor, the gate electrode of which is connected to a first bias voltage terminal, the source electrode of which is connected to the output signal terminal of the power amplifier circuit, and the drain electrode of which is connected to a second bias voltage terminal. The first MOS field effect transistor is an N-type MOS field effect transistor and the third MOS field effect transistor is a P-type MOS field effect transistor, or the first MOS field effect transistor is a P-type MOS field effect transistor and the third MOS field effect transistor is an N-type MOS field effect transistor.

[0005] According to the power amplifier circuit provided in this embodiment of the present application, the source electrode of the third MOS field effect transistor is connected to the drain electrode of the first MOS field effect transistor, and the conductivity type of the third MOS field effect transistor is opposite to that of the first MOS field effect transistor M1. Therefore, the change trend of the gate-source capacitor Cgs of the third MOS field effect transistor with the input voltage is opposite to the change trend of the gate-drain capacitor Cgd of the first MOS field effect transistor with the input voltage, and the gate-drain capacitor of the first MOS field effect transistor basically does not change with the input voltage after compensation, so AM-PM is compensated and the linearity of the power amplifier circuit is improved. Furthermore, the design of the power amplifier circuit is simple.

[0006] In an embodiment, the voltage of the first bias voltage terminal can be set between 0 and Vdd, where Vdd is the power supply voltage, and the second bias voltage terminal can be set to virtual ground, that is, the second bias voltage terminal is grounded via a capacitor.

[0007] For example, in a power amplifier circuit, the power amplifier unit may further include a second MOS field-effect transistor and a first bias sub-circuit. The gate electrode of the second MOS field-effect transistor is connected to the input signal terminal of the power amplifier circuit via the first bias sub-circuit, the drain electrode of the second MOS field-effect transistor is connected to the output signal terminal of the power amplifier circuit, and the source electrode of the second MOS field-effect transistor is grounded. The first bias sub-circuit is configured to control the gate bias voltage of the second MOS field-effect transistor. The DC operating point of the first MOS field-effect transistor is biased to class C and the DC operating point of the second MOS field-effect transistor is biased to class AB, or the DC operating point of the first MOS field-effect transistor is biased to class AB and the DC operating point of the second MOS field-effect transistor is biased to class C.

[0008] The first MOS field effect transistor and the second MOS field effect transistor have the same conductivity type, that is, both the first MOS field effect transistor and the second MOS field effect transistor are N-type MOS field effect transistors or P-type MOS field effect transistors.

[0009] In this application, a first MOS field effect transistor and a second MOS field effect transistor combined by using multi-gate transistor technology are used in a power amplifier unit. The DC operating point of one MOS field effect transistor is biased to class AB, so that the third-order nonlinearity gm" of the transconductance gm of that MOS field effect transistor becomes negative, and the DC operating point of the other MOS field effect transistor is biased to class C, so that the third-order nonlinearity gm" of the transconductance gm of the other MOS field effect transistor becomes positive. In this way, the third-order nonlinearity gm" of the transconductance gm of the two MOS field effect transistors acts in opposite ways, so that the AM-AM of the power amplifier circuit is compensated and the P1dB compression point of the power amplifier circuit is improved.

[0010] For example, the first bias sub-circuit may include a first capacitor and a first resistor. A first end of the first capacitor is connected to the input signal end of the power amplifier circuit, and a second end of the first capacitor is connected to the gate electrode of the second MOS field-effect transistor. A first end of the first resistor is connected to the gate electrode of the second MOS field-effect transistor, and a second end of the first resistor is connected to the third bias voltage end. Thus, the first resistor can be used to control the gate bias voltage of the second MOS field-effect transistor, and the first capacitor can be used to insulate the gate electrode of the first MOS field-effect transistor from the gate electrode of the second MOS field-effect transistor, and the first capacitor can further play a role of blocking direct current and conducting alternating current.

[0011] In specific implementation, the voltage of the third bias voltage terminal may be designed based on the operating state of the second MOS field effect transistor. In the example, the second MOS field effect transistor is an N-type MOS field effect transistor. When the DC operating point of the second MOS field effect transistor is biased to class C, the voltage of the third bias voltage terminal is lower than the threshold voltage of the second MOS field effect transistor. When the DC operating point of the second MOS field effect transistor is biased to class AB, the voltage of the third bias voltage terminal is higher than the threshold voltage of the second MOS field effect transistor.

[0012] For example, in the power amplifier circuit, the power amplifier unit may further include a second bias sub-circuit connected between the input signal terminal of the power amplifier circuit and the gate electrode of the first MOS field effect transistor, the second bias sub-circuit being configured to control the gate bias voltage of the first MOS field effect transistor. Therefore, during practical application, when the input signal terminal of the power amplifier circuit is connected to a transformer, the transformer does not need to control the gate bias voltage of the first MOS field effect transistor, and a common four-port transformer is used, thereby reducing design complexity.

[0013] For example, the second bias sub-circuit may include a second capacitor and a second resistor. A first terminal of the second capacitor is connected to the input signal terminal of the power amplifier circuit, and a second terminal of the second capacitor is connected to the gate electrode of the first MOS field-effect transistor. A first terminal of the second resistor is connected to the gate electrode of the first MOS field-effect transistor, and a second terminal of the second resistor is connected to the fourth bias voltage terminal. Thus, the second resistor can be used to control the gate bias voltage of the first MOS field-effect transistor, and the second capacitor can be used to insulate the gate electrode of the first MOS field-effect transistor from the gate electrode of the second MOS field-effect transistor, and the second capacitor can further play the role of blocking direct current and conducting alternating current.

[0014] In specific implementation, the voltage of the fourth bias voltage terminal may be designed based on the operating state of the first MOS field effect transistor. In the example, the first MOS field effect transistor is an N-type MOS field effect transistor. When the DC operating point of the first MOS field effect transistor is biased to class C, the voltage of the fourth bias voltage terminal is lower than the threshold voltage of the first MOS field effect transistor. When the DC operating point of the first MOS field effect transistor is biased to class AB, the voltage of the fourth bias voltage terminal is higher than the threshold voltage of the first MOS field effect transistor.

[0015] In this application, the gate bias voltage of the third MOS field effect transistor can be further adjusted by adjusting the voltage of the first bias voltage terminal, so that the gate-source capacitor Cgs of the third MOS field effect transistor can be adjusted by adjusting its voltage, so that AM-PM is further compensated and the requirements of the power amplifier circuit for transmitting linearity of different modulation signals are met.

[0016] Furthermore, in the present application, in a certain range, more effective compensation can be further performed for AM-PM by changing the size of the third MOS field effect transistor, so that the linearity of the power amplifier circuit is further improved.

[0017] According to a second aspect, an embodiment of the present application further provides a power amplifier including an input matching circuit, an output matching circuit, and a power amplifier circuit according to the first aspect or an implementation of the first aspect. The output signal terminal of the input matching circuit is connected to the input signal terminal of the power amplifier circuit, and the input signal terminal of the output matching circuit is connected to the output signal terminal of the power amplifier circuit. The solution principle of the power amplifier is the same as that of the above-mentioned power amplifier circuit. Therefore, for the implementation of the power amplifier, please refer to the implementation of the above-mentioned power amplifier circuit. Repeated parts will not be described again.

[0018] In the present application, the power amplifier circuit compensates for AM-AM and AM-PM, and excellent linearity can be implemented, and therefore the power amplifier using the power amplifier circuit also has excellent linearity.

[0019] In a specific implementation, in the power amplifier, the input matching circuit may have a single-ended output, or indeed may have a dual-ended differential output. When the input matching circuit has a single-ended output, the power amplifier includes one power amplification circuit. When the input matching circuit has a dual-ended differential output, the power amplifier may include two power amplification circuits. The power amplifier provided in this embodiment of the present application will be described by using an example in which the input matching circuit has a single-ended input and a dual-ended differential output.

[0020] For example, when a power amplifier has a first power amplifier circuit and a second power amplifier circuit, the power amplifier may further include a third capacitor, a first end of which is connected to the drain electrode of the third MOS field-effect transistor of the first power amplifier circuit, and a second end of which is connected to the drain electrode of the third MOS field-effect transistor of the second power amplifier circuit. A first output signal end of the input matching circuit is connected to the input signal end of the first power amplifier circuit, and a second output signal end of the input matching circuit is connected to the input signal end of the second power amplifier circuit. A first input signal end of the output matching circuit is connected to the output signal end of the first power amplifier circuit, and a second input signal end of the output matching circuit is connected to the output signal end of the second power amplifier circuit. Thus, the first power amplifier circuit and the second power amplifier circuit form a fully differential structure, and the two third MOS field-effect transistors are both connected in series to the third capacitor, thereby eliminating the need for a power supply and increasing the power compensation of the power amplifier.

[0021] Optionally, in the power amplifier provided in this embodiment of the present application, the first bias voltage terminal may be grounded, thereby saving one control terminal and simplifying the structure of the power amplifier.

[0022] For example, the power amplifier may further include a fourth capacitor and a fifth capacitor. The fourth capacitor is connected between the output signal terminal of the first power amplifier circuit and the input signal terminal of the second power amplifier circuit. The fifth capacitor is connected between the output signal terminal of the second power amplifier circuit and the input signal terminal of the first power amplifier circuit. The fourth capacitor and the fifth capacitor are neutralization capacitors configured to provide negative feedback to the first power amplifier circuit and the second power amplifier circuit, thereby improving the reverse isolation and stability of the power amplifier.

[0023] For example, to ensure the output gain of the power amplifier, the power amplifier may further include a drive stage amplifier circuit and an inter-stage matching circuit. The drive stage amplifier circuit is configured to compensate for the output gain of the first power amplifier circuit and the second power amplifier circuit. A first input signal terminal of the drive stage amplifier circuit is connected to a first output signal terminal of the input matching circuit, and a second input signal terminal of the drive stage amplifier circuit is connected to a second output signal terminal of the input matching circuit. A first output signal terminal of the drive stage amplifier circuit is connected to a first input signal terminal of the inter-stage matching circuit, and a second output signal terminal of the drive stage amplifier circuit is connected to a second input signal terminal of the inter-stage matching circuit. A first output signal terminal of the inter-stage matching circuit is connected to an input signal terminal of the first power amplifier circuit, and a second output signal terminal of the inter-stage matching circuit is connected to an input signal terminal of the second power amplifier circuit.

[0024] The power amplifier has a two-stage amplifier structure. The first and second power amplifier circuits are used as output stage amplifier circuits. The driver stage amplifier circuit is configured to compensate for the output gain of the output stage amplifier circuit. The frequency response curves of the two-stage amplifier circuits have roughly the same change trend. Since the output stage amplifier circuit compensates for AM-AM and AM-PM, the power amplifier can achieve excellent linearity without gain degradation.

[0025] In a possible implementation, the drive stage amplifier circuit may include a fourth MOS field effect transistor, a fifth MOS field effect transistor, a sixth MOS field effect transistor, a seventh MOS field effect transistor, a third resistor, a fourth resistor, a sixth capacitor, and a seventh capacitor. The gate electrode of the fourth MOS field effect transistor is connected to the power supply voltage terminal, the drain electrode of the fourth MOS field effect transistor is connected to the first output signal terminal of the drive stage amplifier circuit, and the source electrode of the fourth MOS field effect transistor is connected to the drain electrode of the fifth MOS field effect transistor. The gate electrode of the fifth MOS field effect transistor is connected to the first terminal of the sixth capacitor, the source electrode of the fifth MOS field effect transistor is grounded, and the second terminal of the sixth capacitor is connected to the first input signal terminal of the drive stage amplifier circuit. The gate electrode of the sixth MOS field effect transistor is connected to the power supply voltage terminal, the drain electrode of the sixth MOS field effect transistor is connected to the second output signal terminal of the drive stage amplifier circuit, and the source electrode of the sixth MOS field effect transistor is connected to the drain electrode of the seventh MOS field effect transistor. The gate electrode of the seventh MOS field-effect transistor is connected to a first end of the seventh capacitor, the source electrode of the seventh MOS field-effect transistor is grounded, and the second end of the seventh capacitor is connected to a second input signal end of the driving stage amplifier circuit. The third resistor is connected between the gate electrode of the fifth MOS field-effect transistor and a fifth bias voltage end, and the fourth resistor is connected between the gate electrode of the seventh MOS field-effect transistor and the fifth bias voltage end. In the driving stage amplifier circuit, the fourth MOS field-effect transistor, the fifth MOS field-effect transistor, the sixth MOS field-effect transistor, and the seventh MOS field-effect transistor form a fully differential cascode structure, the third resistor and the fourth resistor are bias resistors, and the sixth capacitor and the seventh capacitor can insulate the gate electrode of the fifth MOS field-effect transistor from the gate electrode of the seventh MOS field-effect transistor, and the sixth capacitor and the seventh capacitor can also play the role of blocking direct current and conducting alternating current.

[0026] In the present application, the fourth MOS field effect transistor, the fifth MOS field effect transistor, the sixth MOS field effect transistor, and the seventh MOS field effect transistor may all be N-type MOS field effect transistors. Alternatively, in specific implementation, the fourth MOS field effect transistor, the fifth MOS field effect transistor, the sixth MOS field effect transistor, and the seventh MOS field effect transistor may all be P-type MOS field effect transistors.

[0027] For example, the drive stage amplifier circuit may further include an eighth capacitor and a ninth capacitor. The eighth capacitor is connected between the source electrode of the fourth MOS field effect transistor and the gate electrode of the seventh MOS field effect transistor. The ninth capacitor is connected between the source electrode of the sixth MOS field effect transistor and the gate electrode of the fifth MOS field effect transistor. The eighth capacitor and the ninth capacitor are neutralization capacitors configured to provide negative feedback to the drive stage amplifier circuit, which may improve the stability of the drive stage amplifier circuit.

[0028] For example, the input matching circuit may include a first transformer and a fifth resistor. The fifth resistor is connected between a first input terminal and a second input terminal of the first transformer, and two output terminals of the first transformer are a first output signal terminal and a second output signal terminal of the input matching circuit, respectively. One terminal of the fifth resistor is connected to the input signal terminal of the input matching circuit, and the other terminal of the fifth resistor is grounded. In the input matching circuit, in addition to transformation, the first transformer may further implement conversion from a single-ended input to a differential output.

[0029] For example, the inter-stage matching circuit may include a second transformer and a tenth capacitor, the tenth capacitor is connected between the first input terminal and the second input terminal of the second transformer, the third input terminal of the second transformer is connected to the power supply voltage terminal, the two output terminals of the second transformer are respectively the first output signal terminal and the second output signal terminal of the inter-stage matching circuit, and the first input terminal and the second input terminal of the second transformer are respectively the first input signal terminal and the second input signal terminal of the inter-stage matching circuit.

[0030] For example, the output matching circuit may include a third transformer, an eleventh capacitor, and a sixth resistor, where the sixth resistor and the eleventh capacitor are both connected between two output terminals of the third transformer, the first input terminal and the second input terminal of the third transformer are the first input signal terminal and the second input signal terminal of the output matching circuit, respectively, the third input terminal of the third transformer is connected to a power supply voltage, one terminal of the sixth resistor is connected to the output signal terminal of the output matching circuit, and the other terminal of the sixth resistor is grounded.

[0031] According to a third aspect, an embodiment of the present application further provides a transmitter, including a circuit board and a power amplifier according to the second aspect or an implementation of the second aspect, electrically connected to the circuit board. Since the solution principle of the transmitter is similar to that of the above-mentioned power amplifier, please refer to the implementation of the above-mentioned power amplifier for the implementation of the transformer. The repeated parts will not be described again.

[0032] For the technical effects that can be achieved in the third aspect, please refer to the description of the technical effects that can be achieved in any possible design of the second aspect, and the details will not be described again here. [Brief explanation of the drawings]

[0033] [Figure 1] 1 is a schematic diagram of the structure of a power amplifier circuit according to an embodiment of the present application; [Figure 2] FIG. 2 is a schematic diagram of the structure of another power amplifier circuit according to an embodiment of the present application. [Figure 3] FIG. 2 is a schematic diagram of the structure of another power amplifier circuit according to an embodiment of the present application. [Figure 4] 1 is a schematic diagram of the structure of a power amplifier according to an embodiment of the present application; [Figure 5] FIG. 2 is a schematic diagram of another power amplifier structure according to an embodiment of the present application; [Figure 6] FIG. 2 is a schematic diagram of another power amplifier structure according to an embodiment of the present application; [Figure 7] FIG. 2 is a schematic diagram of another power amplifier structure according to an embodiment of the present application; [Figure 8] FIG. 2 is a schematic diagram of another power amplifier structure according to an embodiment of the present application; [Figure 9] 7 is a schematic diagram of the structure of a comparison circuit without a compensation unit in the power amplifier shown in FIG. 6; [Figure 10a] 10 shows a curve of the change tendency of the output voltage phase of the power amplifier circuit according to the input power when the power amplifier shown in FIG. 9 does not include a compensation unit. [Figure 10b] 7 shows a curve of the change trend of the output voltage phase of the output matching circuit of the power amplifier shown in FIG. 6 according to the input power. [Figure 10c] 7 shows a curve of the change trend of the output voltage phase of the compensation unit in the power amplifier shown in FIG. 6 according to the input power. [Figure 11] 9 is a schematic diagram of the structure of a comparison circuit without a compensation unit in the power amplifier shown in FIG. 8. [Figure 12a] FIG. 10 is a comparison diagram of the tendency of output voltage phase to change with input power when the input signal is 5.5 GHz. [Figure 12b] FIG. 10 is a comparison diagram of the tendency of output voltage phase to change with input power when the input signal is 5.6 GHz. [Figure 12c] FIG. 10 is a comparison diagram of the tendency of output voltage phase to change with input power when the input signal is 5.7 GHz. [Figure 12d] FIG. 10 is a comparison diagram of the tendency of output voltage phase to change with input power when the input signal is 5.8 GHz. [Figure 13] FIG. 2 is a schematic diagram of another power amplifier structure according to an embodiment of the present application; [Figure 14] 14A and 14B are diagrams of AM-PM emulation results of the power amplifier shown in FIG. 13 at different first bias voltages. DETAILED DESCRIPTION OF THE INVENTION

[0034] To make the objectives, technical solutions, and advantages of the present application clearer, the following will describe the present application in more detail with reference to the accompanying drawings. However, the embodiments can be implemented in multiple forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided to make the present application more comprehensive and complete, and to comprehensively convey the concepts of the embodiments to those skilled in the art. The same reference numerals in the drawings represent the same or similar structures. Therefore, repeated descriptions thereof will be omitted. Terms indicating positions and directions in the present application will be described by using the accompanying drawings as examples. However, modifications may be made as necessary, and all modifications shall fall within the scope of protection of the present application. The accompanying drawings of the present application are merely used to illustrate relative positional relationships and do not represent actual dimensions.

[0035] It should be noted that in order to facilitate a complete understanding of the present application, specific details are described in the following description. However, the present application can be implemented in multiple ways different from those described herein, and those skilled in the art can carry out similar promotions without departing from the scope of the present application. Therefore, the present application is not limited to the specific implementations disclosed below. The following descriptions in this specification are exemplary modes for implementing the present application. However, the descriptions are intended to describe the general principles of the present application, and are not intended to limit the scope of the present application. The scope of protection of the present application should be defined by the appended claims.

[0036] The following describes some terms in the embodiments of the present application to help those skilled in the art understand.

[0037] 1. The operating state of a power amplifier can be classified into three types of operating states based on different conduction angles: Class A (first), Class B (second), and Class C (third). When the operating state is Class A, the conduction angle of the amplifier is 360°. When the operating state is Class B, the conduction angle of the amplifier is 180°. When the operating state is Class C, the conduction angle of the amplifier is less than 180°. When the operating state is Class AB, the conduction angle of the amplifier is between 180° and 360°.

[0038] 2.1 dB compression point (P1dB) is a performance parameter for output power. A higher compression point indicates a higher output power. P1dB refers to the input (or output) power point used when the gain is reduced by 1 dB compared to very low power.

[0039] To facilitate understanding of the power amplification circuit, power amplifier, and transmitter provided in the embodiments of the present application, the following first describes specific application scenarios of the power amplification circuit, power amplifier, and transmitter. The technical solutions provided in the embodiments of the present application may be used in scenarios such as Bluetooth, Zigbee, NB-IoT, 4G LTE, and 5G NR, and may also be used in Wi-Fi systems, etc. It should be noted that the technical solutions provided in the embodiments of the present application are intended to include, but are not limited to, being used in these scenarios and any other suitable systems. The present application will be further described in detail below with reference to the accompanying drawings.

[0040] 1 is a schematic diagram of the structure of a power amplifier circuit according to an embodiment of the present application. The power amplifier circuit 1 may include a power amplification unit 01 and a compensation unit 02. The power amplification unit 01 may include a first MOS field-effect transistor M1. The gate electrode of the first MOS field-effect transistor M1 is connected to the input signal terminal In of the power amplifier circuit 1, the drain electrode of the first MOS field-effect transistor M1 is connected to the output signal terminal Out of the power amplifier circuit 1, and the source electrode of the first MOS field-effect transistor M1 is grounded. The compensation unit 02 may include a third MOS field-effect transistor M3. The gate electrode of the third MOS field-effect transistor M3 is connected to the first bias voltage terminal Vb1, the source electrode of the third MOS field-effect transistor M3 is connected to the output signal terminal Out of the power amplifier circuit 1, and the drain electrode of the third MOS field-effect transistor M3 is connected to the second bias voltage terminal Vb2. The first MOS field effect transistor M1 is an N-type MOS field effect transistor, and the third MOS field effect transistor M3 is a P-type MOS field effect transistor, or the first MOS field effect transistor M1 is a P-type MOS field effect transistor, and the third MOS field effect transistor M3 is an N-type MOS field effect transistor. Figure 1 is illustrated by using an example in which the first MOS field effect transistor M1 is an N-type MOS field effect transistor, and the third MOS field effect transistor M3 is a P-type MOS field effect transistor.

[0041] In the power amplifier circuit provided in this embodiment of the present application, the power amplifier unit 01 includes a first MOS field-effect transistor M1, and the compensation unit 02 includes a third MOS field-effect transistor M3, the source electrode of which is connected to the drain electrode of the first MOS field-effect transistor M1, and the conductivity type of the third MOS field-effect transistor M3 is opposite to that of the first MOS field-effect transistor M1. Therefore, the change trend of the gate-source capacitor Cgs of the third MOS field-effect transistor M3 with respect to the input voltage is opposite to the change trend of the gate-drain capacitor Cgd of the first MOS field-effect transistor M1 with respect to the input voltage, and the gate-drain capacitor of the first MOS field-effect transistor M1 essentially does not change with the input voltage after compensation, thereby achieving AM-PM compensation and improving the linearity of the power amplifier circuit. Furthermore, the design of the power amplifier circuit is simple.

[0042] In an embodiment, the voltage of the first bias voltage terminal can be set between 0 and Vdd, where Vdd is the power supply voltage, and the second bias voltage terminal can be set to virtual ground, that is, the second bias voltage terminal is grounded via a capacitor.

[0043] For example, Figure 2 is a schematic diagram of the structure of another power amplifier circuit according to an embodiment of the present application. In the power amplifier circuit 1, the power amplifier unit 01 may further include a second MOS field-effect transistor M2 and a first bias sub-circuit 011. The gate electrode of the second MOS field-effect transistor M2 is connected to the input signal terminal In of the power amplifier circuit 1 via the first bias sub-circuit 011, the drain electrode of the second MOS field-effect transistor M2 is connected to the output signal terminal Out of the power amplifier circuit 1, and the source electrode of the second MOS field-effect transistor M2 is grounded. The first bias sub-circuit 011 is configured to control the gate bias voltage of the second MOS field-effect transistor M2. The DC operating point of the first MOS field-effect transistor M1 is biased to class C and the DC operating point of the second MOS field-effect transistor M2 is biased to class AB; or the DC operating point of the first MOS field-effect transistor M1 is biased to class AB and the DC operating point of the second MOS field-effect transistor M2 is biased to class C.

[0044] The first MOS field effect transistor M1 and the second MOS field effect transistor M2 have the same conductivity type, that is, the first MOS field effect transistor M1 and the second MOS field effect transistor M2 are both N-type MOS field effect transistors or P-type MOS field effect transistors.

[0045] In this application, a first MOS field effect transistor M1 and a second MOS field effect transistor M2, which are combined by using multigate transistor (MGTR) technology, are used in the power amplifier unit 01. The DC operating point of one MOS field effect transistor is biased to class AB, so that the third-order nonlinearity gm" of the transconductance gm of that MOS field effect transistor becomes negative, and the DC operating point of the other MOS field effect transistor is biased to class C, so that the third-order nonlinearity gm" of the transconductance gm of the other MOS field effect transistor becomes positive. In this way, the third-order nonlinearity gm" of the transconductance gm of the two MOS field effect transistors acts in opposite directions, thereby compensating for the AM-AM of the power amplifier circuit and improving the P1dB compression point of the power amplifier circuit.

[0046] In this application, the nonlinear equation for the mutual conductance gm is expressed as follows:

number

[0047] For example, still referring to FIG. 2 , the first bias sub-circuit 011 may include a first capacitor C1 and a first resistor R1. A first end of the first capacitor C1 is connected to the input signal terminal In of the power amplifier circuit 1, and a second end of the first capacitor C1 is connected to the gate electrode of the second MOS field-effect transistor M2. A first end of the first resistor R1 is connected to the gate electrode of the second MOS field-effect transistor M2, and a second end of the first resistor R1 is connected to the third bias voltage terminal Vb3. Thus, the first resistor R1 is used to control the gate bias voltage of the second MOS field-effect transistor M2, and the first capacitor C1 can be used to insulate the gate electrode of the first MOS field-effect transistor M1 from the gate electrode of the second MOS field-effect transistor M2, and the first capacitor C1 can also play the role of blocking direct current and conducting alternating current.

[0048] In specific implementation, the voltage of the third bias voltage end Vb3 may be designed based on the operating state of the second MOS field effect transistor M2. In this example, the second MOS field effect transistor M2 is an N-type MOS field effect transistor. When the DC operating point of the second MOS field effect transistor M2 is biased to class C, the voltage of the third bias voltage end Vb3 is lower than the threshold voltage of the second MOS field effect transistor M2. When the DC operating point of the second MOS field effect transistor M2 is biased to class AB, the voltage of the third bias voltage end Vb3 is higher than the threshold voltage of the second MOS field effect transistor M2.

[0049] 3 is a schematic diagram of the structure of another power amplifier circuit according to an embodiment of the present application. In the power amplifier circuit 1, the power amplifier unit 01 may further include a second bias sub-circuit 012 connected between the input signal terminal In of the power amplifier circuit 1 and the gate electrode of the first MOS field-effect transistor M1, and the second bias sub-circuit 012 is configured to control the gate bias voltage of the first MOS field-effect transistor M1. Therefore, during practical application of the power amplifier circuit, when the input signal terminal In of the power amplifier circuit 1 is connected to a transformer, the transformer does not need to control the gate bias voltage of the first MOS field-effect transistor M1, and a common four-port transformer is used, thereby reducing design complexity.

[0050] For example, still referring to FIG. 3 , the second bias sub-circuit 012 may include a second capacitor C2 and a second resistor R2. A first terminal of the second capacitor C2 is connected to the input signal terminal In of the power amplifier circuit 1, and a second terminal of the second capacitor C2 is connected to the gate electrode of the first MOS field-effect transistor M1. A first terminal of the second resistor R2 is connected to the gate electrode of the first MOS field-effect transistor M1, and a second terminal of the second resistor R2 is connected to the fourth bias voltage terminal Vb4. Thus, the second resistor R2 can be used to control the gate bias voltage of the first MOS field-effect transistor M1, and the second capacitor C2 can be used to insulate the gate electrode of the first MOS field-effect transistor M1 from the gate electrode of the second MOS field-effect transistor M2, and the second capacitor C2 can also play the role of blocking direct current and conducting alternating current.

[0051] In specific implementation, the voltage of the fourth bias voltage terminal Vb4 may be designed based on the operating state of the first MOS field effect transistor M1. In this example, the first MOS field effect transistor M1 is an N-type MOS field effect transistor. When the DC operating point of the first MOS field effect transistor M1 is biased to class C, the voltage of the fourth bias voltage terminal Vb4 is lower than the threshold voltage of the first MOS field effect transistor M1. When the DC operating point of the first MOS field effect transistor M1 is biased to class AB, the voltage of the fourth bias voltage terminal Vb4 is higher than the threshold voltage of the first MOS field effect transistor M1.

[0052] In this application, the gate bias voltage of the third MOS field effect transistor M3 can be further adjusted by adjusting the voltage of the first bias voltage terminal Vb1, so that the gate-source capacitor Cgs of the third MOS field effect transistor M3 can be adjusted by adjusting its voltage, thereby further compensating for AM-PM and meeting the requirements of the power amplifier circuit for transmitting linearity of different modulation signals.

[0053] Furthermore, in this application, in a certain range, the AM-PM can be further corrected by changing the size of the third MOS field-effect transistor M3 so as to further improve the linearity of the power amplifier circuit.

[0054] According to the above power amplifier circuit according to this embodiment of the present application, excellent linearity can be implemented by compensating AM-AM and AM-PM. Furthermore, the power amplifier circuit is easily designed and does not lose efficiency, so the power amplifier circuit can be applied to radio frequency power amplifiers.

[0055] 4 is a schematic diagram of the structure of a power amplifier according to an embodiment of the present application. The power amplifier 10 includes an input matching circuit 2, an output matching circuit 3, and any one of the above-described power amplifier circuits 1 provided in the embodiments of the present application. The output signal terminal Out2 of the input matching circuit 2 is connected to the input signal terminal In1 of the power amplifier circuit 1, and the input signal terminal In3 of the output matching circuit 3 is connected to the output signal terminal Out1 of the power amplifier circuit 1. The problem-solving principle of the power amplifier 10 is the same as that of the above-described power amplifier circuit 1. Therefore, for the implementation of the power amplifier 10, please refer to the implementation of the above-described power amplifier circuit 1. Repeated parts will not be described again.

[0056] In the present application, the power amplifier circuit compensates for AM-AM and AM-PM, and excellent linearity can be implemented, and therefore the power amplifier using the power amplifier circuit also has excellent linearity.

[0057] In a specific implementation, in the power amplifier, the input matching circuit may have a single-ended output, or indeed may have a dual-ended differential output. When the input matching circuit has a single-ended output, the power amplifier includes one power amplification circuit. When the input matching circuit has a dual-ended differential output, the power amplifier may include two power amplification circuits. The power amplifier provided in this embodiment of the present application will be described by using an example in which the input matching circuit has a single-ended input and a dual-ended differential output.

[0058] 5 is a schematic diagram of the structure of another power amplifier according to an embodiment of the present application. When the power amplifier 10 has a first power amplifier circuit 1a and a second power amplifier circuit 1b, the power amplifier 10 may further include a third capacitor C3, where a first terminal of the third capacitor C3 is connected to the drain electrode of the third MOS field-effect transistor M3 of the first power amplifier circuit 1a and a second terminal of the third capacitor C3 is connected to the drain electrode of the third MOS field-effect transistor M3 of the second power amplifier circuit 1b. The first output signal terminal Out2a of the input matching circuit 2 is connected to the input signal terminal In1a of the first power amplifier circuit 1a, and the second output signal terminal Out2b of the input matching circuit 2 is connected to the input signal terminal In1b of the second power amplifier circuit 1b. The first input signal terminal In3a of the output matching circuit 3 is connected to the output signal terminal Out1a of the first power amplifier circuit 1a, and the second input signal terminal In3b of the output matching circuit 3 is connected to the output signal terminal Out1b of the second power amplifier circuit 1b. Therefore, the first power amplifier circuit 1a and the second power amplifier circuit 1b form a fully differential structure, and the two third MOS field-effect transistors M3 are both connected in series with the third capacitor C3, so that no power supply is required and the power compensation of the power amplifier is not increased.

[0059] 6 is a schematic diagram of the structure of another power amplifier according to an embodiment of the present application. Optionally, in the power amplifier 10 provided in this embodiment of the present application, the first bias voltage terminal Vb1 may be grounded, thereby saving one control terminal and simplifying the structure of the power amplifier 10.

[0060] 6, the power amplifier 10 may further include a fourth capacitor C4 and a fifth capacitor C5. The fourth capacitor C4 is connected between the output signal terminal Out1a of the first power amplifier circuit 1a and the input signal terminal In1b of the second power amplifier circuit 1b. The fifth capacitor C5 is connected between the output signal terminal Out1b of the second power amplifier circuit 1b and the input signal terminal In1a of the first power amplifier circuit 1a. The fourth capacitor C4 and the fifth capacitor C5 are neutralization capacitors configured to provide negative feedback to the first power amplifier circuit 1a and the second power amplifier circuit 1b, thereby improving the reverse isolation and stability of the power amplifier 10.

[0061] For example, Figure 7 is a schematic diagram of the structure of another power amplifier according to an embodiment of the present application. To ensure the output gain of the power amplifier, the power amplifier 10 may further include a driver stage amplifier circuit 4 and an inter-stage matching circuit 5. The driver stage amplifier circuit 4 is configured to compensate for the output gain of the first power amplifier circuit 1a and the second power amplifier circuit 1b. The first input signal terminal In4a of the driver stage amplifier circuit 4 is connected to the first output signal terminal Out2a of the input matching circuit 2, and the second input signal terminal In4b of the driver stage amplifier circuit 4 is connected to the second output signal terminal Out2b of the input matching circuit 2. The first output signal terminal Out4a of the driver stage amplifier circuit 4 is connected to the first input signal terminal In5a of the inter-stage matching circuit 5, and the second output signal terminal Out4b of the driver stage amplifier circuit 4 is connected to the second input signal terminal In5b of the inter-stage matching circuit 5. The first output signal terminal Out5a of the inter-stage matching circuit 5 is connected to the input signal terminal In1a of the first power amplifier circuit 1a, and the second output signal terminal Out5b of the inter-stage matching circuit 5 is connected to the input signal terminal In1b of the second power amplifier circuit 1b.

[0062] The power amplifier has a two-stage amplifier structure. The first power amplifier circuit 1a and the second power amplifier circuit 1b are used as output stage amplifier circuits. The driver stage amplifier circuit 4 is configured to compensate the output gain of the output stage amplifier circuit. The change trends of the frequency response curves of the two-stage amplifier circuits are roughly the same. Since the output stage amplifier circuit compensates for AM-AM and AM-PM, the power amplifier can achieve excellent linearity without gain degradation.

[0063] 8 is a schematic diagram of another power amplifier structure according to an embodiment of the present application. The driver stage amplifier circuit 4 may include a fourth MOS field-effect transistor M4, a fifth MOS field-effect transistor M5, a sixth MOS field-effect transistor M6, a seventh MOS field-effect transistor M7, a third resistor R3, a fourth resistor R4, a sixth capacitor C6, and a seventh capacitor C7. The gate electrode of the fourth MOS field-effect transistor M4 is connected to the power supply voltage terminal VDD, the drain electrode of the fourth MOS field-effect transistor M4 is connected to the first output signal terminal Out4a of the driver stage amplifier circuit 4, and the source electrode of the fourth MOS field-effect transistor M4 is connected to the drain electrode of the fifth MOS field-effect transistor M5. The gate electrode of the fifth MOS field-effect transistor M5 is connected to the first terminal of the sixth capacitor C6, the source electrode of the fifth MOS field-effect transistor M5 is grounded, and the second terminal of the sixth capacitor C6 is connected to the first input signal terminal In4a of the driver stage amplifier circuit 4. The gate electrode of the sixth MOS field effect transistor M6 is connected to the power supply voltage terminal VDD, the drain electrode of the sixth MOS field effect transistor M6 is connected to the second output signal terminal Out4b of the driving stage amplifier circuit 4, and the source electrode of the sixth MOS field effect transistor M6 is connected to the drain electrode of the seventh MOS field effect transistor M7. The gate electrode of the seventh MOS field effect transistor M7 is connected to the first terminal of the seventh capacitor C7, the source electrode of the seventh MOS field effect transistor M7 is grounded, and the second terminal of the seventh capacitor C7 is connected to the second input signal terminal In4b of the driving stage amplifier circuit 4. The third resistor R3 is connected between the gate electrode of the fifth MOS field effect transistor M5 and the fifth bias voltage terminal Vb5, and the fourth resistor R4 is connected between the gate electrode of the seventh MOS field effect transistor M7 and the fifth bias voltage terminal Vb5.In the driving stage amplifier circuit 4, the fourth MOS field effect transistor M4, the fifth MOS field effect transistor M5, the sixth MOS field effect transistor M6, and the seventh MOS field effect transistor M7 form a fully differential cascode structure, the third resistor R3 and the fourth resistor R4 are bias resistors, the sixth capacitor C6 and the seventh capacitor C7 can insulate the gate electrode of the fifth MOS field effect transistor M5 from the gate electrode of the seventh MOS field effect transistor M7, and the sixth capacitor C6 and the seventh capacitor C7 can also play the role of blocking direct current and conducting alternating current.

[0064] In specific implementation, the voltage of the fifth bias voltage terminal Vb5 may be designed based on the operating states of the seventh MOS field effect transistor M7 and the fifth MOS field effect transistor M5. Generally, the DC operating points of the seventh MOS field effect transistor M7 and the fifth MOS field effect transistor M5 are biased to class AB.

[0065] 8, an example in which the fourth MOS field effect transistor M4, the fifth MOS field effect transistor M5, the sixth MOS field effect transistor M6, and the seventh MOS field effect transistor M7 are all N-type MOS field effect transistors is used for explanation. Alternatively, in specific implementation, the fourth MOS field effect transistor M4, the fifth MOS field effect transistor M5, the sixth MOS field effect transistor M6, and the seventh MOS field effect transistor M7 may all be P-type MOS field effect transistors.

[0066] 8, the drive stage amplifier circuit 4 may further include an eighth capacitor C8 and a ninth capacitor C9. The eighth capacitor C8 is connected between the source electrode of the fourth MOS field effect transistor M4 and the gate electrode of the seventh MOS field effect transistor M7. The ninth capacitor C9 is connected between the source electrode of the sixth MOS field effect transistor M6 and the gate electrode of the fifth MOS field effect transistor M5. The eighth capacitor C8 and the ninth capacitor C9 are neutralization capacitors configured to provide negative feedback to the drive stage amplifier circuit 4, which may improve the stability of the drive stage amplifier circuit 4.

[0067] It should be noted that the above is merely an example for describing the specific structure of the driving stage amplifier circuit. During specific implementation, the specific structure of the driving stage amplifier circuit is not limited to the above structure provided in the embodiment of the present application, and may alternatively be other structures known by those skilled in the art. This is not limited here.

[0068] 8, the input matching circuit 2 may include a first transformer T1 and a fifth resistor R5. The fifth resistor R5 is connected between the first input terminal and the second input terminal of the first transformer T1, and the two output terminals of the first transformer T1 are the first output signal terminal Out2a and the second output signal terminal Out2b of the input matching circuit 2, respectively. One terminal of the fifth resistor R5 is connected to the input signal terminal In2 of the input matching circuit 2, and the other terminal of the fifth resistor R5 is grounded. In addition to transformation, in the input matching circuit 2, the first transformer T1 may further implement conversion from a single-ended input to a differential output.

[0069] It should be noted that the above is merely an example for describing the specific structure of the input matching circuit. During specific implementation, the specific structure of the input matching circuit is not limited to the above structure provided in the embodiment of the present application, and may alternatively be other structures known by those skilled in the art. This is not limited here.

[0070] 8, for example, the inter-stage matching circuit 5 may include a second transformer T2 and a tenth capacitor C10. The tenth capacitor C10 is connected between the first input terminal and the second input terminal of the second transformer T2, the third input terminal of the second transformer T2 is connected to the power supply voltage terminal VDD, the two output terminals of the second transformer T2 are the first output signal terminal Out5a and the second output signal terminal Out5b of the inter-stage matching circuit 5, and the first input terminal and the second input terminal of the second transformer T2 are the first input signal terminal In5a and the second input signal terminal In5b of the inter-stage matching circuit 5, respectively.

[0071] It should be noted that the above is merely an example for describing the specific structure of the inter-stage matching circuit. During specific implementation, the specific structure of the inter-stage matching circuit is not limited to the above structure provided in the embodiment of the present application, and may alternatively be other structures known by those skilled in the art. This is not limited here.

[0072] 8, the output matching circuit 3 may include a third transformer T3, an eleventh capacitor C11, and a sixth resistor R6. The sixth resistor R6 and the eleventh capacitor C11 are both connected between two output terminals of the third transformer T3, the first input terminal and the second input terminal of the third transformer T3 are the first input signal terminal In3a and the second input signal terminal In3b of the output matching circuit 3, respectively, the third input terminal of the third transformer T3 is connected to the power supply voltage terminal VDD, one terminal of the sixth resistor R6 is connected to the output signal terminal Out3 of the output matching circuit 3, and the other terminal of the sixth resistor R6 is grounded.

[0073] It should be noted that the above is merely an example for describing the specific structure of the output matching circuit. During specific implementation, the specific structure of the output matching circuit is not limited to the above structure provided in the embodiment of the present application, and may alternatively be other structures known by those skilled in the art. This is not limited here.

[0074] The power amplifier shown in FIG. 6 is used as an example. A comparison circuit without a compensation unit, as shown in FIG. 9, is constructed, and the change trend of the output voltage phase of the power amplifier with input power is simulated. The simulation results show that the change trend of the output voltage phase of the input signal in the frequency band from 5.0 GHz to 6.0 GHz is basically unchanged. Here, 5.2 GHz is used as an example, and the simulation results are shown in FIGS. 10a to 10c. FIG. 10a shows the change trend curve of the output voltage phase of the power amplifier circuit shown in FIG. 9 with input power when the power amplifier does not include a compensation unit. FIG. 10b shows the change trend curve of the output voltage phase of the output matching circuit of the power amplifier shown in FIG. 6 with input power. FIG. 10c shows the change trend curve of the output voltage phase of the compensation unit in the power amplifier shown in FIG. 6 with input power. The simulation results show that the change trend of the output voltage phase of the compensation unit with input power is opposite to the change trend of the output voltage phase of the power amplifier circuit without a compensation unit with input power. Therefore, the change trend of the output voltage phase of the power amplifier circuit with input power after compensation performed by the compensation unit is basically unchanged. Therefore, the simulation results prove that the power amplifier circuit provided in the embodiment of the present application can effectively compensate the phase, improve the nonlinearity, and have a simple structure. Moreover, AM-AM is basically not affected when AM-PM is compensated.

[0075] To further verify the power amplifier circuit provided in the embodiment of the present application through simulation, the amplifier shown in FIG. 8 is used as an example. A comparison circuit without a compensation unit, as shown in FIG. 11, is constructed. The simulation results are shown in FIGS. 12a to 12d. The comparison results show that in the frequency range from 5.5 GHz to 5.8 GHz, the AM-PM value obtained after adding the compensation unit is less than 1°, which is much smaller than the 7° before compensation.

[0076] Furthermore, when the first bias voltage terminals of the first power amplifier circuit and the second power amplifier circuit are adjustable, the power amplifier shown in FIG. 13 is used as an example. The simulation results of AM-PM at different voltages of the first bias voltage terminal Vb1 are shown in FIG. 14. From the results in the figure, it can be seen that the gate bias voltage of the third MOS field-effect transistor M3 can be adjusted by adjusting the voltage of the first bias voltage terminal Vb1. In this way, the gate-source capacitor Cgs of the third MOS field-effect transistor M3 can be adjusted to achieve the optimal setting of AM-PM and meet the requirements for transmitting linearity of different modulation signals.

[0077] The present embodiment further provides a transmitter, including a circuit board and a power amplifier electrically connected to the circuit board. Since the solution principle of the transmitter is similar to that of the above-mentioned power amplifier, please refer to the above-mentioned power amplifier for the implementation of the transformer. The repeated parts will not be described again.

[0078] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application, and in this case, the present application intends to cover these modifications and variations of the present application, provided that they fall within the scope of protection defined by the following claims and their equivalent technologies.

Claims

1. 1. A power amplifier comprising: an input matching circuit, an output matching circuit, a first power amplifier circuit, and a second power amplifier circuit; the first power amplifier circuit includes a power amplification unit of the first power amplifier circuit and a compensation unit of the first power amplifier circuit; the power amplification unit of the first power amplifier circuit has a first MOS field effect transistor in the first power amplifier circuit, a gate electrode of the first MOS field effect transistor of the first power amplifier circuit is connected to an input signal terminal of the first power amplifier circuit, a drain electrode of the first MOS field effect transistor of the first power amplifier circuit is connected to an output signal terminal of the first power amplifier circuit, and a source electrode of the first MOS field effect transistor of the first power amplifier circuit is grounded; the compensation unit of the first power amplifier circuit has a third MOS field effect transistor in the first power amplifier circuit, a gate electrode of the third MOS field effect transistor of the first power amplifier circuit is connected to a first bias voltage terminal of the first power amplifier circuit, and a source electrode of the third MOS field effect transistor of the first power amplifier circuit is connected to the output signal terminal of the first power amplifier circuit; the first MOS field effect transistor of the first power amplifier circuit is an N-type MOS field effect transistor, and the third MOS field effect transistor of the first power amplifier circuit is a P-type MOS field effect transistor, or the first MOS field effect transistor of the first power amplifier circuit is a P-type MOS field effect transistor, and the third MOS field effect transistor of the first power amplifier circuit is an N-type MOS field effect transistor; the second power amplifier circuit includes a power amplification unit of the second power amplifier circuit and a compensation unit of the second power amplifier circuit; the power amplification unit of the second power amplifier circuit has a first MOS field effect transistor in the second power amplifier circuit, a gate electrode of the first MOS field effect transistor of the second power amplifier circuit is connected to an input signal terminal of the second power amplifier circuit, a drain electrode of the first MOS field effect transistor of the second power amplifier circuit is connected to an output signal terminal of the second power amplifier circuit, and a source electrode of the first MOS field effect transistor of the second power amplifier circuit is grounded; the compensation unit of the second power amplifier circuit has a third MOS field effect transistor in the second power amplifier circuit, a gate electrode of the third MOS field effect transistor of the second power amplifier circuit is connected to a first bias voltage terminal of the second power amplifier circuit, and a source electrode of the third MOS field effect transistor of the second power amplifier circuit is connected to the output signal terminal of the second power amplifier circuit; the first MOS field effect transistor of the second power amplifier circuit is an N-type MOS field effect transistor, and the third MOS field effect transistor of the second power amplifier circuit is a P-type MOS field effect transistor, or the first MOS field effect transistor of the second power amplifier circuit is a P-type MOS field effect transistor, and the third MOS field effect transistor of the second power amplifier circuit is an N-type MOS field effect transistor; the power amplifier further comprises a third capacitor, a first end of the third capacitor being connected to a drain electrode of the third MOS field effect transistor of the first power amplifier circuit, and a second end of the third capacitor being connected to a drain electrode of the third MOS field effect transistor of the second power amplifier circuit; an output signal terminal of the input matching circuit is separately connected to an input signal terminal of the first power amplifier circuit and an input signal terminal of the second power amplifier circuit, and an input signal terminal of the output matching circuit is separately connected to an output signal terminal of the first power amplifier circuit and an output signal terminal of the second power amplifier circuit. Power amplifier.

2. The first bias voltage terminal is grounded.

2. The power amplifier of claim 1.

3. the power amplifier further comprises a fourth capacitor and a fifth capacitor; the fourth capacitor is connected between an output signal terminal of the first power amplifier circuit and an input signal terminal of the second power amplifier circuit; the fifth capacitor is connected between an output signal terminal of the second power amplifier circuit and an input signal terminal of the first power amplifier circuit; 2. The power amplifier of claim 1.

4. further comprising a drive stage amplifier circuit and an inter-stage matching circuit; the drive stage amplifier circuit is configured to compensate for the output gain of the first power amplifier circuit and the second power amplifier circuit; the input signal terminal of the driving stage amplifier circuit is connected to the output signal terminal of the input matching circuit, and the output signal terminal of the driving stage amplifier circuit is connected to the input signal terminal of the inter-stage matching circuit; an output signal terminal of the inter-stage matching circuit is connected to an input signal terminal of the first power amplifier circuit and an input signal terminal of the second power amplifier circuit, respectively; 2. The power amplifier of claim 1.

5. the drive stage amplifier circuit includes a fourth MOS field effect transistor, a fifth MOS field effect transistor, a sixth MOS field effect transistor, a seventh MOS field effect transistor, a third resistor, a fourth resistor, a sixth capacitor, and a seventh capacitor; a gate electrode of the fourth MOS field effect transistor is connected to a power supply voltage terminal, a drain electrode of the fourth MOS field effect transistor is connected to a first output signal terminal of the driving stage amplifier circuit, and a source electrode of the fourth MOS field effect transistor is connected to a drain electrode of the fifth MOS field effect transistor; a gate electrode of the fifth MOS field effect transistor is connected to a first end of the sixth capacitor, a source electrode of the fifth MOS field effect transistor is grounded, and a second end of the sixth capacitor is connected to a first input signal end of the driving stage amplifier circuit; a gate electrode of the sixth MOS field effect transistor is connected to the power supply voltage terminal, a drain electrode of the sixth MOS field effect transistor is connected to the second output signal terminal of the driving stage amplifier circuit, and a source electrode of the sixth MOS field effect transistor is connected to the drain electrode of the seventh MOS field effect transistor; a gate electrode of the seventh MOS field effect transistor is connected to a first end of the seventh capacitor, a source electrode of the seventh MOS field effect transistor is grounded, and a second end of the seventh capacitor is connected to a second input signal end of the driving stage amplifier circuit; the third resistor is connected between a gate electrode of the fifth MOS field effect transistor and a fifth bias voltage terminal, and the fourth resistor is connected between a gate electrode of the seventh MOS field effect transistor and the fifth bias voltage terminal; 5. The power amplifier of claim 4.

6. the drive stage amplifier circuit further comprises an eighth capacitor and a ninth capacitor; the eighth capacitor is connected between the source electrode of the fourth MOS field effect transistor and the gate electrode of the seventh MOS field effect transistor; the ninth capacitor is connected between the source electrode of the sixth MOS field effect transistor and the gate electrode of the fifth MOS field effect transistor; 6. The power amplifier of claim 5.

7. each of the power amplification unit of the first power amplification circuit and the power amplification unit of the second power amplification circuit further includes a second MOS field effect transistor and a first bias sub-circuit; a gate electrode of the second MOS field effect transistor is connected to the input signal terminal of a corresponding one of the first power amplifier circuit or the second power amplifier circuit via the first bias sub-circuit, a drain electrode of the second MOS field effect transistor is connected to the output signal terminal of the corresponding one of the power amplifier circuits, and a source electrode of the second MOS field effect transistor is grounded; the first bias sub-circuit is configured to control a gate bias voltage of the second MOS field effect transistor; the DC operating point of the first MOS field effect transistor is biased to class C, and the DC operating point of the second MOS field effect transistor is biased to class AB, or the DC operating point of the first MOS field effect transistor is biased to class AB, and the DC operating point of the second MOS field effect transistor is biased to class C; 2. The power amplifier of claim 1.

8. the first bias sub-circuit includes a first capacitor and a first resistor; a first end of the first capacitor is connected to the input signal end of the corresponding one of the power amplifier circuits, and a second end of the first capacitor is connected to a gate electrode of the second MOS field effect transistor; a first end of the first resistor is connected to a gate electrode of the second MOS field effect transistor, and a second end of the first resistor is connected to a third bias voltage terminal; 8. The power amplifier of claim 7.

9. Each of the power amplifier unit of the first power amplifier circuit and the power amplifier unit of the second power amplifier circuit further includes a second bias sub-circuit connected between the input signal terminal of the corresponding one of the first power amplifier circuit and the gate electrode of the first MOS field effect transistor; the second bias sub-circuit is configured to control a gate bias voltage of the first MOS field effect transistor; 3. The power amplifier of claim 2.

10. the second bias sub-circuit includes a second capacitor and a second resistor; a first end of the second capacitor is connected to the input signal end of the corresponding one of the power amplifier circuits, and a second end of the second capacitor is connected to the gate electrode of the first MOS field effect transistor; a first end of the second resistor is connected to a gate electrode of the first MOS field effect transistor, and a second end of the second resistor is connected to a fourth bias voltage terminal; 10. The power amplifier of claim 9.

11. A transmitter comprising a circuit board and a power amplifier according to any one of claims 1 to 10 electrically connected to the circuit board.

Images