Control circuit, LSI, electronic device, and switch state detection method

Abstract

To prevent a malfunction in pre-charging, regarding a control circuit, an LSI, an electronic device, and a switch state detection method.SOLUTION: In an LSI 106, a first timing signal kcr[n] output to a switch scan output line 102[n] in a switch matrix circuit is fed back from a first output buffer circuit B3[n] to a first input buffer circuit B2[n] and latched in a latch circuit FF2[n]. When all latch outputs kcior[n] become inactive, an output kch of an N-input AND gate ANDKC becomes H level, a second timing signal pcen(m) from a second timing signal generation circuit 403 is output from a 2-input AND gate AND[m] as a pre-charge enable signal pcenfb[m], and a switch scan output terminal KC[n] is pre-charged via a second output buffer circuit B1[m].SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a control circuit, an LSI, an electronic device, and a method for detecting a switch state. [Background technology]

[0002] In electronic keyboard instruments, a keyboard circuit technology has been known in the past that uses a switch matrix circuit to determine the state of each switch, approximately two or three of which are installed for each key on the keyboard, to detect the key press or release state of each key (see, for example, Patent Document 1). This switch matrix circuit has a structure in which multiple switch scan lines and multiple switch input lines are arranged in a matrix (grid), and multiple switches for detecting the key press or release are installed at each intersection of the lines. Two or three switches are arranged for each key, and the key press or release speed of each key is detected by detecting the time difference between when these switches sequentially turn on (hereinafter referred to as "ON") or off (hereinafter referred to as "OFF"). The keyboard of an electronic keyboard instrument has multiple keys (e.g., 61 or 88 keys), and musical tones of the pitch corresponding to each key are generated or muted, for example at a velocity or speed corresponding to the detected key press / release speed for each key. The number of switches on a keyboard is, for example, 61 or 88 keys x 2 or 3 = 122 to 264.

[0003] In a switch matrix circuit, each switch scan line is sequentially set to an active state (low level) one by one in a time-division manner, while detecting whether each switch input line is at an L level or a high level (high level). Each switch input line is pulled up to an H level voltage of the power supply by a pull-up resistor. Therefore, when a switch scan line is active and a switch at each intersection of the switch input lines intersecting with the switch scan line is turned on, the switch input line corresponding to that switch becomes conductive with the active switch scan line, causing the level of that switch input line to become L level, and the ON state of that switch is detected via the input terminal of that switch input line. On the other hand, when a switch at each intersection is turned off or has been turned off, the switch input line corresponding to that switch becomes H level due to the pull-up resistor R, and the OFF state of that switch is detected. When a switch scan line returns from active to inactive (high level), the ON switch remains conductive with the inactive switch scan line, causing the switch input line corresponding to that switch to return from L level to H level. On the other hand, when a switch that is in the ON state is turned OFF, the switch input line corresponding to that switch is pulled up to the H level of the power supply by the pull-up resistor R connected to that switch input line.

[0004] However, the pull-up of this switch input line may not immediately become high due to the transient response of the circuit, including the pull-up resistor R. If the next switch scan line becomes active before the switch input line has fully reached high, the switch input line corresponding to the next switch scan line may be determined to be low (before fully reaching high), even though the switch connected to that switch scan line is off. This may result in the switch being erroneously determined to be on. To address this issue, a technique called precharge is used, which forcibly changes the input terminals of all switch input lines to high output for a short period after the active period of one switch scan line ends. This allows all switch input lines to be rapidly precharged to high immediately after one switch scan line returns to inactive, and other switch scan lines can then be activated immediately thereafter. This shortens the time required to maintain all switch scan lines inactive (high) until the next switch scan line is activated (low) to detect the switch operation state, thereby enabling an increase in the number of switches. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 6040590 Summary of the Invention [Problem to be solved by the invention]

[0006] As mentioned above, to increase the number of switches processed in time division multiplexing, it is desirable to minimize the period during which all switch scan lines are inactive due to precharge. Therefore, it is desirable to switch all switch input lines to the H level (precharge output state) as soon as possible after all switch scan lines enter their inactive period. However, due to manufacturing variations in the dedicated LSIs (large-scale integrated circuits) that control each switch scan line and each switch input line, and variations in the H / L level transitions of internal logic gates, there is a possibility that all switch input lines may accidentally output a H level while one of the switch scan lines is active (Low level). As a result, if there is an ON switch connected to that active switch scan line, a H-level to L-level short circuit is created between the switch input line that has turned H level and the switch scan line that has not yet turned inactive via that switch, resulting in a malfunction of the electronic musical instrument system or damage to the LSI circuit elements.

[0007] An object of the present invention is to prevent malfunctions during precharging. [Means for solving the problem]

[0008] A control circuit in one example embodiment is a circuit for controlling a switch matrix circuit in which a plurality of switch scan output lines and a plurality of switch input lines are wired in a matrix, and a plurality of switches are connected to each intersection of each switch scan output line and each switch input line so as to switch the switch scan output line and the switch input line between conductive and non-conductive states, and includes: a first logic circuit that receives input of a plurality of third signals corresponding to a plurality of first signals that control the plurality of switch scan output lines, respectively, and detects, as a fourth signal, that all of the outputs based on the plurality of third signals have become inactive; and a plurality of second logic circuits that output a plurality of precharge enable signals that put each of the plurality of switch input lines into a precharge state when the fourth signal from the first logic circuit and a plurality of second signals that control putting each of the plurality of switch input lines into a precharge state are input. [Effects of the Invention]

[0009] According to the present invention, it is possible to prevent malfunctions during precharging. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a diagram showing the overall circuit configuration of an embodiment of a keyboard circuit. [Figure 2] 1 is a timing chart illustrating a basic operation of an embodiment of a keyboard circuit. [Figure 3] FIG. 1 is an explanatory diagram of a problem that may occur in a keyboard circuit. [Figure 4] FIG. 2 is a circuit configuration diagram of an LSI in an embodiment of a keyboard circuit. [Figure 5] 4 is an operation timing chart of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. As shown in Figure 1, a keyboard circuit 100 in this embodiment, which is a control circuit, includes a switch matrix circuit 101 and a large scale integrated circuit (LSI) 106.

[0012] The switch matrix circuit 101 is configured by wiring N switch scan output lines 102[0] to 102[N-1] connected to N (N is a natural number) switch scan output terminals KC[0] to KC[N-1] of the LSI 106, respectively, and M switch input lines 103[0] to 103[M-1] connected to M (M is a natural number) switch input terminals KI[0] to KI[M-1], respectively, in a matrix (grid) pattern. At each intersection of each switch scan output line 102[0] to 102[N-1] and each switch input line 103[0] to 103[M-1], one or more switches 104[n][m] are installed for each key constituting the keyboard of an electronic keyboard instrument (not shown), and detect the key's pressed or released state. Each switch 104[n][m] is connected in series with a backflow prevention diode 105[n][m] to switch the switch scan output line 102[n] (0≦n≦N-1) and switch input line 103[m] (0≦m≦M-1) between conductive and non-conductive states. The series-connected switch 104[n][m] and diode 105[n][m] are installed at the intersection of the nth switch scan output line 102[n] and the mth switch input line 103[m]. In FIG. 1, a representative example of the switch 104[n][m] and diode 105[n][m] (0≦n≦N-1) (0≦m≦M-1) is shown as the switch 104 and diode 105 at the intersection of the switch scan line 102[0] and the switch input line 103[0]. Furthermore, each switch input line 103[m] (0≦m≦M-1) is connected to the power supply V DD is connected to.

[0013] The number N of switch scan output terminals KC[n] (0≦n≦N-1) and the number M of switch input terminals KI[m] (0≦m≦M-1) in FIG. 1 are determined by the number of switches used on the keyboard. For example, if the keyboard has 88 keys and each key uses three switches 104, then 88×3=264 switches are used. In this case, if N=8 and M=33, the switch matrix circuit 101 in FIG. 1 can detect the switch states of the 88 keys. The structure of the keyboard is disclosed in, for example, FIG. 1 and paragraphs

[0016] to

[0029] of Patent Document 1 by the present applicant, and therefore a detailed description thereof will be omitted.

[0014] Each of the switch scan output terminals KC[0] to KC[N-1] is active (during switch scanning) when it outputs an L level, and inactive (during no switch scanning) when it outputs an H level. During the period when any of the switch scan output terminals KC[n] among KC[0] to KC[N-1] is made active (outputting an L level) by LSI 106, each switch input terminal KI[m] (0≦m≦M-1) becomes L level if the corresponding switch 104[n][m] is ON, and remains H level due to the pull-up resistor R if the corresponding switch 104[n][m] is OFF. Therefore, by detecting the signal level state of each switch input line 103[m] (0≦m≦M-1) in LSI106 via each switch input terminal KI[m] (0≦m≦M-1), LSI106 can detect the ON or OFF state of switch 104[n][m] connected between the activated switch scan output terminal KC[n] (0≦n≦N-1) and each switch input terminal KI[m] (0≦m≦M-1).

[0015] 1, the signals that the LSI 106 actually generates in the switch matrix circuit 101 are shown in the timing chart of FIG. 2. When any switch scan output terminal KC[n] (0≦n≦N-1) is active, each switch input terminal KI[m] (0≦m≦M-1) becomes an input terminal that detects the ON or OFF state of the switch 104[n][m] (0≦m≦M-1) connected between the switch scan output terminal KC[n]. Hereinafter, in FIG. 2, the period marked "HiZ" is the input state period during which each switch input terminal KI[0] to KI[M-1] (collectively marked KI[M-1:0] in FIG. 2) behaves as an input terminal. That is, during the period HiZ in FIG. 2, when any switch scan output terminal KC[n] is active (L output), the input signal level of each switch input terminal KI[m] (0≦m≦M-1) is L level if the switch 104[n][m] between the active switch scan output terminal KC[n] is ON, and H level if it is OFF.

[0016] On the other hand, in general, during a period when all switch scan output terminals KC[0] to KC[N-1] are inactive (H level), regardless of the operation state of each switch 104, all switch input terminals KI[0] to KI[M-1] are connected to the power supply V DD The switch input terminals KI[0] to KI[M-1] are pulled up to the H level by the pull-up resistor R connected to the switch 104. However, due to the presence of a transient response caused by the resistor R, it takes a certain amount of time for each switch input terminal KI[0] to KI[M-1] to become completely at the H level. For this reason, it takes a certain amount of time for all switch scan output terminals KC[0] to KC[N-1] to be kept inactive (at the H level) until one of the switch scan output terminals KC[n] (0≦n≦N-1) is next made active (at the L level) to detect the state of the switch 104. As a result, it is difficult to improve the time-division performance for detecting the switch state using only the pull-up resistor R, and it also becomes difficult to increase the number of switches.

[0017] Therefore, in this embodiment, when all switch scan output terminals KC[0] to KC[N-1] become inactive (H level), all switch input terminals KI[0] to KI[M-1] are immediately switched to output terminals and output H-level signals for a short period of time. In the timing of the row of switch input terminals KI[M-1:0] in FIG. 2, the period marked "H" corresponds to this period. As a result, during this period, each switch input terminal KI[m] (0≦m≦M-1) can be rapidly set to a complete H level within a short time after all switch scan output terminals KC[0] to KC[N-1] become inactive (H level). This shortens the time required to maintain all switch scan output terminals KC[0] to KC[N-1] inactive (H level) until the next time any switch scan output terminal KC[n] (0≦n≦N-1) is set to active (L level) to detect the state of the switch 104, thereby enabling an increase in the number of switches 104 to be implemented. The operation in which all switch input terminals KI[0] to KI[M-1] immediately switch to output terminals and output H-level signals for a short period of time when all switch scan output terminals KC[0] to KC[N-1] become inactive (H level) is called precharge.

[0018] The timing of each signal in Figure 2 is controlled by a specially designed LSI 106. To make the switch scan cycle as fast as possible, as mentioned above, it is desirable to make the inactive period of all switch scan output terminals KC[0] to KC[N-1] as short as possible, and once this inactive period begins, it is desirable to switch the switch input terminals KI[0] to KI[M-1] to the precharge output state as soon as possible. However, as shown in Figure 3(b), if one of the switch input terminals KI[m] (for example, n=0 in the example of Figure 3(b)) accidentally outputs an H level while the switch scan output terminal KC[n] (for example, n=2 in Figure 3(b)) is active (outputs an L level), then, as shown in Figure 3(a), when switch 104[n][m] (for example, switch 104[2][0] in the example of Figure 3(a)) is turned on, a short circuit path 301 between the H level and L level is created between the switch input terminal KI[m] (=KI[0]) and the switch scan output terminal KC[n] (=KC[2]), which may cause a malfunction of the electronic musical instrument system or damage to LSI 106, etc.

[0019] To prevent such a situation, the LSI 106 has the circuit configuration shown in Fig. 4. In Fig. 4, a first timing signal generation circuit 402 outputs N first timing signals kcr[n] (0 ≦ n ≦ N-1) that activate the switch scan output terminals KC[n] (0 ≦ n ≦ N-1) to which the switch scan output lines 102[n] (0 ≦ n ≦ N-1) are respectively connected, based on the count output of a counter circuit 401 that counts cyclically with the period of the switch matrix.

[0020] Furthermore, the second timing signal generating circuit 403 outputs M second timing signals pcen[m] that respectively precharge (H level) the switch input terminals KI[m] (0≦m≦M−1) to which the switch input lines 103[m] (0≦m≦M−1) are respectively connected. Here, there are M pcen[m], and although they are basically the same signal, they are divided into M signals in order to prevent any of the switch scan output terminals KC[n] from being driven when that terminal is not in use, or to slightly shift the transition as a countermeasure against electromagnetic waves.

[0021] 4, the LSI 106 has N switch scan output terminals KC[n] (0≦n≦N-1) and M switch input terminals KI[m] (0≦m≦M-1). N IO buffer circuits KCIO[n] (0≦n≦N-1), which are the final output stages of the output signal of KC[n], are connected to the switch scan output terminals KC[n] (0≦n≦N-1). In this circuit, the output of the first output buffer circuit B3[n] and the input of the first input buffer circuit B2[n] in the IO buffer circuit KCIO[n] are connected to the switch scan output terminal KC[n]. Therefore, the first timing signal kcr[n] (0≦n≦N-1) supplied from the first timing signal generating circuit 402 to each switch scan output terminal KC[n] (0≦n≦N-1) and output from the first output buffer circuit B3[n] can be read out as kcio[n] (0≦n≦N-1) from each of the N first input buffer circuits B2[n] (0≦n≦N-1). The switch detection logic circuit 400 includes the counter circuit 401, the first timing signal generating circuit 402, and the second timing signal generating circuit 403 described above.

[0022] The switch detection logic circuit 400 also includes an N-input AND gate ANDKC (first logic circuit) that detects when all N latch output signals kcior[n] (0≦n≦N−1) synchronized by a latch circuit consisting of two flip-flops FF2 with signals kcio[n] (0≦n≦N−1) output from the first input buffer circuits B2[n] (0≦n≦N−1) in the IO buffer circuit KCIO[n] become inactive (H level). If the output kch of the N-input AND gate ANDKC is H level, it is guaranteed that all N switch scan output terminals KC[n] (0≦n≦N−1) are inactive, regardless of variations in the LSI 106. Inserting the latch circuit makes it possible to prevent errors in determining that all signals are inactive due to signal fluctuations, compared to simply determining the logic of the output signal kcio[n] from the first input buffer circuit B2[n] (0≦n≦N−1).

[0023] Next, M two-input AND gates AND[m] (0≦n≦M−1) each receive M second timing signals pcen[m] output from the second timing signal generating circuit 403, and output M precharge enable signals (precharge valid signals) pcenfb[m] (0≦n≦M−1) to M IO buffer circuits KIIO[m] (0≦n≦M−1) when the output kch of the N-input AND gate ANDKC is in an inactive state (H level). M switch input terminals KI[m] (0≦m≦M-1) are connected to M IO buffer circuits KIIO[m] (0≦n≦M-1) that receive switch inputs and ultimately output precharge signals. In the IO buffer circuit KIIO[m], M precharge enable signals pcenfb[m] (0≦n≦M-1) received from the switch detection logic circuit 400 are provided as enable signals to M second output buffer circuits B1[m] (0≦n≦M-1). In each of the M second output buffer circuits B1[m] (0≦n≦M-1), output is enabled when the precharge enable signal pcenfb[m] (0≦n≦M-1) is at H level, and output is disabled (input) when it is at L level. An H-level signal is always input to the input of the second output buffer circuit B1[m] (0≦n≦M-1). When the precharge enable signal pcenfb[m] (0≦n≦M-1) is at H level, the second output buffer circuit B1[m] (0≦n≦M-1) outputs H level, and the corresponding switch input terminal KI[m] (0≦n≦M-1) outputs H level, which is a signal that puts the switch input line 103[m] (0≦n≦M-1) into a precharge state. When the precharge enable signal pcenfb[m] (0≦n≦M-1) is at L level, the output of the second output buffer circuit B1[m] (0≦n≦M-1) is disabled. In this case, the switch input terminal KI[m] (0≦n≦M-1) becomes an input terminal, and the level input from the switch input line 103[m] (0≦n≦M-1) is sent as a switch state signal ki[m] (0≦n≦M-1) via the second input buffer circuit B0[m] (0≦n≦M-1) to a switch state determination circuit (not shown) within the switch detection logic circuit 400. The above-mentioned signals ki[m], pcenfb[m], kcio[n], kcr[n] are not directly connected to KIIO[m] and KCIO[n] by the switch detection logic circuit 400, but pass through several stages of combinational circuits, as shown conceptually as 404 in Figure 4. The combinational circuits include selector circuits that select which of the pin alternative functions of LSI106 to pass the signal of, and repeater circuits that shape signals that become distorted over long wiring distances, and these cause manufacturing variations in LSI106 and variations in the transition times between H and L levels of the logic gates.

[0024] In the circuit configuration of the LSI 106 in Figure 4, for example, at the timing indicated by 501 in the timing chart of Figure 5, the signal level transition of the first timing signal kcr[n] is simultaneous with or earlier than the transition of the second timing signal pcen[m], but the signal level transition of the switch scan output terminal KC[n] is delayed relative to the transition of the second timing signal pcen[m]. However, the output kcior[n] of the first input buffer circuit B2[n] is definitely delayed relative to the switch scan output terminal KC[n], and the output kch of the N-input AND gate ANDKC goes high only when all latch output signals kcior[n] (0 ≤ n ≤ N-1) go high. Only when both this kch and the second timing signal pcen[m] output from the second timing signal generating circuit 403 go high does the precharge enable signal pcenfb[m] go high, and the switch input terminal KI[m] enters the precharge output state.

[0025] As described above, when the switch scan output terminal KC[n] is at the L level, the switch input terminal KI[m] is not outputting, and it is possible to prevent the occurrence of a short circuit or a large current flow as described in Fig. 3. That is, in the precharge function of the switch matrix circuit 101, it is possible to logically and reliably prevent a circuit short circuit, regardless of variations in semiconductor manufacturing, etc. According to this embodiment, it is no longer necessary to change the precharge time in the RTL or adjust the delay time in the layout process according to variations in semiconductor manufacturing, etc., and the same RTL can be used in the development of different LSIs. [Explanation of symbols]

[0026] 100 keyboard circuit 101 Switch matrix circuit 102 Switch scan output line 103 Switch input line 104 Switch 105 Diode 106 LSI 400 Switch detection logic circuit 401 Counter 402 First timing signal generating circuit 403 Second timing signal generating circuit 404 Image of a combinational circuit

Claims

1. A circuit for controlling a switch matrix circuit in which a plurality of switch scan output lines and a plurality of switch input lines are wired in a matrix, and a plurality of switches are connected to each intersection of each of the switch scan output lines and each of the switch input lines so as to switch between conduction and non-conduction between the switch scan output lines and the switch input lines, a first logic circuit that receives a plurality of third signals corresponding to a plurality of first signals that respectively control the plurality of switch scan output lines, and detects, as a fourth signal, that all of the outputs based on the plurality of third signals have become inactive; a plurality of second logic circuits that output a plurality of precharge enable signals that place each of the plurality of switch input lines in a precharge state when the fourth signal from the first logic circuit and a plurality of second signals that control placing each of the plurality of switch input lines in a precharge state are input; A control circuit comprising:

2. a first timing signal generating circuit that generates, as the first signals, a plurality of first timing signals that control activation of the plurality of switch scan output lines; a plurality of first output buffer circuits that output the plurality of first timing signals to the plurality of switch scan output lines, respectively; a plurality of first input buffer circuits that respectively receive and output the plurality of first timing signals output from the plurality of first output buffer circuits; a second timing signal generating circuit that generates, as the second signals, a plurality of second timing signals that control the precharge of the plurality of switch input lines, respectively; a plurality of second input buffer circuits each receiving an input state of each of the plurality of switch input lines and outputting a plurality of switch state signals each indicating the input state of each of the plurality of switch input lines; a second output buffer circuit that precharges each of the plurality of switch input lines when each of the plurality of precharge enable signals indicates a valid state; The control circuit of claim 1 , comprising:

3. An LSI including the control circuit according to claim 1.

4. An electronic device comprising the control circuit of claim 1.

5. A circuit for controlling a switch matrix circuit in which a plurality of switch scan output lines and a plurality of switch input lines are wired in a matrix, and a plurality of switches are connected to each intersection of each of the switch scan output lines and each of the switch input lines so as to switch between conduction and non-conduction between the switch scan output lines and the switch input lines, a plurality of third signals corresponding to a plurality of first signals for controlling the plurality of switch scan output lines, respectively, are input, and it is detected as a fourth signal that all of the outputs based on the plurality of third signals have become inactive; when the fourth signal and a plurality of second signals for controlling the precharge state of each of the plurality of switch input lines are input, a plurality of precharge enable signals for putting each of the plurality of switch input lines into a precharge state are output. How to detect the switch state.

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