Method for manufacturing semiconductor light-emitting element

Abstract

To provide a method capable of manufacturing a semiconductor light-emitting element having a narrow partition groove.SOLUTION: A semiconductor light-emitting element includes an epitaxial layer 30 including at least one light-emitting layer and an electrode. The epitaxial layer 30 has a plurality of pixels partitioned by a partition groove 80 in a plan view. A method for manufacturing the semiconductor light-emitting element includes a laminated mask forming step and an etching step. In the laminated mask forming step, a laminated mask 50 is formed that includes a base film 53 formed of a thin film containing an oxide, a lower layer film 51, and an upper layer film 52 laminated in order on the epitaxial layer 30. An etching selection ratio of the lower layer film 51 to the upper layer film 52 is 40 or more. In the etching step, by removing the epitaxial layer 30 in a region exposed without being covered with the laminated mask 50 by etching, the partition groove 80 is vertically formed.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor light-emitting device. [Background technology]

[0002] Conventionally, semiconductor light-emitting elements have been provided with an epitaxial layer in which multiple light-emitting layers with different emission wavelengths are stacked, and the epitaxial layer has multiple pixels partitioned by partition grooves in a planar view, and each pixel has multiple sub-pixels with different emission wavelengths.

[0003] Patent document 1 describes a system having a light-emitting diode (LED) array having first, second, and third pixels separated by one or more trenches extending to a substrate; an LED device mounting area having a first set of electrodes coupled to a first set of contacts on the first pixels, a second set of electrodes coupled to a second set of contacts on the second pixels, and a third set of electrodes coupled to a third set of contacts on the third pixels; and a drive circuit configured to provide independent voltages to one or more of the first set of electrodes, the second set of electrodes, and the third set of electrodes. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2021-508175 Summary of the Invention [Problem to be solved by the invention]

[0005] In conventional semiconductor light-emitting devices that include an epitaxial layer including at least one light-emitting layer, the epitaxial layer having a plurality of pixels defined by partition grooves in a planar view, there has been a demand for narrowing the groove width of the partition grooves to further increase pixel density and / or increase the light-emitting area, but this has been difficult to achieve.

[0006] The present invention has been made in consideration of the above circumstances, and aims to provide a method for manufacturing a semiconductor light-emitting element that is capable of manufacturing a semiconductor light-emitting element having narrow partition grooves, the semiconductor light-emitting element comprising an epitaxial layer including at least one light-emitting layer, the epitaxial layer having a plurality of pixels partitioned by partition grooves in a planar view.

[0007] Another object of the present invention is to provide a semiconductor light emitting device having narrow partition grooves that can be manufactured using the method for manufacturing a semiconductor light emitting device of the present invention. Another object of the present invention is to provide a method for manufacturing a semiconductor light emitting device, which includes the method for manufacturing a semiconductor light emitting element of the present invention. Another object of the present invention is to provide a semiconductor light emitting device including the semiconductor light emitting element of the present invention. [Means for solving the problem]

[0008] In order to solve the above problems, the following means are provided. (1) An epitaxial layer including at least one light-emitting layer and an electrode; a method for manufacturing a semiconductor light-emitting element, wherein the epitaxial layer has a plurality of pixels partitioned by partition grooves in a plan view; a layered mask forming step of forming a layered mask on the epitaxial layer by laminating an underlayer film made of a thin film containing an oxide, a lower layer film, and an upper layer film in this order, the layered mask having an etching selectivity of the lower layer film to the upper layer film of 40 or more; The epitaxial layer in the exposed region not covered by the layer mask is removed by etching, and forming the partition grooves vertically by etching.

[0009] (2) The underlayer film is made of any one selected from SiO2, Al2O3, and Si3N4, The method for producing a semiconductor light-emitting element according to (1), wherein the upper layer film is made of any one selected from Ni, Pt, and Cr.

[0010] (3) The method for manufacturing a semiconductor light-emitting element according to (1), wherein the oxide of the undercoat film is a conductive material. (4) The method for manufacturing a semiconductor light-emitting element according to (3), wherein at least a part of the base film is left in the step of removing the layered mask.

[0011] (5) The method for manufacturing a semiconductor light-emitting element according to (1), wherein the oxide of the underlayer is formed by vapor deposition. (6) The method for manufacturing a semiconductor light-emitting device according to (5), wherein the epitaxial layer is made of GaN, and the uppermost layer of the epitaxial layer is p-type.

[0012] (7) The method for manufacturing a semiconductor light-emitting element according to (1), wherein the base film has a metal bonding layer made of a metal material laminated between the oxide of the base film and the lower layer film. (8) The epitaxial layer is a laminate of a plurality of light-emitting layers having different emission wavelengths, The pixel comprises a plurality of sub-pixels having different emission wavelengths. A method for manufacturing a semiconductor light-emitting device according to any one of (1) to (7). [Effects of the Invention]

[0013] The method for manufacturing a semiconductor light-emitting element of the present invention includes a layer mask formation step of forming a layer mask on an epitaxial layer by laminating, in this order, an underlying film made of a thin film containing an oxide, a lower layer film, and an upper layer film, the layer mask having an etching selectivity of 40 or more, and an etching step of forming vertical partition grooves by etching away exposed regions of the epitaxial layer that are not covered by the layer mask. Therefore, according to the method for manufacturing a semiconductor light-emitting element of the present invention, it is possible to form the side surfaces of the partition grooves so as to rise vertically relative to the upper surface of the epitaxial layer, and to manufacture a semiconductor light-emitting element having partition grooves with narrow groove widths. Therefore, by using the method for manufacturing a semiconductor light-emitting element of the present invention, it is possible to manufacture semiconductor light-emitting elements with higher pixel density and / or a wider light-emitting area. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a side view showing the structure of a semiconductor light emitting element according to a first embodiment. [Figure 2] 1 is a perspective view showing the structure of a semiconductor light emitting element according to a first embodiment. [Figure 3] 2 is a partially enlarged plan view showing an enlarged pixel of the semiconductor light emitting device of the first embodiment. FIG. [Figure 4] 4(A) to 4(E) are perspective views illustrating the steps of manufacturing the semiconductor light emitting device of the first embodiment. [Figure 5] 5(A) to 5(D) are cross-sectional views for explaining the partitioning groove forming step. [Figure 6] 4 is a schematic cross-sectional view showing an example of a semiconductor light emitting device including the semiconductor light emitting element of the first embodiment, including a cross-sectional view of the semiconductor light emitting element in a region corresponding to line II shown in FIG. [Figure 7] FIG. 7 is a schematic diagram showing VR goggles, which is an example of a display device including the semiconductor light emitting device of this embodiment. [Figure 8] FIG. 8 is a partially enlarged plan view showing an enlarged pixel of the semiconductor light emitting device according to the second embodiment. [Figure 9]FIG. 9 is a cross-sectional view of the pixel shown in FIG. 8 taken along lines AA, BB, and CC. [Figure 10] FIG. 10 is a cross-sectional view of the pixel shown in FIG. 8 taken along line DD. [Figure 11] FIG. 10 is a schematic cross-sectional view showing an example of a semiconductor light emitting device including the semiconductor light emitting element of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] In order to solve the above problems, the present inventors have focused on a method for manufacturing a semiconductor light-emitting device and have conducted extensive research as described below. In general, a semiconductor light-emitting device having an epitaxial layer including at least one light-emitting layer, the epitaxial layer having a plurality of pixels partitioned by partition grooves in a planar view, a power supply layer that is the uppermost layer of the epitaxial layer and supplies power to the light-emitting layer, and an electrode provided on the power supply layer, is manufactured using the method described below.

[0016] First, a lamination step is performed to form an epitaxial layer, then a partition groove forming step is performed to form partition grooves in the epitaxial layer to form a plurality of pixels, and then a pixel forming step is performed to form each pixel. In this case, in the partition groove forming step, a mask is typically formed in a predetermined region of the top layer of the epitaxial layer. Next, the epitaxial layer in the exposed region not covered by the mask is removed by etching. This forms the partition groove. After that, the mask is removed from the top surface of the epitaxial layer.

[0017] The present inventors have conducted extensive research into masks to be used in the partition groove formation step, and have found that by using a layered mask formed by laminating a lower layer film and an upper layer film in this order from the epitaxial layer side, in which the etching selectivity of the lower layer film to the upper layer film is 40 or more, it is possible to form the side surfaces of the partition grooves so as to rise vertically to the upper surface of the epitaxial layer, and to manufacture a semiconductor light-emitting device having partition grooves with narrow groove widths.

[0018] Furthermore, the present inventors have found that by forming a base film consisting of a thin film containing one or more oxides that can be used as part of the layered mask on the upper surface of the epitaxial layer before forming the layered mask, it is possible to form the side shapes of the partition grooves so that they rise vertically relative to the upper surface of the epitaxial layer, and to manufacture semiconductor light-emitting elements having partition grooves with narrow groove widths, and have arrived at the present invention.

[0019] The semiconductor light-emitting element and its manufacturing method, and the semiconductor light-emitting device and its manufacturing method of the present invention will be described in detail below with appropriate reference to the drawings. The drawings used in the following description may show characteristic portions enlarged for the sake of clarity. Therefore, the dimensional ratios of each component may differ from the actual ones. The materials, dimensions, etc. exemplified in the following description are merely examples, and the present invention is not limited to them. Appropriate modifications can be made within the scope of the present invention.

[0020] In this specification, an epitaxial layer and an electrode arranged so that a predetermined light-emitting layer in the epitaxial layer can emit light is referred to as a "semiconductor light-emitting element." Furthermore, an element formed by placing the semiconductor light-emitting element on a mounting substrate is referred to as a "semiconductor light-emitting device."

[0021] First Embodiment (semiconductor light emitting element) Fig. 1 is a side view showing the structure of the semiconductor light emitting device of the first embodiment, Fig. 2 is a perspective view showing the structure of the semiconductor light emitting device of the first embodiment, and Fig. 3 is a partially enlarged plan view showing an enlarged pixel of the semiconductor light emitting device of the first embodiment. 1 and 2, the semiconductor light emitting device 1 of the first embodiment includes a sapphire substrate 10, a buffer layer 20, and an epitaxial layer 30. Reference numeral 81 shown in FIGS. 1 and 2 indicates the stacking direction of the sapphire substrate 10, the buffer layer 20, and the epitaxial layer 30.

[0022] [Sapphire substrate structure] The sapphire substrate 10 is made of a plate-like sapphire whose both surfaces are polished to be flat. The thickness of the sapphire substrate 10 is, for example, 300 μm. In the following description, when a semiconductor light-emitting device including the semiconductor light-emitting element 1 is used in a display device, the surface opposite to the surface from which light is emitted is referred to as the "top surface." That is, the surface of the sapphire substrate 10 opposite the viewer's eyes (the upper surface in FIGS. 1 and 2) is referred to as the "top surface." The surfaces of the buffer layer 20 and each layer forming the epitaxial layer 30 opposite the viewer's eyes are also referred to as the "top surface" (the upper surface in FIGS. 1 and 2).

[0023] [Buffer layer configuration] The buffer layer 20 is laminated on the upper surface of the sapphire substrate 10. The buffer layer 20 preferably has a higher refractive index than the sapphire substrate 10. The thickness of the buffer layer 20 is, for example, 2 μm. The buffer layer 20 may be made of AlN, GaN, or the like grown at low temperature.

[0024] [Epitaxial layer structure] 1, the epitaxial layer 30 includes a first n-type layer 301, a first light-emitting layer 30B (light-emitting layer), a first p-type layer 302, a first tunnel junction layer 303, a second n-type layer 304, a second light-emitting layer 30G (light-emitting layer), a second p-type layer 305, a second tunnel junction layer 306, a third n-type layer 307, a third light-emitting layer 30R (light-emitting layer), a third p-type layer 308, a third tunnel junction layer 309, and a fourth n-type layer 310, which are stacked in this order.

[0025] 1, the epitaxial layer 30 has three light-emitting unit layers: a light-emitting unit layer UB in which a first p-type layer 302, a first light-emitting layer 30B, and a first n-type layer 301 are stacked in this order when viewed from above; a light-emitting unit layer UG in which a second p-type layer 305, a second light-emitting layer 30G, and a second n-type layer 304 are stacked in this order when viewed from above; and a light-emitting unit layer UR in which a third p-type layer 308, a third light-emitting layer 30R, and a third n-type layer 307 are stacked in this order when viewed from above. Furthermore, the epitaxial layer 30 has a second tunnel junction layer 306 disposed between the light-emitting unit layer UR and the light-emitting unit layer UG, and a first tunnel junction layer 303 disposed between the light-emitting unit layer UB and the light-emitting unit layer UG.

[0026] The first n-type layer 301 is stacked on the upper surface of the buffer layer 20. The thickness of the first n-type layer 301 is, for example, 2 μm. The first n-type layer 301 is formed of, for example, GaN doped with n-type impurities such as Si.

[0027] The first light emitting layer 30B is stacked on the upper surface of the first n-type layer 301. The first light emitting layer 30B is formed, for example, as a multiple quantum well. The thickness of the first light emitting layer 30B is, for example, 50 nm. The first light emitting layer 30B is configured to be able to generate light with an emission wavelength corresponding to blue.

[0028] The first p-type layer 302 is stacked on the upper surface of the first light emitting layer 30B. The thickness of the first p-type layer 302 is, for example, 180 nm. The first p-type layer 302 is formed of GaN doped with p-type impurities such as Mg.

[0029] The first tunnel junction layer 303 is stacked on the upper surface of the first p-type layer 302. The thickness of the first tunnel junction layer 303 is, for example, 25 nm. The first tunnel junction layer 303 is formed by stacking an n++ GaN layer doped with a high concentration of Si and a p++ GaN layer doped with a high concentration of Mg. Here, n++ means a state where n-type impurities are heavily doped, and p++ means a state where p-type impurities are heavily doped. Note that by providing a tunnel junction layer between the n-type and p-type semiconductors, it becomes possible to pass current from the n-type semiconductor to the p-type semiconductor.

[0030] The second n-type layer 304 is stacked on the upper surface of the first tunnel junction layer 303. The thickness of the second n-type layer 304 is, for example, 400 nm. The second n-type layer 304 is formed of, for example, GaN doped with n-type impurities such as Si.

[0031] The second light emitting layer 30G is stacked on the upper surface of the second n-type layer 304. The second light emitting layer 30G is formed, for example, as a multiple quantum well. The thickness of the second light emitting layer 30G is, for example, 50 nm. The second light emitting layer 30G is configured to be able to generate light with an emission wavelength corresponding to green.

[0032] The second p-type layer 305 is laminated on the upper surface of the second light emitting layer 30G. The thickness of the second p-type layer 305 is, for example, 180 nm. The second p-type layer 305 is formed of GaN doped with p-type impurities such as Mg.

[0033] The second tunnel junction layer 306 is stacked on the upper surface of the second p-type layer 305. The thickness of the second tunnel junction layer 306 is, for example, 25 nm. The second tunnel junction layer 306 is formed by stacking an n++ GaN layer doped with a high concentration of Si and a p++ GaN layer doped with a high concentration of Mg.

[0034] The third n-type layer 307 is stacked on the upper surface of the second tunnel junction layer 306. The third n-type layer 307 has a thickness of, for example, 400 nm. The third n-type layer 307 is formed of, for example, GaN doped with n-type impurities such as Si.

[0035] The third light emitting layer 30R is stacked on the upper surface of the third n-type layer 307. The third light emitting layer 30R is formed, for example, as a multiple quantum well. The third light emitting layer 30R has a thickness of, for example, 50 nm. The third light emitting layer 30R is configured to be able to emit light with an emission wavelength corresponding to red.

[0036] The third p-type layer 308 is laminated on the upper surface of the third light emitting layer 30R. The third p-type layer 308 has a thickness of, for example, 180 nm. The third p-type layer 308 is formed of, for example, GaN doped with p-type impurities such as Mg.

[0037] The third tunnel junction layer 309 is stacked on the upper surface of the third p-type layer 308. The thickness of the third tunnel junction layer 309 is, for example, 25 nm. The third tunnel junction layer 309 is formed by stacking an n++ GaN layer doped with a high concentration of Si and a p++ GaN layer doped with a high concentration of Mg.

[0038] The fourth n-type layer 310 is stacked on the upper surface of the third tunnel junction layer 309. The fourth n-type layer 310 has a thickness of, for example, 400 nm. The fourth n-type layer 310 is formed of, for example, GaN doped with n-type impurities such as Si.

[0039] [Pixel configuration] As shown in Fig. 3, the epitaxial layer 30 of the semiconductor light-emitting element 1 of this embodiment has a plurality of pixels 70 that are partitioned by partitioning grooves 80 in a plan view. As shown in Figs. 2 and 3, each pixel 70 has a plurality of sub-pixels 71 that emit light at different wavelengths. Each pixel 70 in the semiconductor light-emitting element 1 of this embodiment has three sub-pixels 71: a red light-emitting diode 71R, a green light-emitting diode 71G, and a blue light-emitting diode 71B.

[0040] The pixel 70 in the semiconductor light emitting element 1 has a substantially square shape in a plan view. As shown in Fig. 3, the red light emitting diode 71R, the green light emitting diode 71G, and the blue light emitting diode 71B are substantially the same type in a plan view, and have a substantially rectangular shape whose long side is the length of one side of the pixel 70 and whose short side is approximately 1 / 3 the length of one side of the pixel 70. The red light emitting diode 71R, the green light emitting diode 71G, and the blue light emitting diode 71B are formed adjacent to each other in a direction perpendicular to one direction.

[0041] As shown in FIGS. 1 and 2, the partition grooves 80 are recessed (in the stacking direction 81) from the uppermost layer of the epitaxial layer 30 (in this embodiment, the fourth n-type layer 310) toward the sapphire substrate 10. The bottom surfaces of the partition grooves 80 reach the upper surface of the sapphire substrate 10. The side surfaces of the partition grooves 80 are formed approximately perpendicular to the sapphire substrate 10. The depth dimension of the partition grooves 80 in the stacking direction 81 (see FIG. 1) (depth dimension from the upper surface of the fourth n-type layer 310) is approximately 6 μm.

[0042] 3, each pixel 70 is formed in an island shape on the upper surface of the sapphire substrate 10 by a partitioning groove 80 that surrounds the outer periphery of each pixel 70. On the upper surface of the sapphire substrate 10, a plurality of island-shaped pixels 70 are aligned in one direction and in a direction perpendicular to the one direction.

[0043] As shown in Fig. 2, the red light-emitting diode 71R has a light-emitting main body portion 72 and a non-light-emitting portion 73. The uppermost layer (fourth n-type layer 310) of the epitaxial layer 30 is exposed on the upper surface of the light-emitting main body portion 72. The non-light-emitting portion 73 is adjacent to the light-emitting main body portion 72 and aligned in one direction. The non-light-emitting portion 73 is formed by removing the third light-emitting layer 30R through the fourth n-type layer 310 of the epitaxial layer 30. As a result, the third n-type layer 307 is exposed on the upper surface of the non-light-emitting portion 73.

[0044] The upper surface of the light-emitting main body 72 is the upper surface of the fourth n-type layer 310, which is a power supply layer from the third p-type layer 308 side to the third light-emitting layer 30R. A positive electrode 31p, which is an electrode 31, is laminated on the upper surface of the light-emitting main body 72. The upper surface of the non-light-emitting portion 73 is the exposed surface of the third n-type layer 307, which is a power supply layer from the third n-type layer 307 side to the third light-emitting layer 30R. A negative electrode 31n, which is an electrode 31, is laminated on the upper surface of the non-light-emitting portion 73. In the red light-emitting diode 71R, a circuit that supplies electricity to the third light-emitting layer 30R is formed by the positive electrode 31p provided on the fourth n-type layer 310 and the negative electrode 31n provided on the third n-type layer 307.

[0045] The green light-emitting diode 71G has a light-emitting body portion 74 and a non-light-emitting portion 75. The light-emitting body portion 74 has the third light-emitting layer 30R through the fourth n-type layer 310 of the epitaxial layer 30 removed. As a result, the third n-type layer 307 is exposed on the upper surface of the light-emitting body portion 74. The non-light-emitting portion 75 is adjacent to the light-emitting body portion 74 and aligned in one direction. The non-light-emitting portion 75 has the epitaxial layer 30 removed from the second light-emitting layer 30G through the fourth n-type layer 310. As a result, the second n-type layer 304 is exposed on the upper surface of the non-light-emitting portion 75.

[0046] The upper surface of the light-emitting main body 74 is the surface where the third n-type layer 307, which serves as a power supply layer from the second p-type layer 305 side to the second light-emitting layer 30G, is exposed. A positive electrode 31p, which is an electrode 31, is laminated on the upper surface of the light-emitting main body 74. The upper surface of the non-light-emitting portion 75 is the surface where the second n-type layer 304, which serves as a power supply layer from the second n-type layer 304 side to the second light-emitting layer 30G, is exposed. A negative electrode 31n, which is an electrode 31, is laminated on the upper surface of the non-light-emitting portion 75. In the green light-emitting diode 71G, a circuit that supplies electricity to the second light-emitting layer 30G is formed by the positive electrode 31p provided on the third n-type layer 307 and the negative electrode 31n provided on the second n-type layer 304. As shown in FIGS. 1 and 2, the second light-emitting layer 30G is continuous with the red light-emitting diode 71R, which is an adjacent sub-pixel 71, and is also included in the region of the red light-emitting diode 71R.

[0047] The blue light-emitting diode 71B has a light-emitting body portion 76 and a non-light-emitting portion 77. The light-emitting body portion 76 has the epitaxial layer 30 removed from the second light-emitting layer 30G to the fourth n-type layer 310. As a result, the second n-type layer 304 is exposed on the upper surface of the light-emitting body portion 76. The non-light-emitting portion 77 is adjacent to the light-emitting body portion 76 and aligned in one direction. The non-light-emitting portion 77 has the epitaxial layer 30 removed from the first light-emitting layer 30B to the fourth n-type layer 310. As a result, the first n-type layer 301 is exposed on the upper surface of the non-light-emitting portion 77.

[0048] The upper surface of the light-emitting main body 76 is the surface where the second n-type layer 304, which serves as a power supply layer from the first p-type layer 302 side to the first light-emitting layer 30B, is exposed. A positive electrode 31p, which is an electrode 31, is laminated on the upper surface of the light-emitting main body 76. The upper surface of the non-light-emitting portion 77 is the surface where the first n-type layer 301, which serves as a power supply layer from the first n-type layer 301 side to the first light-emitting layer 30B, is exposed. A negative electrode 31n, which is an electrode 31, is laminated on the upper surface of the non-light-emitting portion 77. In the blue light-emitting diode 71B, a circuit that supplies electricity to the first light-emitting layer 30B is formed by the positive electrode 31p provided on the second n-type layer 304 and the negative electrode 31n provided on the first n-type layer 301. As shown in FIGS. 1 and 2, the first light-emitting layer 30B is continuous with the green light-emitting diode 71G, which is an adjacent sub-pixel 71, and is also included in the regions of the green light-emitting diode 71G and the red light-emitting diode 71R.

[0049] As described above, in each subpixel 71, a portion of the epitaxial layer 30 is removed to the extent that the buffer layer 20 is not exposed. Furthermore, power supply layers that supply current from the p-type layer side and n-type layer side of each of the first light-emitting layer 30B, the second light-emitting layer 30G, and the third light-emitting layer 30R are exposed on the upper surface of the epitaxial layer 30. Electrodes 31 are provided on each exposed power supply layer.

[0050] In this embodiment, the power supply layers in the subpixels 71 (red light-emitting diode 71R, green light-emitting diode 71G, and blue light-emitting diode 71B) are the second n-type layer 304, the third n-type layer 307, and the fourth n-type layer 310. In this embodiment, the first tunnel junction layer 303 allows a current to flow from the second n-type layer 304 to the first p-type layer 302. The second tunnel junction layer 306 allows a current to flow from the third n-type layer 307 to the second p-type layer 305. The third tunnel junction layer 309 allows a current to flow from the fourth n-type layer 310 to the third p-type layer 308.

[0051] (Method of manufacturing semiconductor light emitting element) Next, a method for manufacturing the semiconductor light emitting device 1 of this embodiment will be described with reference to Figures 4 and 5. Figures 4(A) to 4(E) are perspective views for explaining the steps for manufacturing the semiconductor light emitting device of the first embodiment. Figures 5(A) to 5(D) are cross-sectional views for explaining the partition groove forming step.

[0052] The manufacturing method of the semiconductor light-emitting element 1 of this embodiment includes a lamination process for forming the epitaxial layer 30, a partition groove formation process for forming partition grooves 80 in the epitaxial layer 30 to form multiple pixels 70, and a pixel formation process for forming multiple sub-pixels 71 in each pixel 70.

[0053] [Lamination process] In the stacking step, a buffer layer 20 and each layer forming an epitaxial layer 30 are stacked in this order on the upper surface of the sapphire substrate 10 by crystal growth using metal organic vapor phase epitaxy (MOVPE), as shown in FIG. 4(A).

[0054] [Partition groove forming process] Next, in the partition groove forming step, as shown in Fig. 4(B), partition grooves 80 are formed in the epitaxial layer 30 and the buffer layer 20. The partition groove forming step includes a layer mask forming step, an etching step, and a layer mask removing step.

[0055] (Layer mask formation process) In the layered mask formation step, as shown in FIG. 5(A), a thin base film 53, a thin metal bonding layer 54, and a lower layer 51 are layered in this order in contact with the entire surface of the uppermost layer of the epitaxial layer 30. The thin underlayer film 53 is, for example, ITO (indium tin oxide) with a thickness of 5 nm. The thin metal bonding layer 54 is, for example, Ti (titanium) with a thickness of 5 nm. The underlayer film 51 is, for example, SiO2 (silicon oxide) with a thickness of 500 nm. These can be formed using, for example, a sputtering device.

[0056] Next, as shown in FIG. 5(B), an upper layer film 52 is laminated on the lower layer film 51 in an area other than where the partitioning grooves 80 are to be formed. First, a resist material is applied to the upper surface of the lower layer film 51 to form a resist film. Next, a resist mask is formed using lithography only in the area where the partitioning grooves 80 are to be formed. Then, the upper layer film 52 is deposited by vapor deposition on the upper surface of the lower layer film 51 exposed from the resist mask and on the upper surface of the resist mask. Thereafter, the resist mask is removed, allowing the upper layer film 52 to be laminated on the area other than where the partitioning grooves 80 are to be formed. The upper layer film 52 is, for example, Ni (nickel) with a thickness of 100 nm. The upper layer film 52 can be formed using, for example, a vapor deposition apparatus.

[0057] 5(C), the lower layer 51, the metal bonding layer 54, and the base film 53 are removed by dry etching using CF4, a fluoride gas, from the region of the lower layer 51 where the partitioning grooves 80 are to be formed, which is not covered by the upper layer 52. In this embodiment, the etching rate of the lower layer 51 with respect to the fluoride gas is sufficiently higher than that of the upper layer 52. Therefore, the side surfaces of the upper layer 52 and the lower layer 51 that form the layered mask 50 are formed so as to rise vertically with an extremely small taper angle. In this manner, the layered mask 50 is formed.

[0058] (etching process) In the etching process, as shown in FIG. 5(D), dry etching using Cl2 (chlorine gas) is performed to remove the buffer layer 20 and the epitaxial layer 30 in the exposed regions not covered by the layer mask 50. The etching is performed to a depth reaching the top surface of the sapphire substrate 10 and is stopped when the etching reaches the top surface of the sapphire substrate 10. As a result, as shown in FIG. 4(B), partition grooves 80 are formed around the periphery of the pixels 70, reaching the top surface of the sapphire substrate 10, and multiple island-shaped pixels 70 are formed on the sapphire substrate 10. At this time, the etching rate of the GaN buffer layer 20 and the epitaxial layer 30 with respect to the layer mask 50 with respect to Cl2 is sufficiently high, and the partition grooves 80 have a deep, vertically sheer shape with an extremely small taper angle.

[0059] (Stacked mask removal process) In the layer mask removal step, the layer mask 50 provided on the upper surface of the epitaxial layer 30 is removed using hydrofluoric acid, which is an aqueous solution containing hydrogen fluoride at a predetermined concentration. As a result, the entire upper surface of the uppermost layer of the epitaxial layer 30 is exposed, as shown in FIG. 4(B).

[0060] Experiments by the inventors have confirmed that the above-described partition groove formation process can form partition grooves 80 with wall angles of 89 degrees relative to the upper surface of the sapphire substrate 10. Furthermore, it has been confirmed that partition grooves 80 with wall angles of 87 degrees can be formed when the ITO thickness of the thin-film undercoat film 53 is 20 nm and other conditions are the same. When the partition grooves 80 with wall angles of 89 degrees and 87 degrees are 6 μm deep, the inclined surface effect of the partition grooves 80 (6 μm × tan (taper angle)) can be suppressed to 0.1 μm and 0.3 μm, respectively. Theoretically, partition grooves 80 with widths of 0.3 μm or 0.7 μm can be formed. Alternatively, with a margin, partition grooves 80 with widths of 0.5 μm or 1 μm can be formed. This allows for increased pixel density and / or a wider light-emitting area.

[0061] In the laminate mask forming step of the partition groove forming step, oxides such as Al2O3 and nitrides such as Al2O3 can be used instead of SiO2 as the material for the lower layer film 51. Furthermore, Pt, Cr, etc. can be used instead of Ni as the material for the upper layer film 52.

[0062] The materials of the lower layer 51 and the upper layer 52 are combined so that the etching selectivity of the material of the lower layer 51 relative to the material of the upper layer 52 is 40 or more in the step of etching the layered mask 50. By using such a combination, the etching rate of the lower layer 51 relative to the upper layer 52 is sufficiently high. For example, the etching selectivity of the lower layer 51 made of SiO to the upper layer 52 made of Ni is approximately 50.

[0063] Instead of ITO, conductive oxides such as In2O3-SnO2 (90-10 wt%) and AZO[ZnO:Al]-IZO[In2O3-ZnO] (90-10 wt%) can be used as the material for the thin-film underlayer 53. Instead of Ti, Ni, Cr, or the like can be used as the material for the thin-film metal bonding layer 54. Furthermore, the metal bonding layer 54 may be formed as needed, or may not be formed.

[0064] The thickness of the base film 53 and the metal bonding layer 54 may be within a range that allows the desired perpendicular partitioning grooves 80 to be formed, but it is desirable that the total thickness of the thin films be 40 nm or less. In this case, the thickness is 1 / 10 or less of the 400 nm thickness of the fourth n-type layer 310. In order to further suppress the influence of the base film 53 and the metal bonding layer 54, the thickness may be 25 nm or less, or 10 nm or less.

[0065] In the etching step of the partitioning groove forming step, SF6, CHF3, or the like can be used as the material of the fluoride gas used to remove the lower layer film 51, the metal bonding layer 54, and the base film 53 instead of CF4.

[0066] [Pixel formation process] Next, in the pixel formation step, as shown in FIGS. 4(C) to 4(E), the surface on which the sub-pixels 71 are to be formed is exposed. First, a resist mask is laminated on the entire upper surface of the top layer of the epitaxial layer 30 shown in FIG. 4(B) in a region that will become the light-emitting main body 72. The resist mask can be formed in the same manner as when the upper layer 52 is laminated. Then, by dry etching using Cl2, the third light-emitting layer 30R to the fourth n-type layer 310 of the epitaxial layer 30 are removed. As a result, as shown in FIG. 4(C), the region where the resist mask is laminated, that will become the light-emitting main body 72, remains in a protruding shape. Then, the third n-type layer 307 is exposed in the region where the resist mask is not laminated (see FIGS. 1 and 2).

[0067] Next, a resist mask is deposited on the regions where the light-emitting main body portion 72, the non-light-emitting portion 73, and the light-emitting main body portion 74 will be formed. Then, dry etching is performed using Cl2 to remove the second light-emitting layer 30G to the third n-type layer 307 in the epitaxial layer 30 in the regions where the resist mask is not deposited. As a result, as shown in FIG. 4(D), the second n-type layer 304 is exposed in the regions where the resist mask is not deposited (see FIGS. 1 and 2).

[0068] Next, a resist mask is deposited on the regions where the light-emitting main body portion 72, the non-light-emitting portion 73, the light-emitting main body portion 74, the non-light-emitting portion 75, and the light-emitting main body portion 76 will be formed. Then, dry etching is performed using Cl2 to remove the first light-emitting layer 30B to the second n-type layer 304 in the epitaxial layer 30 in the regions where the resist mask is not deposited. As a result, as shown in FIG. 4(E), the first n-type layer 301 is exposed in the regions where the resist mask is not deposited (see FIG. 2), and this becomes the region where the non-light-emitting portion 77 will be formed.

[0069] In this way, sub-pixels 71 are formed by forming electrodes 31 on each layer of the epitaxial layer 30 exposed in the areas forming the light-emitting main body portion 72, the non-light-emitting portion 73, the light-emitting main body portion 74, the non-light-emitting portion 75, the light-emitting main body portion 76, and the non-light-emitting portion 77 in a planar view (electrode formation process).

[0070] The electrode 31 is formed after forming a passivation film (not shown) made of SiO2 with an opening in the region where the electrode 31 is to be formed by a known method on the entire upper surface of the epitaxial layer 30. After the electrode 31 is formed, the passivation film is removed by a known method. By carrying out the above steps, the semiconductor light emitting device 1 of this embodiment is obtained.

[0071] (Semiconductor light-emitting device) Next, the semiconductor light emitting device of this embodiment will be described with reference to Fig. 6. Fig. 6 is a schematic cross-sectional view showing an example of a semiconductor light emitting device including the semiconductor light emitting element of the first embodiment, and includes a cross-sectional view of the semiconductor light emitting element in a region corresponding to line II shown in Fig. 3. As shown in FIG. 6, the semiconductor light emitting device 100 of this embodiment is configured by mounting the semiconductor light emitting element 1 of the first embodiment on a mounting substrate 90.

[0072] For example, sapphire, Si, low thermal expansion glass, etc. are used for the mounting substrate 90. Wiring 91 made of Cu, Au, etc. is formed on the surface of the mounting substrate 90 on which the semiconductor light emitting element 1 is mounted. In the semiconductor light-emitting device 100 of this embodiment, as shown in FIG. 6, multiple sub-pixels 71 (red light-emitting diode 71R, green light-emitting diode 71G, and blue light-emitting diode 71B) of each pixel 70 of the semiconductor light-emitting element 1 are integrated into each pixel 70.

[0073] As a method for mounting the semiconductor light emitting element 1 of the first embodiment on the mounting substrate 90, for example, a method can be used in which the positive electrode 31p and the negative electrode 31n (see FIGS. 2 and 3) of each of the red light emitting diode 71R, the green light emitting diode 71G, and the blue light emitting diode 71B of the semiconductor light emitting element 1 are electrically connected to the wiring 91 via metal bumps 92. The metal bumps 92 may be made of, for example, Au, Cu, an alloy of Au and Su, or the like.

[0074] (display device) FIG. 7 is a schematic diagram showing VR goggles, which is an example of a display device including the semiconductor light emitting device of this embodiment. VR (Virtual Reality) goggles 200 shown in FIG. 7 include a plurality of semiconductor light emitting devices 100 mounted on a mounting substrate. 7, the semiconductor light emitting device 100 included in the VR goggles 200 is placed in front of the viewer's eyes 202, with lenses 201 sandwiched between them. The distance between the semiconductor light emitting device 100 and the viewer's eyes 202 is approximately 5 cm.

[0075] The semiconductor light-emitting element 1 of this embodiment provided in the semiconductor light-emitting device 100 is disposed on the sapphire substrate 10 so that the epitaxial layer 30 is on the opposite side of the viewer's eyes 202. Therefore, in the VR goggles 200, light emitted from the epitaxial layer 30 passes through the sapphire substrate 10 and reaches the viewer's eyes 202.

[0076] The semiconductor light emitting device 100 provided in the VR goggles 200 shown in Fig. 7 is a self-luminous display in which, for example, 320 x 180 pixels are densely arranged in a dot matrix. The width of the pixels of the semiconductor light emitting device 100 may be less than 100 µm. The width of the pixels of the semiconductor light emitting device 100 is formed to a size of, for example, 60 µm or 12 µm.

[0077] (Operation in the first embodiment) The manufacturing method of the semiconductor light-emitting element 1 of the first embodiment includes a layer mask forming process in which a base film 53 made of a thin film of conductive oxide is formed and placed in contact with a predetermined region of the top layer of the epitaxial layer 30, and a lower layer film 51 and an upper layer film 52 are stacked on top of the base film 53 in this order to form a layer mask 50 in which the etching selectivity of the lower layer film 51 to the upper layer film 52 is 40 or more; an etching process in which the epitaxial layer 30 in the exposed region not covered by the layer mask 50 is removed by etching to form a partition groove 80; and a layer mask removal process in which the layer mask 50 is removed from the top surface of the epitaxial layer 30. Therefore, according to the manufacturing method of the semiconductor light-emitting element 1 of the first embodiment, the side shape of the partition groove 80 can be formed so as to rise vertically relative to the upper surface of the epitaxial layer 30, and a semiconductor light-emitting element 1 having a partition groove 80 with a narrow groove width can be manufactured.

[0078] Furthermore, because the base film 53 is made of a thin film of a conductive oxide, even if at least a portion of the base film 53 remains, it does not adversely affect the characteristics as a power supply layer of the fourth n-type layer 310 exposed on the upper surface of the epitaxial layer 30. For this reason, when the semiconductor light-emitting element 1 is manufactured using the manufacturing method of the present invention, the formation of the partitioning grooves 80 can prevent the electrical characteristics of the semiconductor light-emitting element 1 from being impaired. Therefore, according to the manufacturing method of the semiconductor light-emitting element 1 of this embodiment, it is possible to increase the pixel density and / or increase the light-emitting area, and to obtain a semiconductor light-emitting element 1 having good electrical characteristics.

[0079] In the manufacturing method of this embodiment, the base film 53 disposed in contact with a predetermined region of the upper surface of the epitaxial layer 30 is made of a thin film of conductive oxide and is sufficiently thin. Therefore, the influence of the base film 53 on the layered mask 50 is slight. Furthermore, the influence of the base film 53 on the side shape of the partition grooves 80 formed using the layered mask 50 is negligible. Therefore, according to the manufacturing method of the semiconductor light-emitting element 1 of this embodiment, the partition grooves 80 can be formed so as to rise perpendicularly to the upper surface of the epitaxial layer 30.

[0080] The present invention is not limited to the first embodiment described above, and for example, the following embodiments are also included within the technical scope of the present invention. (Variation) The stacking order of the first light emitting layer 30B, the second light emitting layer 30G, and the third light emitting layer 30R of the semiconductor light emitting element 1 of the first embodiment is not limited to the stacking order of the semiconductor light emitting element 1 of the first embodiment. Furthermore, although the semiconductor light emitting device 1 of the first embodiment has been described as having three light emitting layers, it may have a single light emitting layer.

[0081] Furthermore, in the semiconductor light-emitting element 1 of the first embodiment, the depth of the partitioning grooves 80 has been described as reaching the upper surface of the sapphire substrate 10 as an example, but the depth of the partitioning grooves 80 may reach the buffer layer 20 but not reach the sapphire substrate 10. Furthermore, although the semiconductor light emitting element 1 of the first embodiment has been described as including the sapphire substrate 10 and the buffer layer 20, it may not include the sapphire substrate 10 and the buffer layer 20. For example, after the semiconductor light emitting element 1 is mounted on the mounting substrate 90, the sapphire substrate 10, or the sapphire substrate 10 and the buffer layer 20, may be removed by laser lift-off.

[0082] Second Embodiment (semiconductor light emitting element) Fig. 8 is a partially enlarged plan view showing an enlarged pixel of the semiconductor light emitting device of the second embodiment. Fig. 9 is a cross-sectional view corresponding to lines AA, BB, and CC of the pixel shown in Fig. 8. Fig. 10 is a cross-sectional view corresponding to line DD of the pixel shown in Fig. 8.

[0083] In the semiconductor light emitting device 2 of the second embodiment, the same components as those in the semiconductor light emitting device 1 of the first embodiment are denoted by the same reference numerals and detailed description thereof will be omitted. Furthermore, in the semiconductor light emitting device 2 of the second embodiment, the materials and shapes of components having the same configuration as those in the semiconductor light emitting device 1 of the first embodiment, as well as the manufacturing method, can be applied mutatis mutandis to the semiconductor light emitting device 1 of the first embodiment.

[0084] The semiconductor light-emitting element 2 of the second embodiment differs from the first embodiment in the configuration of the epitaxial layer 30 whose outermost surface is the third p-type layer 308, the pixel configuration in which all of the electrodes 31 of the pixel 70 are formed on the base film 53a of the stacked mask 50, and the process of forming the partition grooves in which the thin base film 53 and the thin metal bonding layer 54 are formed by vapor deposition.

[0085] [Epitaxial layer structure] In the semiconductor light emitting device 1 of the first embodiment, the epitaxial layer 30 has been described as having the third tunnel junction layer 309 and the fourth n-type layer 310. However, as shown in Figures 9 and 10, the epitaxial layer 30 of the semiconductor light emitting device 2 of the second embodiment does not have these layers. Therefore, the uppermost layer of the epitaxial layer 30 is the third p-type layer 308.

[0086] [Pixel configuration] The epitaxial layer 30 of the semiconductor light-emitting element 2 of this embodiment, like the epitaxial layer 30 of the semiconductor light-emitting element 1 of the first embodiment, has a plurality of pixels 70 partitioned by partitioning grooves 80 in a planar view, and each pixel 70 has a plurality of sub-pixels 71 (a red light-emitting diode 71R, a green light-emitting diode 71G, and a blue light-emitting diode 71B) with different emission wavelengths.

[0087] The epitaxial layer 30 of the semiconductor light-emitting element 2 of the second embodiment differs from the epitaxial layer 30 of the semiconductor light-emitting element 1 of the first embodiment in that the multiple sub-pixels 71 are partitioned into red light-emitting diodes 71R, green light-emitting diodes 71G, and blue light-emitting diodes 71B in plan view by sub-pixel partition grooves 802 extending from the upper surface of the epitaxial layer 30 to the sapphire substrate 10, as shown in Figures 8 and 10.

[0088] Furthermore, the epitaxial layer 30 of the semiconductor light-emitting element 2 of the second embodiment differs from the epitaxial layer 30 of the semiconductor light-emitting element 1 of the first embodiment in that, as shown in Figures 8 to 10, each sub-pixel 71 is divided into light-emitting main body portions 72, 74, 76 and non-light-emitting portions 73, 75, 77 in a planar view by a dividing groove 801 that extends from the upper surface of the epitaxial layer 30 to the n-type layer of a predetermined light-emitting unit layer.

[0089] 9, blue light-emitting diode 71B has a light-emitting body portion 76 and a non-light-emitting portion 77. A dividing groove 801 is provided between light-emitting body portion 76 and non-light-emitting portion 77 of blue light-emitting diode 71B, and reaches first n-type layer 301 of light-emitting unit layer UB including first light-emitting layer 30B.

[0090] 9, a positive electrode 31p (first electrode) and a negative electrode 31n (second electrode), which are electrodes 31, are arranged via a base film 53a on the power supply layer, which is the uppermost layer (third p-type layer 308) of the epitaxial layer 30. Specifically, the positive electrode 31p is laminated as a light-emitting main body portion-side electrode on the surface of the epitaxial layer 30 facing the light-emitting main body portion 76, and the negative electrode 31n is laminated as a non-light-emitting portion-side electrode on the surface of the non-light-emitting portion 77.

[0091] 9, a conductive via 32p (first conductive via) extending to the second n-type layer 304 located closer to the positive electrode 31p than the light-emitting unit layer UB including the first light-emitting layer 30B is connected to the positive electrode 31p. Also, a conductive via 32n (second conductive via) extending to the first n-type layer 301 included in the light-emitting unit layer UB including the first light-emitting layer 30B is connected to the negative electrode 31n.

[0092] 9, the green light-emitting diode 71G has a light-emitting body portion 74 and a non-light-emitting portion 75. A dividing groove 801 is provided between the light-emitting body portion 74 and the non-light-emitting portion 75 of the green light-emitting diode 71G, and reaches the second n-type layer 304 in the light-emitting unit layer UG including the second light-emitting layer 30G.

[0093] 9, a positive electrode 31p (first electrode) and a negative electrode 31n (second electrode), which are electrodes 31, are arranged via a base film 53a on the power supply layer, which is the uppermost layer (third p-type layer 308) of the epitaxial layer 30. Specifically, the positive electrode 31p is laminated as a light-emitting main body portion-side electrode on the surface of the epitaxial layer 30 on the light-emitting main body portion 74 side, and the negative electrode 31n is laminated as a non-light-emitting portion-side electrode on the surface of the non-light-emitting portion 75 side.

[0094] 9, a conductive via 32p (first conductive via) extending to the third n-type layer 307 located closer to the positive electrode 31p than the light-emitting unit layer UG including the second light-emitting layer 30G is connected to the positive electrode 31p. Also, a conductive via 32n (second conductive via) extending to the second n-type layer 304 in the light-emitting unit layer UG including the second light-emitting layer 30G is connected to the negative electrode 31n.

[0095] 9, the red light-emitting diode 71R has a light-emitting body portion 72 and a non-light-emitting portion 73. A dividing groove 801 is provided between the light-emitting body portion 72 and the non-light-emitting portion 73 of the red light-emitting diode 71R, and reaches the third n-type layer 307 in the light-emitting unit layer UR including the third light-emitting layer 30R.

[0096] 9, a positive electrode 31p (first electrode) and a negative electrode 31n (second electrode), which are electrodes 31, are arranged via a base film 53a on the power supply layer, which is the uppermost layer (third p-type layer 308) of the epitaxial layer 30. Specifically, the positive electrode 31p is laminated as a light-emitting main body portion-side electrode on the surface of the epitaxial layer 30 facing the light-emitting main body portion 72, and the negative electrode 31n is laminated as a non-light-emitting portion-side electrode on the surface of the non-light-emitting portion 73.

[0097] As shown in FIG. 9, the negative electrode 31n is connected to a conductive via 32n (second conductive via) that extends to the third n-type layer 307 in the light-emitting unit layer UR including the third light-emitting layer 30R. The positive electrode 31p of the red light-emitting diode 71R is provided on the third p-type layer 308, which is present between the positive electrode 31p and the third light-emitting layer 30R, via an underlying film 53a. Therefore, there is no need to provide a conductive via 32p.

[0098] With the above configuration, in the blue light-emitting diode 71B, the green light-emitting diode 71G, and the red light-emitting diode 71R, a circuit is formed that conducts electricity to the first light-emitting layer 30B, the second light-emitting layer 30G, and the third light-emitting layer 30R, respectively, by the positive electrode 31p and the negative electrode 31n provided on the upper surface of the epitaxial layer 30 (third p-type layer 308) via the base film 53a. As shown in FIG. 9, all the positive electrodes 31p (first electrodes) and all the negative electrodes 31n (second electrodes) of the semiconductor light emitting element 2 of this embodiment are formed on the same surface.

[0099] The grooves of the conductive vias 32n on the non-light-emitting portions 73, 75, and 77 side are preferably formed, for example, when forming the dividing grooves 801 of the same subpixel. Also, the grooves of the conductive vias 32p on the light-emitting main body portions 74 and 76 side are preferably formed, for example, when forming the dividing grooves 801 of the same depth for different subpixels. The dividing grooves 801 of the blue light-emitting diode 71B and the green light-emitting diode 71G, and the grooves of the conductive vias 32 having the same depth as the dividing grooves 801 of the blue light-emitting diode 71B and the green light-emitting diode 71G, may be formed in several steps, or a groove of the required depth may be formed all at once.

[0100] Moreover, the positive electrode 31p and the negative electrode 31n are both disposed on the upper surface of the epitaxial layer 30 (third p-type layer 308) via an undercoat film 53a. Therefore, the positive electrode 31p and the negative electrode 31n can be simultaneously formed of the same material and to the same thickness by a sputtering method, a vapor deposition method, or the like. With this configuration, the heights of the mounting surfaces of the electrodes 31 of the semiconductor light emitting element 2 of the second embodiment can be easily aligned. As a result, the semiconductor light emitting element 2 can be easily and stably mounted on the mounting substrate 90.

[0101] [Partition groove forming process] (Layer mask formation process) In the semiconductor light emitting device 2 of the second embodiment, the thin-film base film 53 and the thin-film metal bonding layer 54 are, for example, 5 nm thick ITO (indium tin oxide) and 5 nm thick Ti (titanium), similar to the semiconductor light emitting device 1 of the first embodiment. However, while the thin-film base film 53 and the thin-film metal bonding layer 54 are formed by a sputtering apparatus in the semiconductor light emitting device 1 of the first embodiment, the semiconductor light emitting device 2 of the second embodiment differs in that they are formed by a vapor deposition apparatus. Note that the base film 51 is, for example, 500 nm thick SiO2, formed by a sputtering apparatus, similar to the first embodiment.

[0102] (Stacked mask removal process) In the layer mask removal step, the layer mask 50 is removed using a buffered hydrofluoric acid solution instead of the hydrofluoric acid used in the first embodiment. Furthermore, when removing the layer mask 50, the upper layer film 52, the lower layer film 51, and the metal bonding layer 54 are removed from the layer mask 50 provided on the upper surface of the epitaxial layer 30, leaving at least a portion of the base film 53. As a result, an base film 53a is formed on the entire upper surface of the uppermost layer of the epitaxial layer 30, as shown in FIGS. 9 and 10 .

[0103] The buffered hydrofluoric acid solution used to remove the layered mask 50 is a mixed solution of ammonium hydrogen fluoride, ammonium fluoride, and water. The materials forming the upper layer film 52, the lower layer film 51, and the metal bonding layer 54 have a sufficiently higher etching rate with respect to the buffered hydrofluoric acid solution than the material forming the base film 53. Therefore, removing the layered mask 50 using the buffered hydrofluoric acid solution makes it easy to leave at least a portion of the base film 53 of the layered mask 50 on the entire upper surface of the top layer of the epitaxial layer 30. The concentrations of ammonium hydrogen fluoride and ammonium fluoride in the buffered hydrofluoric acid solution can be determined appropriately depending on the material of the layered mask 50, the thickness of each layer forming the layered mask 50, and the like.

[0104] The semiconductor light emitting element 2 mounted on the semiconductor light emitting device 101 of this embodiment shown in Fig. 11 is obtained by removing the sapphire substrate 10 and the buffer layer 20 from the semiconductor light emitting element 2 shown in Fig. 8 to Fig. 10. Therefore, in the semiconductor light emitting element 2 included in the semiconductor light emitting device 101 shown in Fig. 11, each sub-pixel 71 (red light emitting diode 71R, green light emitting diode 71G, and blue light emitting diode 71B) is completely separated and independently mounted on the mounting substrate 90.

[0105] The semiconductor light emitting element 2 of the second embodiment can be mounted on the mounting substrate 90 using the same method as that used to mount the semiconductor light emitting element 1 of the first embodiment.

[0106] A known method for manufacturing a semiconductor light-emitting device 101 configured as shown in Fig. 11 is a pick-and-place method in which pixels of each color are manufactured and then arranged in a predetermined position on a mounting substrate 90. However, arranging and mounting many pixels one by one is very time-consuming. In addition, it is not easy to arrange minute pixels with high positional precision. In contrast, in a semiconductor light emitting device mounting the semiconductor light emitting element 1 of the first embodiment or the semiconductor light emitting element 2 of the second embodiment, all of the pixels 70 can be mounted together with the sapphire substrate 10 on the mounting substrate 90, so that minute pixels can be easily arranged with high positional precision. Furthermore, the partition grooves 80, which have a narrow groove width, allow the pixels 70 to be mounted at narrow intervals.

[0107] Furthermore, in the semiconductor light emitting element 2 of the second embodiment, the positive electrodes 31p and negative electrodes 31n of all the sub-pixels 71 are formed on the same plane. Therefore, the positive electrodes 31p and negative electrodes 31n of the semiconductor light emitting element 2 can be easily and stably mounted on the wiring 91 of the mounting substrate 90, which are formed on the same plane.

[0108] Furthermore, because the semiconductor light emitting element 2 can be stably bonded to the mounting substrate 90, for example, the sapphire substrate 10, or the sapphire substrate 10 and the buffer layer 20, can be easily removed after the semiconductor light emitting element 2 is mounted on the mounting substrate 90. More specifically, for example, when the sapphire substrate 10, or the sapphire substrate 10 and the buffer layer 20 are removed using a method such as laser lift-off, the sapphire substrate 10, or the sapphire substrate 10 and the buffer layer 20 can be removed in a stable state without damaging the structure of the semiconductor light emitting device 101.

[0109] As a result, as actually shown in Figure 11, in the semiconductor light-emitting device 101, the side surfaces of the pixels 70 and sub-pixels 71 are perpendicular to the mounting substrate 90, and the side surfaces of adjacent pixels 70 and sub-pixels 71 are parallel and closely spaced apart.

[0110] (Operation in the second embodiment) In the semiconductor light emitting element 2 of the second embodiment, similarly to the method for manufacturing the semiconductor light emitting element 1 of the first embodiment, the side surface of the partitioning grooves 80 can be formed so as to rise vertically to the upper surface of the epitaxial layer 30, and a semiconductor light emitting element 2 having partitioning grooves 80 with narrow groove widths can be manufactured. Therefore, a semiconductor light emitting element 2 can be obtained that can increase pixel density and / or increase the light emitting area. Furthermore, the outermost surface of the semiconductor light emitting device 2 of the second embodiment is the third p-type layer 308, which is easily damaged by exposure to plasma, but the thin base film 53 and the thin metal bonding layer 54 are formed by a deposition apparatus that does not expose them to plasma. This prevents the third p-type layer 308 from being damaged and adversely affecting its electrical properties, such as increasing its resistance. Furthermore, in a process after the partitioning grooves 80 are formed, even if the third tunnel junction layer 309 and the fourth n-type layer 310 are not present on the third p-type layer 308, the third p-type layer 308 can be protected by the base film 53a.

[0111] Third Embodiment (semiconductor light emitting element) In the semiconductor light emitting device of the third embodiment, the same materials and shapes as those of the semiconductor light emitting device 2 of the second embodiment and the manufacturing method thereof can be applied mutatis mutandis to the semiconductor light emitting device 2 of the second embodiment.

[0112] The semiconductor light emitting device of the third embodiment, like the semiconductor light emitting device 2 of the second embodiment, does not include the third tunnel junction layer 309 and the fourth n-type layer 310, and the upper surface of the epitaxial layer 30 is the third p-type layer 308. Meanwhile, unlike the semiconductor light emitting device 2 of the second embodiment, the semiconductor light emitting device of the third embodiment is similar to the semiconductor light emitting device 1 of the first embodiment in that the stacked layer mask 50 is entirely removed from the upper surface of the epitaxial layer 30 in the stacked layer mask removing step, and an electrode is formed on the upper surface of the epitaxial layer 30 exposed by removing the stacked layer mask 50 in the electrode forming step.

[0113] In the semiconductor light emitting device of the third embodiment, the layered mask 50 and the layered mask forming process are different from those of the semiconductor light emitting device 1 of the first embodiment and the semiconductor light emitting device 2 of the second embodiment.

[0114] In the semiconductor light emitting device of the third embodiment, in the layer mask formation step, a film made of the same material as the underlayer film 51 is formed by vapor deposition in contact with the upper surface of the third p-type layer 308 (the upper surface of the epitaxial layer 30) as the thin underlayer film 53. Thereafter, the underlayer film 51 is formed by sputtering without using the metal bonding layer 54. The underlayer film 53 formed by vapor deposition is, for example, SiO2 with a thickness of 20 nm, and the underlayer film 51 formed by sputtering is, for example, SiO2 with a thickness of 500 nm.

[0115] Even if the material is the same, the film quality will differ depending on the manufacturing conditions, and it is desirable that the base film 53 formed by the vapor deposition method be a thin film, for example, 50 nm or less, in which the influence is not significant.

[0116] (Operation in the third embodiment) In the semiconductor light emitting element of the third embodiment, similarly to the manufacturing methods of the semiconductor light emitting element 1 of the first embodiment and the semiconductor light emitting element 2 of the second embodiment, the side surface of the partitioning grooves 80 can be formed so as to rise vertically to the upper surface of the epitaxial layer 30, and a semiconductor light emitting element 1 having partitioning grooves 80 with narrow groove widths can be manufactured. Therefore, a semiconductor light emitting element 2 can be obtained that can increase pixel density and / or increase the light emitting area.

[0117] Furthermore, the outermost surface of the semiconductor light emitting device of the third embodiment is the third p-type layer 308, which is susceptible to damage when exposed to plasma, but the thin base film 53 and the thin metal bonding layer 54 are formed by a deposition apparatus that does not expose them to plasma. This prevents the third p-type layer 308 from being damaged and adversely affecting its electrical properties, such as increasing its resistance.

[0118] Furthermore, when a film made of the same material as underlying film 51 is formed by vapor deposition on the upper surface of epitaxial layer 30 as underlying film 53, underlying film 53 can be bonded to underlying film 51 with sufficient strength without providing metal bonding layer 54. Therefore, compared to the case where metal bonding layer 54 is provided, it can be easily formed with fewer steps.

[0119] In the semiconductor light-emitting devices of the first to third embodiments described above, the epitaxial layer 30 is a laminate of three light-emitting layers with different emission wavelengths, namely, a first light-emitting layer 30B, a second light-emitting layer 30G, and a third light-emitting layer 30R, and each pixel 70 has three sub-pixels 71, each of which is a red light-emitting diode 71R, a green light-emitting diode 71G, and a blue light-emitting diode 71B. Compared to an epitaxial layer having only one light-emitting layer, an epitaxial layer having a plurality of laminated light-emitting layers has a more pronounced effect due to the fact that the side surface of the partition groove can be formed to rise vertically to the upper surface of the epitaxial layer. However, the epitaxial layer of the semiconductor light-emitting device of the present invention may include at least one light-emitting layer, and may have only one light-emitting layer and no subpixels. A semiconductor light-emitting device having an epitaxial layer with only one light-emitting layer is suitable for use in, for example, a monochrome dot matrix display.

[0120] Although several embodiments and modifications of the present invention have been described, these embodiments and modifications are merely examples and do not limit the scope of the invention as claimed. These novel embodiments and modifications can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the present invention. Furthermore, not all combinations of features described in these embodiments and modifications are necessarily essential to the means for solving the problems of the invention. Furthermore, these embodiments and modifications are included within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0121] 1, 2...Semiconductor light emitting element 10...Sapphire substrate 31...Electrode 20...Buffer layer 30...Epitaxial layer 30B...first light-emitting layer (light-emitting layer) 30G...Second light-emitting layer (light-emitting layer) 30R...Third light-emitting layer (light-emitting layer) 50...Layered mask 80...Dividing groove 70...pixels 71...Subpixel 301...first n-type layer (power supply layer) 304...Second n-type layer (power supply layer) 307...Third n-type layer (power supply layer) 310...Fourth n-type layer (power supply layer)

Claims

1. an epitaxial layer including at least one light-emitting layer and an electrode; a method for manufacturing a semiconductor light-emitting element, wherein the epitaxial layer has a plurality of pixels partitioned by partition grooves in a plan view; a layered mask forming step of forming a layered mask on the epitaxial layer by laminating an underlayer film made of a thin film containing an oxide, a lower layer film, and an upper layer film in this order, wherein the etching selectivity of the lower layer film to the upper layer film is 40 or more; The epitaxial layer in the exposed region not covered by the layer mask is removed by etching, and forming the partition grooves vertically by etching.

2. The lower layer film is SiO ２ , Al ２ O ３ , Si ３ N ４ It consists of any one selected from The upper layer film is made of any one selected from Ni, Pt, and Cr. The method for manufacturing the semiconductor light emitting device according to claim 1 .

3. The oxide of the underlayer is a conductive material. The method for manufacturing the semiconductor light emitting device according to claim 1 .

4. In the step of removing the layered mask, at least a part of the base film is left. The method for manufacturing a semiconductor light emitting device according to claim 3 .

5. The oxide of the underlayer is formed by vapor deposition. The method for manufacturing the semiconductor light emitting device according to claim 1 .

6. The epitaxial layer is made of GaN, and the top layer of the epitaxial layer is p-type. The method for manufacturing a semiconductor light-emitting device according to claim 5 .

7. the underlayer film has a metal bonding layer made of a metal material laminated between the oxide of the underlayer film and the lower layer film; The method for manufacturing the semiconductor light emitting device according to claim 1 .

8. the epitaxial layer is a laminate of a plurality of light-emitting layers having different emission wavelengths, The pixel comprises a plurality of sub-pixels having different emission wavelengths. The method for manufacturing the semiconductor light-emitting device according to claim 1 .

Images