Transconductance amplifier, controller circuit, and dc / dc converter including the same

Abstract

To provide a transconductance amplifier capable of appropriately controlling gm according to an input voltage.SOLUTION: A transconductance amplifier 22 generates an output voltage obtained by amplifying a difference between an input voltage and a reference voltage. The transconductance amplifier 22 includes a differential amplifier circuit 280 including an input differential pair 282 to which the input voltage and the reference voltage are input and which operates according to a tail current and an output circuit 284 which generates an output voltage provided as an active load of the input differential pair, and a current control circuit 200 which controls the tail current. A current control circuit 200 is configured to increase the tail current in response to a current supply condition being met. The current supply condition is that the input voltage is lower than a first threshold voltage equal to or lower than the reference voltage or that the input voltage is higher than a second threshold voltage equal to or higher than the reference voltage.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a transconductance amplifier, a controller circuit, and a DC / DC converter including the same. [Background technology]

[0002] Various DC / DC converters use an error amplifier that receives a feedback voltage to bring their output voltage closer to a desired voltage. Patent Document 1 describes a step-up DC / DC converter equipped with an error amplifier that amplifies the error between a feedback voltage corresponding to the output voltage and a reference voltage. Patent Document 2 describes a step-down DC / DC converter equipped with an error amplifier that generates an error signal corresponding to the difference between a feedback voltage corresponding to the output voltage and the reference voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-187421 [Patent Document 2] Japanese Patent Application Publication No. 2018-107930

[0004] [overview] However, the inventors have come to recognize the following problem: When the load of a DC / DC converter fluctuates, if an error amplifier circuit including an error amplifier cannot respond to the fluctuation quickly enough, fluctuations in the output voltage of the DC / DC converter will increase.

[0005] The response speed of the error amplifier circuit can be increased by using a transconductance amplifier as the error amplifier and increasing its transconductance (hereinafter referred to as "gm"). However, in this case, there is a concern that the stability of the DC / DC converter's output voltage during steady state operation may decrease.

[0006] The present disclosure has been made in view of the above circumstances, and one of its exemplary purposes is to provide a transconductance amplifier that can appropriately control gm in accordance with an input voltage.

[0007] A transconductance amplifier according to one embodiment of the present disclosure generates an output voltage by amplifying the difference between an input voltage and a reference voltage. The transconductance amplifier includes a differential amplifier circuit that receives the input voltage and the reference voltage and includes an input differential pair that operates in response to a tail current and an output circuit that generates an output voltage provided as an active load of the input differential pair, and a current control circuit that controls the tail current. The current control circuit is configured to increase the tail current in response to a current supply condition being satisfied. The current supply condition is when the input voltage falls below a first threshold voltage that is equal to or less than the reference voltage, or when the input voltage exceeds a second threshold voltage that is equal to or greater than the reference voltage.

[0008] Any combination of the above components and conversion of the expressions of the present disclosure into methods, devices, systems, etc. are also valid aspects of the present disclosure. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram of a DC / DC converter according to a first embodiment. [Figure 2] FIG. 2 is a block diagram of the first error amplifier according to the embodiment. [Figure 3] FIG. 3 is a circuit diagram of the first current control circuit according to the embodiment. [Figure 4] FIG. 4 is a circuit diagram of the second current control circuit according to the embodiment. [Figure 5] FIG. 5 is a circuit diagram of the differential amplifier circuit according to the embodiment. [Figure 6] FIG. 6 is a diagram showing changes in the first output current supplied by the first current control circuit and the second output current supplied by the second current control circuit relative to the feedback voltage. [Figure 7]FIG. 7 is a diagram showing an example of the output voltage of the error amplifier circuit according to the first embodiment, and a timing chart of the output voltage of the error amplifier circuit according to the first comparison technique and the error amplifier circuit according to the second comparison technique. [Figure 8] FIG. 8 is a diagram showing the first output current and the second output current during the period T1 shown in FIG. [Figure 9] FIG. 9 is a diagram showing the first output current and the second output current during the period T2 shown in FIG. [Figure 10] FIG. 10 is a circuit diagram of the first current control circuit according to the second embodiment. [Figure 11] FIG. 11 is a circuit diagram of the second current control circuit according to the same embodiment. [Figure 12] FIG. 12 is a diagram showing a voltage dividing circuit according to a third modification.

[0010] [Detailed explanation] (overview) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0011] A transconductance amplifier according to one embodiment generates an output voltage by amplifying the difference between an input voltage and a reference voltage. The transconductance amplifier includes a differential amplifier circuit that receives the input voltage and the reference voltage and includes an input differential pair that operates in response to a tail current and an output circuit that generates an output voltage provided as an active load for the input differential pair, and a current control circuit that controls the tail current. The current control circuit is configured to increase the tail current in response to a current supply condition being satisfied. The current supply condition is when the input voltage falls below a first threshold voltage that is equal to or less than the reference voltage, or when the input voltage exceeds a second threshold voltage that is equal to or greater than the reference voltage.

[0012] With this configuration, when the input voltage is lower than the first threshold voltage or higher than the second threshold voltage, the tail current of the differential amplifier circuit increases, thereby enabling the gm of the transconductance amplifier to be appropriately controlled according to the input voltage.

[0013] In one embodiment, the current control circuit may include a differential circuit to which an input voltage and a reference voltage are input, a current mirror circuit provided as an active load of the differential circuit, and a current supply circuit provided as an active load of the current mirror circuit. The current mirror circuit may supply a current corresponding to a differential current of the differential circuit to the current supply circuit in response to a current supply condition being satisfied. The current supply circuit may contribute an output current corresponding to the current supplied from the current mirror circuit to the tail current.

[0014] In one embodiment, the differential circuit may be configured such that the first threshold voltage is a voltage that is lower than the reference voltage by a first offset voltage, or the second threshold voltage is a voltage that is higher than the reference voltage by a second offset voltage.

[0015] In one embodiment, the differential circuit may include one or more first transistors to which an input voltage is input and one or more second transistors to which a reference voltage is input. The first and second transistors form a differential pair and may be of the same type. The number of first transistors may be different from the number of second transistors.

[0016] In one embodiment, the differential circuit may include a first transistor to which an input voltage is input, and a second transistor forming a differential pair with the first transistor, and a first threshold voltage or a second threshold voltage may be input to the second transistor.

[0017] In one embodiment, when the current mirror circuit is a first current mirror circuit, the current supply circuit may include a second current mirror circuit provided as an active load of the first current mirror circuit and a third current mirror circuit provided as an active load of the second current mirror circuit. The second current mirror circuit may be configured to copy a current corresponding to a differential current of the differential circuit supplied from the first current mirror circuit in response to a current supply condition being satisfied. The third current mirror circuit may be configured to copy the current copied by the second current mirror circuit to generate an output current.

[0018] In one embodiment, the current control circuit may include a first current control circuit and a second current control circuit. The first current control circuit may be configured to increase the tail current in response to the input voltage falling below a first threshold voltage. The second current control circuit may be configured to increase the tail current in response to the input voltage rising above a second threshold voltage.

[0019] In one embodiment, the first current control circuit may include a first differential circuit receiving an input voltage and a reference voltage, a first current mirror circuit provided as an active load of the first differential circuit, and a first current supply circuit provided as an active load of the first current mirror circuit. The second current control circuit may include a second differential circuit receiving an input voltage and a reference voltage, a fourth current mirror circuit provided as an active load of the second differential circuit, and a second current supply circuit provided as an active load of the fourth current mirror circuit. The first current mirror circuit may supply a current corresponding to the differential current of the first differential circuit to the first current supply circuit in response to the input voltage falling below a first threshold voltage. The first current supply circuit may contribute a first output current corresponding to the current supplied from the first current mirror circuit to the tail current. The fourth current mirror circuit may supply a current corresponding to the differential current of the second differential circuit to the second current supply circuit in response to the input voltage exceeding a second threshold voltage. The second current supply circuit may contribute a second output current corresponding to the current supplied from the fourth current mirror circuit to the tail current.

[0020] In one embodiment, the first differential circuit may be configured such that the first threshold voltage is a voltage that is lower than the reference voltage by a first offset voltage, and the second differential circuit may be configured such that the second threshold voltage is a voltage that is higher than the reference voltage by a second offset voltage.

[0021] In one embodiment, the output circuit may be configured as a cascode current mirror circuit.

[0022] In one embodiment, a controller circuit for a DC / DC converter may include the transconductance amplifier. The input voltage may be a feedback voltage of the output voltage of the DC / DC converter.

[0023] In one embodiment, the controller circuit may be monolithically integrated on a single semiconductor chip.

[0024] In one embodiment, a DC / DC converter may include the controller circuit.

[0025] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0026] In this specification, "component A is connected to component B" includes not only a case where component A and component B are directly physically connected, but also a case where component A and component B are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0027] Similarly, "component C is connected (provided) between component A and component B" includes not only a case where component A and component C, or component B and component C, are directly connected, but also a case where they are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0028] In addition, in this specification, symbols attached to electrical signals such as voltage signals and current signals, or circuit elements such as resistors, capacitors, and inductors, represent the respective voltage values, current values, or circuit constants (resistance values, capacitance values, inductances) as necessary.

[0029] In this specification, "mono-integrated" includes cases where all of the circuit components are formed on a semiconductor substrate, and cases where the main components of the circuit are mono-integrated, and some resistors, capacitors, etc. may be provided outside the semiconductor substrate to adjust the circuit constants.

[0030] (First embodiment) FIG. 1 is a block diagram of a DC / DC converter 1 according to a first embodiment. The DC / DC converter 1 receives an input voltage V IN Output voltage V according to OUT1 The DC / DC converter 1 according to this embodiment includes a controller circuit 10 and a peripheral circuit 12.

[0031] The controller circuit 10 is a circuit for controlling the operation of the DC / DC converter 1, and may be integrated onto a single semiconductor chip. The controller circuit 10 according to this embodiment includes a first error amplifier 22, a clamp circuit 30, a second error amplifier 32, a pulse generator 34, a comparator 36, a logic circuit 38, a sense amplifier circuit 40, a buffer circuit 42, resistors R1 to R4, capacitors C1 and C2, a high-side driver DH, a low-side driver DL, a high-side transistor MH, a low-side transistor ML, a feedback pin FB, a bootstrap pin BST, a switching pin SW, and a sensing pin CSNS.

[0032] The feedback pin FB is connected to the output voltage V of DC / DC converter 1. OUT1 is fed back. Output voltage V OUT1 is divided by resistors R1 and R2 to produce the output voltage V OUT1 The feedback voltage V FB is generated, where V FB =V OUT1 ×R2 / (R1+R2). Feedback voltage V FB is input to the non-inverting input terminal of the first error amplifier 22 and the non-inverting input terminal of the comparator 36.

[0033] The first error amplifier 22 is a transconductance amplifier that converts the input voltage into a reference voltage V REF1 The output voltage V is the amplified difference between AMP1 Specifically, the first error amplifier 22 generates a feedback voltage V FB (input voltage) and the reference voltage V input to the inverting input terminal REF1The output voltage V is the amplified difference between AMP1 The detailed configuration of the first error amplifier 22 will be described later.

[0034] The resistor R3 and capacitor C1 for phase compensation are connected in series. The end of the resistor R3 opposite to the capacitor C1 is connected to the output terminal of the first error amplifier 22. The end of the capacitor C1 opposite to the resistor R3 is connected to ground. Here, the first error amplifier 22, the resistor R3, and the capacitor C1 constitute the error amplifier circuit 20. The output voltage V of the first error amplifier 22 AMP1 is generated as the output voltage of the error amplifier circuit 20 after being phase compensated by the resistor R3 and the capacitor C1. The clamp circuit 30 AMP1 Clamp the

[0035] When a load (not shown) of the DC / DC converter 1 fluctuates, the input signal (input voltage V FB ) fluctuations occur. The response speed of the error amplifier circuit 20 to fluctuations in the input signal is limited by the product of gm of the first error amplifier 22 and the capacitance value of the capacitor C1, i.e., gm × C1. The higher this product, the faster the response speed of the error amplifier circuit 20, allowing it to respond quickly to load fluctuations. Therefore, the higher the gm of the first error amplifier 22, the faster the response speed of the error amplifier circuit 20.

[0036] The second error amplifier 32 receives the signal V from the sense amplifier circuit 40 at its non-inverting input terminal. SNS and the output voltage V input to the inverting input terminal AMP1 The amplified voltage V C A resistor R4 and a capacitor C2 for phase compensation are connected in series. One end of the resistor R4 opposite to the capacitor C2 is connected to the output terminal of the second error amplifier 32. One end of the capacitor C2 opposite to the resistor R4 is connected to ground.

[0037] The pulse generator 34 generates a voltage V CA pulse signal S for controlling the duty ratio based on P The pulse generator 34 generates a periodic signal of a sawtooth wave or a ramp wave and a voltage V C The pulse generator 34 may also include a generator of a clock signal for generating a sawtooth wave or a ramp wave.

[0038] The comparator 36 detects the feedback voltage V FB and the reference voltage V REF1 The logic circuit 38 generates a signal S2 according to the result of the comparison with the signal S2. The signal S2 may be used by the logic circuit 38 when the load is light.

[0039] The logic circuit 38 generates a pulse signal S P The high-side driver DH drives the high-side transistor MH based on the high-side control signal SH. The low-side driver DL drives the low-side transistor ML based on the low-side control signal SL. In response to the driving of the high-side transistor MH and the low-side transistor ML, the input voltage V IN Output voltage V according to OUT1 is generated.

[0040] The high-side transistor MH and the low-side transistor ML are each composed of an N-channel MOS (Metal Oxide Semiconductor) transistor. The source of the high-side transistor MH is connected to the switching pin SW, and the drain of the high-side transistor MH is connected to the input voltage V IN The source of the low-side transistor ML is connected to the ground, and the drain of the low-side transistor ML is connected to the switching pin SW.

[0041] The sense amplifier circuit 40 detects the current I flowing through the low-side transistor ML. M and outputs a signal V according to the detection result. SNS Generate.

[0042] The buffer circuit 42 receives the signal S1 as an input, and has an output terminal connected to the high-side driver DH and the bootstrap pin BST.

[0043] The peripheral circuit 12 includes an inductor L and capacitors C3 and C4. One end of the capacitor C3 is connected to the bootstrap pin BST, and the other end of the capacitor C3 is connected to the switching pin SW. One end of the inductor L is connected to the switching pin SW, and the other end of the inductor L is connected to the feedback pin FB. An output voltage V OUT1 is output. A capacitor C4 is provided between the other end of the inductor L1 and the ground.

[0044] 2 is a block diagram of the first error amplifier 22 according to this embodiment. The first error amplifier 22 according to this embodiment includes a current control circuit 200 and a differential amplifier circuit 280.

[0045] The differential amplifier circuit 280 outputs a feedback voltage V FB and the reference voltage V REF1 Output voltage amplified by the difference VAMP1 The differential amplifier circuit 280 generates a tail current I tail This includes the input differential pair that operates according to the tail current I tail By controlling the magnitude of the error, the gm of the first error amplifier 22 is adjusted.

[0046] The current control circuit 200 controls the tail current I tail Specifically, the current control circuit 200 controls the tail current I tail The current supply condition is configured to increase the reference voltage V REF1 A first threshold voltage V th1 The feedback voltage V FB or the reference voltage V REF1 above the second threshold voltage V th2The feedback voltage V FB is to exceed.

[0047] The current control circuit 200 according to this embodiment includes a first current control circuit 220 and a second current control circuit 260. The first current control circuit 220 controls a first threshold voltage V th1 The feedback voltage V FB In response to this, the tail current I of the input differential pair of the differential amplifier circuit 280 tail The second current control circuit 260 is configured to increase the second threshold voltage V th2 The feedback voltage V FB In response to this, the tail current I tail is configured to increase

[0048] 3 is a circuit diagram of the first current control circuit 220 according to this embodiment. The first current control circuit 220 according to this embodiment includes a first differential circuit 222, a current source 224, a first current mirror circuit 226, and a first current supply circuit 240. The voltage V shown in FIG. REG is set by using an LDO (Low Dropout) (not shown) to IN is the voltage generated based on

[0049] The first differential circuit 222 outputs a feedback voltage V FB and the reference voltage V REF1 is input to the first differential circuit 222. The first differential circuit 222 generates differential currents I2 and I3 according to the current I1 supplied from the current source 224. The first differential circuit 222 according to this embodiment generates differential currents I2 and I3 according to the first threshold voltage V th1 is the reference voltage V REF1 than the offset voltage V OFF1 (>0) is configured to be a lower voltage. Therefore, V th1 =V REF1 -V OFF1 The offset voltage V OFF1 The magnitude of the feedback voltage V FB It may be set appropriately depending on the magnitude of fluctuations.

[0050] The first differential circuit 222 includes a transistor M1 and a plurality of transistors M2 each forming a differential pair with the transistor M1. In the first differential circuit 222, the transistor M1 is connected to a feedback voltage V FB The first transistor is connected to the reference voltage V REF1 is the second transistor to which

[0051] The transistor M1 and the multiple transistors M2 are of the same type, specifically, P-channel MOS transistors. The number of transistors M1 is different from the number of transistors M2. Hereinafter, when the number of transistors in one differential pair is different from the number of transistors in the other differential pair, this is also referred to as "different multi-numbers." Specifically, the number of transistors M1 is 1, and the number of transistors M2 is n (n is an integer greater than or equal to 2).

[0052] The gate of transistor M1 is connected to the feedback voltage V FB Therefore, the gate of the transistor M1 is connected to the non-inverting input terminal INP, which receives the feedback voltage V FB The source of the transistor M1 is connected to the current source 224 in common with the sources of the plurality of transistors M2. The gates of the plurality of transistors M2 are connected to the reference voltage V REF1 Therefore, the gates of the plurality of transistors M2 are connected to the inverting input terminal INN, which is supplied with the reference voltage V REF1 is entered.

[0053] The first current mirror circuit 226 is provided as an active load of the first differential circuit 222. The first current mirror circuit 226 according to this embodiment is connected to a first threshold voltage V th1 The feedback voltage V FBIn response to the difference between the differential currents I2 and I3 of the first differential circuit 222 falling below the threshold, a current I5 corresponding to the differential currents I2 and I3 of the first differential circuit 222 is supplied to the first current supply circuit 240. Here, I2 is the sum of the drain currents flowing through the n transistors M2, and I3 is the drain current of the transistor M1. The current I5 is the drain current of the transistor M5.

[0054] The first current mirror circuit 226 includes transistors M3 and M4, each configured as an N-channel MOS transistor. The gate of the transistor M3 is connected in common with the gate of the transistor M4 and to the drain of the transistor M3. The drain of the transistor M3 is connected to the drains of the plurality of transistors M2. The source of the transistor M3 is connected in common with the source of the transistor M4 and to ground. The drain of the transistor M4 is connected to the drain of the transistor M1.

[0055] The first current supply circuit 240 is provided as an active load of the first current mirror circuit 226. The first current supply circuit 240 outputs a first output current I OUT1 , the tail current I tail The first current supply circuit 240 according to the present embodiment includes a second current mirror circuit 242 and a third current mirror circuit 244.

[0056] The second current mirror circuit 242 is provided as an active load of the first current mirror circuit 226. The second current mirror circuit 242 is connected to a first threshold voltage V th1 The feedback voltage V FB When the differential currents I2 and I3 of the first differential circuit 222 fall below the threshold voltage Vcc, the second current mirror circuit 242 copies a current I5 that corresponds to the differential currents I2 and I3 of the first differential circuit 222 and is supplied from the first current mirror circuit 226. The second current mirror circuit 242 includes transistors M5 and M6, each of which is configured as an N-channel MOS transistor.

[0057] The gate of the transistor M5 is connected to the drain of the transistor M5 in common with the gate of the transistor M6. The drain of the transistor M5 is connected to the drain of the transistor M4. The source of the transistor M5 is connected to the ground in common with the source of the transistor M6. A current I6, which is a copy of the current I5 supplied from the first current mirror circuit 226, flows through the transistor M6.

[0058] The third current mirror circuit 244 is provided as an active load of the second current mirror circuit 242. The third current mirror circuit 244 copies the current I6 copied by the second current mirror circuit 242 to generate the first output current I OUT1 The third current mirror circuit 244 includes transistors M7 and M8, each of which is configured as a P-channel MOS transistor.

[0059] The gate of the transistor M7 is connected to the drain of the transistor M7 in common with the gate of the transistor M8. The drain of the transistor M7 is connected to the drain of the transistor M6. The drain of the transistor M8 is connected to the differential amplifier circuit 280. The transistor M8 outputs a first output current I 1 , which is a copy of the current I 6 flowing through the transistor M6. OUT1 This first output current I OUT1 The tail current I of the differential amplifier circuit 280 flows through the current supply line 246 connected to the drain of the transistor M8. tail contribute to.

[0060] The configuration of the first current control circuit 220 according to this embodiment has been described above. The operation of the first current control circuit 220 according to this embodiment will now be described.

[0061] V th1 =V REF1 -V OFF1 ≦V FB Then, I2=I3=I4. Current I4 is the current flowing through transistor M4. Offset voltage V OFF1This is caused by the fact that the number of transistors M2 is larger than the number of transistors M1. At this time, no current is supplied to the second current mirror circuit 242 (I5 = 0).

[0062] A load fluctuation occurs in the DC / DC converter 1, and the feedback voltage V FB decreases and V th1 >V FB When this happens, I2 < I3. At this time, since the current I2 is copied in the first current mirror circuit 226, I2 = I4, and a current of I5 (= I3 - I4) is supplied to the second current mirror circuit 242. This current I5 is copied to generate a current I6, and a first output current I OUT1 is generated by copying the current I6. This first output current I OUT1 contributes to the tail current I tail of the differential amplifier circuit 280.

[0063] V th1 >V FB When, as V FB becomes smaller, I OUT1 becomes larger, but the first output current I OUT1 is generated based on the current I1 supplied from the current source 224. Therefore, the upper limit of I OUT1 is I max1 corresponding to I1.

[0064] FIG. 4 is a circuit diagram of a second current control circuit 260 according to the present embodiment. The second current control circuit 260 includes a second differential circuit 262, a current source 264, a fourth current mirror circuit 266, and a second current supply circuit 270. The current source 264, the fourth current mirror circuit 266, and the second current supply circuit 270 may each have substantially the same configuration as the current source 224, the first current mirror circuit 226, and the first current supply circuit 240 that the first current control circuit 220 has.

[0065] The second differential circuit 262 receives the feedback voltage V FB and the reference voltage V REF1 . The second differential circuit 262 has a second threshold voltage V th2 as the reference voltage VREF1 than the second offset voltage V OFF2 (>0) is configured to be a higher voltage. Therefore, V th2 =V REF1 +V OFF2 The second offset voltage V OFF2 The magnitude of the feedback voltage V FB It may be set appropriately depending on the magnitude of fluctuations.

[0066] The second differential circuit 262 differs from the first differential circuit 222 of the first current control circuit 220 in that the non-inverting input terminal INP and the inverting input terminal INN are reversed. The second current control circuit 260 may have substantially the same configuration as the first current control circuit 220, except for the non-inverting input terminal INP and the inverting input terminal INN. Therefore, the second offset voltage V OFF2 is the first offset voltage V OFF1 may be the same as (V OFF2 =V OFF1 In the second differential circuit 262, the transistor M2 is connected to the feedback voltage V FB The first transistor M1 is connected to the reference voltage V REF1 is the second transistor to which

[0067] The fourth current mirror circuit 266 is provided as an active load of the second differential circuit 262. The fourth current mirror circuit 266 is connected to a second threshold voltage V th2 The feedback voltage V FB In response to this, the differential current I 12 ,I 13 Current I according to 15 to the second current supply circuit 270.

[0068] The second current supply circuit 270 is provided as an active load of the fourth current mirror circuit 266. The second current supply circuit 270 receives the current I 15 The second output current I OUT2The tail current I tail is configured to contribute to

[0069] The second current supply circuit 270 includes a fifth current mirror circuit 272 provided as an active load of the fourth current mirror circuit 266, and a sixth current mirror circuit 274 provided as an active load of the fifth current mirror circuit 272. The fifth current mirror circuit 272 is connected to a feedback voltage V FB is the second threshold voltage V th2 In response to the fact that the differential current I 12 ,I 13 Current I according to 15 The sixth current mirror circuit 274 is provided to copy the current I copied by the fifth current mirror circuit 272. 16 Copy the second output current I OUT2 is provided to generate

[0070] The operation of the second current control circuit 260 will now be described. th2 =V REF1 +V OFF2 ≧V FB When I 12 =I 13 =I 14 Current I 12 is the sum of the drain currents of n transistors M2, and the current I 13 is the drain current of transistor M1, and the current I 14 is the current flowing through the transistor M4. At this time, no current is supplied to the second current supply circuit 270 (I 15 =0).

[0071] When a load fluctuation occurs, the feedback voltage V FB rises and V th2 <V FB So, I 12 13 At this time, the current I 12 is copied because I 12 =I​14 The current I 14 is the current flowing through the transistor M4. The second current supply circuit 270 includes 15 (=I 13 -I 14 ) current is supplied. This current I 15 is copied and the current I 16 is generated, and the current I 16 The second output current I OUT2 This second output current I OUT2 The tail current I of the differential amplifier circuit 280 flows through the current supply line 276 connected to the drain of the transistor M8. tail contribute to.

[0072] V th2 <V FB When V FB The larger I OUT2 becomes larger, but the second output current I OUT2 is supplied by current source 264. 11 Therefore, I OUT2 The upper limit of I is determined by I1. max2 In this embodiment, I max2 =I max1 Let's say.

[0073] 5 is a circuit diagram of a differential amplifier circuit 280 according to this embodiment. The differential amplifier circuit 280 includes an input differential pair 282, an output circuit 284, and current sources 286, 288, and 290.

[0074] The input differential pair 282 is connected to the feedback voltage V FB and the reference voltage V REF is input, and the tail current I tailThe input differential pair 282 operates in accordance with the input signal. The input differential pair 282 includes transistors M11 and M12, each configured as a P-channel MOS transistor. The gate of the transistor M11 is connected to the non-inverting input terminal INP, and the gate of the transistor M12 is connected to the inverting input terminal INN. The source of the transistor M11, together with the source of the transistor M12, is connected to the current source 286 and the current control circuit 200 (specifically, the current supply lines 246 and 276).

[0075] The output circuit 284 is provided as an active load for the input differential pair 282, and the differential current I 22 ,I 23 Output voltage V according to AMP1 The output circuit 284 according to this embodiment is configured as a cascode current mirror circuit. The output circuit 284 includes transistors M13 to M16, each configured as an N-channel MOS transistor.

[0076] The gate of the transistor M13 is connected to the drain of the transistor M15 in common with the gates of the transistors M14 to M16. The source of the transistor M13 is connected to the source of the transistor M14 in common with the ground. The drain of the transistor M13 is connected to the source of the transistor M15 in common with the drain of the transistor M11. The drain of the transistor M14 is connected to the source of the transistor M16 in common with the drain of the transistor M12. The drain of the transistor M15 is connected to the current source 288. The drain of the transistor M16 is connected to the current source 290 and the output terminal OUT. The output voltage V AMP1 is output from the output terminal OUT.

[0077] gm is the tail current I supplied to the input differential pair 282 tail Specifically, the tail current I tail As shown above, the feedback voltage V FB is the first threshold voltage V th1 When the first output current I OUT1 is the tail current Itail Also, the feedback voltage V FB is the second threshold voltage V th2 When the second output current I OUT2 is the tail current I tail This contributes to the feedback voltage V FB V th1 ≦V FB ≦V th2 If it is outside the range of tail is the current I supplied from the current source 286. 21 This increases gm, allowing the error amplifier circuit 20 to respond quickly to load fluctuations.

[0078] FIG. 6 shows the first output current I supplied by the first current control circuit 220. OUT1 and the second output current I supplied by the second current control circuit 260 OUT2 The feedback voltage V FB 6, the horizontal axis represents the change in the feedback voltage V FB Shows.

[0079] As shown in Figure 6, the first output current I OUT1 is V th1 ≦V FB When , it is 0. The first output current I OUT1 is V th1 >V FB When the feedback voltage V FB Here, the first threshold voltage V th1 A third threshold V th3 When the first output current I OUT1 is V th3 >V FB When I max1 becomes a constant value.

[0080] Second output current I OUT2 is V th2 ≧V FB When , it is 0. Second output current I OUT2 is V th2 <V FB When the feedback voltage VFB Here, the second threshold voltage V th2 A fourth threshold V th4 When the second output current I OUT2 is V th4 <V FB When I max2 becomes a constant value.

[0081] FIG. 7 shows the output voltage V OUT1 and the output voltage V of the error amplifier circuit according to the first comparison technique. OUT8 and V of the error amplifier circuit according to the second comparison technique. OUT9 7 is a timing chart showing the current I L is the output current flowing through the inductor L of the DC / DC converter 1.

[0082] The error amplifier circuit according to the first comparative technique is a circuit in which the first error amplifier 22 according to this embodiment is replaced with the error amplifier according to the first comparative technique. The error amplifier circuit according to the second comparative technique is a circuit in which the first error amplifier 22 according to this embodiment is replaced with the error amplifier according to the second comparative technique. The error amplifier according to the first comparative technique differs from the first error amplifier 22 according to this embodiment in that it does not include the current control circuit 200. The error amplifier according to the second comparative technique is an error amplifier in which gm is larger than that of the error amplifier according to the first comparative technique.

[0083] At timing t1 and timing t2, a load fluctuation occurs, and the current I L changes. In response to this, the output voltage V OUT1 ,V OUT8 ,V OUT9 fluctuates, but the output voltage V OUT1 is the output voltage V OUT8 This is because the gm of the first error amplifier 22 is controlled by the current control circuit 200.

[0084] The output voltage V of the error amplifier circuit according to comparative technique 2 OUT9 In this case, since gm is larger than that of comparative technology 1, fluctuations in the output voltage V OUT8 However, by increasing gm, the output voltage V OUT9 In contrast, in the error amplifier circuit 20 according to this embodiment, gm is suppressed during steady state, so the output voltage V OUT9 Compared to the steady-state output voltage V OUT1 Therefore, according to the error amplifier circuit 20 of this embodiment, the output voltage V OUT1 While stabilizing the output voltage V OUT1 This can suppress fluctuations.

[0085] Furthermore, the inventors investigated the frequency characteristics of the DC / DC converter 1 according to this embodiment and the frequency characteristics of a DC / DC converter using the error amplifier circuit according to comparative technique 1, and confirmed that there is no difference in the frequency characteristics between the two DC / DC converters. This result indicates that the current control circuit 200 according to this embodiment does not affect the frequency characteristics of the error amplifier circuit 20. Therefore, the current control circuit 200 according to this embodiment OUT1 This makes it possible to improve the response speed to load fluctuations while maintaining stability.

[0086] FIG. 8 shows the first output current I OUT1 and the second output current I OUT2 At the top of FIG. 8, the output voltage V OUT1 The feedback voltage V FB As shown in Figure 8, V FB <V th1 In the period T3, I OUT1 >0. This increases the gm of the differential amplifier circuit 280 during the period T3, improving the response speed of the error amplifier circuit 20. As a result, the feedback voltage V FB(i.e., the output voltage V of DC / DC converter 1) OUT1 The decrease in the

[0087] Also, V FB >V th2 In the period T4, I OUT2 >0. As a result, the gm of the differential amplifier circuit 280 increases during the period T4, and the response speed of the error amplifier circuit 20 improves. As a result, the feedback voltage V FB (i.e., the output voltage V of DC / DC converter 1) OUT1 In this way, the rise of the feedback voltage V FB (i.e., the output voltage V of DC / DC converter 1) OUT1 fluctuations) are suppressed.

[0088] FIG. 9 shows the first output current I OUT1 and the second output current I OUT2 As shown in FIG. FB >V th2 In the period T5, OUT2 >0, and V FB <V th1 In the period T6, OUT1 >0. As a result, in the period T2, similar to the period T1, the feedback voltage V FB (i.e., the output voltage V of DC / DC converter 1) OUT1 fluctuations) are suppressed.

[0089] The DC / DC converter 1 according to this embodiment has been described above, and in particular the details of the first error amplifier 22. The first error amplifier 22 according to this embodiment detects the tail current I tail a differential amplifier circuit 280 including an input differential pair 282 that operates in response to a tail current I tail The current control circuit 200 controls the tail current I in response to the current supply condition being satisfied. tailThe current supply condition is configured to increase the reference voltage V REF1 A first threshold voltage V th1 The feedback voltage V FB or the reference voltage V REF1 above the second threshold voltage V th2 The feedback voltage V FB is to exceed.

[0090] With this configuration, the feedback voltage V FB is the first threshold voltage V th1 If the voltage drops below the second threshold voltage V th2 When the tail current I tail This increases the feedback voltage V FB The gm of the first error amplifier 22 can be appropriately controlled in accordance with the above.

[0091] Furthermore, the first current control circuit 220 according to this embodiment controls the first threshold voltage V th1 is the reference voltage V REF1 than the first offset voltage V OFF1 The second current control circuit 260 according to this embodiment is configured to have a voltage that is lower by the second threshold voltage V th2 is the reference voltage V REF1 than the second offset voltage V OFF2 The voltage is configured to be higher by that amount.

[0092] This prevents the gm of the first error amplifier 22 from increasing during steady state, and mainly reduces fluctuations in the load (specifically, the feedback voltage V FB When a fluctuation occurs in the output voltage V of the error amplifier circuit 20 during normal operation, the gm of the first error amplifier 22 can be increased. OUT1 When a load fluctuation occurs, gm is increased to stabilize the output voltage V OUT1 This can suppress fluctuations.

[0093] (Second embodiment) In the second embodiment, the configuration of the current control circuit (more specifically, the first current control circuit and the second current control circuit) of the first error amplifier is mainly different from that of the current control circuit 200 of the first embodiment. The first error amplifier of the second embodiment may have a configuration in which the current control circuit 200 in the first error amplifier 22 of the first embodiment is replaced with the current control circuit of the second embodiment. Furthermore, the DC / DC converter of the second embodiment may have substantially the same configuration as the DC / DC converter 1 of the first embodiment, except for the first error amplifier.

[0094] 10 is a circuit diagram of a first current control circuit 320 according to the second embodiment. The first current control circuit 320 according to the second embodiment controls a first threshold voltage V th5 The feedback voltage V FB In response to this, the tail current I tail The first output current I OUT3 is configured to generate

[0095] The first current control circuit 320 according to the second embodiment includes a first differential circuit 322, a current source 324, a first current mirror circuit 326, and a first current supply circuit 340. The current source 324, the first current mirror circuit 326, and the first current supply circuit 340 according to the second embodiment may have substantially the same configurations as the current source 224, the first current mirror circuit 226, and the first current supply circuit 240 of the first current control circuit 220 according to the first embodiment, respectively.

[0096] The first differential circuit 322 receives the current I supplied from the current source 224. 31 The differential current I according to 32 ,I 33 The first differential circuit 322 according to the second embodiment includes transistors M21 and M22 and a resistor R 11 ,R 12 In the first differential circuit 322, the transistor M21 outputs a feedback voltage V FB The transistor M22 is a first transistor to which a first threshold voltage V th5is the second transistor to which

[0097] The transistors M21 and M22 are each formed of a P-channel MOS transistor. The gate of the transistor M21 is connected to the non-inverting input terminal INP. The source of the transistor M21 and the source of the transistor M22 are connected in common to the current source 324. The drain of the transistor M21 is connected to the drain of the transistor M4. The drain of the transistor M22 is connected to the drain of the transistor M3.

[0098] Resistance R 11 ,R 12 are connected in series. The inverting input terminal INN is connected to the resistor R 11 The gate of the transistor M22 is connected to one end of the resistor R 11 and resistance R 12 The gate of transistor M22 is connected between the reference voltage V REF1 The divided voltage V A1 is input, where V A1 =V REF1 ×R 12 / (R 11 +R 12 ) Therefore, the first offset voltage V OFF3 is V OFF3 =V REF1 -V A1 =V REF1 ×R 11 / (R 11 +R 12 ) The first threshold voltage V th5 is V th5 =V REF1 -V OFF3 =V A1 is.

[0099] V th5 ≦V FB When I 32 =I 33 =I 34 Here, the current I 33 is the drain current of transistor M21, and the current I 32is the drain current of transistor M22, and the current I 34 is the current flowing through the transistor M4. At this time, no current is supplied to the first current supply circuit 340 (I 35 =0). current I 35 is the drain current of transistor M5.

[0100] Load fluctuations occur, and V FB V th5 >V FB So, I 32 33 At this time, the current I 32 is copied because I 32 =I 34 and the first current supply circuit 340 is I 35 (=I 33 -I 34 ) is supplied. Current I 34 is the current flowing through transistor M4. Current I 35 The first output current I according to OUT3 is the tail current I of the differential amplifier circuit 280. tail contribute to.

[0101] 11 is a circuit diagram of a second current control circuit 360 according to the second embodiment. The second current control circuit 360 according to the second embodiment controls a feedback voltage V FB is the second threshold voltage V th6 In response to exceeding the threshold, the tail current I tail The second output current I OUT4 is configured to generate

[0102] The second current control circuit 360 according to the second embodiment includes a second differential circuit 362, a current source 364, a fourth current mirror circuit 366, and a second current supply circuit 380. The current source 364, the fourth current mirror circuit 366, and the second current supply circuit 380 according to the second embodiment may have substantially the same configurations as the current source 224, the first current mirror circuit 226, and the first current supply circuit 240 of the first current control circuit 220 according to the first embodiment, respectively. ​

[0103] The second differential circuit 362 receives a current I supplied from a current source 364. 41 The differential current I according to 42 ,I 43 The second differential circuit 362 according to the second embodiment includes transistors M21 and M22 and a resistor R 21 ~R 23 In the second differential circuit 362, the transistor M22 outputs a feedback voltage V FB The transistor M21 is a first transistor to which a second threshold voltage V th6 is the second transistor to which

[0104] The source of the transistor M21 is connected to the current source 364 in common with the source of the transistor M22. The gate of the transistor M22 is connected to the non-inverting input terminal INP. 21 ~R 23 are connected in series. The inverting input terminal INN is connected to the resistor R 22 and resistance R 23 The gate of the transistor M21 is connected between the resistor R 21 and resistance R 22 The gate of transistor M21 is connected to the reference voltage V REF1 and the reference voltage V REF2 (>V REF1 ) and the voltage V A2 is input, where V A2 =(V REF2 -V REF1 )×R 22 / (R 21 +R 22 ) Therefore, the second offset voltage V OFF4 is V OFF4 =V A2 -V REF1 The second threshold voltage V th6 is V th6 =V REF1 +V OFF4 =V A2 is.

[0105] V th6 ≧VFB When I 42 =I 43 =I 44 Here, the current I 43 is the drain current of transistor M21, and the current I 42 is the drain current of transistor M22, and the current I 44 is the current flowing through the transistor M4. At this time, no current is supplied to the second current supply circuit 380 (I 45 =0). current I 45 is the drain current of transistor M5.

[0106] Load fluctuations occur, and V FB rises and V th6 <V FB So, I 42 43 At this time, the current I 42 is copied because I 42 =I 44 and the second current supply circuit 380 is I 45 (=I 43 -I 44 ) current is supplied. This current I 45 The second output current I OUT4 is the tail current I of the differential amplifier circuit 280. tail contribute to.

[0107] Even when the first current control circuit 320 and the second current control circuit 360 are configured as described above, the feedback voltage V FB is the first threshold voltage V th5 If the voltage drops below the second threshold voltage V th6 When the tail current I tail This increases the feedback voltage V FB In accordance with this, the gm of the first error amplifier according to the second embodiment can be appropriately controlled.

[0108] (First Modification) ​In the above embodiment, an example of generating an offset voltage is described by varying the number of multiples of the differential pair in the differential circuit of the current control circuit (First Embodiment), or by dividing the reference voltage using a resistor in the differential circuit of the current control circuit (Second Embodiment). The method of generating the offset voltage is not limited to this. For example, with the same number of multiples, a differential circuit may be configured with two transistors of different sizes as a differential pair. It is also possible to generate an offset voltage by varying the sizes of these two transistors in this way.

[0109] (Second Variation Example) In the first embodiment, an example of varying the number of multiples by setting the number of transistors M1 to 1 and the number of transistors M2 to n in the first differential circuit 222 and the second differential circuit 262 has been described. However, the number of transistors M1 is not limited to this and may be set to m (m: an integer of 2 or more). In this case, for example, by setting m < n, it becomes possible to generate an appropriate offset voltage.

[0110] (Third Variation Example) In the second embodiment, an example of generating the first threshold voltage V th1 and the second threshold voltage V th2 using two voltage dividing circuits in the first differential circuit 322 of the first current control circuit 320 and the second differential circuit 362 of the second current control circuit 360 has been described. However, it is not limited to this, and it is also possible to generate the voltage that becomes these two threshold voltages using one voltage dividing circuit. 〔

[0111] FIG. 12 is a diagram showing a voltage dividing circuit 400 according to the third variation example. The voltage dividing circuit 400 according to the third variation example includes resistors R 31 ~R 34 connected in series. Between resistor R 33 and resistor R 34 , a voltage V REF1 obtained by dividing the reference voltage V A3 is generated. V A3 = V REF1 × R 34 / (R 33 + R 34 ). Also, between resistor R31 and resistance R 32 Between REF1 and the reference voltage V REF2 The voltage V obtained by dividing the difference A4 is generated, where V A4 =(V REF2 -V REF1 )×R 32 / (R 31 +R 32 ) Resistance R 31 ~R 34 By adjusting the resistance value of A3 is used as the first threshold voltage, and the voltage V A4 can be used as the second threshold voltage.

[0112] (Application example) In the above embodiment, the first error amplifier 22 or the error amplifier circuit 20 including the first error amplifier 22 is used in a DC / DC converter that is a switching regulator. However, the first error amplifier 22 or the error amplifier circuit 20 may be used in various DC / DC converters, for example, in a linear regulator such as an LDO.

[0113] (supplement) Although the embodiments of the present disclosure have been described using specific terms, this description is merely an example to facilitate understanding and does not limit the scope of the present disclosure or the claims, and the scope of the present invention is defined by the claims. Furthermore, not only the embodiments but also embodiments, examples, and modifications not described herein are included in the scope of the present invention. One or more elements of the first embodiment can be combined with one or more elements of the second embodiment.

[0114] (Addendum) One aspect of the technology disclosed in this specification can be understood as follows.

[0115] (Item 1) A transconductance amplifier that generates an output voltage by amplifying a difference between an input voltage and a reference voltage, a differential amplifier circuit including an input differential pair to which the input voltage and the reference voltage are input and which operates in response to a tail current, and an output circuit which generates the output voltage and is provided as an active load of the input differential pair; and a current control circuit which controls the tail current; the current control circuit is configured to increase the tail current in response to a current supply condition being satisfied; the current supply condition is that the input voltage is lower than a first threshold voltage that is equal to or lower than the reference voltage, or that the input voltage is higher than a second threshold voltage that is equal to or higher than the reference voltage; Transconductance amplifier.

[0116] (Item 2) the current control circuit includes a differential circuit to which the input voltage and the reference voltage are input, a current mirror circuit provided as an active load of the differential circuit, and a current supply circuit provided as an active load of the current mirror circuit; the current mirror circuit supplies a current corresponding to the differential current of the differential circuit to the current supply circuit in response to the current supply condition being satisfied; the current supply circuit contributes an output current corresponding to the current supplied from the current mirror circuit to the tail current; Item 1. The transconductance amplifier according to item 1.

[0117] (Item 3) the differential circuit is configured so that the first threshold voltage is a voltage lower than the reference voltage by a first offset voltage, or so that the second threshold voltage is a voltage higher than the reference voltage by a second offset voltage. Item 2. The transconductance amplifier according to item 2.

[0118] (Item 4) the differential circuit includes one or more first transistors to which the input voltage is input and one or more second transistors to which the reference voltage is input; the first transistor and the second transistor form a differential pair and are of the same type; the number of the first transistors is different from the number of the second transistors; Item 3. The transconductance amplifier according to item 3.

[0119] (Item 5) the differential circuit includes a first transistor to which the input voltage is input, and a second transistor forming a differential pair with the first transistor; the first threshold voltage or the second threshold voltage is input to the second transistor; Item 3. The transconductance amplifier according to item 3.

[0120] (Item 6) the current supply circuit includes, when the current mirror circuit is a first current mirror circuit, a second current mirror circuit provided as an active load of the first current mirror circuit, and a third current mirror circuit provided as an active load of the second current mirror circuit; the second current mirror circuit is provided to copy a current corresponding to the differential current of the differential circuit, which is supplied from the first current mirror circuit, in response to the current supply condition being satisfied; the third current mirror circuit is configured to copy the current copied by the second current mirror circuit to generate the output current; 6. The transconductance amplifier according to any one of items 2 to 5.

[0121] (Item 7) the current control circuit includes a first current control circuit and a second current control circuit; the first current control circuit is configured to increase the tail current in response to the input voltage falling below the first threshold voltage; the second current control circuit is configured to increase the tail current in response to the input voltage exceeding the second threshold voltage. Item 1. The transconductance amplifier according to item 1.

[0122] (Item 8) the first current control circuit includes a first differential circuit to which the input voltage and the reference voltage are input, a first current mirror circuit provided as an active load of the first differential circuit, and a first current supply circuit provided as an active load of the first current mirror circuit; the second current control circuit includes: a second differential circuit to which the input voltage and the reference voltage are input; a fourth current mirror circuit provided as an active load of the second differential circuit; and a second current supply circuit provided as an active load of the fourth current mirror circuit; the first current mirror circuit supplies a current corresponding to a differential current of the first differential circuit to the first current supply circuit in response to the input voltage falling below the first threshold voltage; the first current supply circuit contributes a first output current corresponding to the current supplied from the first current mirror circuit to the tail current; the fourth current mirror circuit supplies a current corresponding to a differential current of the second differential circuit to the second current supply circuit in response to the input voltage exceeding the second threshold voltage; the second current supply circuit contributes a second output current corresponding to the current supplied from the fourth current mirror circuit to the tail current; Item 7. The transconductance amplifier according to item 7.

[0123] (Item 9) the first differential circuit is configured so that the first threshold voltage is a voltage that is lower than the reference voltage by an amount corresponding to a first offset voltage; the second differential circuit is configured so that the second threshold voltage is a voltage higher than the reference voltage by a second offset voltage. Item 9. The transconductance amplifier according to item 8.

[0124] (Item 10) The output circuit is composed of a cascode current mirror circuit. 10. The transconductance amplifier according to any one of items 1 to 9.

[0125] (Item 11) 1. A controller circuit for a DC / DC converter, comprising: A transconductance amplifier according to any one of items 1 to 10, The input voltage is a feedback voltage of the output voltage of the DC / DC converter. Controller circuit.

[0126] (Item 12) Integrated on a single semiconductor chip Item 12. The controller circuit of item 11.

[0127] (Item 13) Item 13. A controller circuit according to item 11 or 12. DC / DC converter. [Explanation of symbols]

[0128] 1 DC / DC converter, 10 controller circuit, 12 peripheral circuit, 20 error amplifier circuit, 22 first error amplifier (transconductance amplifier), 32 second error amplifier, 34 pulse generator, 36 comparator, 38 logic circuit, 40 sense amplifier circuit, 42 buffer circuit, 200 current control circuit, 220, 320 first current control circuit, 222, 322 first differential circuit, 224, 264, 286, 288, 290, 324 current source, 226, 326 first current mirror circuit, 240, 340 first current supply circuit, 242 second current mirror circuit, 244 third current mirror circuit, 246, 276 current supply line, 260, 360 second current control circuit, 262, 362 second differential circuit, 266, 366 fourth current mirror circuit, 270, 380 Second current supply circuit, 280 differential amplifier circuit, 282 input differential pair, 284 output circuit, L inductor, C1 to C4 capacitors, R1 to R4, R 11 ~R 13Resistor, DH high-side driver, DL low-side driver, MH high-side transistor, ML low-side transistor, M1 to M8, M11 to M14, M21, M22 transistors, INP non-inverting input terminal, INN inverting input terminal, OUT output terminal.

Claims

1. A transconductance amplifier that generates an output voltage by amplifying a difference between an input voltage and a reference voltage, a differential amplifier circuit including an input differential pair to which the input voltage and the reference voltage are input and which operates in response to a tail current, and an output circuit which generates the output voltage and is provided as an active load of the input differential pair; and a current control circuit which controls the tail current; the current control circuit is configured to increase the tail current in response to a current supply condition being satisfied; the current supply condition is that the input voltage is lower than a first threshold voltage that is equal to or lower than the reference voltage, or that the input voltage is higher than a second threshold voltage that is equal to or higher than the reference voltage; Transconductance amplifier.

2. the current control circuit includes a differential circuit to which the input voltage and the reference voltage are input, a current mirror circuit provided as an active load of the differential circuit, and a current supply circuit provided as an active load of the current mirror circuit; the current mirror circuit supplies a current corresponding to the differential current of the differential circuit to the current supply circuit in response to the current supply condition being satisfied; the current supply circuit contributes an output current corresponding to the current supplied from the current mirror circuit to the tail current; 2. The transconductance amplifier of claim 1.

3. the differential circuit is configured so that the first threshold voltage is a voltage lower than the reference voltage by a first offset voltage, or so that the second threshold voltage is a voltage higher than the reference voltage by a second offset voltage.

3. The transconductance amplifier of claim 2.

4. the differential circuit includes one or more first transistors to which the input voltage is input and one or more second transistors to which the reference voltage is input; the first transistor and the second transistor form a differential pair and are of the same type; the number of the first transistors is different from the number of the second transistors; 4. The transconductance amplifier of claim 3.

5. the differential circuit includes a first transistor to which the input voltage is input, and a second transistor forming a differential pair with the first transistor; the first threshold voltage or the second threshold voltage is input to the second transistor; 4. The transconductance amplifier of claim 3.

6. the current supply circuit includes, when the current mirror circuit is a first current mirror circuit, a second current mirror circuit provided as an active load of the first current mirror circuit, and a third current mirror circuit provided as an active load of the second current mirror circuit; the second current mirror circuit is provided to copy a current corresponding to the differential current of the differential circuit, which is supplied from the first current mirror circuit, in response to the current supply condition being satisfied; the third current mirror circuit is configured to copy the current copied by the second current mirror circuit to generate the output current; 3. The transconductance amplifier of claim 2.

7. the current control circuit includes a first current control circuit and a second current control circuit; the first current control circuit is configured to increase the tail current in response to the input voltage falling below the first threshold voltage; the second current control circuit is configured to increase the tail current in response to the input voltage exceeding the second threshold voltage.

2. The transconductance amplifier of claim 1.

8. the first current control circuit includes a first differential circuit to which the input voltage and the reference voltage are input, a first current mirror circuit provided as an active load of the first differential circuit, and a first current supply circuit provided as an active load of the first current mirror circuit; the second current control circuit includes a second differential circuit to which the input voltage and the reference voltage are input, a fourth current mirror circuit provided as an active load of the second differential circuit, and a second current supply circuit provided as an active load of the fourth current mirror circuit; the first current mirror circuit supplies a current corresponding to a differential current of the first differential circuit to the first current supply circuit in response to the input voltage falling below the first threshold voltage; the first current supply circuit contributes a first output current corresponding to the current supplied from the first current mirror circuit to the tail current; the fourth current mirror circuit supplies a current corresponding to a differential current of the second differential circuit to the second current supply circuit in response to the input voltage exceeding the second threshold voltage; the second current supply circuit contributes a second output current corresponding to the current supplied from the fourth current mirror circuit to the tail current; 8. The transconductance amplifier of claim 7.

9. the first differential circuit is configured so that the first threshold voltage is a voltage that is lower than the reference voltage by an amount corresponding to a first offset voltage; the second differential circuit is configured so that the second threshold voltage is a voltage higher than the reference voltage by an amount corresponding to a second offset voltage; 9. The transconductance amplifier of claim 8.

10. The output circuit is composed of a cascode current mirror circuit.

2. The transconductance amplifier of claim 1.

11. 1. A controller circuit for a DC / DC converter, comprising: A transconductance amplifier according to any one of claims 1 to 10, The input voltage is a feedback voltage of the output voltage of the DC / DC converter. Controller circuit.

12. Integrated on a single semiconductor chip 12. The controller circuit of claim 11.

13. 12. A controller circuit according to claim 11, DC / DC converter.

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