Amplifying circuit, and multi-stage amplifier

Abstract

To suppress a decrease in operation speed after saturation relative to that before saturation in an amplifying circuit.SOLUTION: An amplifying circuit 100 includes: a differential pair 1 comprising a first FET 11 and a second FET 12; a first load 31 connected to the first FET 11; a second load 32 connected to the second FET 12; a differential pair 2 comprising a third FET 23 and a fourth FET 24; a third load 33 connected to the third FET 23; a fourth load 34 connected to the fourth FET 24; a first switching element 41 connected in parallel to a first load 31; and a second switching element 42 connected in parallel to a second load 32. Gates of the first FET 11 and the third FET 23 are connected to each other, and gates of the second FET 12 and the fourth FET 24 are connected to each other. The first switching element 41 transits into a conduction state as a drain-source voltage of the first FET 11 increases, and the second switching element 42 transits into a conduction state as a drain-source voltage of the second FET 12 increases.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an amplifier circuit and a multistage amplifier. [Background technology]

[0002] Amplifier circuits that increase the amplitude of AC input signals or the voltage of DC input signals based on power supplied from a power source are used in a variety of application circuits and are built into a variety of electronic devices. As an example, amplifier circuits are preferably used as preamplifiers in the front stage of comparators. A preamplifier for a comparator is required to quickly amplify the small differential voltage determined by the comparator with high gain and output it to the comparator. To achieve such high-speed, high-gain amplification, circuit topologies have been proposed in the past, in which differential pairs with relatively simple load circuit topologies, such as resistive loads and diode loads, are cascaded to operate in an open loop (see, for example, Non-Patent Documents 1 to 3). Such circuit topologies have a simple circuit topology for the differential pairs, which reduces the parasitic capacitance of nodes involved in signal transmission, such as input and output. Furthermore, such circuit topologies are capable of high-speed operation and can achieve high gain by increasing the number of cascaded stages, thereby achieving the high-speed and high-gain performance required of preamplifiers installed in the front stage of a comparator. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Marcel. JM Pelgrom, “Analog-to-Digital Conversion (4th Ed.)”, p.602 [Non-patent document 2] Geraid, Miller et al., “An 18b 10us Self-calibrating ADC”, ISSCC, 1990 [Non-patent document 3] “A Design Techniques for High-speed, High-Resolution Comparators”, JSSC, 1992 Summary of the Invention [Problem to be solved by the invention]

[0004] Not only amplifiers with the above circuit topology, but also amplifiers with a differential pair in the input stage can experience saturation of the output voltage up to the power supply voltage depending on the input differential voltage level. This is because the output voltage range of the differential pair is limited by the power supply voltage. In particular, the later differential pair of a cascaded differential pair is more likely to experience output voltage saturation because the input differential voltage level tends to be higher. In relation to such output voltage saturation, a problem that occurs in an amplifier circuit that includes a differential pair with a diode load in the input stage will be described with reference to FIGS. 8 and 9.

[0005] Fig. 8 shows a conventional differential pair 900 having a diode load formed by a P-channel MOSFET 900a, and Fig. 9 schematically shows changes in the non-inverting input voltage Vip and inverting input voltage Vim of the differential pair 900 of Fig. 8, as well as the non-inverting output voltage Vop and inverting output voltage Vom relative to these two input voltages. In the conventional differential pair 900 shown in Fig. 8, when a voltage that causes the positive and negative output voltages Vop and Vom to saturate is input, the MOSFET 900a that forms the diode load on the output voltage side (the non-inverting output voltage Vop side in Fig. 9) that saturates on the high power supply potential VDD side will operate close to operating in the cutoff region.

[0006] That is, as the drain voltage on the inverting output voltage Vop side increases due to the input of a large non-inverting input voltage Vip, the gate voltage of the MOSFET 900a on the inverting output voltage Vop side, which is diode-connected to the drain, also increases. The increase in gate voltage reduces the gate-source voltage, which increases the drain-source resistance and causes the MOSFET 900a to stop passing current. As a result, as shown in FIG. 9, the output voltage Vop rises to a certain level, and then the rate of rise slows down and it gradually rises to the saturation voltage Vsat. In other words, the change in the output voltage slows down, and its ability to follow changes in the input voltage decreases.

[0007] Furthermore, when the input voltage returns from a saturated state to a level at which the output voltage is not saturated, no current is supplied from the cut-off MOSFET 900a. Therefore, as shown in FIG. 9, the non-inverted output voltage Vop changes slowly from the saturation voltage Vsat, resulting in poor response to the input voltage. In other words, even if the amplifier circuit includes a differential pair with a diode load in the input stage, which is inherently capable of high-speed operation, when the output voltage becomes saturated, the operating speed drops before and after the saturation state.

[0008] Furthermore, as shown in FIG. 9, the saturation voltage Vsat is lower than the high power supply potential VDD by one threshold voltage (Vth) of the MOSFET 900a, reducing the maximum voltage that can be output. In other words, the output voltage range is limited, making it impossible to output a rail-to-rail voltage. Thus, an amplifier circuit including a differential pair with a diode load in its input stage may not be able to output a voltage approximately equal to the power supply voltage.

[0009] In view of the above-mentioned problems, an object of the present invention is to suppress at least the decrease in operating speed before and after saturation of the output voltage in an amplifier circuit including a differential pair with a diode load. [Means for solving the problem]

[0010] An amplifier circuit according to an embodiment of the present invention comprises a first input differential pair configured to be able to differentially amplify a signal by first and second MOSFETs, both of a first conductivity type, a first load configured by diode-connected MOSFETs and connected to the first MOSFET, and a second load configured by diode-connected MOSFETs and connected to the second MOSFET. The amplifier circuit further comprises a second input differential pair configured to be able to differentially amplify a signal by third and fourth MOSFETs, both of the first conductivity type, a third load connected to the drain of the third MOSFET, a fourth load connected to the drain of the fourth MOSFET, a first switching element connected in parallel with the first load, and a second switching element connected in parallel with the second load, wherein a gate of the first MOSFET is connected to a gate of the third MOSFET and a gate of the second MOSFET are connected to a gate of the fourth MOSFET, the first switching element is configured to transition to a conductive state as the drain-source voltage of the first MOSFET increases, and the second switching element is configured to transition to a conductive state as the drain-source voltage of the second MOSFET increases.

[0011] A multistage amplifier according to an embodiment of the present invention is a multistage amplifier including a plurality of amplifiers connected in cascade, at least one of which is configured by the above-described amplifier circuit. [Effects of the Invention]

[0012] According to the amplifier circuit and multistage amplifier of the present invention, it is believed that in an amplifier circuit including a differential pair with a diode load, it is possible to suppress a decrease in operating speed before and after saturation of the output voltage. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 2 is a circuit diagram illustrating an example of an amplifier circuit according to the first embodiment. [Figure 2]3A and 3B are diagrams illustrating changes in each input voltage and each output voltage when the non-inverted output voltage in the amplifier circuit of the first embodiment is saturated. [Figure 3] 10A and 10B are diagrams illustrating the input voltages, the output voltages, and the currents of the various parts in the process in which the non-inverted output voltage approaches saturation in the amplifier circuit of the embodiment. [Figure 4] FIG. 10 is a circuit diagram illustrating an example of an amplifier circuit according to a second embodiment. [Figure 5] FIG. 3 is a diagram illustrating an example of parasitic capacitance in the amplifier circuit of the first embodiment. [Figure 6] FIG. 1 is a circuit diagram illustrating an example of a multistage amplifier according to an embodiment. [Figure 7] FIG. 4 is a timing chart showing an offset voltage cancellation operation in the multistage amplifier according to the embodiment. [Figure 8] FIG. 1 is a circuit diagram showing a conventional differential pair. [Figure 9] FIG. 10 is a diagram schematically illustrating output voltages and output voltages in a conventional differential pair. DETAILED DESCRIPTION OF THE INVENTION

[0014] With reference to the drawings, amplifier circuits and multistage amplifiers according to embodiments of the present invention will be described in order. However, the amplifier circuits and multistage amplifiers of the present invention are not limited to the embodiments described below. For example, the circuits shown in the drawings may include circuit elements that are not shown, and conversely, may not include all of the circuit elements shown. Furthermore, each element shown in the drawings may have any characteristics or constants, and it should be understood that the characteristics and constants of each element are limited only by the claims.

[0015] <Amplifier circuit of the first embodiment> 1 shows an amplifier circuit 100 having a differential pair in an input stage, which is an example of an amplifier circuit according to a first embodiment. The amplifier circuit 100 has a first input terminal 61i, a second input terminal 62i, a first output terminal 61o, and a second output terminal 62o. The amplifier circuit 100 amplifies a differential voltage between a voltage input to the first input terminal 61i and a voltage input to the second input terminal 62i by a predetermined gain, and outputs the amplified voltage as a differential voltage between the first output terminal 61o and the second output terminal 62o. In the description of the amplifier circuit and the multi-stage amplifier according to the embodiment, the potential at each terminal or each node relative to the GND potential is also simply referred to as the "voltage" of each terminal or each node.

[0016] <First input differential pair and its load element> The amplifier circuit 100 includes a first input differential pair 1, a first load 31, a second load 32, and a constant current source 51. The first input differential pair 1 is configured with a first MOS field effect transistor (first MOSFET) 11 and a second MOS field effect transistor (second MOSFET) 12. The first load 31 is configured with a MOS field effect transistor (MOSFET) 31a and is connected to the first MOSFET 11. The second load 32 is configured with a MOS field effect transistor (MOSFET) 32a and is connected to the second MOSFET 12. The drain and gate of the MOSFET 31a are connected, and the drain and gate of the MOSFET 32a are connected. That is, the MOSFETs 31a and 32a are both diode-connected.

[0017] The first MOSFET 11 and the second MOSFET 12 have the same conductivity type (first conductivity type). In the amplifier circuit 100 of Fig. 1, the first MOSFET 11 and the second MOSFET 12 are both N-channel MOSFETs having n-type channels. Note that the first MOSFET 11 and the second MOSFET 12 constituting the first input differential pair 1 may be P-channel MOSFETs having p-type channels in an embodiment different from that of Fig. 1 (see Fig. 4).

[0018] On the other hand, the MOSFET 31a and the MOSFET 32a constituting the first load 31 or the second load 32 both have a conductivity type (second conductivity type) different from the conductivity type of the first MOSFET 11 and the second MOSFET 12. In the amplifier circuit 100 of Fig. 1, the MOSFET 31a and the MOSFET 32a are both P-channel MOSFETs. Note that, in an embodiment different from that of Fig. 1, when the first MOSFET 11 and the second MOSFET 12 are P-channel MOSFETs, i.e., when the first conductivity type is p-type, the MOSFET 31a and the MOSFET 32a may be N-channel MOSFETs.

[0019] The source of the first MOSFET 11 and the source of the second MOSFET 12 are connected to each other and to the negative electrode (current input terminal) of the constant current source 51. The positive electrode (current output terminal) of the constant current source 51 is connected to the low power supply potential VSS of the amplifier circuit 100. The gate of the first MOSFET 11 is connected to the first input terminal 61i of the amplifier circuit 100, and the gate of the second MOSFET 12 is connected to the second input terminal 62i of the amplifier circuit 100. The drain of the first MOSFET 11 is connected to the drain and gate of a MOSFET 31a constituting the first load 31 and to the first output terminal 61o of the amplifier circuit 100. The drain of the second MOSFET 12 is connected to the drain and gate of a MOSFET 32a constituting the second load 32 and to the second output terminal 62o of the amplifier circuit 100. The sources of the MOSFETs 31a and 32a are both connected to the high power supply potential VDD of the amplifier circuit 100.

[0020] The first load 31 and the second load 32 provide the first MOSFET 11 and the second MOSFET 12 with the current that the constant current source 51 attempts to draw. The first load 31 and the second load 32 are active loads. The amount of current flowing through the drain of the first MOSFET 11 increases as the drain-source voltage of the first MOSFET 11 increases. When the input differential voltage of the differential pair formed by the first MOSFET 11 and the second MOSFET 12 is small, i.e., when a small signal is input, the first load 31 maintains saturation region operation, so the magnitude of the load does not change. Instead, the output voltage of the first output terminal 61o decreases in proportion to the current flowing through the drain of the first MOSFET 11. Similarly, when the drain-source voltage of the second MOSFET 12 decreases, the amount of current flowing through the drain of the second MOSFET 12 decreases, and the output voltage of the second output terminal 62o increases. As a result, the differential voltage between the first input terminal 61i and the second input terminal 62i is amplified. In this way, the first input differential pair 1 is configured to perform differential amplification. In the amplifier circuit 100 of FIG. 1, the first input terminal 61i is an inverting input terminal, the second input terminal 62i is a non-inverting input terminal, the first output terminal 61o is a non-inverting output terminal, and the second output terminal 62o is an inverting output terminal.

[0021] <Second input differential pair and its load elements, etc.> The amplifier circuit 100 of the embodiment further includes a second input differential pair 2, a third load 33, a fourth load 34, a constant current source 52, a first switching element 41, and a second switching element 42. The second input differential pair 2 is configured with a third MOS field-effect transistor (third MOSFET) 23 and a fourth MOS field-effect transistor (fourth MOSFET) 24. The third load 33 is connected to the drain of the third MOSFET 23. The fourth load 34 is connected to the drain of the fourth MOSFET 24. In the amplifier circuit 100 of FIG. 1, the third load 33 is configured with a MOS field-effect transistor (MOSFET) 33a, and the fourth load 34 is configured with a MOS field-effect transistor (MOSFET) 34a. The drain and gate of the MOSFET 33a are connected, and the drain and gate of the MOSFET 34a are connected. That is, the MOSFETs 33a and 34a are both diode-connected. It should be noted that "MOS field effect transistor" and "MOSFET" are hereinafter also referred to simply as "FET."

[0022] The third FET 23 and the fourth FET 24 both have the same conductivity type (first conductivity type) as the conductivity type of the first FET 11 and the second FET 12. That is, in the amplifier circuit 100 of Fig. 1, the third FET 23 and the fourth FET 24 are both N-channel MOSFETs, like the first FET 11 and the second FET 12. Note that in an embodiment different from that of Fig. 1, if the first FET 11 and the second FET 12 are P-channel MOSFETs, that is, if the first conductivity type is p-type, the third FET 23 and the fourth FET 24 may also be P-channel MOSFETs.

[0023] On the other hand, the FET 33a and FET 34a constituting the third load 33 or the fourth load 34 both have a conductivity type (second conductivity type) different from the conductivity type of the third FET 23 and the fourth FET 24, i.e., the first conductivity type. In the amplifier circuit 100 of FIG. 1, the FET 33a and FET 34a are both P-channel MOSFETs. Note that, in an embodiment different from FIG. 1, when the third FET 23 and the fourth FET 24 are P-channel MOSFETs, i.e., when the first conductivity type is p-type, the FET 33a and FET 34a may be N-channel MOSFETs.

[0024] The source of the third FET 23 and the source of the fourth FET 24 are connected to each other and to the negative electrode (current input terminal) of the constant current source 52. The positive electrode (current output terminal) of the constant current source 52 is connected to the low power supply potential VSS of the amplifier circuit 100. The gate of the third FET 23 is connected to the gate of the first FET 11 and thus to the first input terminal 61i of the amplifier circuit 100. The gate of the fourth FET 24 is connected to the gate of the second FET 12 and thus to the second input terminal 62i of the amplifier circuit 100. The drain of the third FET 23 is connected to the drain and gate of the FET 33a that constitutes the third load 33. The drain of the fourth FET 24 is connected to the drain and gate of the FET 34a that constitutes the fourth load 34. The sources of the FET 33a and the FET 34a are both connected to the high power supply potential VDD of the amplifier circuit 100.

[0025] The third load 33 and the fourth load 34 collectively provide the current drawn by the constant current source 52 to the third FET 23 and the fourth FET 24. The third load 33 and the fourth load 34 are active loads. The amount of current flowing through the drain of the third FET 23 increases as the drain-source voltage of the third FET 23 increases. When the input differential voltage of the differential pair formed by the third FET 23 and the fourth FET 24 is small, i.e., when a small signal is input, the third load 33 maintains saturation region operation, so the magnitude of the load does not change, and the output voltage decreases in proportion to the current flowing through the drain of the third FET 23. Similarly, as the drain-source voltage of the fourth FET 24 decreases, the amount of current flowing through the drain of the fourth FET 24 decreases, and the output voltage increases. As a result, a voltage obtained by amplifying the differential voltage between the first input terminal 61i and the second input terminal 62i is generated between the drain of the third FET 23 and the drain of the fourth FET 24. In this way, the second input differential pair 2 is configured to be capable of differential amplification.

[0026] <Two switching elements> The first switching element 41 and the second switching element 42 each have at least two controlled terminals and at least one control terminal. The first switching element 41 and the second switching element 42 change the conduction state between the two controlled terminals in response to the electrical state of the control terminal 413 or the control terminal 423. The first switching element 41 is connected in parallel to the first load 31 with respect to the two controlled terminals 411 and 412. The second switching terminal 42 is connected in parallel to the second load 32 with respect to the two controlled terminals 421 and 422. That is, the controlled terminal 411 of the first switching element 41 and one end of the first load 31 are both connected to the high power supply potential VDD, and the controlled terminal 412 of the first switching element 41 is connected to the other end of the first load 31. A controlled terminal 421 of the second switching element 42 and one end of the second load 32 are both connected to the high power supply potential VDD, and a controlled terminal 422 of the second switching element 42 and the other end of the second load 32 are connected.

[0027] In the amplifier circuit 100 of FIG. 1, the first switching element 41 and the second switching element 42 are configured by metal-oxide-semiconductor field-effect transistors (MOSFETs) having p-type channels of a second conductivity type (first conductivity type) different from the conductivity type (second conductivity type) of the first FET 11 and the second FET 12. The first switching element 41 is configured by an FET 41a, and the second switching element 42 is configured by an FET 42a. The source and drain of the FET 41a function as controlled terminals 411 and 412, respectively, of the first switching element 41, and the gate functions as a control terminal 413. The source of the FET 41a is connected to a high power supply potential VDD, and the drain of the FET 41a is connected to the drain and gate of the FET 31a, the drain of the first FET 11, and the first output terminal 61o. The source and drain of the FET 42a function as controlled terminals 421 and 422, respectively, of the second switching element 42, and the gate functions as a control terminal 423. The source of the FET 42a is connected to the high power supply potential VDD, and the drain of the FET 42a is connected to the drain and gate of the FET 32a, the drain of the second FET 12, and the second output terminal 62o.

[0028] 1, first switching element 41 is configured to transition to a conductive state with respect to conductivity between two controlled terminals 411 and 412 as the drain-source voltage of first FET 11 increases. Meanwhile, second switching element 42 is configured to transition to a conductive state with respect to conductivity between two controlled terminals 421 and 422 as the drain-source voltage of second FET 12 increases in amplifier circuit 100 of FIG. 1. That is, in amplifier circuit 100 of FIG. 1, even if the operating region of first load 31 shifts to, for example, the cutoff region as the drain-source voltage of first FET 11 increases and current supply from first load 31 is disrupted, the operating region of FET 41a remains, for example, in the saturation region or linear region without reaching the cutoff region, thereby maintaining ease of current flow between the source and drain of FET 41a. Therefore, the increase in the voltage at first output terminal 61о is not hindered by the shift of the operating region of first load 31 to the cutoff region. Similarly, even if the operating region of second load 32 shifts, for example, to the cutoff region as the drain-source voltage of second FET 12 increases and current supply from second load 32 is disrupted, the operating region of FET 42a remains, for example, in the saturation region or linear region without reaching the cutoff region, thereby maintaining the ease of current flow between the source and drain of FET 42a. Therefore, the increase in the voltage at second output terminal 62о is not hindered by the shift of the operating region of second load 32 to the cutoff region.

[0029] Because the conduction states of the first switching element 41 and the second switching element 42 transition as described above, a decrease in operating speed before and after saturation of the non-inverting output voltage Vop on the high power supply potential side is suppressed, as shown in FIG. 2. Furthermore, it may be possible to widen the output voltage range compared to conventional techniques. FIG. 2 also shows an example of changes in the non-inverting output voltage Vop and the inverting output voltage Vom when a non-inverting input voltage Vip and an inverting input voltage Vim that cause the non-inverting output voltage Vop to saturate on the high power supply potential VDD side are input to the input terminals 61i and 62i. The time required for the non-inverting output voltage Vop to reach saturation is approximately the same as the time required for the inverting output voltage Vom to reach saturation on the low power supply potential side, and the time required for the non-inverting output voltage Vop to recover from saturation is approximately the same as the time required for the inverting output voltage Vom to recover from saturation.

[0030] Furthermore, the saturation voltage Vsat of the non-inverting output voltage Vop on the high power supply potential VDD side nearly reaches VDD. That is, in FIG. 2, the saturation voltage Vsat does not drop from the high power supply potential VDD by the threshold voltage of the FET 31a, so the output voltage range is wider than in the past (see Vsat in FIG. 9). FIG. 2 shows an example in which the non-inverting output voltage Vop saturates on the high power supply potential VDD side, but similarly, when the inverting output voltage Vom saturates on the high power supply potential VDD side, the decrease in operating speed before and after saturation of the inverting output voltage Vom is suppressed. Furthermore, the output voltage range may be wider than in the past.

[0031] <Operation of the Amplifier Circuit of the Embodiment> 1 and FIG. 3, the reasons why the decrease in operating speed before and after saturation illustrated in FIG. 2 can be suppressed and the output voltage range can be expanded will be explained below, along with the actions of the first and second switching elements 41, 42. FIG. 3 shows an enlarged view of the period during which the non-inverted output voltage Vop and the inverted output voltage Vom shown in FIG. 2 approach saturation. In addition to the input voltages Vip, Vim and the output voltages Vop, Vom shown in FIG. 2, FIG. 3 also shows the current I31 flowing through the first load 31 and the current Is1 flowing from the first switching element 41 to the first FET 11.

[0032] As shown in FIG. 3, when a non-inverting input voltage Vip and an inverting input voltage Vim are input such that the non-inverting output voltage Vop saturates at the high power supply potential VDD, the current I31 flowing from the first load 31 to the first FET 11 decreases as the non-inverting input voltage Vip increases and the inverting input voltage Vim decreases. Meanwhile, although not shown in FIG. 3, the current flowing from the second load 32 to the second FET 12 increases. The non-inverting output voltage Vop also increases, while the inverting output voltage Vom decreases. During this time, a current Is1 also flows from the first switching element 41 to the first FET 11. The current Is1 increases as the non-inverting input voltage Vip increases because the gate voltage of the FET 41a decreases. However, once the non-inverting output voltage Vop reaches VDD, the voltage no longer increases, and the current Is1 quickly becomes zero.

[0033] As long as the rising non-inverting output voltage Vop is sufficiently lower than a potential (VDD-Vth) that is lower than the high power supply potential VDD by the threshold voltage Vth of the FET 31a constituting the first load 31, a sufficient current is supplied from the first load 31 to the first FET 11. However, when the rising non-inverting output voltage Vop reaches (VDD-Vth), the resistance value of the first load 31 increases rapidly, and the first FET 11 is almost completely depleted of the current I31. In a conventional amplifier circuit, the current supply from the diode load is almost completely eliminated on the side that saturates at the high power supply potential, and the rate of rise of the output voltage slows down. The output voltage then saturates at a potential lower than the high power supply potential by the threshold voltage of the FET constituting the diode load.

[0034] In contrast, the amplifying device 100 of the embodiment is provided with the first switching element 41, which suppresses a decrease in the rate of increase of the non-inverted output voltage Vop. Moreover, the non-inverted output voltage Vop may be able to rise to approximately the high power supply potential VDD.

[0035] That is, as described above, the first switching element 41 is configured to maintain a conductive state as the drain-source voltage of the first FET 11 increases. During the period in which the non-inverting input voltage Vip increases and the inverting input voltage Vim decreases, as shown in FIG. 3, the drain-source voltage of the first FET 11 increases because the gate voltage of the first FET 11 decreases. Therefore, the first switching element 41 maintains a conductive state as the non-inverting input voltage Vip increases, and continues to supply the current Is1 to the first FET 11 when the operating region of the first load 31 transitions to the cutoff region as shown in FIG. 3, causing the current I31 to approach zero. Furthermore, because the control terminal 413 of the first switching element 41 is not directly affected by the non-inverting output voltage Vop, the first switching element 41 can supply the current Is1 as long as the non-inverting output voltage Vop exceeds VDD-Vth but does not exceed VDD, as shown in FIG. 3. Therefore, the non-inverting output voltage Vop can quickly reach saturation near VDD. That is, the decrease in the rate of increase of the non-inverted output voltage Vop until it reaches saturation is suppressed.

[0036] Furthermore, the first switching element 41 is not restricted by the threshold voltage Vth of the FET 31a with respect to the conductivity (i.e., voltage drop) between the controlled terminal 411 and the controlled terminal 412 in the conductive state. Therefore, the non-inverted output voltage Vop of the first output terminal 61o connected to the controlled terminal 412 of the first switching element 41 can rise to approximately the high power supply potential VDD. In other words, the output voltage range may be expanded.

[0037] 1, the gate of FET 41a is connected to the drain of fourth FET 24 so that first switching element 41 transitions to a conductive state as the drain-source voltage of first FET 11 increases. That is, the gate of FET 41a is also connected to the gate and drain of FET 34a constituting fourth load 34. Furthermore, the gate of FET 42a is connected to the drain of third FET 23 so that second switching element 42 transitions to a conductive state as the drain-source voltage of second FET 12 increases. That is, the gate of FET 42a is also connected to the gate and drain of FET 33a constituting third load 33.

[0038] In the amplifier circuit 100 of FIG. 1, in which the FETs 41a and 42a are connected to the second input differential pair 2, when the gate voltage of the fourth FET 24 increases, the drain voltage of the fourth FET 24 decreases, causing the drain and gate voltages of the FET 34a and the gate voltage of the FET 41a to decrease. The gate voltage of the fourth FET 24 increases as the non-inverting input voltage Vip increases. In contrast, the drain-source voltage of the first FET 11 increases when the non-inverting input voltage Vip increases because the inverting input voltage Vim decreases. Therefore, when the drain-source voltage of the first FET 11 increases with the increase in the non-inverting input voltage Vip, the FET 41a transitions to a more conductive state as the gate voltage decreases, reducing the on-resistance of the first switching element 41. In other words, the current Is1 flowing from the first switching element 41 to the first FET 11 increases. Therefore, as described above, the decrease in the rate of increase of the non-inverting output voltage Vop is suppressed. Furthermore, the non-inverted output voltage Vop can rise to approximately the high power supply potential VDD.

[0039] In the amplifier circuit 100 of the embodiment, the non-inverting output voltage Vop can recover from saturation more quickly than in the conventional amplifier circuit when the non-inverting input voltage Vip drops after reaching saturation. That is, as shown in FIG. 3 , while the first load 31 transitions to the cutoff region and the current I31 approaches zero, the first switching element 41 continues to supply the current Is1 to the first input differential pair 1. This current supply is maintained regardless of whether the non-inverting output voltage Vop reaches saturation or recovers. Therefore, compared to when no current is supplied to the first input differential pair 1 from sources other than the first load 31 and the second load 32, the transient change in the non-inverting output voltage Vop of the first input differential pair 1 progresses more quickly when the non-inverting output voltage Vop begins to rise, especially when the non-inverting output voltage Vop exceeds VDD-Vth but does not exceed VDD. When recovering from a saturated state, for example, as shown in FIG. 2, it is possible for the non-inverted output voltage Vop to recover from saturation on the high power supply potential side in approximately the same time as the recovery time of the inverted output voltage Vom from saturation on the low power supply potential side.

[0040] 3 shows an example in which the non-inverted output voltage Vop saturates on the high power supply potential VDD side, but even when the inverted output voltage Vom saturates on the high power supply potential VDD side, the decrease in the rate of increase of the inverted output voltage Vom is suppressed. Furthermore, the inverted output voltage Vom may be able to rise to approximately the high power supply potential VDD. These effects are achieved by the second switching element 42. Because the operation of the second switching element 42 is similar to the operation of the first switching element 41 described above, the operation of the second switching element 42 will be explained below in an appropriately simplified manner.

[0041] When the inverting input voltage Vim and the non-inverting input voltage Vip are input such that the inverting output voltage Vom saturates at the high power supply potential VDD, the current flowing from the second load 32 to the second FET 12 decreases. Furthermore, the inverting output voltage Vom rises, and the non-inverting output voltage Vop falls. During this time, a current that increases with the rise in the inverting input voltage Vim also flows through the second FET 12 from the second switching element 42. When the rising inverting output voltage Vom reaches a potential (VDD-Vth) that is lower than the high power supply potential VDD by the threshold voltage Vth of the FET 32a constituting the second load 32, the resistance value of the second load 32 rises sharply, and almost no current is supplied from the second load 32 to the second FET 12. However, the amplifier circuit 100 of this embodiment is provided with the second switching element 42. As described above, the second switching element 42 is configured to transition to a highly conductive state as the drain-source voltage of the second FET 12 increases, thereby reducing the on-resistance of the second switching element 42.

[0042] Specifically, when the gate voltage of the third FET 23 increases, the drain voltage of the third FET 23 decreases, and the drain and gate voltages of the FET 33a and the gate voltage of the FET 42a also decrease. The gate voltage of the third FET 23 increases as the inverting input voltage Vim increases. In contrast, the drain-source voltage of the second FET 12 increases when the inverting input voltage Vim increases because the non-inverting input voltage Vip decreases. Therefore, when the drain-source voltage of the second FET 12 increases as the inverting input voltage Vim increases, the FET 42a transitions to a more highly conductive state as the gate voltage decreases. That is, the second switching element 42 transitions to a conductive state as the drain-source voltage of the second FET 12 increases, increasing the current flowing to the second FET 12.

[0043] Since the control terminal 423 of the second switching element 42 is not directly affected by the inverted output voltage Vom, current continues to flow from the second switching element 42 to the second FET 12 even when the inverted output voltage Vom exceeds (VDD - Vth). Therefore, a decrease in the rising speed of the inverted output voltage Vom until saturation is suppressed, and the inverted output voltage Vom can reach saturation quickly. Also, the second switching element 42 is not subject to the constraints based on the threshold voltage Vth of the FET 32a regarding the resistance (i.e., voltage drop) between the controlled terminal 421 and the controlled terminal 422 in the conductive state. Therefore, the inverted output voltage Vom of the second output terminal 62o connected to the controlled terminal 422 of the second switching element 42 can rise to approximately the high power supply potential VDD, and thus the output voltage range may be expanded.

[0044] When the inverted output voltage Vom that has reached saturation returns from saturation as the inverted input voltage Vim decreases, it can return faster than before, similar to when the non-inverted output voltage Vop returns from saturation. Therefore, even in the return from the saturated state, the inverted output voltage Vom can return from saturation on the high power supply potential side in approximately the same time as the return time from saturation on the low power supply potential side of the non-inverted output voltage Vop.

[0045] In the amplifier circuit 100 of the embodiment illustrated in FIG. 1, an example is given where the first FET 11 and the second FET 12 of the first conductivity type are N-channel MOSFETs. Therefore, in the amplifier circuit 100 of FIG. 1, the first switching element 41 configured to transition to the conductive state as the drain-source voltage of the first FET 11 increases transitions to the conductive state as the potential (drain voltage) of the drain of the fourth FET 24 decreases. On the other hand, the second switching element 42 configured to transition to the conductive state as the drain-source voltage of the second FET 12 increases transitions to the conductive state as the potential (drain voltage) of the drain of the third FET 23 decreases. <P-channel MOSFET input differential pair>

[0046] Unlike the amplifier circuit 100 of FIG. 1 , the amplifier circuit of the embodiment may include P-channel MOSFETs as the first conductivity type first FET 11 and second FET 12, as in the second embodiment shown in FIG. 4 . That is, the first conductivity type may be p-type. Similar to the amplifier circuit 100 of FIG. 1 , the amplifier circuit 101 of the second embodiment shown in FIG. 4 includes a first input differential pair 1, a first load 31, a second load 32, a second input differential pair 2, a third load 33, a fourth load 34, a first switching element 41, a second switching element 42, a first input terminal 61i, a second input terminal 62i, a first output terminal 61o, a second output terminal 62o, and constant current sources 51 and 52. The first input differential pair is configured to be differentially amplified by the first conductivity type first FET 11 and the second FET. The second input differential pair is configured to be capable of differential amplification by a third FET 23 and a fourth FET 24, both of the same first conductivity type as the first FET 11 and the second FET 12. In the amplifier circuit 101 of Fig. 4, the first FET 11 and the second FET 12 are both P-channel MOSFETs. Therefore, the third FET 23 and the fourth FET 24 are also P-channel MOSFETs.

[0047] The gate of the first FET 11, the gate of the third FET 23, and a first input terminal 61i (inverting input terminal) are connected, and the gate of the second FET 12, the gate of the fourth FET 24, and a second input terminal 62i (non-inverting input terminal) are connected. The drain of the first FET 11 is connected to a first output terminal 61o (non-inverting output terminal), and the drain of the second FET 12 is connected to a second output terminal 62o (inverting output terminal).

[0048] The first load 31 is composed of an FET 31a and is connected to the drain of the first FET 11. The second load 32 is composed of an FET 32a and is connected to the drain of the second FET 12. The third load 33 is composed of an FET 33a and is connected to the drain of the third FET 23. The fourth load 34 is composed of an FET 34a and is connected to the drain of the fourth FET 24. The FETs 31a, 32a, 33a, and 34a are all diode-connected.

[0049] The first switching element 41 is configured with an FET 41a, and the source and drain of the FET 41a function as one and the other of two controlled terminals of the first switching element 41, respectively, and the gate of the FET 41a functions as a controlled terminal of the first switching element 41. The first switching element 41 is connected in parallel to the first load 31. The second switching element 42 is configured with an FET 42a, and the source and drain of the FET 42a function as one and the other of two controlled terminals of the second switching element 42, respectively, and the gate of the FET 42a functions as a controlled terminal of the second switching element 42. The second switching element 42 is connected in parallel to the second load 32.

[0050] The gate of FET 41a constituting the first switching element 41 is connected to the drain of the fourth FET 24 and the gate and drain of FET 34a. The drain of FET 41a, together with the drain and gate of FET 31a, is connected to the first output terminal 61o. The gate of FET 42a constituting the second switching element 42 is connected to the drain of the third FET 23 and the gate and drain of FET 33a. The drain of FET 42a, together with the drain and gate of FET 32a, is connected to the second output terminal 62o. FET 31a, FET 32a, FET 33a, FET 34a, FET 41a, and FET 42a are all MOSFETs of a conductivity type (second conductivity type) different from the first conductivity type, and therefore are N-channel MOSFETs.

[0051] In the amplifier circuit 101, the sources of the first FET 11 and the second FET 12 are connected to the positive electrode (current output terminal) of a constant current source 51. The negative electrode (current input terminal) of the constant current source 51 is connected to a high power supply potential VDD of the amplifier circuit 101. The sources of the third FET 23 and the fourth FET 24 are connected to the positive electrode of a constant current source 52. The negative electrode of the constant current source 52 is connected to the high power supply potential VDD. Meanwhile, the sources of the FETs 31a, 32a, 33a, 34a, 41a, and 42a are connected to a low power supply potential VSS of the amplifier circuit 101.

[0052] In the amplifier circuit 101, the first switching element 41 is also configured to transition to a conductive state with respect to conductivity between the two controlled terminals 411 and 412 as the drain-source voltage of the first FET 11 increases. In an amplifier circuit 101 in which the first FET 11 and the second FET 12 are P-channel MOSFETs, the first switching element 41 configured in this manner transitions to a conductive state with respect to conductivity between the two controlled terminals 421 and 422 as the drain-source voltage of the second FET 12 increases. In an amplifier circuit 101 in which the first FET 11 and the second FET 12 are P-channel MOSFETs, the second switching element 42 configured in this manner transitions to a conductive state with respect to conductivity between the two controlled terminals 421 and 422 as the drain-source voltage of the second FET 12 increases. In an amplifier circuit 101 in which the first FET 11 and the second FET 12 are P-channel MOSFETs, the second switching element 42 configured in this manner transitions to a conductive state with respect to conductivity between the two controlled terminals 421 and 422 as the drain-source voltage of the third FET 23 increases. In the amplifier circuit 101, the first switching element 41 and the second switching element 42 are configured in this way, which suppresses a decrease in the operating speed before and after saturation of each output voltage on the low power supply potential side, and also may widen the output voltage range compared to conventional circuits.

[0053] 4 differs from the amplifier circuit 100 of FIG. 1 in that the first switching element 41 and the second switching element 42 function when each output voltage saturates at the low power supply potential VSS side rather than the high power supply potential VDD side. However, in the amplifier circuit 101, the first switching element 41 and the second switching element 42 transition to a conductive state so that current flows through the first FET 11 or the second FET 12 when the non-inverted output voltage Vop or the inverted output voltage Vom saturates at the low power supply potential VSS side. In other words, the amplifier circuit 101 operates based on the same logic as the amplifier circuit 100 of FIG. 1. The operation of the amplifier circuit 101 will be described briefly below.

[0054] For example, when input voltages are applied that cause the non-inverting output voltage Vop to saturate at the low power supply potential VSS, the current flowing from the first FET 11, to which the high inverting input voltage Vim is applied, to the first load 31 decreases. The non-inverting output voltage Vop then decreases, while the inverting output voltage Vom increases. During this time, a current that increases as the non-inverting input voltage Vip decreases flows through the first switching element 41 from the first FET 11. When the decreasing non-inverting output voltage Vop reaches a potential (VSS+Vth) that is higher than the low power supply potential VSS by the threshold voltage Vth of the FET 31a constituting the first load 31, the resistance value of the first load 31 increases rapidly, and almost no current can flow from the first FET 11 to the first load 31. However, the first switching element 41 is configured to transition to a highly conductive state when the first load 31a transitions to the cutoff region. As the non-inverting output voltage Vop drops, the first load 31a transitions to a cutoff region, causing the first switching element 41 to transition to a conductive state, increasing the current flowing through the first FET 11. Because the control terminal 413 of the first switching element 41 is not directly affected by the non-inverting output voltage Vop, current continues to flow through the first switching element 41 from the first FET 11 even when the non-inverting output voltage Vop falls below (VSS + Vth). This prevents a decrease in the rate at which the non-inverting output voltage Vop drops to saturation, allowing the non-inverting output voltage Vop to quickly reach saturation. Furthermore, the resistance (voltage drop) between the controlled terminal 411 and the controlled terminal 412 of the first switching element 41 in the conductive state is not restricted by the threshold voltage Vth of the FET 31a. Therefore, the non-inverting output voltage Vop at the first output terminal 61o connected to the controlled terminal 412 of the first switching element 41 can drop to approximately the low power supply potential VSS, which may expand the output voltage range.

[0055] When the non-inverting output voltage Vop, which has reached saturation, recovers from saturation as the non-inverting input voltage Vip increases, recovery can be achieved more quickly than in the past, as described above with respect to the amplifier circuit 100 of Fig. 1. Therefore, even when recovering from a saturated state, the non-inverting output voltage Vop can recover from saturation on the low power supply potential side in approximately the same time as the recovery time of the inverting output voltage Vom from saturation on the high power supply potential side.

[0056] Even when the inverted output voltage Vom saturates on the low power supply potential VSS side in the amplifier circuit 101, the action of the second switching element 42 suppresses a decrease in the rate of fall of the inverted output voltage Vom. Furthermore, the inverted output voltage Vom may be able to fall to approximately the low power supply potential VSS. Thus, in the amplifier circuit 101, a decrease in the operating speed before and after saturation of each output voltage on the low power supply potential side is suppressed. Furthermore, it may be possible to expand the output voltage range compared to conventional circuits.

[0057] In the amplifier circuit of the embodiment, as can be understood from the description of amplifier circuit 100 in FIG. 1 , when the output voltage of either the non-inverting side or the inverting side becomes saturated, the first switching element or the second switching element replaces or assists the function of the first load or the second load. That is, when one output voltage approaches saturation, the first load or the second load, which is formed of a diode-connected FET, becomes saturated while maintaining the gate threshold voltage between its source and drain, and almost no current flows through the load. In this way, the first switching element or the second switching element replaces or assists the function of the first load or the second load, which is unable to fully function as a load for the first input differential pair.

[0058] In the amplifier circuit of the embodiment, a voltage that changes in the opposite direction to the direction of change in the gate voltage of the load element whose function the switching element replaces or supports is applied to the control terminals of the first switching element and the second switching element. That is, the gates of the two FETs constituting the first input differential pair and the two FETs constituting the second input differential pair are connected so that such a voltage is applied to the control terminals of the switching elements. Specifically, the gates of the FETs of the second input differential pair to which each switching element is connected are connected to the gates of the FETs of the first input differential pair that are connected to the load element opposite to the load element that the switching element replaces or supports. Therefore, the first switching element and the second switching element can be fully conductive when the first load or the second load that the switching element replaces or supports stops flowing current. The amplifier circuit of the embodiment includes a second input differential pair that may be a replica of the first input differential pair and operates in conjunction with the first input differential pair that provides the amplifier circuit function, and switching elements controlled by the second input differential pair. The replica input differential pair and the switching element can suppress the decrease in operating speed around the time when the output voltage is saturated, and can also widen the output voltage range.

[0059] <Switching element characteristics> In the amplifier circuit 100 of FIG. 1 and the amplifier circuit 101 of FIG. 4, the first switching element 41 and the second switching element 42 are both configured with MOSFETs (FETs) 41a and 42a, respectively. By configuring each switching element with a FET, the saturated output voltage can be controlled to reach approximately the high power supply potential VDD or the low power supply potential VSS. That is, when the drain voltage of each FET constituting the second input differential pair 2 reaches a voltage above or below the threshold voltage of the FET constituting each switching element, the potential difference across each switching element drops to the extremely small drain-source saturation voltage of the FET constituting each switching element. In other words, the resistance across each switching element drops to the on-resistance of the FET constituting each switching element. Therefore, the saturated output voltage can reach approximately the high power supply potential VDD or the low power supply potential VSS.

[0060] Furthermore, if each switching element is configured as an FET, the current flowing through each switching element can be continuously changed by continuously changing the conduction state of each switching element according to the drain voltage of each FET constituting the second input differential pair 2. Each switching element may change the conduction state between the two controlled terminals in this manner continuously or stepwise, or may simply switch the conduction state between the two controlled terminals between at least a closed state (on state) and an open state (off state). Even in this case, when the output voltage is saturated, the first switching element 41 or the second switching element 42 is closed, allowing current to be supplied to or flow from the first input differential pair 1.

[0061] 1, the first switching element 41 may transition to a closed state when the difference between the high power supply potential VDD and the potential of the drain of the fourth FET 24 becomes equal to or greater than a predetermined first threshold, and the second switching element 42 may transition to a closed state when the difference between the high power supply potential VDD and the potential of the drain of the third FET 23 becomes equal to or greater than a predetermined second threshold. Also, in the amplifier circuit 101 of FIG. 4, the first switching element 41 may transition to a closed state when the difference between the low power supply potential VSS and the potential of the drain of the fourth FET 24 becomes equal to or greater than a predetermined third threshold, and the second switching element 42 may transition to a closed state when the difference between the low power supply potential VSS and the potential of the drain of the third FET 23 becomes equal to or greater than a predetermined fourth threshold.

[0062] The predetermined first threshold, the predetermined second threshold, the predetermined third threshold, and the predetermined fourth threshold are values ​​greater than the threshold Vth of the first load 31, the FET 31a, the second load 32, and the FET 32a used, and preferably are values ​​sufficiently greater than these threshold Vth.

[0063] The first switching element 41 and the second switching element 42 need only be able to switch the conductivity between the controlled terminals between at least two states, a closed state and an open state, and therefore do not have to be configured as MOSFETs as in the example of Fig. 1. The first switching element 41 and the second switching element 42 may be, for example, various semiconductor switches such as gallium nitride field effect transistors (GaN_FETs), photocouplers, or various relays such as electromagnetic relays.

[0064] <Parasitic capacitance associated with the output terminal> FIG. 5 shows the amplifier circuit 100 of FIG. 1 again. FIG. 5 also shows the parasitic capacitances associated with the first output terminal 61o and the second output terminal 62o. The first output terminal 61o is accompanied by a gate-to-source parasitic capacitance Cg1 of FET 31a, a drain-to-source parasitic capacitance Cd1 of FET 31a, a drain-to-source parasitic capacitance Cd2 of FET 41a, and a drain-to-source parasitic capacitance Cd3 of the first FET 11. Meanwhile, the second output terminal 62o is accompanied by a gate-to-source parasitic capacitance Cg2 of FET 32a, a drain-to-source parasitic capacitance Cd4 of FET 32a, a drain-to-source parasitic capacitance Cd5 of FET 42a, and a drain-to-source parasitic capacitance Cd6 of the second FET 12. Each FET may be composed of multiple FETs (sub-FETs) with the same structure and characteristics that are connected in parallel by connecting their gates, sources, and drains together. In this case, the parasitic capacitance between each terminal of each FET is the product of the parasitic capacitance between each terminal of the sub-FETs that make up each FET and the number of sub-FETs (number of multipliers).

[0065] 5, assume that FET 31a and FET 32a are each composed of (n1) sub-FETs, FET 41a and FET 42a are each composed of (n2) sub-FETs, and the gate-source parasitic capacitances of the sub-FETs are all uniformly Csg and the drain-source parasitic capacitances of the sub-FETs are all uniformly Csd. In this case, the parasitic capacitance (C1) between the first output voltage 61o and the high power supply potential VDD is the sum of the gate-source parasitic capacitances and drain-source parasitic capacitances of the (n1) sub-FETs constituting FET 31a and the (n2) drain-source parasitic capacitances constituting FET 41a, and is given by C1 = Csg × n1 + Csd × (n1 + n2). Similarly, the parasitic capacitance (C2) between the second output voltage 62o and the high power supply potential VDD is given by C2 = Csg × n1 + Csd × (n1 + n2).

[0066] On the other hand, in the conventional amplifier circuit shown in FIG. 8, if the MOSFET 900a constituting each diode load is configured with a total of (n1 + n2) sub-FETs, where (n1) is the number of sub-FETs of FET31a and (n2) is the number of sub-FETs of FET41a, as assumed above, the parasitic capacitance Cc between each output terminal outputting the output voltages Vop and Vom and the high power supply potential VDD is Cc = Csg × (n1 + n2) + Csd × (n1 + n2). That is, when compared under the same conditions regarding the number of FETs seen from the output terminal to the load side, the amplifier circuit of the embodiment has a smaller parasitic capacitance associated with each output terminal on the load side than the conventional amplifier circuit by (Csg × n2). Therefore, the amplifier circuit of the embodiment may be able to operate faster than the conventional amplifier circuit even when the output voltage is not saturated. In the above comparison, the amplifier circuit of the embodiment and the conventional amplifier circuit have the same drain-source parasitic capacitance, but the gate-source parasitic capacitance formed by a thin gate insulating film is generally larger than the drain-source parasitic capacitance formed across the channel. Therefore, the amplifier circuit of the embodiment, which has a small gate-source parasitic capacitance, may contribute to high-speed operation.

[0067] Considering the general tendency that the drain-source parasitic capacitance of MOS field-effect transistors is relatively small, the number of FETs constituting the first switching element 41 and the second switching element 42 may be increased as indicated by the dashed lines in FIG. 5. FIG. 5 conceptually illustrates an FET 41b and an FET 42b constituting the first switching element 41 and the second switching element 42, respectively. As shown in FIG. 5, increasing the number of FETs constituting each switching element can reduce the resistance between the two controlled terminals when each switching element is in the closed state. That is, in the amplifier circuit 100 or the amplifier circuit 101 (see FIG. 4), it is possible to increase the saturation speed or recovery speed when each output voltage saturates on the high power supply potential VDD side, or to increase the saturation speed or recovery speed when each output voltage saturates on the low power supply potential VSS side.

[0068] As is clear from FIG. 5 , providing more FETs constituting each switching element increases the drain-source parasitic capacitance associated with each output terminal. However, as noted above, the drain-source parasitic capacitance of MOS field-effect transistors is generally small. Therefore, it is presumed that adding more FETs will have little effect on the high-speed operation of the amplifier circuit 100 or 101 of the embodiment. In fact, it may be preferable to reduce the resistance between the controlled terminals of each switching element when it is in the closed state. For example, in applications where the input voltage amplitude is relatively large, it may be preferable to configure each switching element with many FETs to expand the output voltage range. On the other hand, in applications where the input signal amplitude is relatively small and faster operation is required, it may be preferable to minimize the number of FETs constituting each switching element to enable faster operation.

[0069] Providing a larger number of FETs constituting each switching element can be achieved by configuring each switching element with a larger number of sub-FETs. Furthermore, when the gates of the FETs constituting each switching element are formed on a plane, the effect of reducing the resistance value of each switching element in the closed state can also be achieved by increasing the ratio (W / L ratio) of the gate width (W) to the gate length (L). Therefore, for example, the size of the FET 41a constituting the first switching element 41 and the size of the FET 42a constituting the second switching element 42 may both be larger than the size of the FET 31a and the size of the FET 32a. The "size" of each FET used here is a measure of the gate size of each FET. For example, when the gates are formed on a plane, it may be the W / L ratio described above. Furthermore, when each FET is configured with sub-FETs connected in parallel, the "size" of each FET used here may be the number of sub-FETs connected in parallel (the number of multipliers).

[0070] When each output voltage recovers from a saturated state, it is preferable that the first switching element 41 and the second switching element 42 quickly return to the state when the input differential voltage (Vip-Vim) becomes 0. By quickly returning the first switching element 41 and the second switching element 42 to such a state, the influence of the conduction state of the first switching element 41 and the second switching element 42 on the recovery operation of each output voltage from saturation in the first input differential pair 1 can be reduced. From this perspective, it is preferable that the gate voltages of the FETs 41a and 42a change faster than the gate voltages of the FETs 31a and 32a when the non-inverting input voltage Vip and the inverting input voltage Vim change. In other words, it is preferable that the gate voltages of the FET 33a constituting the third load 33 and the FET 34a constituting the fourth load 34 change faster than the gate voltages of the FETs 31a and 32a when the input voltages change. Therefore, in terms of appropriate recovery from the saturated state, it is preferable to use FETs 33a, 34a, 41a, and 42a that are smaller in size than FETs 31a and 32a so that the gate voltage changes relatively quickly.

[0071] <Multi-stage amplifier> Next, a multistage amplifier according to an embodiment of the present invention will be described with reference to Fig. 6. Fig. 6 shows a multistage amplifier 200, which is an example of a multistage amplifier according to an embodiment.

[0072] As shown in FIG. 6, the multistage amplifier 200 includes multiple amplifiers connected in series (or cascade). The multistage amplifier 200 in the example of FIG. 6 includes three amplifiers: amplifier 100a, amplifier 100b, and amplifier 100c. Note that the multistage amplifier of the embodiment may include any number of amplifiers, not limited to three. In the multistage amplifier 200, a differential voltage input to amplifier 100a is amplified by first-stage amplifier 100a, second-stage amplifier 100b, and third-stage amplifier 100c, respectively, and output from amplifier 100c. FIG. 6 also shows a comparator Cmp that receives the output voltage of the multistage amplifier 200 as a non-inverting input voltage Vip4 and an inverting input voltage Vim4. The comparator Cmp compares the output voltage or output signal of the multistage amplifier 200 with a predetermined reference voltage or the like.

[0073] Among the three cascaded amplifiers 100a, 100b, and 100c, the non-inverting output voltage from one amplifier is input to the next amplifier as a non-inverting input voltage. Also, the inverting output voltage from one amplifier is input to the next amplifier as an inverting input voltage. A non-inverting input voltage Vip1 and an inverting input voltage Vim1 are input to amplifier 100a, and a non-inverting output voltage Vop1 and an inverting output voltage Vom1 are output. A non-inverting input voltage Vip2 and an inverting input voltage Vim2 are input to amplifier 100b, and a non-inverting output voltage Vop2 and an inverting output voltage Vom2 are output. A non-inverting input voltage Vip3 and an inverting input voltage Vim3 are input to amplifier 100c, and a non-inverting output voltage Vop3 and an inverting output voltage Vom3 are output.

[0074] In the multistage amplifier 200 of the embodiment, at least one of the amplifiers, such as the amplifiers 100a to 100c, is configured with the amplifier circuit of the embodiment described with reference to Figures 1 and 4. Therefore, it is considered that a decrease in operating speed before and after saturation of the output voltage in one or more of the amplifiers is suppressed, and multistage amplification with little delay when the output voltage is saturated is realized. In addition, the output voltage range may be expanded compared to conventional amplifiers. In particular, in multistage amplifiers that amplify an input voltage over multiple stages, the output voltage is prone to saturation. Therefore, it is considered useful to use a multistage amplifier 200 including an amplifier circuit of the embodiment, which suppresses a decrease in operating speed when saturated and allows the voltage when saturated to approach a high power supply potential or a low power supply potential.

[0075] In the multistage amplifier 200, all of the amplifiers may be configured with the amplifier circuit of the embodiment, or only one of the amplifiers may be configured with the amplifier circuit of the embodiment. For example, only the final-stage amplifier (e.g., amplifier 100c in the example of FIG. 6) may be configured with the amplifier circuit of the embodiment. Alternatively, the first-stage amplifier (e.g., amplifier 100a in the example of FIG. 6) may be configured with an amplifier circuit that does not include the second input differential pair 2 or the switching elements 41 and 42 (see FIG. 1), and the other amplifiers may be configured with the amplifier circuit of the embodiment. Since output voltage saturation is more likely to occur in the final-stage amplifier than in the first-stage amplifier, configuring the subsequent-stage amplifier with the amplifier circuit of the embodiment may efficiently suppress a decrease in operating speed when the output voltage is saturated.

[0076] Furthermore, in the multistage amplifier 200, multiple amplifiers such as amplifiers 100a to 100c may include a mixture of amplifier circuits according to the embodiment shown in FIG. 1, in which the first input differential pair 1 includes an N-channel FET, and amplifier circuits according to the embodiment shown in FIG. 4, in which the first input differential pair 1 includes a P-channel FET. As an example, some amplifiers in the initial stage may be configured with amplifier circuits according to the embodiment in which the first input differential pair 1 includes a P-channel MOSFET (hereinafter also referred to as a "P-type amplifier circuit"), and the remaining amplifiers in the final stage may be configured with amplifier circuits according to the embodiment in which the first input differential pair 1 includes an N-channel MOSFET (hereinafter also referred to as an "N-type amplifier circuit"). Because P-channel FETs may have better noise characteristics, using P-type amplifier circuits in the initial stage amplifiers that amplify small signals can reduce noise contamination of small signals. On the other hand, in the final stage, where amplification is advanced, noise contamination is less likely to be a substantial problem, and maintaining high-speed operation may be more important. Therefore, by using an N-type amplifier circuit including an N-channel FET capable of high-speed operation as the final-stage amplifier, it may be possible to quickly eliminate group delay and other issues that occur in multi-stage amplification.

[0077] The multistage amplifier 200 of FIG. 6 further includes a plurality of capacitors 7 and a plurality of switches 8. Each capacitor 7 is arranged on two connection paths 91, 92 between each of the plurality of amplifiers. That is, in the example of FIG. 6, the capacitors 7 are arranged on the connection paths 91, 92 between the amplifiers 100a and 100b, and on the connection paths 91, 92 between the amplifiers 100b and 100c. In FIG. 6, the capacitors 7 are also arranged on the connection paths 9a, 9b between the amplifier 100c and the comparator Cmp. The switches 8 are connected between a midpoint potential VCM and one end of each capacitor 7. The midpoint potential VCM is an intermediate potential between the high power supply potential VDD and the low power supply potential VSS of the multistage amplifier 200. That is, VCM=(VDD+VSS) / 2.

[0078] One of the two terminals of each capacitor 7, which is connected to the switch 8, is connected to the input terminal of the amplifier located downstream of the connection path 91 or 92 to which the capacitor 7 is connected. On the other hand, the other of the two terminals of the capacitor 7, opposite to the one connected to the switch 8, is connected to the output terminal of the amplifier located upstream of the connection path 91 or 92 to which the capacitor 7 is connected.

[0079] Specifically, between amplifier 100a and amplifier 100b, capacitor 7 arranged on connection path 91 is connected between the non-inverting output terminal of amplifier 100a and the non-inverting input terminal of amplifier 100b, and capacitor 7 arranged on connection path 92 is connected between the inverting output terminal of amplifier 100a and the inverting input terminal of amplifier 100b. Between amplifier 100b and amplifier 100c, capacitor 7 arranged on connection path 91 is connected between the non-inverting output terminal of amplifier 100b and the non-inverting input terminal of amplifier 100c, and capacitor 7 arranged on connection path 92 is connected between the inverting output terminal of amplifier 100a and the inverting input terminal of amplifier 100b. Furthermore, between amplifier 100c and comparator Cmp, capacitor 7 arranged on connection path 9a is connected between the non-inverting output terminal of amplifier 100c and the non-inverting input terminal of comparator Cmp, and capacitor 7 arranged on connection path 9b is connected between the inverting output terminal of amplifier 100c and the inverting input terminal of comparator Cmp.

[0080] One end of each switch 8 is connected to the midpoint potential VCM. The other end of each switch 8, which is connected to one end of each capacitor 7, is also connected to an input terminal of the amplifier 100b, an input terminal of the amplifier 100c, or an input terminal of the comparator Cmp. In the multi-stage amplifier 200, all of the switches 8 are collectively switched between an open state and a closed state. Each switch 8 may be a semiconductor switch such as an FET, or may be any type of relay such as an electromagnetic relay. Any element capable of switching the internal conduction state can be used for each switch 8.

[0081] The operation of multistage amplifier 200 including capacitor 7 and switch 8 will be described with reference to FIG. 7 as well. Representing the output voltages and input voltages of each amplifier in FIG. 6, FIG. 7 schematically shows the changes in the non-inverting output voltage Vop2 and the inverting output voltage Vom2 of amplifier 100b, and the non-inverting input voltage Vip3 and the inverting input voltage Vim3 of amplifier 100c. While the output voltages of amplifier 100a, the input voltages of amplifier 100b, and the output voltages of amplifier 100c, which are not shown in FIG. 7, may differ in amplitude, their timing is similar to that of the output voltages or input voltages shown in FIG. 7.

[0082] FIG. 7 further shows the state CAP of the capacitor 7 and the state SW of the switch 8. In FIG. 7, a high level of the state SW of the switch 8 indicates that all switches 8 are in a closed state (on state), and a low level indicates that all switches 8 are in an open state (off state). The hatching with diagonal lines in the CAP of the capacitor 7 shown in FIG. 7 indicates that the capacitor 7 is charged or discharged by the potential difference between both ends of the capacitor 7, thereby storing a charge corresponding to the potential difference between both ends. The hatching with dots in the CAP of FIG. 7 indicates that the capacitor 7 retains the charge that it has already stored. Note that the "charge corresponding to" the potential difference between both ends of the capacitor 7 is an amount of charge expressed as (the potential difference between both ends of the capacitor 7) x (the capacitance value of the capacitor 7). While the capacitor 7 is charged or discharged by the potential difference between both ends, the potential difference between both ends of the capacitor 7 is sampled by the capacitor 7 by storing or discharging charge in the capacitor 7 so that the amount of charge stored remains an amount corresponding to the potential difference between both ends.

[0083] As shown in FIG. 7, before an amplification operation is performed in period P2, switch 8 is closed in period P1. As shown in FIG. 7, a midpoint potential VCM is applied to each input voltage of amplifier 100c. The midpoint potential VCM is also applied to one end of capacitor 7 connected to switch 8. During period P1, switch 8 connected to each input terminal of amplifier 100b is also closed, so ideally, the midpoint potential VCM is output from each output terminal of amplifier 100b. However, if amplifier 100b has an offset voltage Vofs with respect to the midpoint potential VCM, then each output terminal of amplifier 100b outputs a non-inverted output voltage Vop and an inverted output voltage Vom that are shifted from the midpoint potential VCM by Vofs (VCM + Vofs). (For simplicity, it is assumed that the offset voltage of the non-inverted output voltage Vop and the offset voltage of the inverted output voltage Vom are the same, Vofs.) That is, when the switch 8 is closed, a potential difference substantially equal to the offset voltage Vofs is applied across the capacitor 7, and a charge corresponding to the offset voltage Vofs of the amplifier 100b is accumulated in the capacitor 7.

[0084] Then, after the end of period P1 of an arbitrary length, when the transition to period P2 begins, all switches 8 are controlled to the open state (OFF state), and each amplifier amplifies the input voltage. Meanwhile, capacitor 7, to which midpoint potential VCM is no longer applied, continues to hold across its terminals the offset voltage Vofs sampled during period P1. During period P2, amplifier 100b outputs a non-inverting output voltage Vop2 and an inverting output voltage Vom2 superimposed with the offset voltage Vofs, as shown in FIG. 7. However, because capacitor 7 holds the offset voltage Vofs sampled during period P1 across its terminals as described above, the offset voltage Vofs superimposed on the non-inverting output voltage Vop2 and the inverting output voltage Vom2 is canceled by capacitor 7. Therefore, as shown in FIG. 7, amplifier 100c receives the non-inverting input voltage Vip3 and the inverting input voltage Vim3, from which the offset voltage Vofs has been eliminated. That is, an auto-zero effect is achieved for the offset voltage of amplifier 100b. A similar effect is achieved for amplifier 100c.

[0085] 7, the charge stored in capacitor 7 during period P1 is held for period P3 after the end of period P2. However, because there is a possibility that charge may be released from capacitor 7 due to leakage current or the like, it is preferable to charge or discharge capacitor 7 again during period P1 before the next period P2 in which an amplification operation is performed so as to accumulate a charge corresponding to offset voltage Vofs. Therefore, it is preferable that switch 8 be capable of repeatedly switching between its open and closed states. For example, the open and closed states of switch 8 may be configured to be repeatedly switched at any timing by a controller (not shown), such as a microcomputer.

[0086] In a high-speed amplifier, it is preferable to reduce the size of each FET, such as FET 11 and FET 12 in FIG. 1, in order to reduce the parasitic capacitance of each FET. However, amplifiers including such small FETs tend to have a relatively large offset voltage as a trade-off for high-speed operation. Therefore, in a multistage amplifier such as multistage amplifier 200 shown in FIG. 6, it is particularly beneficial to cancel the offset voltage of each amplifier using the auto-zero function. [Explanation of symbols]

[0087] 100, 101 Amplifier circuit 100a~100c amplifier 200 Multi-stage amplifier 1 First input differential pair 11 First MOSFET 12 Second MOSFET 2 Second input differential pair 23 Third MOSFET 24 4th MOSFET 31 1st load 31a MOSFET forming the first load 32 2nd load 32a MOSFET forming the second load 33 Third load 33a MOSFET forming the third load 34 4th load 34a MOSFET forming the fourth load 41 first switching element 41a MOSFET constituting the first switching element 42 second switching element 42a MOSFET constituting the second switching element 7 Capacitors 8 Switch 91, 92 Amplifier connection paths VCM midpoint potential VDD High power supply potential VSS Low power supply potential

Claims

1. a first input differential pair configured to be capable of differentially amplifying a signal by a first MOSFET and a second MOSFET, both of which are of a first conductivity type; a first load configured with a diode-connected MOSFET and connected to the first MOSFET; a second load configured with a diode-connected MOSFET and connected to the second MOSFET; An amplifier circuit comprising: The amplifier circuit further comprises: a second input differential pair configured to be capable of differentially amplifying a signal by a third MOSFET and a fourth MOSFET, both of the first conductivity type; a third load connected to the drain of the third MOSFET; a fourth load connected to the drain of the fourth MOSFET; a first switching element connected in parallel to the first load; a second switching element connected in parallel to the second load; Equipped with the gate of the first MOSFET and the gate of the third MOSFET are connected together; the gate of the second MOSFET and the gate of the fourth MOSFET are connected together; the first switching element is configured to transition to a conductive state as the drain-source voltage of the first MOSFET increases; the second switching element is configured to transition to a conductive state as the drain-source voltage of the second MOSFET increases.

2. the first switching element is configured to transition to a conductive state in response to a drop in the potential of the drain of the fourth MOSFET; 2. The amplifier circuit according to claim 1, wherein the second switching element is configured to transition to a conductive state in response to a drop in the potential of the drain of the third MOSFET.

3. the first switching element is configured to transition to a conductive state in response to an increase in the potential of the drain of the fourth MOSFET; 2. The amplifier circuit according to claim 1, wherein the second switching element is configured to transition to a conductive state in response to an increase in the potential of the drain of the third MOSFET.

4. the first switching element and the second switching element are configured by MOSFETs of a conductivity type different from the first conductivity type, a gate of the MOSFET constituting the first switching element is connected to the drain of the fourth MOSFET; 2. The amplifier circuit according to claim 1, wherein the gate of the MOSFET constituting the second switching element is connected to the drain of the third MOSFET.

5. the third load and the fourth load are each configured by a diode-connected MOSFET having a conductivity type different from the first conductivity type, a gate of the MOSFET constituting the first switching element and a gate of the MOSFET constituting the fourth load are connected to each other; 5. The amplifier circuit according to claim 4, wherein the gate of the MOSFET constituting the second switching element is connected to the gate of the MOSFET constituting the third load.

6. 6. The amplifier circuit according to claim 5, wherein the size of the FET constituting the first switching element and the size of the MOSFET constituting the second switching element are both larger than the size of the MOSFET constituting the first load and larger than the size of the MOSFET constituting the second load.

7. A multi-stage amplifier including a plurality of amplifiers connected in cascade, A multistage amplifier, wherein at least one of the plurality of amplifiers is configured by the amplifier circuit according to any one of claims 1 to 6.

8. a capacitor disposed in a connection path between each of the plurality of amplifiers; a switch connected between a midpoint potential of the power supply voltages of the plurality of amplifiers and one end of the capacitor; the one end of the capacitor is connected to an input terminal of an amplifier at a subsequent stage of the connection path, and the other end opposite to the one end is connected to an output terminal of an amplifier at a previous stage of the connection path, 8. The multistage amplifier according to claim 7, wherein when said switch is closed, a charge corresponding to an offset voltage of said preceding amplifier is stored in said capacitor.

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