FinFET TRANSISTOR, METHOD OF PRODUCING FinFET TRANSISTOR, AND REINFORCED THIN-FILM DEVICE

Abstract

To provide a reinforced thin-film device which has higher crystalline quality for epitaxial growth, with a size above 4 inches in high-mobility semiconductor material.SOLUTION: A reinforced thin-film device (100) includes: a substrate (101) for supporting an epitaxial layer; a mask layer (103) patterned with a plurality of nanosize cavities (102) disposed on the substrate to form a needle pad; and a thin film (105) of lattice-mismatched semiconductor disposed on the mask layer, where the thin film comprises a plurality of parallel-spaced semiconductor needles (104) of the lattice-mismatched semiconductor embedded in the thin film, where the semiconductor needles are substantially vertically disposed in the axial direction toward the substrate in the nanosize cavities of the mask layer, and where a lattice-mismatched semiconductor epilayer (106) is provided on the thin film supported by the epilayer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Priority claim This patent application claims priority to Swedish Patent Application No. 183014, filed April 22, 2018, which is incorporated herein in its entirety.

[0002] The present invention relates generally to the surface preparation of silicon wafers and devices for heterogeneous integration of III-V materials on silicon. [Background technology]

[0003] Moore's Law predicts that the number of transistors on a chip will grow exponentially, doubling the number of transistors every 24 months. However, this creates a problem when electronics are scaled down to the nanoscale. The scaling down of electronics has been ongoing since the early 1970s. The miniaturization of transistors has increased performance per cost, leading to exponential growth in the semiconductor market. This has led to continued investment in semiconductor technology, driving further miniaturization of electronics. The semiconductor industry faces the challenge of replacing silicon-based CMOS to continue improving performance. The shrinking of silicon transistors will eventually reach its limits.

[0004] A unique feature of silicon-based field-effect transistors (MOSFETs) is that their performance improves as their dimensions decrease. Advances in process techniques have reduced the size of field-effect transistors, resulting in an exponential increase in performance with transistor density. Modern logic circuits are based on transistors with complementary characteristics. These are called n-type and p-type MOSFETs (or simply NMOS and PMOS transistors). The driving force behind scaling is the ever-shortening of the electrode and n- and p-channel lengths. CMOS circuits use PMOS and NMOS transistors, which have enabled the fabrication of very dense integrated circuits.

[0005] Recent scaling of MOSFETs has led to heat dissipation of approximately 100W / cm 2 Because of this, they are at the limit of scaling in terms of power. Power density cannot be increased further without incurring intensive packaging and cooling costs, making these chips impractical for most applications. While silicon's ability to form native oxides has been particularly useful in integrated circuits, high-k oxides are being valued for compound semiconductors. In particular, it is the geometric shrinking of CMOS transistors that has made modern computers possible. Continuing development in electronics requires new solutions for implementing novel types of semiconductor materials on inexpensive silicon wafers.

[0006] Attention has focused on a group of materials suitable for improving the performance of CMOS transistors, known as III-V semiconductors. These semiconductors combine elements from groups III and V of the periodic table and are attractive because they possess electronic properties many times superior to those of silicon. Semiconductor materials such as germanium and graphene are also attractive alternatives for the fabrication of electronic components. Their excellent electron transport properties could make them crucial for the development of nanoelectronics. III-V semiconductors such as GaAs, InAs, and InP, as well as their ternary and quaternary alloys, combine elements from columns III and V of the periodic table. To achieve competitive III-V CMOS technology, these materials must be fabricated on a silicon platform very similar to Si-CMOS, requiring co-integration of III-V semiconductors with germanium or with separate III-V semiconductors on silicon. However, fabricating high-quality channel materials on silicon substrates is extremely challenging, especially for III-V semiconductors. Current III-V CMOS technology for continued integrated circuit fabrication is a leading candidate for future CMOS. The future role of current CMOS technology in future CMOS technologies is outlined in the International Technology Roadmap for Semiconductors (ITRS). Generally, around the 10-14 nm node, alternative channel materials will be required to achieve the performance targets set out in the International Technology Roadmap for Semiconductors (ITRS).

[0007] However, the possibility of combining III-V materials as alloys is of primary interest due to their properties, which allow them to be epitaxially grown in various heterostructures with different bandgaps for electronics using gas-phase chemical processes. III-V materials can be epitaxially fabricated by vapor deposition from pyrolyzed precursor molecules of group III and group V elements. However, these materials cannot be grown on just any surface; to achieve high crystal quality, crystal planes of the materials with equal or similar lattice constants must be prepared. Heterostructures within AlGaInAs alloys, such as InGaAs / GaAs / InGaAs and GaN / InGaN / GaN structures, form quantum wells, respectively, enabling the recombination of charge carriers (electrons and holes) for photonic components. Therefore, III-V semiconductors are of great interest not only for photonic applications such as lasers and LEDs, but also due to the direct transitions in III-V materials. These semiconductor materials are also of interest for the fabrication of semiconductor components due to their extremely high mobility in high frequency electronics, ballistic electron transport in 1D nanostructures, and charge carrier trapping in 0D and 1D nanostructures for quantum electronics, respectively. Some III-V semiconductors, such as indium antimonide, have very high mobilities for negative charge carriers, while others, such as germanium, have very high mobilities for positive charge carriers. III-V semiconductor materials enable photonic applications integrated on silicon wafers. Graphene has an electron mobility of 200,000 cm 2 V -1 s -1 , silicon is about 1,400 cm 2 V -1 s -1 , indium antimonide is approximately 77,000 cm 2 V -1 s -1Although graphene has excellent electron mobility, its low hole mobility makes it unsuitable for CMOS electronics. In CMOS electronics, high electron mobility alone is not enough, but graphene has a hole mobility of 1,900 cm 2 V -1 s -1 Second only to germanium with an electron mobility of 850 cm 2 V -1 s -1 InSb has the highest mobility of positive charge carriers for p-doped and n-doped channel materials. One of the most important issues in realizing III-V CMOS is heterogeneous integration on a silicon platform.

[0008] For III-V compound semiconductors to become an alternative technology for integrated circuits, corresponding drivers such as Si-based CMOS are required. The process flow for III-V MOSFETs must be similar to that of silicon-based CMOS technology. Also, co-integration of different III-V semiconductors on industrially usable wafers with a diameter of 8 to 12 inches is required. To date, single III-V compound semiconductors on silicon have been demonstrated. Although thick buffer layers have been used in demo components, commercial co-integration requires thin buffer layers of less than 400 nm.

[0009] In the paper "J.A. del Alamo et al., III-V CMOS: the key to sub-10 nm electronics?, Microsystems Technology Laboratories, MIT, 2011 MRS Spring Meeting and Exhibition Symposium P: Interface Engineering for Post-CMOS Emerging Channel Materials," it is stated that the power density of CMOS is about 100W / cm. 2The paper also describes the challenges of co-integrating III-V heterostructures on large-area wafers, such as silicon wafers, which have thin buffer layers and low defect densities. In particular, the paper describes the problems encountered when co-integrating islands of two different thin-film structures side by side. One of the crucial factors is the large difference in the lattice constants of the materials.

[0010] The paper "J.A. del Alamo et al., The prospects for 10 nm III-V CMOS, Microsystems Technology Laboratories, MIT, Rm. 39-567, Cambridge, MA 02139, USA" describes the challenges inherent in the need to integrate two different materials very closely together on a silicon wafer, depending on the candidate p-channel material.

[0011] The problem, described in the document "International Technology Roadmap for Semiconductors 2009 Edition Emerging Research Materials," is the use of semiconductors other than silicon, such as III-V semiconductors, which have low electron mobility but low hole mobility. Germanium has high hole mobility, but its electron mobility is not as high as that of III-V compound semiconductors. Another problem is achieving high-mobility n-channel and p-channel transistors in co-integrated transistors using different channel materials to take advantage of the high mobility of the respective charge carriers. Another problem is the selective growth of alternative transistor channel materials at desired locations on a silicon wafer, with controllable location and orientation.

[0012] The paper "International Technology Roadmap for Semiconductors 2011 Edition Emerging Research Materials" lists the challenges as of 2011, projected for the period from 2018 to 2026. Of particular interest is the invention of new CMOS technologies that can replace conventional CMOS technologies. According to Moore's Law and the ITRS, transistors are expected to shrink to 10 nm in 2017, 7 nm in 2019, 5 nm in 2020, and 3 nm in 2023. In particular, the paper notes that the co-integration of III-V semiconductors for CMOS with germanium is challenging. Even if integration is achieved, defect control and doping control are required, further complicating the problem. Furthermore, activation of dopant atoms in germanium requires high process temperatures for n-doping, whereas doping activation of III-V materials can be performed at low temperatures. These two competing requirements may require fabrication of the germanium component prior to growth of the III-V material, further complicating the integration of III-V materials with germanium.

[0013] In particular, the paper notes that the co-integration of III-V semiconductors for CMOS with germanium is difficult, but even if integration is achieved, the need for defect control and doping control further complicates the problem. Furthermore, activation of dopant atoms in germanium requires high process temperatures for n-doping, whereas doping activation of III-V materials can be performed at low temperatures. These two competing requirements may require fabrication of germanium components before growth of III-V materials, further complicating the integration of III-V materials with germanium.

[0014] In his doctoral dissertation, "High-Performance III-V PMOSFET," A. Nainani (2011) notes that III-V materials have long been sought for use as transistor channels in high-performance transistor components at low voltages, as scaling of silicon CMOS technology has only provided limited benefits. The paper also notes that the biggest challenge for III-V field-effect transistors for post-silicon CMOS applications is heterogeneous integration of III-V materials with the silicon platform. Another challenge is integrating p-type components, including germanium, as the p-MOSFET channel with n-type III-V MOSFETs.

[0015] In the paper "Nature 479.7373 (2011): 317-323," J.A. Del Alamo et al., "Nanometre-scale electronics with III-V compound semiconductors," they state that the greatest challenge for post-Si CMOS is preparing a substrate on which NMOS and PMOS transistors can be fabricated side-by-side. Specifically, they state that integrating NMOS and PMOS transistors on silicon is a problem that must be solved to realize III-V CMOS. The greatest possible advancement required is the side-by-side integration of III-V NMOS and III-V PMOS transistors on a silicon substrate. Technology budgets dictate the use of primarily silicon wafers to achieve Moore's Law cost structures. Buffer layers must be thin for economic reasons, such as short epitaxial growth times, but also for thermal reasons, such as heat dissipation. The growth rate of epilayers for III-V semiconductors and their alloys is approximately 1–2 μm / h. The buffer layer for III-V semiconductors on silicon is approximately 1.5 μm thick. The biggest challenge for III-V CMOS is to fabricate a hybrid substrate for NMOS and PMOS transistors, in which islands of two different materials with different lattice constants are formed side-by-side on a flat surface. The paper states that this is an important issue, but one that has not received enough attention.

[0016] To produce cheaper gallium nitride substrates, buffer layers have been fabricated on silicon, followed by thin film growth using graded alloys of semiconductor materials ranging from aluminum nitride to gallium nitride. This is done to fabricate gallium nitride-based materials, particularly electrical components for planar LEDs, by using a two-dimensional electron gas to form planar GaN / InGaN / GaN quantum wells defined by thin layers of InGaN, typically about 1-5 nm thick. The lattice constants of III-V semiconductors make it difficult to fabricate thin films of III-V materials on silicon without cracking during fabrication on large wafers.

[0017] A further development of silicon CMOS technology is the so-called silicon FinFET technology, which uses anisotropically etched silicon semiconductors with multiple gate contacts between the source and drain. The difficulty in scaling planar CMOS is maintaining acceptable gate control of the current through the transistor. FinCMOSFETs have the advantage that horizontally elongated structures can be very easily coated with contacts that provide favorable electrostatic control of the current through the transistor. However, one of the challenges of FinFETs is the high resistance resulting from the narrow bandgap semiconductors. Furthermore, FinFET technology is limited by top-down processing techniques at transistor nodes below 10 nm.

[0018] Aside from their exceptional electronic properties, III-V semiconductors and materials like graphene are difficult to fabricate on large silicon wafers. For III-V semiconductors, this is particularly true because they are lattice-mismatched semiconductors, meaning that the lattice constants in the atomic crystal lattice are significantly different from those of silicon. This creates stress in the silicon wafer, resulting in bending and micro-fractures. Coating pure gallium nitride (a lattice-mismatched semiconductor) on silicon makes the silicon wafer prone to cracking. The previously mentioned method for coating silicon with gallium nitride involves growing a buffer layer using a complex process in which the silicon wafer is coated with multiple alloys of aluminum gallium nitride, with various doping and aluminum gallium nitride alloys used to ensure uniform stress in the buffer layer. This process is difficult to scale to large silicon wafers of various volumes, particularly because it requires optimization for each device and silicon wafer. Furthermore, the large number of layers required for the aluminum gallium nitride alloy epilayer results in long process times, making large-scale production prohibitively expensive.

[0019] LED manufacturers grow III-nitride semiconductors on sapphire substrates, but sapphire substrates are prohibitively expensive, costing approximately $400 for a 6-inch wafer. Silicon electronics manufacturers are facing the next challenge of switching to III-V materials to improve the performance of integrated circuits, which today require III-V solid semiconductor wafers with thicknesses of 200 to 300 micrometers. According to the International Technology Roadmap for Semiconductors (ITRS), there are currently no readily available products for disk products larger than the 2-inch III-V semiconductors required by the semiconductor industry.

[0020] One way to mitigate the aforementioned problems is to use lateral overgrowth of III-V materials. Such a solution is described, inter alia, in U.S. Patent Application Publication No. 2010 / 0072513, in which a semiconductor material is coated onto a crystalline substrate having a first semiconductor material and a mask disposed on the surface of the crystalline substrate. The semiconductor material includes a crystalline overgrowth of a second semiconductor material that fills openings and covers the mask, thereby reducing dislocations. A drawback of such a solution is that III-V materials are brittle, and the combination of two different lattice-mismatched semiconductor materials, or a III-V material with germanium, or other combinations of materials with different lattice constants on the same crystalline substrate, can lead to wafer cracking, especially for larger wafer diameters, e.g., 4-12 inches.

[0021] U.S. Patent No. 7,250,359 describes a method for introducing tension into a wafer when integrating germanium on silicon. The same specification further discloses a method for growing III-V materials on silicon by etching a V-shaped recess in the silicon, followed by epitaxial lattice-mismatched growth of the III-V materials on the silicon. The purpose is to limit the size of the GaN substrate due to the stress in the material. Furthermore, the thickness of the GaN film can affect the wavelength shift of light emitted from GaN-based optical components. Typically, GaN epilayers crack due to stress and strain in the crystal structure. The drawback of this method is that a lot of stress remains in the material due to the lattice mismatch, which limits the size of the epitaxial substrate for lattice-mismatched semiconductors.

[0022] U.S. Patent No. 9,379,204 describes a method for etching a wafer of III-V material and refilling it with III-V material to provide a dislocation-free III-V semiconductor. The drawback of this method is that the lattice mismatch causes a lot of residual tension in the material. Furthermore, the mechanical performance of the wafer is not sufficient for the purpose of co-integrating a wide variety of III-V materials, which results in different stresses in the wafer over a large area of ​​more than 2 inches.

[0023] One method for forming FinFET components with associated III-V materials on a silicon substrate is described in U.S. Patent Application Publication No. 2014 / 0264607. According to this solution, a non-silicon-based semiconductor is grown in a trench having a length-to-thickness ratio, forming a lattice-mismatched semiconductor material in the trench. Also described is a method for doping various portions of the semiconductor fin to form source and drain contacts to the semiconductor fin. A drawback of this method is that the lattice-mismatched growth of the semiconductor fin on the silicon substrate leaves the wafer brittle. A major problem is that the lattice constant of III-V semiconductors makes it difficult to fabricate thin films of III-V materials on silicon, and large wafer substrates can crack during fabrication. In particular, dislocations can propagate through the semiconductor fin.

[0024] Wang et al., Small, 13, 2017, 1700929, describes a method for synthesizing graphene by CVD using a germanium epilayer as a catalyst. A 200-nm-thick germanium film was sputtered onto a highly doped p-Si wafer with a 300-nm SiOx oxide layer. It is particularly desirable to form graphene to avoid metal contamination. Under vacuum, a mixture of 23 sccm hydrogen and 230 sccm argon was introduced to atmospheric pressure. Without changing the gas flow, the germanium epilayer was heated to near its melting point of 900–930°C. Methane gas was added to the reactor at 0.7 sccm for 60–360 minutes. A drawback of this method for producing a germanium layer to catalyze graphene growth is that the sputtering process results in poor crystalline quality for quantum electronic components, including graphene.

[0025] In summary, problems exist with known methods for fabricating III-V and other materials on silicon. One problem is that defects in thin III-V films on silicon wafers larger than 6 inches using known buffer layer techniques preclude fabrication of thin buffer layers as thin as 50-100 nm on III-V semiconductors on silicon for electronic components.

[0026] Another problem is the thick III-V thin films on silicon, which can improve the crystal quality to a limited extent, but this leads to other photonic problems such as wavelength shift due to the thick buffer layer on silicon and poor heat dissipation due to the power density of III-V CMOS, which can be improved by thinning the epilayer of the III-V semiconductor on silicon. Summary of the Invention

[0027] Accordingly, embodiments of the present invention seek to mitigate, alleviate or eliminate one or more of the defects, drawbacks or problems in the art as mentioned above, singly or in any combination, by preferably providing a reinforced thin film in accordance with the appended claims.

[0028] It is emphasized that as used in this specification, the term "comprises" is used to specify the presence of stated features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

[0029] The object of the present invention is to provide reinforced wafers with higher crystalline quality for epitaxial growth than wafers currently producible in sizes greater than 4 inches in large scale, high mobility semiconductor materials using conventional techniques or buffer layers for electronic components.

[0030] A further object of the present invention is to provide silicon wafers that are free of the cracks caused by the growth of III-V semiconductor materials that cause current silicon wafers to warp. Industrial applications also require wafers to be compatible with robotic handling, such as those used in equipment for 6- to 12-inch wafers, so that a robotic arm (which uses vacuum suction to access the wafer) can move the wafer into and out of the process chamber. This makes it cheaper to manufacture high-performance electronic components based solely on the higher charge carrier mobility of silicon, while silicon wafers can serve as a platform for many processes designed for specific industrial-scale wafer dimensions, such as 2-inch, 4-inch, 6-inch, 8-inch, and 12-inch wafers. It also enables the epitaxial fabrication of integrated circuits for post-silicon CMOS components, as well as integrated nanoelectronics and photonics on silicon wafers, with extremely high precision.

[0031] It is another object of the present invention to provide the silicon wafers described herein as a means for building quantum computing devices on the wafers.

[0032] The above mentioned objects are achieved by a thin film device according to the attached independent claims, with particular embodiments being set out in the dependent claims.The present invention therefore aims to provide a high strength thin film alternative to large scale III-V semiconductor wafers, thereby enabling the controlled growth of III-V semiconductor epilayers (or graphene) on silicon to create functional electrical components.

[0033] Another objective of the present invention is to integrate various high-mobility semiconductors onto a silicon platform for post-silicon CMOS components. Such co-integration has been documented as extremely difficult and is considered a major challenge for III-V CMOS. Another objective of the present invention is to provide a means for VLSI III-V CMOS to align and control the size of epitaxial layers as multiple islands of different semiconductor materials side-by-side on a wafer. To achieve the goals set out in the International Technology Roadmap for Semiconductors (ITRS), it is necessary to co-integrate islands of two semiconductor materials with different lattice constants on a silicon wafer. A further objective of the present invention is to provide a means for post-silicon CMOS nanoelectronics platforms beyond the sub-10 nm transistor node, which are difficult to fabricate using top-down processing approaches for quantum computers.

[0034] A first aspect of the present invention is a reinforced thin-film device comprising: a substrate having an upper surface for supporting an epilayer; a mask layer patterned with a plurality of nano-sized cavities disposed on the substrate to form needle pads; and a thin film of a lattice-mismatched semiconductor disposed on the mask layer, the thin film comprising a plurality of parallel-spaced semiconductor needles of the lattice-mismatched semiconductor embedded therein, the plurality of semiconductor needles being disposed within the plurality of nano-sized cavities of the mask layer and axially substantially perpendicular to the substrate; a lattice-mismatched semiconductor epilayer provided on the thin film supported by the lattice-mismatched semiconductor epilayer; and preferably the substrate is a silicon wafer having a diameter of more than 2 inches. Further embodiments of the present invention are defined in the dependent claims, and features of the second and subsequent aspects of the present invention may be used mutatis mutandis for the first aspect.

[0035] Simply put, the reinforcement provided by the thin film is vertical reinforcement due to the semiconductor needles embedded in the thin film. Semiconductor needles made of III-V materials with diameters of 5-10 nm have significantly better strength properties compared to bulk semiconductor materials. The reinforcement allows elastic deformation of these semiconductor needles and prevents dislocation propagation. The pattern of how the needles are embedded in the close-packed thin film also contributes to the reinforcement.

[0036] The first advantage of the reinforced thin film device is that the bulk of the III-V semiconductor growth of the semiconductor needles on silicon is grown at up to 30 μm / h, compared to 1 μm / h for conventional thick buffer layers on silicon. The shorter initial growth time for the nanowires significantly reduces the overall growth time for the III-V semiconductor thin film, allowing for the formation of sub-100 nm thin films with higher crystalline quality than micrometer-thick buffer layers.

[0037] An additional benefit is that reinforced thin-film devices enable III-V semiconductor wafers with diameters of 6 to 12 inches without dislocation propagation due to lattice strain. The nanoscale, densely packed reinforcements limit dislocation propagation, thereby preventing cracking and breaking of the silicon wafer into multiple pieces. Furthermore, for homoepitaxial crystal growth of two distinct high-mobility p-type and n-type channels, the densely packed nanowires embedded in the thin film reduce the number of dislocations that can propagate, improving the crystal quality of the transistor channels.

[0038] Another advantage is that thin films can be grown on silicon substrates to heights on the order of billionths of a meter, thereby replacing large 250-1,000 μm thick solid wafers of the same material. Currently used III-V semiconductor wafers are based on group III and group V precursors, which have limited abundance. Silicon, an extremely abundant element that can be extracted from sand, is substituted for the relatively rare group III and group V precursors.

[0039] Another advantage is that the thin films do not need to be grown heteroepitaxially or on substrates with a suitable crystal orientation, such as (111) planar silicon wafers.

[0040] Another advantage is that there is no need to contaminate the MOCVD chamber with aluminum for GaN growth.

[0041] Another advantage is that reinforced thin-film devices enable the growth of graphene islands on germanium-on-silicon substrates, i.e., with graphene, the semiconductor material with the highest electron mobility to date.

[0042] Another advantage is that heat generated by the CMOS transistors can be effectively dissipated through the thin epi layers of the thin-film device.

[0043] Another advantage is that by controlling the positioning of the nanowires at specific locations on the silicon wafer, it is possible to grow islands of different III-V and germanium layers side by side for planar NMOS and PMOS transistors on the reinforced wafer.

[0044] Another advantage is that activation of the dopant atoms for the germanium islands can be done prior to the growth of the III-V islands.

[0045] Another advantage is the ability to control the location of the epitaxial islands and their growth for VLSI III-V / III-V fin CMOS TFETs.

[0046] Another advantage is the ability to define thin intrinsic epi layers for PMOS and NMOS pin tunneling transistors on the reinforced wafer, which means that scaling of III-V finFETs to sub-7nm nodes becomes possible.

[0047] Another advantage is that epilayers of indium antimonide can be fabricated on silicon wafers to produce epitaxially grown nanostructures for topological quantum computers on silicon wafers.

[0048] The present invention, together with further objects, advantages, embodiments and features thereof, may best be understood by referring to the following description and the accompanying drawings, in which: [Brief explanation of the drawings]

[0049] [Figure 1] FIG. 1 shows a reinforced thin film device 100. [Figure 2] FIG. 2 shows an embodiment 200 of a reinforced thin film device in which a plurality of parallel, spaced apart supported semiconductor nanoneedles 204 are arranged in a hexagonal close-packed configuration. [Figure 3] FIG. 3 illustrates an embodiment of a reinforced thin film device 300 in which an epilayer is formed consisting of individual islands of a first lattice-mismatched semiconductor 315a and a second lattice-mismatched semiconductor 315b. [Figure 4] FIG. 4 is a schematic diagram showing a fin semiconductor device structure 420 on an epi layer 406. [Figure 5A] FIG. 4 is a schematic diagram showing a fin semiconductor device structure 420 on an epilayer island 405 with a surrounding gate electrode 424. [Figure 5B] FIG. 1 is a schematic diagram showing two epilayer islands 415a and 415b in InGaAs and Ge. [Figure 6] FIG. 4 is a three-dimensional view of a thin film device 400 with thin film islands 1515 in InGaAs and thin film 415b in germanium. [Figure 7] FIG. 1 illustrates one embodiment of the present invention for a process 1000 for growing a silicon wafer with an epilayer of GaN. [Figure 8] FIG. 1 is a schematic diagram illustrating the co-integration of high charge carrier mobility III-V semiconductors, III-V semiconductors, and III-V epilayers. [Figure 9]FIG. 9 is a schematic diagram similar to FIG. 8 showing the co-integration of two III-V epilayer islands. [Figure 10] FIG. 6 shows that a thin film 605 can be placed on germanium 605 with an epilayer 606 of graphene. [Figure 11] 11 is a graphene monolayer viewed from above according to the embodiment of FIG. 10. [Figure 12A] FIG. 12C is a schematic diagram of a hybrid III-V CMOSFET system (700′) combined with FIG. 12B. [Figure 12B] FIG. 7 is a schematic top view illustrating two III-V FinFETs electrically coupled as a III-V / III-V CMOS inverter based on the co-integration of two epilayer islands 715a, 715b with protruding epitaxial semiconductor fins. [Figure 13] 8 is a schematic side view showing a cross section of an epilayer 806 containing a heterostructure (841, 842) of III-V semiconductors with p- and n-doping, respectively, forming a pn junction in the nanowire radial direction. [Figure 14] 9 is a schematic side view showing a cross section of an epitaxial layer 906 including a heterostructure (941, 942, 943) of III-V semiconductors with different bandgaps, with a thin intermediate layer 942 of 1 to 10 nm. [Figure 15] Figure 11 shows an embodiment of a Majorana T-gate 1100 with branches grown on a heterostructure (1150, 1152, 1153, 1154, 1155) with barrier materials of III-V materials (1152, 1154) and nanotrees with superconducting contacts 1156, 1159, 1158. [Figure 16] FIG. 20 illustrates an embodiment 2000 of topological quantum computation as a braid of quantum mechanical wave functions of principal quantum particles, such as pairs of fermions with T-shaped gates having nodes containing three adjacent energy barrier segments. [Figure 17] FIG. 20 shows an embodiment 2000 with an energy diagram for topological quantum operations according to FIG. 16. DETAILED DESCRIPTION OF THE INVENTION

[0050] In the drawings, similar or corresponding features are designated by the same reference numerals. Before describing the present invention in detail, it should be understood that the present invention is not limited to any particular substrate or epilayer embodiment. The present invention is not limited to any three-dimensional embodiment of a transistor channel material unless such spatial limitations are indicated. Furthermore, the present invention is not limited to any particular epitaxially grown semiconductor. As used herein, "lattice-mismatched" and "non-lattice-matched" refer to semiconductors that intentionally have a substantial lattice mismatch with the substrate designated for semiconductor material growth. Hereinafter, "thin film" should be interpreted as an epitaxially grown semiconductor layer less than 100 nm thick. Also, as used herein, "III-V nanoparticles" refers to nanoparticles in the InAlGaN or InGaAsP material systems, and "mask layer" refers to a layer used to prevent epitaxial deposition of semiconductors on a substrate. "Nanotree" refers to a tree portion, which is a branched nanostructure. The terms "semiconductor needle," "nanoneedle," and "nano-sized needle" can be used interchangeably and refer to elongated semiconductor structures with a radius of less than 100 nm. For example, gallium arsenide, a III-V semiconductor, is a lattice-mismatched semiconductor for growing gallium arsenide on a silicon wafer. In other words, gallium arsenide cannot simply be grown on a silicon wafer without introducing stress into the crystal structure. It is understood that the terms used herein are intended to describe specific embodiments only, without any intention of limitation. In addition, the use of the singular forms "one" and "the" herein also includes the plural form unless the context dictates otherwise.

[0051] This specification illustrates basic approaches to the present disclosure, and it will be understood that those skilled in the art may devise various arrangements which, although not explicitly described or shown herein, embody the basic approaches to the present disclosure and are within its scope.

[0052] FIG. 1 illustrates one embodiment of a reinforced thin-film device 100, including a silicon wafer 101 having a top surface supporting an epilayer. A mask layer 103 is patterned with a plurality of nanostructures 102′ disposed on the silicon wafer 101. A thin film of a lattice-mismatched semiconductor 105 is disposed on the mask layer 103, with nanowires embedded in the thin film 105. Within the nano-sized cavities 102 of the mask layer, the nanowires are oriented axially perpendicular and parallel to the substrate. Alternatively, the mask may be configured with a plurality of nano-sized holes having a diameter of 1 to 80 nm, and semiconductor needles 104 of the same thickness may be disposed in the nano-sized holes. The nano-sized holes 102 may be deep holes for growing nanowires along the c-axis of a wurtzite crystal structure. Alternatively, the nanowires may be p-doped and aligned along the c-axis of the wurtzite crystal structure. The mask layer forms needle pads with free-standing nanowires of the same semiconductor material as the epilayer. The silicon wafer 101 is preferably greater than 2 inches in diameter.

[0053] The following describes embodiments and specific embodiments related to FIG. 1. The thin film 105 is reinforced with nanowires 104 by semiconductor growth from semiconductor crystals embedded in nano-sized holes 102 in a mask layer 103. The mask layer 103 prevents crystal growth on the substrate and also acts as a semiconductor particle holder. The nanowires 104 abut against a passivation layer 103, which is used to orient the nanowires relative to the flat surface of the silicon wafer. The lateral overgrowth of the nanowires 104 can be 100-200 nm thick relative to the thickness of the thin film 105. The semiconductor crystals can be designated as III-V semiconductors, and GaN-based semiconductor crystals can be used.

[0054] According to the present invention, nanowires 104 are nucleated from semiconductor nanoparticles in the C-axis direction of the crystal structure. Thus, nanowires 104 can be obtained that have a wurtzite C-plane top surface with M-plane sidewalls along their length. The length of the wurtzite nanowire segments can be, for example, 10-50 nm, and the distance between the nanowires can be, for example, 100-300 nm. According to the present invention, nanowires 104 are nucleated from semiconductor nanoparticles in the C-axis direction of the crystal structure. Thus, nanowires 104 can be obtained that have a wurtzite C-plane top surface with M-plane sidewalls along their length. The length of the wurtzite nanowire segments can be, for example, 10-50 nm, and the distance between the nanowires can be, for example, 100-300 nm. On the wurtzite nanowire segments, zinc blende nanowires can be <0001> From hexagonal close packing of atoms on the crystal plane to zinc blende type <111> The growth involves an abrupt change in the zinc-blende crystal structure, accompanied by a change to cubic close-packing of the crystal planes. High p-doping of the nanowires can be used to facilitate the transition from the original zinc-blende crystal structure to the wurtzite crystal structure, and the small width of the nanowires can also contribute to this transition. A two-dimensional semiconductor layer is grown on top of the zinc-blende nanowires. The wurtzite segments of the nanowires can be grown at low pressure (100 mbar). The synthesis equation for GaN can be written as Ga + NH3 = GaN + 3 / 2H2. The preferred process conditions for growing III-N nanowires from GaN nanoparticles are (TMG) = [10.20] sccm, (NH3) = [10.20] sccm, P = [100, 150] mbar, and T = [1000, 1100] C.On gallium nitride thin films, p-doped GaN epilayers can be grown under the process conditions of (TMG) = [400, 500] sccm, (Mg3N2) = [100, 250] sccm, (NH3) = [900, 100] sccm, P = [100, 250] mbar, and T = [800, 1000] C, while InGaN can be grown under the process conditions of (TEG) = [80, 110] sccm, (TMIn) = [600, 700] sccm. 00] sccm, (NH3) = [900, 1100] sccm, P = [100, 250] mbar, and T = [800, 900] C, and n-doped GaN can be grown under process conditions of (TMG) = [400, 500] sccm, (NH3) = [900, 1100] sccm, P = [100, 250] mbar, and T = [800, 1000] C. Nucleation of wurtzite nanowires 104' can be induced by the mole fraction of p-type dopant elements in the epitaxial process gas flow. Such a reinforcing thin film is preferably grown under the following process conditions: (TMG)=[400,500] sccm, (NH3)=[900,1100] sccm, P=[100,250] mbar, T=[800,1000]C.

[0055] Indium phosphide nanowires can be grown on silicon wafers using gold particle-assisted growth. For wet etching of the gold, gold can be sputtered onto the wafer and lithographically patterned. After nanowire growth, the remaining gold can be removed by wet etching. Nanowire growth occurs by forming a vapor of these elements, which react at the crystal surface. The reaction can be simplified as In(CH3)3(g) + PH3(g) = InP(s) + 3CH4(g). The precursors trimethylindium (TMI), phosphine (PH3), DMZn, and TESn can be used to grow InP nanowires. The total process gas flow rate can be 13.0 liters per minute with hydrogen gas as the carrier gas. The mole fraction of DMZn can be configured for p-doping to grow nanowires with a wurtzite crystal structure. The reactor temperature for III-V nanowire growth can be 420°C, where growth is initiated on a doped sample corresponding to DMZn as the dopant to the reactor by adding TMIn. On top of the InP nanowires, another compound semiconductor is grown by lateral overgrowth to form InP nanowires as needle pads within the thin film. The growth reaction for InAs can be written as In(CH3)3(g) + As3(g) = InAs(s) + 3CH4(g).

[0056] The elongated semiconductor crystals preferably have nanowire 104 segments with a wurtzite crystal structure. The challenges of growing different semiconductor nanowires on silicon substrates are not only due to differences in lattice constants, but also due to the fact that <111> The need for proper crystal orientation of the substrate for the growth of III-V nanowires with a zinc-blende crystal structure in the B direction is also a major challenge. The wurtzite crystal structure of non-nitride semiconductors is not possible with bulk semiconductor growth, but is possible with nanowire growth. Because wurtzite crystals are polar, stacking errors from the wurtzite crystal structure can cause zinc-blende structures to be formed. <111> Nanowires can be grown in a lateral direction, e.g., as lateral overgrowths in bulk gallium arsenide zinc blende or gallium nitride wurtzite thin films, where the nanowires form embedded reinforcements in the thin films and prevent crack and dislocation propagation.

[0057] The nanopores 102, which also serve as nanoparticle holders, may be formed in the range of 5 to 20 nm to grow nanoneedles with a wurtzite crystal structure. In situ p-doping of nanowires 104 can also be used to nucleate III-V semiconductor nanowires with a wurtzite crystal structure. The growth of nanowires 104 is explained by the vapor-liquid-solid (VLS) model and the vapor-solid-solid (VSS) model. The energy barrier for two-dimensional nucleation decreases during doping, allowing nanowires to nucleate at nanoparticle radii much smaller than those of non-p-doped nanowires 104. Thus, the advantage of a p-doped semiconductor core is that nanowires nucleate at radii much smaller than those of the semiconductor particles. As the nanoparticle radius decreases, the driving force for nucleation increases, with a low energy barrier similar to that of the transition state in a chemical reaction. The length of the nanowire depends on the overall growth rate over time.

[0058] According to the present invention, semiconductor particles of different semiconductor materials can be deposited on nanoscale regions 102 of silicon nitride 103 on a silicon wafer. When the process gas for growing each semiconductor on the semiconductor particles is turned on, nanowires grow within the nanoscale holes, with the diameter of the nanowires 104 being determined by the diameter of the nanoscale holes 102. An advantage of this process is that the growth is lattice-adaptive, eliminating the need for catalyst particles to grow nanowires on silicon substrates, for example. This also prevents Ostwald ripening, which typically leads to unequal nanowire lengths. Because of the lattice-matched growth, dislocations are limited to the initial growth phase, and when semiconductor crystals are grown from the nanoscale holes, growth rates of approximately 50 μm / h (0.8 nm / min) improve the crystalline quality of the nanowires and the semiconductor crystals.

[0059] Nanowires are preferably grown at the nanoscale using metalorganic vapor phase epitaxy (MOPVE), a currently commercially available method for growing nanowires. Crystal growth in accordance with the present invention is achieved by supplying vapors of elements that react with the crystal surfaces of semiconductor nanoparticles to nano-sized pores. For nanowire growth, the base flow rate of Group V gases can be in the range of 10-30 sccm.

[0060] The epilayer can be fabricated from C-plane gallium nitride (for dislocation-free gallium nitride grown on silicon wafers), (110) germanium (for graphene grown on silicon wafers), or islands of (110) germanium and III-V semiconductors. Reinforcement of the thin film by vertically arranged nanowires in the epilayer significantly improves the crystalline quality of large semiconductor wafers (4-12 inches in diameter) compared to solid semiconductor wafers or buffer layers on silicon, due to the material strength properties of the nanoneedles. The nanoneedles are preferably fabricated through a process in which lattice-matched semiconductors are grown from nanoparticles of the same semiconductor material. In this way, nanoneedles or nanowires can be grown from nano-sized holes in a mask layer that is inert to the vapor deposition of the semiconductor epilayer. The thin film is thus reinforced by multiple nanowires embedded in the thin film as needle pads. In fact, nanowires 104 made of III-V materials have significantly better strength properties than bulk materials, e.g., Young's bulk modulus increases from about 90 GPa to about 180 GPa in the case of gallium arsenide. Details of the mechanical properties of nanowires are described in Wang et al., Adv. Mater. 2011, 23, 1356-1360, which is incorporated herein by reference.

[0061] The nanowires 104 can be fabricated using metal organic chemical vapor deposition (MOCVD), and the thickness of the holes in the mask for growing the nanowires 104 can be configured to nucleate wurtzite crystal structures having dimensions between 5 and 25 nm for elastic deformation of the nanowires.

[0062] Nanowires 104 can be grown in a close-coupled showerhead MOCVD reactor. In this way, highly reproducible growth of nanowires 104 at defined locations on large wafer surfaces is achieved. III-V semiconductors can be grown by decomposition of precursor molecules reacting with hydride gases. For example, the group III precursor is trimethylindium and the group V precursor is phosphine (PH3).

[0063] The disadvantages of conventional nanowire 104 growth methods compared to the preferred self-assembly method of the present invention are outlined as follows.

[0064] Nanowire growth by aerotaxy utilizes nanowire growth in the gas phase, which <100> Desired crystal orientation for growth and alignment of nanoscale components on silicon substrates <111> Although etching of metal particles can be achieved, for example, by etching gold using reactive ion etching (RIE), this method does not provide a means for co-integrating different high-mobility semiconductors such as InSb and germanium. Lithographic definition of gold for nanowire growth does not provide a route for co-integration of various high-mobility semiconductors. Although epitaxial layers can be fabricated on silicon, the large difference in lattice constants prevents co-integration.

[0065] Nanowire growth by self-assembly of semiconductor nanocrystals within lithographically defined nanosized holes for nanowire growth is a preferred method of nanowire growth according to the present invention. This allows for the side-by-side co-integration of two distinct semiconductor materials via the self-assembly of semiconductor nanocrystals. Single-crystalline semiconductor nanoparticles self-assembled from colloidal suspensions during solvent evaporation and homoepitaxial growth from such semiconductor nanoparticles provide a method for the side-by-side co-integration of two different high-mobility semiconductors as epilayer-shaped islands.

[0066] The thin epitaxial layer is achieved by not compensating for the difference in lattice constant between the epilayer and the nanowire in the direction perpendicular to the substrate 101. The buffer layer mentioned in the prior art requires starting with a substrate with a lattice constant close to that of the desired channel material and repeating the epitaxial growth of a III-V alloy with a lattice constant gradient through multiple epilayers, i.e., strained layer epitaxy, until the lattice constant is sufficiently close to that of the desired channel material. According to the present invention, lattice constant buffering is not required for integration on silicon substrates by homoepitaxially growing the same material as the self-assembled semiconductor nanocrystals.

[0067] The semiconductor nanoparticles are preferably produced by irradiating a pre-grown epitaxial layer on an inert substrate, such as sapphire for gallium nitride crystals, with a femtosecond laser to thermally fuse the epitaxial layer into a plurality of semiconductor nanoparticles. The nanoparticles from which the nanowires grow are preferably aluminum nitride, gallium nitride, gallium arsenide, indium phosphide, indium antimony, or a semiconductor alloy.

[0068] 2 shows a thin film device 200 comprising a plurality of parallel, spaced apart supported semiconductor needles 204 arranged in a hexagonal close-packed configuration. The individual nanowires 204 can be arranged on a substrate at distances of 30-100 nm, forming a densely packed structure of semiconductor needles made from lattice-mismatched semiconductors.

[0069] The co-integration method according to the present invention finds particular utility for CMOS devices and is described below with specific embodiments in conjunction with FIGS. 3-12. The present invention allows precise control of the location of NMOS and PMOS transistors for each type of epitaxial island for VLSI III-V CMOS processing. This method allows for thin epitaxial islands to be realized, allowing for heat dissipation using the PMOS and NMOS transistors in CMOS circuits. The high nanowire growth rate and lateral nanowire overgrowth significantly improve the crystalline quality of the thin two-dimensional epilayer on silicon, preventing dislocation propagation into electronic components in a direction perpendicular to the substrate. Furthermore, because the germanium islands can be processed before the III-V islands are grown, activation of the p-type dopants in the germanium islands can occur independently of the III-V islands. According to the invention, it is preferred to co-integrate epilayer islands on a silicon substrate using germanium for the p-channel and a III-V semiconductor for the n-channel, or one selected from III-V semiconductors with particularly high mobility for positive charge carriers.

[0070] FIG. 3 shows a reinforced thin film device 300 that includes an epilayer consisting of a plurality of individual islands of a first lattice-mismatched semiconductor 315a and a second lattice-mismatched semiconductor 315b.

[0071] Figure 4 is a schematic diagram of a fin semiconductor structure 420 on an epi layer 406. A fin of semiconductor material can be grown from a mask layer, where a fin semiconductor structure less than 10 nm wide and 50-200 nm long can be epitaxially grown.

[0072] FIG. 5A shows a fin semiconductor structure 420 on an epilayer island 405 and a surrounding gate electrode 424.

[0073] In FIG. 5B, the thin-film device 400 has two epilayer islands: 415a in InGaAs and 415b in Ge. Within each epilayer island, there is a fin semiconductor structure 420a in InGaAs and a fin semiconductor structure 420b in Germanium. To compensate for the low hole mobility and match the high electron mobility of the NMOS transistor, it is preferable to configure the PMOS transistor for one-dimensional ballistic hole transport. Thus, the PMOS and NMOS transistors can be configured to include multiple FinFET transistors or multiple vertical nanowire field-effect transistors on top of the two epilayer islands: 415a in InGaAs and 415b in Ge. A three-dimensional view of the thin-film device 400 is shown in FIG. 6, showing the epilayer island 415a in InGaAs and the epilayer island 415b in Germanium.

[0074] The embodiment of the present invention shown in FIG. 7 relates to a process (1000) for reinforcing GaN thin films on silicon, comprising the steps of: providing a substrate (1001) with a mask layer containing at least one nanopore; self-assembling at least one GaN nanoparticle on the substrate (1002) within the at least one nanopore; and growing at least one III-N nanowire having a wurtzite crystal structure from the GaN nanoparticle by epitaxial lateral overgrowth of the GaN nanoparticle in the wurtzite c-axis direction within the nanopore (1003). The GaN nanoparticles self-assemble within the nanopore due to capillary forces from an evaporated suspension of the GaN nanoparticles. The precursor flow rate of ammonia gas may be in the range of 10-30 sccm. The GaN nanoparticles can be self-assembled within the at least one nanopore by neutralizing acidic and alkaline ligands provided on the GaN nanoparticles and the substrate, respectively.

[0075] According to the present invention, it is preferable to co-integrate one or more III-V semiconductors. Such co-integration is shown in FIG. 8 with III-V epilayer 515a of a III-V semiconductor with high positive charge carrier mobility and III-V semiconductor epilayer 515b of a III-V semiconductor with high negative charge carrier (electron) mobility. A protruding epitaxially grown core portion 520 is visible from above, representing ex-situ pnp-doped core portions 520″, 520″, 520″. Mask layer 517 includes epilayer islands 515a, 515b in recesses or large openings where the epilayer is not lattice-matched to the substrate. Also, according to FIG. 9, two III-V epilayer islands can be co-integrated on a silicon substrate.

[0076] The thin film may be disposed on a germanium epilayer 605 on silicon with an epilayer of graphene 606. One such embodiment is shown in FIG.

[0077] In some embodiments, the thin film 605 provided is InAs, InP, GaAs, AlAs, ZnO, ZnS, AlP, GaP, AlP, GaN, AlN, InN, CdSe, or alloys of AlInAs, InGaAs, AlGaAs, GaInP, and AlGaN. The epilayer 606 may be disposed using any of InAs, InP, GaAs, AlAs, ZnO, ZnS, AlP, GaP, GaN, AlN, InN, CdSe, or alloys of AlInAs, InGaAs, AlGaAs, GaInP, and AlGaN. The thin film 605 may be lattice-matched to the epilayer 606. These epilayers may also be islands in certain embodiments.

[0078] In FIG. 10 , a graphene monolayer 606 is supported by a plurality of densely packed nanowires 604 embedded in a thin film 605. The nanowires 604 are arranged by vertical growth from semiconductor nanoparticles 602. A graphene monolayer, such as that shown in FIG. 11 , may also be grown on (110) germanium. Details regarding the fabrication of graphene on germanium surfaces are described in “Lee et al., Science, Apr 18, 2014: Vol. 344, Issue 6181, pp. 286-289,” which is incorporated herein by reference. The advantage of using graphene is primarily to avoid the wrinkles of graphene monolayers on small surfaces of wafers for electrical components such as graphene quantum electronics.

[0079] Figure 12A, in combination with Figure 12B, schematically illustrates a hybrid III-V CMOSFET system (700'). A substrate includes a nanostructured cavity configured to contain a single semiconductor nanoparticle. The nanosized cavity incorporates a semiconductor particle of a high-mobility semiconductor. Two epilayer islands (715a, 715b) with high electron and hole mobility are grown by epitaxially growing islands of semiconductor material. A PMOS transistor (720', 720'', 720''') and an NMOS transistor (720', 720'', 720''') are provided on each epilayer. The PMOS transistor may also be configured for one-dimensional ballistic hole transport to compensate for its low hole mobility and match the high electron mobility of the NMOS transistor. A source contact (724a', 724a''), a drain contact (724c', 724c'') and a gate contact (724b', 724b'') are disposed on each doped portion of the epilayer island.

[0080] Figure 12B shows a schematic top view of two III-V FinFETs electrically coupled as a III-V / III-V CMOS inverter based on the co-integration of two epitaxial islands 715a, 715b with protruding epitaxial semiconductor fins. According to the present invention, it is preferable to thin the channel material in FinFET technology to a one-dimensional semiconductor. In particular, electron transport increases when the radius of the one-dimensional semiconductor is on the order of 7-18 nm.

[0081] The reinforced thin film device 100 may comprise a thin epitaxial III-V epilayer for forming a series of epitaxial islands according to the present invention. A mask layer is deposited on each epitaxial island, and an elongated cavity is opened in the center of each epitaxial island by lithography, such as EBL or nanoimprint lithography, within the mask layer. The mask layer 103 is preferably silicon nitride. Within each elongated cavity, an elongated epitaxial fin semiconductor structure is grown, e.g., 50-100 nm in length. Thus, the elongated cavities preferably have nanostructured widths of approximately 5-50 nm, creating horizontally elongated epitaxial protrusions. These protruding epitaxial fins are in situ p-doped and n-doped, respectively, and configured as PMOS and NMOS transistors. A 1-10 nm (preferably 10, 7, 5, or 1 nm) intrinsic shell layer for a current ITRS transistor node is grown on the protruding epitaxial portion. An in-situ doped shell layer is grown on top of the intrinsic epitaxial shell layer. The inner shell layer can form the transistor source, and the outer shell layer can form the drain. The horizontal protruding epitaxial portions can be in-situ pin-doped and in-situ nip-doped, respectively, in the radial direction of the elongated epitaxial protrusion on the substrate. To form a contact with the intrinsic shell layer, a high-k dielectric oxide is deposited on the central portion of the protruding epitaxial portion in the epitaxial radial direction, dividing the protruding epitaxial portion into two.

[0082] To lithographically fabricate metal contacts on the protruding epitaxial portions at each end of the pin junction, one metal contact is fabricated on the inner core portion of the protruding epitaxial portion and one contact is fabricated on the outer shell. Charge carriers, i.e., electrons and holes, tunnel through the intrinsic layer, but if the gate contact substantially surrounds the intrinsic layer, radial current flow in the protruding epitaxial pin semiconductor structure is switched on and off with the gate voltage, creating a charge carrier channel for passage along the pin direction from the core to the outer layer located within the gate electrode. Given that the size of the gate electrode is limited by lithography and the doping of the pnp or npn transition in the longitudinal direction is limited by localized dopant atoms, it is advantageous to have a rapidly grown crystalline shell that allows control of the thickness of the epitaxial intrinsic layer in the 1-10 nm range, and particularly in the 1-5 nm range using MOVPE. An advantage of core-shell-based FinFET transistors is that the contacts can be fabricated in the same plane as the substrate.

[0083] It is preferable to grow a wide bandgap barrier layer that defines the tunneling capability of electrons between the protruding core portions of the intrinsic layer. By lithographically defining a nanostructured oxide layer over the middle portion of the protruding portion, a barrier shell can be grown only on the remaining portion.

[0084] A combination of germanium nanocrystals and InSb nanocrystals is preferably used for growing islands on silicon wafers for CMOS transistors according to the present invention. The precursor material iBuGe can be used for growing germanium nanowires.

[0085] In III-V / Ge CMOS, to match the conductivity of positive charge carriers to the high mobility of negative charge carriers, it is preferable to use multiple PMOS transistors in combination with a single NMOS transistor, or to configure protruding epitaxial portions to confine electrons within a one-dimensional semiconductor to a radius shorter than that of NMOS transistors by adjusting the height of the protruding epitaxial portions and the thickness of the cavities, respectively, for ballistic transport. The valence band of the semiconductor becomes anisotropic due to the influence of stress in the crystal structure, separating the light and heavy charge valence bands of positive charge carriers. The protruding epitaxial portions of NMOS transistors may have a mobility matching that of PMOS and may have a radius in the range of 7 to 18 nm, as electron mobility increases linearly over this range. However, this improvement is minimal for III-V semiconductor materials.

[0086] Figure 13 shows a schematic side view of a cross section of an epitaxial layer 806 containing a heterostructure (841, 842) of III-V semiconductors with different bandgaps, with a thin intermediate region of 1-10 nm. The epitaxial layer 806 contains III-nitride nanowires arranged on the epitaxial layer. The nanowires have an LED structure seen from the inside out, consisting of an n-GaN core wire and a p-GaN shell.

[0087] According to the dispersion relation, the energy of an electron can be written as a function of the wave vector of the band structure of a bulk semiconductor and thus approximated by a parabola. Thus, the charge carrier density is inversely proportional to the square root of the electron energy when the electron is trapped in two dimensions and free in one. Similarly, the charge carrier density is constant for electrons trapped in one dimension and increases slightly as the square root of the free electron energy in three dimensions. Therefore, for use in photonic components, it is preferable to trap electrons in one-dimensional semiconductors so that the charge density diverges near the conduction band edge.

[0088] Figure 14 shows a schematic side view of a cross section of an epitaxial layer 906 containing a heterostructure (941, 942, 943) of III-V semiconductors with different bandgaps and a thin 1-10 nm intermediate layer. The heterostructure may be in situ doped in either of the outer shells for modulation doping of the quantum wells. The abutting outer semiconductor layer has a larger bandgap than the intermediate layer 942 within the heterostructure. The heterostructure can be implemented for III-nitride nanowires with an LED structure (viewed from the inside to the outside of the core-shell nanowire) of GaN core / AlGaN shell / GaN barrier shell / InGaN active layer shell / GaN barrier shell / GaN shell, where the C-plane is the most polar plane for gallium nitride.

[0089] In the following, we will discuss devices for post-III-V CMOS applications, particularly those that are embodiments of Majorana quantum computers, which require substrates with very few dislocations among III-V semiconductors, such as the thin-film devices mentioned above. In contrast to electrons, Majorana fermions are their own antiparticles. For Majorana quasiparticles, the creation and annihilation operators are c = γ1 + iγ2 and

[0090]

number

[0091]

number

[0092] Figure 15 shows a schematic diagram of a T-shaped gate 1100 as a nanotree on an indium antimonide epilayer supporting a vertically free-standing, completely dislocation-free, crystalline indium antimonide nanowire (1152, 1153, 1157, 1154) on a silicon wafer, with a thickness of 1-10 nm. A nanowire branch 1157 is grown on the vertical nanowire segment 1153 (see the band structure in Figure 17 ; the E(z) and z directions are perpendicular to the substrate, and the E(x) direction is the x direction along the axial direction of the branch in Figure 15 ). The vertical nanowire may have two axially arranged energy barrier semiconductor materials (1152, 1154) along the branch electrode 1157. The vertically arranged indium antimonide nanowire may include at least two singlet-wave superconducting (s-wave) wraparound gate electrodes. The nanowire branch 1157 may include an s-wave superconducting electrode 1158.

[0093] In one-dimensional nanowires, Majorana quantum particles, known as Majorana fermions paired with the end states of each quantum well (1153, 1154), arise depending on the strength of the magnetic field and the configuration of the band structure known as the "Majorana zero gap." The T-shaped gate arrangement is preferred for nanotrees because the energy barrier material segments (1154, 1153) can be epitaxially grown in situ along the nanowire in a vertical direction toward the substrate, and the energy barrier material segments can be grown in situ along the branch 1157 with seed particles. Furthermore, it is preferable to provide a band structure with two parabolic bands for electron transport for spin-up and spin-down, i.e., a "spin-orbit split," through semiconductors with high spin-orbit coupling, such as indium antimonide alloys.

[0094] The nanotrees (1150, 1152, 1153, 1154, 1155, 1157) have branches 1157 that can be formed by gold seed particles and chemical vapor deposition (MOVPE). The branches 1157 can be grown by aerosol deposition of gold seed particles along the axial direction of the vertical nanowire 1155 between GaSb, GaAsSb, or InAsSb (1152, 1154) semiconductor barrier segments. Details of nanotree growth methods are described in the scientific paper "Kimberly Dick et al., Nature Materials, Vol. 3, 2004," which is incorporated herein by reference. To perform topological quantum computation, it is preferable to electrostatically deplete at least a portion of the nanowire.

[0095] Hereinafter, without any intention of limitation, an embodiment of topological quantum operation will be described in combination with the embodiment of FIG. 15 according to FIGS. 16 and 17.

[0096] Topological quantum operation (2000) is provided by providing a T-gate (2001) with two Majorana fermions in each of the first quantum well 1150 and the second quantum well 1155, and positively biasing the T-gate with a voltage across electrodes 1159 and 1158, thereby causing Majorana fermions to flow (2002) from the horizontally disposed nanowire portion 1150 to the wire branch 1157. Applying a voltage across electrodes 1159 and 1158 lowers the energy barrier in the L-shaped heterostructure InSb(1150) / GaInSb / InSb(1153) / GaInSb / InSb(1157).

[0097] Then, by applying a bias voltage (2003) across electrodes 1156 and 1159 that lowers the energy barrier of the horizontal nanowire of FIG. 16 according to FIG. 17, the second Majorana fermions flow from the first quantum well 1155 to the second quantum well 1150. Then, by applying a positive bias voltage (2004) across electrodes 1158 and 1156, the energy barrier of the heterostructure InSb(1157) / GaInSb / InSb(1153) / GaInSb / InSb(1155) is lowered, and the Majorana fermions then flow from the nanowire branch 1157 to the node quantum well 1153 and then to the second quantum well 1155. Thus, the original wave functions of the two Majorana quasiparticles are braided and returned to the same positions (2005) as they were originally at 2001.

[0098] The T-gate can perform multiple quantum operations by braiding two wave functions in vertically arranged heterostructure nanowires into single, double, triple, etc. To detect annihilated Majorana fermions, it is preferable to interconnect multiple T-gates.

[0099] For the segments (1154, 1153, 1152, 1157), it is preferable to provide a band gap for each semiconductor or its alloy according to the energy diagram of FIG.

[0100] A 16-bit qubit nanotree register can be constructed via multiple qubits on the same vertical nanowire describing superposition wave functions. One of the major challenges of Majorana quantum computers is that disturbances in the crystal structure can lead to the generation of interfering quasiparticles, so various heterostructures are preferably formed from in-situ grown semiconductor materials. Each N-qubit register for each nanotree can be coupled to other quantum gates via their respective quantum wells. Using 100 quantum wells, the number of quantum gates can be increased by 1.26*10 times compared to a conventional computer. 301157. An advantage of this embodiment 1100 is the enormous potential computational capacity. Another advantage is that thousands of indium antimony alloy nanotrees with an extremely low dislocation rate can be grown on a silicon wafer with in situ barrier segments grown perpendicular to the substrate and along the branches 1157.

[0101] The Schottky barrier is small for indium antimonide metal contacts, which is advantageous because small magnetic fields can be used to generate Majorana fermions. The contacts to the nanotrees can be made of superconducting NbTiN material. Spin blockade can also be used to detect the spin of fermions in quantum dots. This allows for the realization of a topological quantum computer with low decoherence and quantum states that protect the braided Majorana state. Further details regarding quantum computing for topological quantum information, quasiparticle-based memory, or logic operations are disclosed in "Nature Nanotechnology, 13, 192-197 (2018)," which is incorporated herein by reference.

[0102] An example of an embodiment includes a reinforced thin-film device and a III-V FinFET transistor, the III-V FinFET transistor further including two nanostructured electrodes radially surrounding a source end and a drain end of the protruding core portion, respectively, in a direction perpendicular to a longitudinal direction of the core portion, a central portion of the protruding core portion being surrounded by a high-k dielectric oxide shell having a nanostructured gate electrode radially surrounding the oxide shell in the perpendicular direction, the protruding core portion being pnp-doped or npn-doped, the central portion being n-doped or p-doped, and the vertical thickness being less than 10 nm, the protruding core portion configured to match a higher intrinsic mobility of negative charge carriers over positive charge carriers via a protruding epitaxial portion having a height and width, respectively, to confine electrons to a one-dimensional semiconductor for ballistic transport, the epitaxial protrusion having a radius in the range of 7-18 nm, and preferably the oxide shell is amorphous hafnium oxide. Multiple PMOS transistors can be combined with a single NMOS transistor for hybrid III-V / III-V CMOS or III-V / Ge CMOS.

[0103] Another example of an embodiment is a thin-film device including a germanium thin film and germanium nanowire needle pads embedded in the thin film. Graphene can be grown on the germanium thin film by CVD to fabricate graphene electrical contacts or electronic components. In other embodiments, the graphene layer can be a two-dimensional monolayer or graphene island, and can be functionalized with biomolecules, organic molecules, antibodies, proteins, or DNA for graphene transistors coated with Ti / Pd / Au electrical contacts and in contact with microfluidic channels. In some thin-film device embodiments, the device is a biosensor including a thin-film device having a germanium epilayer on which a monolayer of graphene is disposed, the monolayer of graphene functionalized with at least one biomolecule or organic molecule, and the monolayer of graphene coated with Ti, Pd, or Au contacts.

[0104] One example of an embodiment is a nanowire-based display in which specific nanowires are grown on different micro-sized surfaces to create red, green, and blue pixels, with the blue coming from nitride nanowires and the red and green coming from III-V nanowire quantum wells. In such an embodiment, the nanowires are grown at decreasing temperatures, starting with III-nitride nanowires from GaN nanoparticles and then III-V nanowires with gold catalyst particles. Another advantage of this embodiment is that III-N alloys can be combined with III-V alloys to create bandgaps for RGB LEDs. The bandgaps of In1-xGaxN are configured to support blue electroluminescence, while the bandgaps of InAlGaAsP semiconductor alloys support red and green electroluminescence. Modulation dopant atoms on both sides of the quantum well are moved to the bottom of the quantum well in a diode structure. In situ doping of the nanowire heterostructure, as well as the energy barrier semiconductor, can provide charge carriers to the quantum well, resulting in an extremely high density of charge carriers in the two-dimensional charge carrier gas.

[0105] Another example of an embodiment of the present invention relates to a reinforced thin-film device, the reinforced thin-film device including a gate stack including an epilayer having a semiconductor channel of a III-V semiconductor, a substantially thin wide bandgap semiconductor layer in a central portion of the semiconductor channel epitaxially disposed on the semiconductor channel for trapping impurity states, and a high-k oxide layer disposed on the high-k dielectric semiconductor and the wide bandgap semiconductor. The gate stack may be provided for a planar pnp or npn transistor, a nanowire transistor, or a FinFET transistor.

[0106] In one embodiment of the present invention, AlGaN / GaN is grown on a silicon wafer and patterned to form top-down nanowires. The nanowires are laterally overgrown, resulting in the growth of a fused GaN film on the silicon reinforced with AlGaN / GaN nanowires. In another embodiment, InP nanowires are selectively grown on (111) silicon and laterally overgrown, resulting in the growth of a thin InP film on the silicon.

[0107] In one embodiment of the present invention, GaN is disposed on a silicon wafer and the backside of the wafer is dry reactive ion etched to release the GaN film.

[0108] Another example of embodiment 806 relates to a III-N nanowire LED, comprising a doped core wire and shell layers having a lower bandgap than the core wire, the shell layers being in situ etched, and the core wire including surrounding electrical contacts. Where the core wire is in situ p-doped, at least one shell layer is n-doped. Where the core wire is in situ n-doped, at least one shell layer is p-doped.

[0109] Another example of an embodiment of a thin film device includes a III-V nanowire laser, which includes a nanowire having a p-doped core wire and an n-doped shell layer on the nanowire surrounding the core wire that forms a diode band structure, where the diode band structure can be maximized for photonic applications of III-V materials on silicon if the core wire is in situ p-doped during C-face growth with the highest possible growth rate from the polar C-face and the shell layer is intrinsically doped and n-doped with a lower growth rate from the nonpolar M-face or nonpolar A-face. These nanowire laser structures are capable of integration with silicon CMOS electronics.

[0110] In one exemplary embodiment of a thin film device, the epilayer is comprised of III-V semiconductor and germanium with respective epitaxially protruding portions having longitudinal npn-doped and pnp-doped segments, respectively, of which the intermediate doped portion may be 10-14 nm thick for III-V / Ge or III-V / III-V CMOSFETs, where the protruding portions are grown on hybrid epilayer islands of high mobility p-channel and n-channel material, respectively.

[0111] Another embodiment of the present invention relates to a process for growing III-N nanowires on a thin-film device, preferably having a gallium nitride epilayer, including: providing a thin-film device having a mask layer containing at least one nanopore; self-assembling at least one GaN nanoparticle on the substrate within the at least one nanopore; and growing at least one III-N nanowire having a wurtzite crystal structure from the GaN nanoparticles, preferably by epitaxial lateral overgrowth of the GaN nanoparticles in the wurtzite c-axis direction within the at least one nanopore. The GaN nanoparticles are self-assembled within the nanopores by capillary forces from an evaporating suspension of GaN nanoparticles. The ammonia gas precursor flow rate may be in the range of 10-30 sccm. The GaN nanoparticles can be self-assembled within the at least one nanopore by neutralizing acidic and alkaline ligands on the GaN nanoparticles within the at least one nanopore and on the substrate, respectively. The GaN nanoparticles can be produced by thermal laser synthesis from GaN powder.

[0112] Another example of an embodiment relates to a III-N nanowire LED (100), which includes a doped core wire (840) of wurtzite crystal structure on a substrate and a first shell layer (842) having a lower bandgap than the core wire (103), wherein the core wire (841) includes a second doped shell layer on the first shell layer, where the core wire is grown on a substrate of a crystal structure different from wurtzite. The substrate is zinc blende for growth of III-V nanowires. <111> A or <111> B. The core wire can include a surrounding electrical contact and / or the second shell layer can include a transparent electrical contact. The transparent electrical contact can be ITO.

[0113] Another example of an embodiment relates to a III-N nanowire LED, which includes a doped core wire (841') and a shell layer (842') having a lower bandgap than the core wire (841'), the shell layer being in-situ etched (840'), and the core wire (841') including surrounding electrical contacts. The core wire may be in-situ p-doped, and at least one shell layer (843') may be n-doped. The core wire may be in-situ n-doped if at least one shell layer is p-doped.

[0114] Another example of an embodiment is a thin-film device including a III-nitride nanowire epilayer and III-V nanowires, where the III-nitride nanowires are grown from GaN nanoparticles. An advantage of this embodiment is that it allows for the fabrication of light-emitting diodes (LEDs) that cover the entire optical spectrum and produce white light on inexpensive silicon substrates. Another advantage of this embodiment is that it eliminates the need for a phosphorescent layer, as in blue LEDs, to achieve white light. The shell layer can be etched in situ to the same height as the core nanowire, eliminating the need for luminescence from the C-plane. An advantage of this embodiment is that wavelengths are more distinct when luminescence is differentiated between different crystal planes. Furthermore, it avoids the shift in wavelength spectrum that occurs when a thin film is fabricated on silicon.

[0115] In another example of an embodiment of a reinforced thin film device, the elongated epitaxial protrusion has respective pin doped segments in the radial direction, of which the middle intrinsic segment may be 7-10 nm thick for a III-V pin / III-V nip finCMOS FET.

[0116] One embodiment of the present invention relates to a process (1000) for fabricating III-V FinFETs (420, 424), the process comprising: providing a substrate including epilayer islands (415 a, 415 b); depositing an epitaxial growth mask layer for epitaxial growth in contact with the epilayer islands; lithographically defining an elongated cavity having a nanostructured width in a central portion on the epilayer islands; and epitaxially protruding a core portion (420 a, 420 b) from the elongated cavity to a nanostructured height in a plane perpendicular to the epilayer islands (415 a, 415 b) to fabricate a one-dimensional semiconductor for ballistic charge carrier transport in the longitudinal direction, wherein the semiconductor of the epilayer islands (415 a) is selected from a III-V semiconductor having high mobility for positive charge carriers or a III-V semiconductor having high electron mobility. The process may include growing a protruding core portion with a mask layer, growing a wide bandgap barrier shell along the length of the elongated protruding core portion (420) to produce a central recess filled with an intrinsically doped substantially thin shell, and growing an in-situ doped shell on the barrier shell, wherein the protruding core portion and the in-situ doped shell are in-situ doped to form a pin junction in a radial direction at a central portion of the protruding core portion. The central portion may be less than 10 nm, and the intrinsic layer may have a nanostructured thickness of less than 7 nm to surround charge carriers in the zero-dimensional semiconductor in the longitudinal direction. To divert heat in III-V CMOS circuits, the length of the nanowire and the thickness of the epilayer may be less than 400 nm.

[0117] In another embodiment of the present invention, the PMOS transistor can include a core-shell structure with a pin connection segment, and the NMOS transistor can include a core-shell structure with a pin connection segment, and preferably the nanowire includes an intrinsically doped segment having a thickness of 5-7 nm. The PMOS transistor can also include a nanowire epitaxially grown on an epilayer island, and the NMOS transistor includes a nanowire grown on the epilayer island.

[0118] Another example of embodiment 806 is an epilayer formed by a reinforced thin film device having a III-N nanowire diode structure, the epilayer including a doped core wire of wurtzite crystal structure on a substrate and a first shell layer having a lower bandgap than the core wire, the core wire forming a doped second shell layer on the first shell layer, the core wire grown on a substrate of a crystal structure other than wurtzite. The substrate may be zinc blende for growth of III-V nanowires. <111> A or <111> B. The core wire may also include a surrounding electrical contact.

[0119] Another example of an embodiment is a Majorana quantum computer 900, comprising: a crystalline substrate (901); a first heterostructure nanowire (967) of a III-V semiconductor arranged parallel to the substrate (901) by lateral overgrowth of elongated trenches (961′); and a second heterostructure nanowire (966) arranged perpendicular to the first heterostructure nanowire (967), the second heterostructure nanowire (966) being substantially lattice-matched to the first nanowire having a central junction, the vertical nanowire (966) comprising a wide bandgap semiconductor material, a superconducting wraparound gate electrode (962) surrounding the second vertical nanowire (966), and two superconducting electrodes (961, 963) disposed at the ends of the first nanowire. The superconducting electrodes may be s-wave superconductors. The first heterostructure nanowire and the second vertical heterostructure nanowire may each be arranged as an indium antimonide nanowire. The two-dimensional graphene islands may be arranged to be part of a Majorana quantum gate having a structured band structure.

[0120] Another example of an embodiment relates to a nanotree including a tandem heterostructure, the tandem heterostructure including a heterostructure nanowire of a III-V semiconductor including a first island and a second island along its axial direction, the first island configured for a Majorana quantum state forming a first qubit, and the second island configured for a second Majorana quantum state forming a second qubit. The heterostructure nanowire can have two substantially short energy barrier segments such that the first qubit and the second qubit can form a superposition wave function. The heterostructure nanowire can include a branch made of substantially the same semiconductor as the nanowire to form a T-shaped gate. The energy barrier segment can be a substantially thin segment having a thickness of 2 to 3 nm.

[0121] Another example of embodiment 1100'' relates to a III-V semiconductor gate, which includes a three-way intersection of III-V semiconductors (1153, 1157, 1154) including three nanowire segments to perform a topological braiding operation of two Majorana wave functions for Majorana fermions, each nanowire segment including at least one heterostructure having a substantially thin energy barrier material.

[0122] Preferred Embodiments A reinforced thin film device (100, 200, 500) comprising: a substrate (101) having an upper surface for supporting an epitaxial layer; a mask layer (103) patterned with a plurality of nano-sized cavities (102, 102') disposed on the substrate (101) to form needle pads; and a thin film (105) of a lattice-mismatched semiconductor disposed on the mask layer (103), the thin film (105) including a plurality of parallel, spaced-apart semiconductor needles (104, 204) of the lattice-mismatched semiconductor embedded within the thin film (105); and a thin film (105) in which the semiconductor needles (104, 204) are disposed substantially vertically in an axial direction toward the substrate (101) within the nano-sized cavities (102, 102') of the mask layer (103), and a lattice-mismatched semiconductor epitaxial layer (106) is provided on the thin film supported by the lattice-mismatched semiconductor epitaxial layer (106), preferably the substrate (101) is a silicon wafer with a diameter of more than 2 inches. The parallel, spaced-apart semiconductor needles (204) of the lattice-mismatched semiconductor may be arranged in a hexagonal close-packed structure with a distance of 50 to 100 nm between the lattice-mismatched semiconductor. The nano-sized cavities (102, 102') may be nano-sized holes with a diameter of 5 to 25 nm, and the semiconductor needles (104, 204) of the same thickness are formed within the nano-sized holes. The epilayer may include multiple individual islands of at least two different lattice-mismatched semiconductors (406). The thin film (505) may be disposed within germanium (505), and the epilayer may be graphene (506). The nano-sized cavities (102, 102') may be substantially deep. The epilayer may include semiconductor fins of the same semiconductor material as the epilayer. The semiconductor islands may be substantially close-packed with a distance of 200 to 500 nm. The epilayer may include at least one heterostructure (506, 606) of III-V semiconductor alloys having different bandgaps with a thin interlayer (1 to 10 nm). The interlayer may have a smaller bandgap than the adjacent semiconductors in the heterostructure (506, 606). The semiconductor needle of the present invention may have at least a portion with a wurtzite crystal structure.

[0123] Although modifications and variations may be suggested by those skilled in the art, it is the intention of the inventors to encompass within the scope of the disclosure herein all modifications and variations that reasonably and appropriately fall within the scope of the disclosure disclosed herein. The present invention has been described above with reference to specific embodiments. However, other embodiments than those described are equally possible within the scope of the present invention. Method steps other than those described may also be provided within the scope of the present invention. Different features and steps of the present invention may also be combined in combinations other than those described. For example, various features of the embodiments may be combined, mutatis mutandis, in combinations other than those described. The scope of the present invention is limited only by the appended claims.

Claims

1. A reinforced thin film device (100, 200, 500) comprising: a substrate (101) having a top surface for supporting an epilayer; a mask layer (103) patterned with a plurality of nano-sized cavities (102, 102') disposed on the substrate (101) for forming needle pads; a thin film (105) of a lattice-mismatched semiconductor disposed on the mask layer (103), the thin film (105) including a plurality of parallel, spaced apart semiconductor needles (104, 204) of the lattice-mismatched semiconductor embedded within the thin film (105), the plurality of semiconductor needles (104, 204) being disposed axially substantially perpendicularly towards the substrate (101) within the plurality of nano-sized cavities (102, 102') of the mask layer (103); Equipped with a lattice-mismatched semiconductor epitaxial layer (106) is provided on the thin film supported by the lattice-mismatched semiconductor epitaxial layer (106), and the substrate (101) is preferably a silicon wafer having a diameter of more than 2 inches; Reinforced thin film device (100, 200, 500).

2. 10. The reinforced thin film device of claim 1, wherein the plurality of parallel spaced apart semiconductor needles of lattice-mismatched semiconductor are arranged in a hexagonal close-packed configuration with a distance of 50-100 nm of lattice-mismatched semiconductor.

3. The reinforced thin film device (300) of claims 1 and 2, wherein the plurality of nano-sized cavities (102, 102') are nano-sized holes having a hole diameter of 5 to 25 nm, and are nano-sized holes for providing the semiconductor needles (104, 104) of the same thickness within the nano-sized holes.

4. The reinforced thin film device (400) of claims 1 to 3, wherein the epilayer comprises a plurality of individual islands of at least two different lattice-mismatched semiconductors (406).

5. 5. The reinforced thin film device (500) of claims 1 to 4, wherein the thin film (505) is disposed in germanium (505) and the epilayer is graphene (506).

6. The reinforced thin film device (100) of any one of claims 1 to 5, wherein the plurality of nano-sized cavities (102, 102') are substantially deep.

7. The reinforced thin film device (100) of claims 1 to 6, wherein the epilayer comprises a semiconductor fin of the same semiconductor material as the epilayer.

8. A reinforced thin film device (100) according to any one of claims 4 to 7, wherein said plurality of islands are substantially close packed with a distance of 200 to 500 nm.

9. 9. The reinforced thin film device (600, 700) of claim 1, wherein the epilayer comprises at least one heterostructure (506, 606) of III-V semiconductor alloys having different bandgaps with a thin intermediate layer of 1-10 nm, the intermediate layer having a smaller bandgap than the abutting semiconductors in the heterostructure (506, 606).

10. The reinforced thin film device (100) of claims 1 to 9, wherein the semiconductor needles have at least a portion that is of a wurtzite crystal structure.

Images