Reservoir computer and control method of reservoir computer

Abstract

To provide a reservoir computer with low power consumption by controlling a period during which voltage is applied to a drain.SOLUTION: A reservoir computer is provided, comprising: a FeFET of which a gate electrode is connected to a gate voltage generation circuit that inputs gate voltage in the form of a triangular wave with peaks of positive voltage and negative voltage to the gate electrode and of which a drain is connected to a sense circuit that applies drain voltage and detects a drain current by converting it from analog to digital; and a first switch arranged between the sense circuit and the drain. The gate voltage generation circuit includes a charge pump circuit for applying positive voltage, a charge pump circuit for applying negative voltage, a pulse generation circuit, and a Vref regulator.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a reservoir computer and a method for controlling a reservoir computer. [Background technology]

[0002] Patent Document 1 describes a semiconductor device equipped with a ferroelectric memory cell. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-161307 Summary of the Invention [Problem to be solved by the invention]

[0004] However, related semiconductor devices require a constant voltage to be applied to the drain for readout, resulting in high power consumption. Therefore, an object of the present disclosure is to provide a reservoir computer or the like that controls the period for applying a voltage to the drain and consumes low power.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, the reservoir computer includes a first switch disposed between the sense circuit and the drain. [Effects of the Invention]

[0007] According to the embodiment, it is possible to provide a reservoir computer or the like with low power consumption by controlling the period during which a voltage is applied to the drain. [Brief explanation of the drawings]

[0008] [Figure 1] 10A and 10B are diagrams illustrating changes in the state of a reservoir computer according to an embodiment. [Figure 2] FIG. 1 shows the changes in input (Vg), drain voltage (Vd), and read current (Id) of the associated reservoir computer. [Figure 3] FIG. 1 shows the changes in input (Vg), drain voltage (Vd), and read current (Id) of the associated reservoir computer. [Figure 4] FIG. 2 is a schematic diagram of a circuit constituting a reservoir computer according to the first embodiment. [Figure 5] FIG. 2 is a diagram illustrating a gate voltage generating circuit of the reservoir computer according to the first embodiment. [Figure 6] FIG. 10 is a diagram showing the application timing of the drain voltage of the reservoir computer according to the first embodiment. [Figure 7] FIG. 10 is a diagram showing the timing of applying a drain voltage when reading out a reservoir computer multiple times according to the second embodiment. [Figure 8] FIG. 11 is a diagram showing the timing when a gate voltage is applied multiple times to a reservoir computer according to the third embodiment. [Figure 9] FIG. 11 is a schematic diagram of a circuit constituting a reservoir computer according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. Furthermore, each element shown in the drawings as a functional block performing various processes can be configured, for example, in hardware terms by a CPU (Central Processing Unit), memory, or other circuits, and in software terms by a program loaded into memory. Therefore, these functional blocks can be realized by hardware, software running on hardware, or a combination thereof. In addition, the same elements are designated by the same reference numerals in each drawing, and redundant explanations are omitted as necessary.

[0010] The above-described program can be stored and supplied to a computer using various types of non-transitory computer-readable media. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic storage media (e.g., flexible disks, magnetic tapes, hard disk drives), magneto-optical storage media (e.g., magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / Ws, and semiconductor memories (e.g., mask ROMs, PROMs (Programmable ROMs), EPROMs (Erasable PROMs), flash ROMs, and RAMs (Random Access Memory)). The program can also be supplied to a computer by various types of transitory computer-readable media. Examples of transitory computer-readable media include electrical signals, optical signals, and electromagnetic waves. The transitory computer-readable media can supply the program to a computer via a wired communication path such as an electric wire or optical fiber, or via a wireless communication path.

[0011] (Description of Reservoir Computer and Problems According to the Embodiment) FIG. 1 is a diagram showing changes in the state of a reservoir computer according to an embodiment. FIG. 2 is a diagram showing changes in the input (Vg), drain voltage (Vd), and read current (Id) of a related reservoir computer. FIG. 3 is a diagram showing changes in the input (Vg), drain voltage (Vd), and read current (Id) of a related reservoir computer. The reservoir computer according to an embodiment and the problem will be described with reference to FIGS. 1 to 3.

[0012] As shown in FIG. 1 , the semiconductor device constituting the reservoir computer according to the embodiment includes a source, a drain, a back, and a gate. The semiconductor device is also called an FeFET (Ferroelectric Field Effect Transistor). The source and drain are formed in a semiconductor layer. The back is formed between the source and drain. The back is, for example, a P-type well region. The back is at the same potential as the source. An interlayer (IL) formed of a paraelectric film and a ferroelectric film are provided between the gate electrode and the semiconductor layer. The ferroelectric film is a charge storage layer. The ferroelectric film preferably includes HZO (Hafnium Zirconium Oxide) containing Al (Aluminum) or AlN (Aluminum Nitride). The HZO film is a ferroelectric film. Doping the HZO film with Al or AlN produces a ferroelectric film with even greater polarization capacity.

[0013] Such FeFETs are characterized by their long memory retention times, and therefore the circuits and control methods of the present disclosure can be applied to any FeFET that has a longer memory retention time than the related FeFET.

[0014] The source is grounded. For example, input data Vg is input to the gate electrode, and a voltage is applied to the drain to detect the drain current Id between the source and drain, which is the reservoir state. Here, the input Vg is the number of times the gate voltage is input. The reservoir state changes depending on the polarization state and charge trap state of the FeFET. Due to this polarization state and charge trap state, the drain current shows hysteresis with respect to the gate voltage and does not change linearly. For this reason, the FeFET has a memory function. The FeFET can detect reservoir states X1, X2, X3, and X4, for example, depending on the drain current Id. i-1 , X i Shows.

[0015] The reservoir calculation is performed in two steps: (1) updating the reservoir state based on input (changes in polarization state and charge trap state), and (2) outputting the reservoir state (output of drain current).

[0016] Figure 2 shows an example of sequential readout. When a gate voltage Vg is applied, the sequential drain current Id is detected. Since sequential readout performs (1) and (2) simultaneously, the drain current always flows, resulting in a large current consumption.

[0017] Figure 3 shows an example of inputting multiple times and reading once. Even if (1) and (2) are simply separated, the drain current always flows, resulting in high power consumption.

[0018] (Description of Reservoir Computer According to First Embodiment) FIG. 4 is a schematic diagram of a circuit constituting the reservoir computer according to the first embodiment. FIG. 5 is a diagram illustrating a gate voltage generation circuit of the reservoir computer according to the first embodiment. FIG. 6 is a diagram illustrating the application timing of the drain voltage of the reservoir computer according to the first embodiment. The reservoir computer according to the first embodiment will be described with reference to FIGS. 4 to 6.

[0019] As shown in FIG. 4, the reservoir computer 400 according to the first embodiment includes a gate voltage generating circuit 401, a switch timing circuit 402, and a sense circuit 403. A first switch is disposed between the drain and the sense circuit 403. The switch timing circuit 402 is connected to the first switch and controls the first switch. The switch timing circuit switches, for example, at a period of 500 ns. The sense circuit 403 includes a circuit 408 that applies a positive voltage Vd to the drain and a circuit 409 that performs analog-to-digital conversion of the drain current Id. The positive voltage is, for example, 50 mV. The sense circuit 403 detects the drain current Id.

[0020] 5, the gate voltage generation circuit 401 includes a charge pump circuit 404 that applies a positive voltage, a pulse generator 405, a Vref regulator 406, and a charge pump circuit 407 that applies a negative voltage. The Vref regulator has a function of adjusting the reference voltage Vref.

[0021] As shown in (a) on the right side of FIG. 5, when data is input, a pulse generator 405 generates a triangular pulse. As shown in (b) on the right side of FIG. 5, a desired gate voltage is obtained when a charge pump circuit 404 that applies a positive voltage to the triangular wave output from the pulse generator 405, the pulse generator 405, a Vref regulator 406, and a charge pump circuit 407 that applies a negative voltage operate. The desired gate voltage is a triangular wave with positive and negative voltage peaks. For example, the desired gate voltage is a triangular wave with a maximum value of 4V and a minimum value of -2V, with 1V as the reference.

[0022] As shown in the upper diagram of Fig. 6, the reservoir computer according to the first embodiment is provided with a switch timing circuit 402, which allows adjustment of the detection timing of the drain current Id of the sense circuit. As shown in the lower diagram of Fig. 6, for example, the gate voltage Vg is applied multiple times in a period Tp. The read period T Read A voltage Vd is applied to the drain at point t1, and the drain current Id is read out at point t2.

[0023] In this way, when data is input, the drain switch is switched to ground potential to update the reservoir state without flowing drain current.When the reservoir state is read, the drain switch is switched and the drain current is read.

[0024] With the above configuration, it is possible to provide a reservoir computer with low power consumption by controlling the period during which a voltage is applied to the drain.

[0025] (Description of Reservoir Computer According to Second Embodiment) 7 is a diagram showing the timing of application of drain voltage when reading out the reservoir computer according to the second embodiment multiple times. The reservoir computer according to the second embodiment will be described with reference to FIG. 7. The reservoir computer according to the second embodiment differs from the reservoir computer according to the first embodiment in that reading out is performed multiple times.

[0026] As shown in FIG. 7, for example, the gate voltage Vg is applied multiple times in a period Tp. Read A voltage Vd is applied to the drain multiple times. Then, Id is read out at multiple read points. That is, after inputting a gate voltage to the gate electrode, the reservoir computer applies a voltage to the drain multiple times without any additional input to read out the state of the reservoir. At these multiple read points, the drain current Id changes over time from the drain current due to the polarization state + charge trap state to the drain current due to polarization.

[0027] By utilizing this state, the amount of information in the reservoir obtained from one set of input can be increased, which means that the amount of information can be increased without increasing the number of FeFETs, thereby improving recognition accuracy with low power consumption.

[0028] (Description of Reservoir Computer According to Third Embodiment) FIG. 8 is a diagram showing the timing when a gate voltage is applied multiple times to the reservoir computer according to the third embodiment. FIG. 9 is a schematic diagram of a circuit constituting the reservoir computer according to the third embodiment. The reservoir computer according to the third embodiment will be described with reference to FIGS. 8 and 9. The reservoir computer according to the third embodiment differs from the reservoir computer according to the first embodiment in that an interval is provided for inputting the gate voltage.

[0029] As shown in FIG. 8, the reservoir computer control method according to the third embodiment inserts intervals Ti1, Ti2, Ti3, and Ti4 between inputs to the FeFET. Ti1, Ti2, Ti3, and Ti4 may be the same or different periods. That is, the reservoir computer control method according to the third embodiment updates the state of the FeFET reservoir by inputting the gate voltage multiple times and changes the time between multiple inputs of the gate voltage. The reservoir computer control method according to the third embodiment utilizes transient responses of the FeFET, such as relaxation of the polarization state and charge detrapping, that occur during these intervals for reservoir computing. This improves the nonlinearity of the FeFET response, thereby improving reservoir performance.

[0030] Furthermore, the reservoir computer control method according to the third embodiment can change the interval time, so that input information can be Ti1, Ti2, Ti3, and Ti4 in addition to "1" and "0." Therefore, the reservoir computer control method according to the third embodiment can input analog data and multi-bit data.

[0031] 9, the reservoir computer 900 according to the third embodiment includes a gate voltage application timing circuit 901 in addition to the gate voltage generation circuit 401, the switch timing circuit 402, and the sense circuit 403. A second switch is disposed between the gate voltage generation circuit 401 and the gate electrode. The second switch is controlled by the gate voltage application timing circuit 901.

[0032] The timing of applying the gate voltage Vg is controlled by the gate voltage application timing circuit 901. Therefore, the gate voltage application timing circuit 901 can control the intervals Ti1, Ti2, and Ti3.

[0033] The embodiments can be combined with each other, that is, the second embodiment and the third embodiment can be combined.

[0034] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible within the scope of the gist of the invention. [Explanation of symbols]

[0035] 400 reservoir computer, 401 gate voltage generation circuit, 402 switch timing circuit, 403 sense circuit, 404 charge pump circuit for applying positive voltage, 405 pulse generator, 406 Vref regulator, 407 charge pump circuit for applying negative voltage, 408 circuit for applying positive voltage to drain, 409 circuit for analog-to-digital conversion of drain current, 900 reservoir computer, 901 gate voltage application timing circuit

Claims

1. a FeFET (Ferroelectric Field Effect Transistor) whose gate electrode is connected to a gate voltage generating circuit that inputs a gate voltage, which is a triangular wave having positive and negative voltage peaks, to the gate electrode, and whose drain is connected to a sense circuit that applies a drain voltage and detects the drain current by analog-to-digital conversion; a first switch disposed between the sense circuit and the drain.

2. 2. The reservoir computer according to claim 1, wherein the gate voltage generating circuit comprises a charge pump circuit that applies a positive voltage, a charge pump circuit that applies a negative voltage, a pulse generator, and a Vref regulator.

3. updating the state of the reservoir of the FeFET by applying the gate voltage multiple times; 2. The reservoir computer of claim 1, wherein the first switch is used to apply no voltage to the drain while updating the state of the reservoir and to apply a voltage to the drain when reading the reservoir.

4. 4. The reservoir computer according to claim 3, wherein after the gate voltage is input to the gate electrode, a voltage is applied to the drain multiple times without additional input to read out the state of the reservoir.

5. 2. The reservoir computer of claim 1, further comprising a second switch disposed between the gate electrode and the gate voltage generating circuit.

6. updating the state of the reservoir of the FeFET by applying the gate voltage multiple times; 4. The reservoir computer of claim 3, wherein the time between multiple inputs of the gate voltage is varied.

7. 2. The reservoir computer according to claim 1, wherein the FeFET uses HZO (hafnium zirconium oxide) having Al or AlN as a charge storage layer.

8. An FeFET (Ferroelectric Field Effect Transistor) whose gate electrode is connected to a gate voltage generation circuit that inputs a gate voltage that is a triangular wave with positive and negative voltage peaks, and whose drain is connected to a sense circuit that applies a drain voltage and detects the drain current by analog-to-digital conversion; a first switch disposed between the sense circuit and the drain.

9. 9. The reservoir computer control method according to claim 8, wherein the gate voltage generating circuit comprises a charge pump circuit for applying a positive voltage, a charge pump circuit for applying a negative voltage, a pulse generator, and a Vref regulator.

10. updating the state of the reservoir of the FeFET by applying the gate voltage multiple times; 9. The method of claim 8, wherein the first switch is used to apply no voltage to the drain while updating the state of the reservoir and to apply a voltage to the drain when reading the reservoir.

11. 11. The control method for a reservoir computer according to claim 10, further comprising: applying a voltage to the drain multiple times without additionally inputting the gate voltage to the gate electrode, to read out the state of the reservoir.

12. 9. The reservoir computer control method according to claim 8, further comprising a second switch disposed between the gate electrode and the gate voltage generating circuit.

13. updating the state of the reservoir of the FeFET by applying the gate voltage multiple times; The reservoir computer control method according to claim 10, wherein the time between the multiple inputs of the gate voltage is changed.

14. 9. The reservoir computer control method according to claim 8, wherein the FeFET uses HZO (hafnium zirconium oxide) having Al or AlN in a charge storage layer.

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