Oscillator circuit

Abstract

To provide an oscillator circuit which performs spectrum spreading.SOLUTION: An oscillator circuit includes an oscillator, to which a control signal is inputted, for outputting a first clock signal having an oscillation frequency according to the control signal. The oscillator circuit includes a frequency-voltage conversion circuit, to which the first clock signal is inputted, for outputting a detection voltage according to the oscillation frequency. The oscillation circuit includes an operational amplifier, to which the detection voltage and a reference voltage are inputted, for outputting a control signal according to a difference voltage between the detection voltage and the reference voltage to the oscillator. The frequency-voltage conversion circuit further includes a variable resistance part for generating a detection voltage by dividing a predetermined voltage, and the variable resistance part is configured so as to make the resistance value variable.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to an oscillator circuit. [Background technology]

[0002] A frequency locked loop (FLL) is widely used as a clock generator. Also, a spread spectrum technology is known that can reduce radiation noise by constantly changing the oscillation frequency. Patent Document 1 discloses a related technology. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2016 / 105187 Summary of the Invention [Problem to be solved by the invention]

[0004] The technology of Patent Document 1 uses a triangular wave to spread the spectrum of the oscillation signal. To generate the triangular wave, a triangular wave generating circuit (oscillating circuit) using an operational amplifier is provided. In this case, an analog circuit must be used, making it difficult to reduce the circuit area. [Means for solving the problem]

[0005] One embodiment of an oscillator circuit disclosed herein includes an oscillator that receives a control signal and outputs a first clock signal having an oscillation frequency corresponding to the control signal. The oscillator circuit includes a frequency-to-voltage conversion circuit that receives the first clock signal and outputs a detection voltage corresponding to the oscillation frequency. The oscillator circuit includes an operational amplifier that receives a detection voltage and a reference voltage and outputs a control signal to the oscillator that corresponds to the difference between the detection voltage and the reference voltage. The frequency-to-voltage conversion circuit further includes a variable resistor that generates the detection voltage by dividing a predetermined voltage and is configured to be able to vary its resistance value.

[0006] In the above configuration, feedback control is performed so that the detection voltage coincides with the reference voltage. This stabilizes the control signal, thereby stabilizing the oscillation frequency of the first clock signal. The oscillation frequency of the first clock signal can be varied (i.e., spectrum spread) by varying the resistance value of the variable resistor section. The circuit that varies the resistance value of the variable resistor section can be configured with a digital circuit such as a logic circuit. Therefore, the circuit area can be reduced compared to an oscillation circuit that performs spectrum spread using an analog circuit. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a circuit configuration diagram of an oscillator circuit 1. FIG. [Figure 2] FIG. 2 is a circuit diagram of a variable resistance section 30. [Figure 3] FIG. 2 is a circuit diagram of a frequency divider circuit 37. [Figure 4] FIG. 2 is a circuit diagram of an up / down counter 38. [Figure 5] 10 is a timing chart of the up / down counter 38. [Figure 6] 10 is a graph showing the change over time of a combined resistance value R33. [Figure 7] 10 is a graph showing the change over time of the oscillation frequency fOUT. DETAILED DESCRIPTION OF THE INVENTION

[0008] (Configuration of oscillator circuit 1) 1 shows a circuit configuration diagram of an oscillator circuit 1 according to this embodiment. The oscillator circuit 1 is an FLL (frequency locked loop) oscillator circuit. The oscillator circuit 1 mainly includes a frequency-to-voltage conversion circuit 10, an oscillator 40, a level shift circuit 41, a differential voltage-to-current conversion circuit 50, and a reference voltage generation circuit 60.

[0009] The reference voltage generating circuit 60 generates a reference voltage V ref The reference voltage generating circuit 60 generates and outputs a power supply voltage V DD The reference voltage generating circuit 60 receives the power supply voltage V DD is divided by a voltage divider circuit (not shown) to obtain the reference voltage V ref Generate.

[0010] The differential voltage-to-current conversion circuit 50 includes an operational amplifier 51, a PMOSFET 52, a capacitor 53, and a resistor 54. The non-inverting input terminal of the operational amplifier 51 is connected to a reference voltage V ref is input, and the inverting input terminal is supplied with the detection voltage V fV is input. Detection voltage V fV The output terminal of the operational amplifier 51 outputs an output voltage V o The output terminal of the operational amplifier 51 is connected to the gate terminal of the PMOSFET 52, and is also connected to the source terminal of the PMOSFET 52 via a capacitor 53 and a resistor element 54. The source terminal of the PMOSFET 52 is connected to the power supply voltage V DD is input, and the control current I OSC is output. Control current I OSC is the detection voltage V fV and the reference voltage V ref This is a control signal that corresponds to the differential voltage between

[0011] Control current I OSCis input to the oscillator 40. The oscillator 40 is a constant current driven CMOS ring oscillator. A clock signal CLK0 is output from the oscillator 40 and input to a level shift circuit 41. The clock signal CLK0 is generated by a control current I OSC Oscillation frequency f according to OUT is a signal having the following structure:

[0012] The level shift circuit 41 adjusts the voltage level of the input clock signal CLK0 and outputs it as a first clock signal CLK1. The first clock signal CLK1 has an oscillation frequency f OUT In this embodiment, the level shift circuit 41 shifts the voltage amplitude of the first clock signal CLK1 from the ground voltage V SS (0V) and power supply voltage V DD (1.8V). The first clock signal CLK1 output from the level shift circuit 41 is output to the outside via the output terminal OT1, and is also input to the frequency-voltage conversion circuit 10.

[0013] The frequency-voltage conversion circuit 10 converts the oscillation frequency f of the first clock signal CLK1 OUT Depending on fV The frequency-voltage conversion circuit 10 mainly comprises a variable resistance section 30 and a switched capacitor section 20. The variable resistance section 30 and the switched capacitor section 20 generate a power supply voltage V DD and ground voltage V SS and are connected in series between the first clock signal and the second clock signal. The variable resistance section 30 has a variable resistance value R30. The variable resistance section 30 is configured to be able to vary (jitter) the variable resistance value R30. The switched capacitor section 20 is a part that performs a switching operation based on the first clock signal, thereby functioning pseudo as a resistor having a pseudo resistance value R20.

[0014] The output node N1 connecting the variable resistor section 30 and the switched capacitor section 20 outputs the detection voltage V fV That is, the power supply voltage V is output by the variable resistance R30 and the pseudo resistance R20. DD is divided to obtain the detection voltage VfV is generated. The pseudo resistance value R20 causes the oscillation operation of the FLL method. Furthermore, the variation of the variable resistance value R30 causes the spread spectrum operation. The details of these operations will be described later.

[0015] The switched capacitor section 20 includes a PMOSFET 21, an NMOSFET 22, and a capacitor 23. The output node N1 and the ground voltage V SS A PMOSFET 21 and an NMOSFET 22 are connected in series between the PMOSFET 21 and the NMOSFET 22. A first clock signal CLK1 is input to the gates of the PMOSFET 21 and the NMOSFET 22. One end of the capacitor 23 is connected to a connection node N2 between the PMOSFET 21 and the NMOSFET 22. The other end of the capacitor 23 is connected to a ground voltage V SS and is connected via a capacitor 11 to an output node N1.

[0016] (Configuration of variable resistance section 30) 2 shows a circuit configuration diagram of the variable resistor section 30. The variable resistor section 30 mainly includes a resistor group 31, a trimming signal generation circuit 35, and a spread spectrum signal generation circuit 36. The resistor group 31 includes a trimming resistor group 32, a spread spectrum resistor group 33, and a fixed resistor 34. The trimming resistor group 32 is configured to generate a voltage equal to the oscillation frequency f of the first clock signal CLK1. OUT The spread spectrum resistor group 33 is a resistor group for setting the oscillation frequency f OUT The fixed resistor 34 is a resistor group for spreading the spectrum of the oscillation frequency f. The fixed resistor 34 is a resistive element for setting the minimum value when the combined resistance of the resistor group 31 is minimum (i.e., when the bypass switches ST1 to ST8 and SS1 to SS4 are all turned on). OUT This narrows the adjustment range of the resistance value by the trimming resistor group 32, making it possible to reduce the resistance adjustment step and the number of bits of the trimming resistor group 32. One end of the trimming resistor group 32 is connected to the power supply voltage VDD The other end of the trimming resistor group 32 is connected to one end of the spread spectrum resistor group 33 via a connection node N3. The other end of the spread spectrum resistor group 33 is connected to one end of a fixed resistor 34 via a connection node N4. The other end of the fixed resistor 34 is connected to the switched capacitor section 20 via an output node N1.

[0017] The spread spectrum resistor group 33 will be described. The spread spectrum resistor group 33 includes four resistors RS1 to RS4 and four bypass switches SS1 to SS4. The resistors RS1 to RS4 are connected in series between the connection node N3 and the connection node N4. The fourth resistor RS4 is connected to the first resistor RS1 by a power supply voltage V DD The output terminal of the first resistor RS1 is connected to the output node N1, and the detection voltage V fV is output. Each of the bypass switches SS1 to SS4 is arranged in parallel with each of the resistors RS1 to RS4. The bypass switches SS1 to SS4 may be, for example, PMOS switches or NMOS switches.

[0018] The relationship between the resistance values ​​of the resistors RS1 to RS4 will be explained using n (n is a natural number of 1 or more). The resistance value of the nth resistor is 2 times the resistance value of the first resistor. (n-1) That is, in this embodiment, the ratio of the resistance values ​​from the first resistor (RS1) to the fourth resistor (RS4) is "1:2:4:8".

[0019] Multiple resistors having the resistance ratios described above can be formed by various methods. For example, resistors with various resistance values ​​can be formed by preparing multiple reference resistor elements having the same resistance value and connecting them in parallel or series. In this example, multiple 948 Ω reference resistor elements were prepared. The first resistor (RS1) through the fourth resistor (RS4) were configured with 16 parallel, 8 parallel, 4 parallel, and 2 parallel reference resistor elements. As a result, the resistance values ​​of the first resistor (RS1) through the fourth resistor (RS4) were set to 59.25 Ω, 118.5 Ω, 237 Ω, and 474 Ω, respectively.

[0020] The relationship between the on-resistance values ​​of the bypass switches SS1 to SS4 will be described using n. The on-resistance value of the nth bypass switch is 2 times the on-resistance value of the first bypass switch. (n-1) The ratio of the on-resistance values ​​from the first bypass switch (SS1) to the fourth bypass switch (SS4) is 1:2:4:8. In this embodiment, the on-resistance values ​​from the first bypass switch (SS1) to the fourth bypass switch (SS4) are set to 10 Ω, 20 Ω, 40 Ω, and 80 Ω. This can be achieved, for example, by configuring 128, 64, 32, or 16 parallel PMOS switches.

[0021] The trimming resistor group 32 will now be described. The trimming resistor group 32 includes eight resistors RT1 to RT8 and eight bypass switches ST1 to ST8. The resistors RT1 to RT8 are connected to the power supply voltage V DD The eighth resistor RT8 is connected in series between the first resistor RT1 and the connection node N3. DD Each of the bypass switches ST1 to ST8 is connected in parallel to each of the resistors RT1 to RT8.

[0022] The relationship between the resistance values ​​of the resistors RT1 to RT8 of the trimming resistor group 32 is similar to the relationship between the resistance values ​​of the resistors RS1 to RS4 of the aforementioned spread spectrum resistor group 33. In addition, the relationship between the on-resistance values ​​of the bypass switches ST1 to ST8 of the trimming resistor group 32 is similar to the relationship between the on-resistance values ​​of the bypass switches SS1 to SS4 of the aforementioned spread spectrum resistor group 33. That is, the ratio of the resistance values ​​from the first resistor (RT1) to the eighth resistor (RT8) is "1:2:4:8:16:32:64:128", and specific example values ​​are "59.25Ω, 118.5Ω, 237Ω, 474Ω, 948Ω, 1896Ω, 3792Ω, and 7584Ω". The ratio of the on-resistance values ​​from the first bypass switch (ST1) to the eighth bypass switch (ST8) is "1:2:4:8:16:32:64:128", and specific examples of the values ​​are "10Ω, 20Ω, 40Ω, 80Ω, 160Ω, 320Ω, 640Ω, 1280Ω." Note that the specific content of the trimming resistor group 32 is the same as that of the spread spectrum resistor group 33 described above, and therefore a detailed description thereof will be omitted.

[0023] The spread spectrum signal generation circuit 36 ​​will now be described. The spread spectrum signal generation circuit 36 ​​is a circuit that generates spread spectrum signals Q1 to Q4. The spread spectrum signals Q1 to Q4 are signals that fluctuate (jitter) the combined resistance value R33 of the spread spectrum resistor group 33 at a predetermined frequency by controlling the switching operation of each of the bypass switches SS1 to SS4. This achieves spectrum spreading. The spread spectrum signal generation circuit 36 ​​includes a frequency divider circuit 37 and an up / down counter 38. A first clock signal CLK1 and a signal CRB1 are input to the frequency divider circuit 37. The frequency divider circuit 37 outputs a frequency-divided clock signal CLK_D obtained by dividing the first clock signal CLK1.

[0024] The up / down counter 38 is an n-bit counter circuit having the same number of bits as the number of resistors in the spread spectrum resistor group 33. In this embodiment, the up / down counter 38 is a 4-bit counter circuit. The up / down counter 38 switches from counting up to counting down when the counter value reaches a maximum value, and switches from counting down to counting up when the counter value reaches a minimum value. The up / down counter 38 receives the divided clock signal CLK_D and the signal STB / CRB. The up / down counter 38 performs a count operation based on the divided clock signal CLK_D. The up / down counter 38 outputs spread spectrum signals Q1 to Q4, which are 4-bit counter values. The spread spectrum signals Q1 to Q4 are input to the bypass switches SS1 to SS4.

[0025] Each of the four bypass switches SS1 to SS4 is turned on and off based on the spread spectrum signals Q1 to Q4. That is, when the spread spectrum signals Q1 to Q4 are "1," the bypass switches SS1 to SS4 are in the "off" state. On the other hand, when the spread spectrum signals Q1 to Q4 are "0," the bypass switches SS1 to SS4 are in the "on" state. This allows the combined resistance value R33 of the spread spectrum resistor group 33 to be changed in 16 steps.

[0026] Specifically, the combined resistance value R33 is a maximum value R when all of the bypass switches SS1 to SS4 are off. max (888.75Ω), and when all are on, the minimum value R min When only the bypass switch SS4 of the most significant bit is on (i.e., when Q4, Q3, Q2, and Q1 are (0111)), the combined resistance value R33 is the median value R med (355Ω).

[0027] The circuit configuration of the frequency divider circuit 37 will be described using Figure 3. The frequency divider circuit 37 has a structure in which eight D flip-flops FF1 to FF8 are connected in series. A first clock signal CLK1 is input to the CLK terminal of the first-stage D flip-flop FF1. The Q output of each flip-flop is input to the CLK terminal of the next stage, and the QB output is input to the D terminal of the current stage. Furthermore, a signal CRB1 is input to the CRB terminal of each flip-flop. A frequency-divided clock signal CLK_D is output from the Q terminal of the eighth-stage D flip-flop FF8.

[0028] In the D flip-flops FF1 to FF8, the Q output of the next stage has a half period with respect to the Q output of the previous stage. Therefore, the frequency divider circuit 37 functions as an 8-stage frequency divider circuit. That is, the oscillation frequency f of the first clock signal CLK1 is OUT But 1 / 2 8 In this embodiment, the oscillation frequency f of the first clock signal CLK1 is OUT is 160MHz, and the oscillation frequency f of the divided clock signal CLK_D D is 0.625MHz.

[0029] The circuit configuration of the up / down counter 38 will be described with reference to Fig. 4. The up / down counter 38 includes a counter circuit 70 and a switching circuit 90.

[0030] The counter circuit 70 includes D-FF circuits 71 to 74, EX-OR circuits 75 to 80, and AND circuits 81 and 82. The frequency-divided clock signal CLK_D is input to the CLK terminals of the D-FF circuits 71 to 74. Each of the D-FF circuits 71 to 74 operates at the rising edge of the frequency-divided clock signal CLK_D. The signals STB / CRB are input to the STB terminals of the D-FF circuits 71 to 73 and the CRB terminal of the D-FF circuit 74. The QB terminal of the FF circuit 71 is connected to the D terminal of the D-FF circuit 71. The output terminals of the EX-OR circuits 77, 79, and 80 are connected to the D terminals of the D-FF circuits 72 to 74. Spread-spectrum signals Q1 to Q4 are output from the Q terminals of the D-FF circuits 71 to 74.

[0031] The EX-OR circuit 75 receives the spread spectrum signal Q1 and the switching signal CH_SIG. The EX-OR circuit 76 receives the spread spectrum signal Q2 and the switching signal CH_SIG. The EX-OR circuit 77 receives the output of the EX-OR circuit 75 and the spread spectrum signal Q2. The EX-OR circuit 78 receives the spread spectrum signal Q3 and the switching signal CH_SIG. The EX-OR circuit 79 receives the output of the AND circuit 81 and the spread spectrum signal Q3. The EX-OR circuit 80 receives the output of the AND circuit 82 and the spread spectrum signal Q4. The AND circuit 81 receives the output of the EX-OR circuit 75 and the output of the EX-OR circuit 76. The AND circuit 82 receives the output of the EX-OR circuit 78 and the output of the AND circuit 81.

[0032] The switching circuit 90 includes a NAND circuit 91, an OR circuit 92, an EX-OR circuit 93, and a D-FF circuit 94. The NAND circuit 91 and the OR circuit 92 receive the spread spectrum signals Q1 to Q4. The outputs of the NAND circuit 91 and the OR circuit 92 are received by the EX-OR circuit 93. The signal T_OR_B output from the EX-OR circuit 93 is received by the CLK terminal of the D-FF circuit 94. The QB terminal of the D-FF circuit 94 is connected to the D terminal of the D-FF circuit 94. The signals STB / CRB are received by the CRB terminal of the D-FF circuit 94. The Q terminal of the D-FF circuit 94 outputs a switching signal CH_SIG. The switching signal CH_SIG switches the operation of the counter circuit 70 between an up-counter and a down-counter.

[0033] The trimming signal generation circuit 35 will be described with reference to FIG. 2. The trimming signal generation circuit 35 is a circuit for adjusting (trimming) the combined resistance value R32 of the trimming resistor group 32. The trimming signal generation circuit 35 includes D-FF circuits D1 to D8. Trimming input signals IN1 to IN8 are input to each of the D-FF circuits D1 to D8. Trimming output signals OUT1 to OUT8 output from each of the D-FF circuits D1 to D8 are input to bypass switches ST1 to ST8. A trimming clock signal CLK_T and a reset signal CRB2 are input to each of the D-FF circuits D1 to D8 via signal lines (not shown).

[0034] Each of the eight bypass switches ST1 to ST8 is turned on and off based on the trimming output signals OUT1 to OUT8. That is, when the trimming output signals OUT1 to OUT8 are "1," the bypass switches ST1 to ST8 are in the "off" state. On the other hand, when the trimming output signals OUT1 to OUT8 are "0," the bypass switches ST1 to ST8 are in the "on" state. This allows the combined resistance value R32 of the trimming resistor group 32 to be changed in 256 steps.

[0035] (Overview of operation of oscillator circuit 1) An outline of frequency control in the FLL oscillator circuit 1 will be described. The first clock signal CLK1 output from the oscillator 40 via the level shift circuit 41 has an oscillation frequency f OUT This oscillation frequency f OUT is the control current I OSC The larger the value, the higher the control current I OSC In the frequency-voltage conversion circuit 10, the detection voltage V fV The detection voltage V fV is the oscillation frequency f OUT is a voltage that is inversely proportional to

[0036] Then, the operational amplifier 51 detects the detection voltage V fV is the reference voltage V refFeedback control is performed so that the oscillation frequency f OUT When the detection voltage V fV rises, the output voltage V of the operational amplifier 51 o (the gate voltage of the PMOSFET 52) decreases. As a result, the control current I OSC increases, and the oscillation frequency f OUT On the other hand, the oscillation frequency f OUT When the detection voltage V fV decreases, the output voltage V of the operational amplifier 51 o (the gate voltage of the PMOSFET 52) rises. As a result, the control current I OSC decreases, and the oscillation frequency f OUT This reduces the control current I OSC is stabilized, and the oscillation frequency f of the first clock signal CLK1 OUT As a result, the oscillation frequency f due to temperature changes, etc. OUT The variation in the

[0037] (Spread spectrum operation) The following describes the spread spectrum operation using the spread spectrum resistor group 33. As described above, the ratio of the resistance values ​​of the resistors RS1 to RS4 and the ratio of the on-resistance values ​​of the bypass switches SS1 to SS4 is 2 (n-1) In addition, the power supply voltage V DD The resistance value increases toward the left side. With this resistance value relationship, when the 4-bit values ​​of the spread spectrum signals Q1 to Q4 are increased sequentially, the combined resistance value R33 can be increased sequentially in equal steps. Also, when the 4-bit values ​​of the spread spectrum signals Q1 to Q4 are decreased sequentially, the combined resistance value R33 can be decreased sequentially in equal steps. In other words, the combined resistance value R33 can be changed in 16 steps in a linear manner (i.e., with a constant amount of change).

[0038] Specific operations will be described with reference to FIGS. 5 and 6. FIG. 5 is a timing chart of the up / down counter 38. FIG. 6 is a graph showing the time change of the combined resistance value R33. When the signal STB / CRB is 0V, the up / down counter 38 is in a standby state. In this state, the spread spectrum signals Q1 to Q3 are HI (power supply voltage V DD ), the spread spectrum signal Q4 becomes LO (0 V) (see time t0 in FIG. 5). That is, in the standby state, the combined resistance value R33 is the above-mentioned median value R med This becomes:

[0039] At time t1, the signal STB / CRB becomes HI and the up / down counter 38 starts to operate. Since the switching signal CH_SIG is LO (0V) at the start of operation, the up-counter operates from time t1 to time t2. Therefore, as shown in FIG. 6, the combined resistance value R33 is the median value R med to maximum value R max The LVDS increases linearly in equal steps up to

[0040] At time t2, when all of the spread spectrum signals Q1 to Q4 become HI, the output of the NAND circuit 91 becomes LO. Therefore, the signal T_OR_B output from the EX-OR circuit 93 rises (arrow Y1), and the switching signal CH_SIG switches to HI (arrow Y2). Therefore, at time t2, the up / down counter 38 switches to a down counter. Then, from time t2 to t3, the down counter operates. Therefore, as shown in FIG. 6, the combined resistance value R33 is equal to the maximum value R max to the minimum value R min The value decreases linearly in equal steps to

[0041] At time t3, when all of the spread spectrum signals Q1 to Q4 become LO, the output of the OR circuit 92 becomes LO. Therefore, the signal T_OR_B output from the EX-OR circuit 93 rises (arrow Y3), and the switching signal CH_SIG switches to LO (arrow Y4). Therefore, at time t3, the up / down counter 38 switches to an up-counter. Then, from time t3 to t4, the up-counter operates. Therefore, as shown in FIG. 6, the combined resistance value R33 is set to a minimum value R min to maximum value R max The operation thereafter is repeated, so a description thereof will be omitted.

[0042] 6, the combined resistance value R33 of the spread spectrum resistor group 33 can be varied to have a digital pseudo triangular wave. The spread spectrum resistor group 33 is included in the resistor group 31 of the variable resistor unit 30. Therefore, the combined resistance value of the variable resistor unit 30 can also be varied to have a pseudo triangular wave in the same way. The detection voltage V fV is the power supply voltage V DD Therefore, the detection voltage V fV The detection voltage V can be varied to have a pseudo-triangular waveform. fV According to the fluctuation of OSC As a result, as shown in FIG. 7, the oscillation frequency f of the first clock signal CLK1 can be varied. OUT , the target oscillation frequency f TA It can be varied to have a pseudo triangular wave around the center, thereby enabling spectrum spreading.

[0043] In addition, the oscillation frequency f OUT The fluctuation range VR of the target oscillation frequency f can be set in various ways. TA The tolerance was set at ±1%.

[0044] (Target oscillation frequency f TA (Setting operation) The target oscillation frequency f using the trimming resistor group 32 TA This setting operation can be performed, for example, when testing a semiconductor chip that includes the oscillator circuit 1, or when testing various devices incorporating the oscillator circuit 1 before shipping.

[0045] First, the signal STB / CRB is set to LO to put the up / down counter 38 into a standby state. As a result, as described above, the combined resistance value R33 of the spread spectrum resistor group 33 is set to the median value R med It can be made into.

[0046] Next, the D-FF circuits D1 to D8 in the trimming signal generating circuit 35 are reset to their initial values ​​using the reset signal CRB2. Then, the trimming input signals IN1 to IN8 are varied using a signal generating circuit (not shown). This allows the combined resistance value R32 of the trimming resistor group 32 to be adjusted (trimmed) in 256 steps. As a result, the detection voltage V fV By adjusting in 256 steps, the oscillation frequency f OUT can be adjusted in 256 steps. OUT is the target oscillation frequency f TA When an 8-bit value of the trimming input signals IN1 to IN8 that satisfies the above condition is found, the 8-bit value is stored in the trimming signal generation circuit 35 using the trimming clock signal CLK_T.

[0047] (effect) Conventionally, a technique using a triangular wave to spectrum-spread the oscillation frequency using an FLL is known. Another technique is known in which a triangular wave generating circuit (oscillating circuit) using an operational amplifier is used to generate a triangular wave. In this case, since an analog circuit is required, it is difficult to reduce the circuit area. Therefore, the technique of this specification allows the oscillation frequency f of the first clock signal CLK1 to be varied by varying the combined resistance value of the variable resistor section 30. OUTThe spread spectrum signal generating circuit 36 ​​(Figs. 3 and 4) for varying the combined resistance value can be configured with a digital circuit such as a logic circuit. Therefore, it is possible to reduce the circuit area compared to an oscillator circuit that performs spectrum spreading using an analog circuit.

[0048] Compared to digital circuits, analog circuits do not benefit as much from area reductions achieved through miniaturization. Therefore, it is difficult to reduce the circuit size of spread spectrum circuits using analog circuits such as operational amplifiers, even with each generation. On the other hand, the technology of this specification makes it possible to configure a spread spectrum circuit using a digital circuit. Therefore, the more miniaturization progresses with each generation, the more it becomes possible to reduce the circuit area.

[0049] The detection voltage V fV is the reference voltage V ref In the technology of this specification, feedback control is performed so that the detected voltage V fV and the reference voltage V ref Both are connected to a common power supply voltage V DD This generates the power supply voltage V DD Even when the detection voltage V fV and the reference voltage V ref This prevents fluctuations in the differential voltage between the output and the output, making it possible to further stabilize the oscillation operation of the FLL system.

[0050] Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives alone is technically useful.

[0051] (Variation) The spread spectrum signal generation circuit 36 ​​included in the variable resistance unit 30 may have various configurations. For example, the spread spectrum signal generation circuit 36 ​​may be a pseudorandom value generation circuit that updates an n-bit pseudorandom value based on the frequency-divided clock signal CLK_D. Furthermore, each of the n bypass switches SS1 to SSn may be configured to be capable of being turned on and off based on each bit of the n-bit pseudorandom value.

[0052] The various values ​​in this specification are merely examples and can be changed in various ways. For example, the number of resistors in the spread spectrum resistor group 33 and the number of bits of the spread spectrum signal are not limited to "4".

[0053] The trimming signal generation circuit 35 may have various configurations. For example, it may be configured to include an 8-bit up / down counter and sequentially update the trimming output signals OUT1 to OUT8 in accordance with the trimming clock signal CLK_T. This eliminates the need for the trimming input signals IN1 to IN8, allowing the trimming signal generation circuit 35 to be simplified.

[0054] The circuit configuration of the variable resistance section 30 is an example, and can be modified in various ways. For example, a fixed resistor or a variable resistor may be inserted on the connection path between the output node N1 and the switched capacitor section 20.

[0055] Control current I OSC is an example of a control signal. Power supply voltage V DD is an example of a predetermined voltage. The divided clock signal CLK_D is an example of a second clock signal.

[0056] Aspects of the present technology are listed below. [Aspect 1] an oscillator that receives a control signal and outputs a first clock signal having an oscillation frequency according to the control signal; a frequency-to-voltage conversion circuit that receives the first clock signal and outputs a detection voltage corresponding to the oscillation frequency; an operational amplifier to which the detection voltage and a reference voltage are input, and which outputs the control signal according to a difference voltage between the detection voltage and the reference voltage to the oscillator; An oscillator circuit comprising: the frequency-voltage conversion circuit further includes a variable resistor unit that generates the detection voltage by dividing a predetermined voltage, the variable resistor unit being configured to be able to vary its resistance value; Oscillator circuit. [Aspect 2] the variable resistance section includes a spread spectrum resistor group, the spread spectrum resistor group includes n first resistor units (n is a natural number equal to or greater than 1) connected in series, and n first bypass switches arranged in parallel with each of the n first resistor units, The resistance value of the n-th first resistor section is twice the resistance value of the first first resistor section. (n-1) 2. The oscillator circuit of claim 1, wherein the oscillation frequency is 1. [Aspect 3] the n-th first resistor unit is connected to the predetermined voltage side, 3. The oscillation circuit according to aspect 2, wherein the detection voltage is output from an output terminal of a first first resistor unit. [Aspect 4] The on-resistance value of the n-th first bypass switch is 2 times the on-resistance value of the first first bypass switch. (n-1) 3. The oscillator circuit of claim 2, wherein the oscillation frequency is 1.2 kHz. [Aspect 5] the variable resistance unit further includes an n-bit counter circuit having the same number of bits as the number of the first resistance units, the counter circuit performing a count operation based on a second clock signal having a frequency different from the first clock signal, and outputting an n-bit counter value; each of the n first bypass switches is configured to be capable of being turned on and off based on each bit of the n-bit counter value; 3. The oscillator circuit of claim 2, wherein the counter circuit switches from counting up to counting down when the counter value reaches a maximum value, and switches from counting down to counting up when the counter value reaches a minimum value. [Aspect 6] 6. The oscillation circuit according to claim 5, wherein the second clock signal is a signal obtained by dividing the frequency of the first clock signal. [Aspect 7] the variable resistance unit further includes a pseudo-random value generation circuit that updates an n-bit pseudo-random value based on a second clock signal having a frequency different from that of the first clock signal; 3. The oscillation circuit of claim 2, wherein each of the n first bypass switches is configured to be capable of being turned on and off based on each bit of the n-bit pseudorandom value. [Aspect 8] 8. The oscillation circuit according to claim 7, wherein the second clock signal is a signal obtained by dividing the frequency of the first clock signal. [Aspect 9] the variable resistor section further includes a trimming resistor group connected in series with the spread spectrum resistor group, the trimming resistor group includes m second resistor units (m is a natural number equal to or greater than 1) connected in series, and m second bypass switches arranged in parallel with each of the m second resistor units, The resistance value of the m-th second resistor section is twice the resistance value of the first second resistor section. (m-1) 3. The oscillator circuit of claim 2, wherein the oscillation frequency is 1.2 kHz. [Aspect 10] 10. The oscillation circuit according to aspect 9, wherein the m-th second resistor section is connected to the predetermined voltage side. [Aspect 11] The on-resistance value of the m-th second bypass switch is 2 times the on-resistance value of the first second bypass switch. (m-1) 11. The oscillator circuit of claim 9 or 10, wherein the oscillation circuit is a multiple of the oscillation circuit. [Aspect 12] the variable resistance unit further includes a trimming circuit configured to be able to control the on / off operation of each of the m second bypass switches, The trimming circuit adjusts the combined resistance value of the trimming resistor group to 2 m 12. The oscillator circuit of any one of aspects 9-11, wherein the oscillation circuit is adjustable in stages. [Aspect 13] the frequency-voltage conversion circuit includes a switched capacitor unit that performs a switching operation based on the first clock signal; 13. The oscillation circuit according to any one of aspects 1 to 12, wherein the detection voltage is generated by dividing the predetermined voltage using the switched capacitor unit and the variable resistor unit. [Aspect 14] 14. The oscillation circuit according to any one of aspects 1 to 13, wherein the reference voltage is a divided voltage of the predetermined voltage. [Explanation of symbols]

[0057] 1: Oscillator circuit 10: Frequency-to-voltage conversion circuit 20: Switched capacitor section 30: Variable resistor section 40: Oscillator 50: Differential voltage-to-current conversion circuit 51: Operational amplifier CLK1: First clock signal f OUT : Oscillation frequency V fV :Detection voltage V DD : Power supply voltage V ref : Reference voltage

Claims

1. an oscillator that receives a control signal and outputs a first clock signal having an oscillation frequency according to the control signal; a frequency-to-voltage conversion circuit that receives the first clock signal and outputs a detection voltage corresponding to the oscillation frequency; an operational amplifier to which the detection voltage and a reference voltage are input, and which outputs the control signal according to a difference voltage between the detection voltage and the reference voltage to the oscillator; An oscillator circuit comprising: the frequency-voltage conversion circuit further includes a variable resistor unit that generates the detection voltage by dividing a predetermined voltage, the variable resistor unit being configured to be able to vary its resistance value; Oscillator circuit.

2. the variable resistance section includes a spread spectrum resistor group, the spread spectrum resistor group includes n first resistor units (n is a natural number equal to or greater than 1) connected in series, and n first bypass switches arranged in parallel with each of the n first resistor units, The resistance value of the n-th first resistor section is twice the resistance value of the first first resistor section. （ｎ－１） 2. The oscillator circuit of claim 1, wherein the oscillation frequency is 1.0 kHz.

3. the n-th first resistor unit is connected to the predetermined voltage side, 3. The oscillation circuit according to claim 2, wherein the detection voltage is output from an output terminal of a first first resistor section.

4. The on-resistance value of the n-th first bypass switch is 2 times the on-resistance value of the first first bypass switch. （ｎ－１） 3. The oscillator circuit of claim 2, wherein the oscillation frequency is 1.0 kHz.

5. the variable resistance unit further includes an n-bit counter circuit having the same number of bits as the number of the first resistance units, the counter circuit performing a count operation based on a second clock signal having a frequency different from the first clock signal, and outputting an n-bit counter value; each of the n first bypass switches is configured to be capable of being turned on and off based on each bit of the n-bit counter value; 3. The oscillator circuit according to claim 2, wherein the counter circuit switches from counting up to counting down when the counter value reaches a maximum value, and switches from counting down to counting up when the counter value reaches a minimum value.

6. 6. The oscillation circuit according to claim 5, wherein the second clock signal is a signal obtained by dividing the frequency of the first clock signal.

7. the variable resistance unit further includes a pseudo-random value generation circuit that updates an n-bit pseudo-random value based on a second clock signal having a frequency different from that of the first clock signal; 3. The oscillation circuit according to claim 2, wherein each of the n first bypass switches is configured to be capable of being turned on and off based on each bit of the n-bit pseudorandom value.

8. 8. The oscillation circuit according to claim 7, wherein the second clock signal is a signal obtained by dividing the frequency of the first clock signal.

9. the variable resistor section further includes a trimming resistor group connected in series with the spread spectrum resistor group, the trimming resistor group includes m second resistor units (m is a natural number equal to or greater than 1) connected in series, and m second bypass switches arranged in parallel with each of the m second resistor units, The resistance value of the m-th second resistor section is twice the resistance value of the first second resistor section. （ｍ－１） 3. The oscillator circuit of claim 2, wherein the oscillation frequency is 1.0 kHz.

10. The oscillation circuit according to claim 9 , wherein the mth second resistor section is connected to the predetermined voltage side.

11. The on-resistance value of the m-th second bypass switch is 2 times the on-resistance value of the first second bypass switch. （ｍ－１） 10. The oscillator circuit of claim 9, wherein the oscillation frequency is 100 kHz.

12. the variable resistance unit further includes a trimming circuit configured to be able to control the on / off operation of each of the m second bypass switches, The trimming circuit adjusts the combined resistance value of the trimming resistor group to 2 ｍ 10. The oscillator circuit of claim 9, wherein the oscillator circuit is adjustable in steps.

13. the frequency-voltage conversion circuit includes a switched capacitor unit that performs a switching operation based on the first clock signal; 13. The oscillation circuit according to claim 1, wherein the detection voltage is generated by dividing the predetermined voltage by the switched capacitor section and the variable resistor section.

14. 13. The oscillation circuit according to claim 1, wherein the reference voltage is a divided voltage of the predetermined voltage.

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