Field-effect transistor

Abstract

To provide a field-effect transistor capable of improving the maximum available power gain.SOLUTION: In a field-effect transistor 1, multiple unit transistors are arranged side by side in a direction d1, and each has a source electrode S, a drain electrode D, and a gate electrode 4. A gate wiring 10 extends in the direction d1 and connects the multiple gate electrodes 4. A signal input electrode G1 is connected to the gate wiring 10. At least one impedance element 18a is connected between the gate wiring 10 and the signal input electrode G1. The connection position of the impedance element 18a to the gate wiring 10 is closer to one end of the gate wiring 10 in the direction d1 than the signal input electrode G1.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to high frequency field effect transistors (FETs). [Background technology]

[0002] In recent years, wireless communication systems and wireless power transmission systems have been developed. These systems require high-frequency amplifier elements. For example, Patent Document 1 discloses a high-frequency multi-finger type MOSFET. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-16686 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional field-effect transistors, the more fingers there are, the lower the maximum available power gain (MAG) at high frequencies. It is therefore desirable to improve the MAG.

[0005] The present disclosure has been made in view of the above problems, and one of its exemplary purposes is to provide a field effect transistor that can improve the maximum available power gain. [Means for solving the problem]

[0006] In order to solve the above problems, a field effect transistor according to one embodiment of the present disclosure comprises a plurality of unit transistors arranged in a line in one direction, each having a source electrode, a drain electrode, and a gate electrode; a gate wiring extending in one direction and connecting the plurality of gate electrodes; a signal input electrode connected to the gate wiring; and at least one impedance element connected between the gate wiring and the signal input electrode, the connection position of which is closer to one end of the gate wiring in one direction than the signal input electrode.

[0007] Any combination of the above components, or mutual substitution of the components or expressions of the present disclosure between methods, systems, etc., are also valid aspects of the present disclosure. [Effects of the Invention]

[0008] According to the present disclosure, a field effect transistor capable of improving the maximum available power gain can be provided. [Brief explanation of the drawings]

[0009] [Figure 1] 1(a) and 1(b) are plan views showing the configuration of a field effect transistor of a comparative example. [Figure 2] FIG. 10 is a diagram showing the frequency dependence of MAG in a field effect transistor of a comparative example. [Figure 3] 1 is a plan view showing a configuration of a field effect transistor according to an embodiment; [Figure 4] 10A and 10B are diagrams showing simulation results of high-frequency characteristics of the field-effect transistor of the embodiment and the field-effect transistor of the comparative example; [Figure 5] FIG. 10 is a plan view showing another configuration example of the field effect transistor according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] The present inventors have conducted research into field-effect transistors for high frequencies in the microwave and millimeter-wave bands and have come to the following conclusions. Figures 1(a) and 1(b) are plan views showing the configuration of a comparative field-effect transistor 100. The field-effect transistor 100 is disposed on a semiconductor substrate (not shown) and has a multi-finger structure consisting of multiple unit transistors 2 connected in parallel.

[0011] 1(a) shows a configuration in which a via 20 is provided in the source electrode S of each of multiple unit transistors 2. The via 20 is connected to a ground conductor (not shown) on the back surface of the semiconductor substrate. FIG. 1(b) shows a configuration in which a via 20 is provided in the source electrode S of each of unit transistors 2 at both ends, and these two source electrodes S are connected by a connecting conductor 24 such as an air bridge. The source electrodes S of unit transistors 2 other than those at both ends are also connected to the connecting conductor 24.

[0012] 1(a) and 1(b) show an example in which the number of unit transistors 2 connected in parallel is 10. The number of parallel connections can also be called the number of gate fingers. Each of the unit transistors 2 has a gate electrode 4, a source electrode S, and a drain electrode D. The gate electrode 4 can also be called a gate finger.

[0013] One end of each of the multiple gate electrodes 4 is connected to a gate wiring 10 extending in one direction d1. A signal input electrode G1 is connected to the gate wiring 10. The width of the gate electrode 4 is defined as a gate finger width Wg. The field effect transistor 100 has a known configuration, and therefore further detailed description will be omitted.

[0014] FIG. 2 shows the frequency dependence of MAG in a field-effect transistor 100 of a comparative example. In this example, the field-effect transistor 100 is a HEMT (High Electron Mobility Transistor). FIG. 2 shows simulation results for GaN HEMTs with a gate length of 0.15 μm, a gate finger width Wg=50 μm, and a parallel number of 2, 6, or 10. These simulation results were obtained by simulation using an equivalent circuit model created from measured values ​​of a GaN HEMT with a parallel number of "2." The bias conditions during HEMT measurement were Vds=28 V and Ids=50 mA / mm. In the simulation circuit, the gate wiring 10 was used as a transmission line.

[0015] As shown in FIG. 2, in the field effect transistor 100 of the comparative example, in a high frequency band of, for example, approximately 40 GHz or higher, the MAG decreases as the number of unit transistors 2 connected in parallel increases.

[0016] After much consideration and analysis, the inventors have found that one of the main reasons for the phenomenon in which MAG decreases as the number of unit transistors 2 connected in parallel increases is that the behavior of the gate wiring 10 as a distributed constant line becomes more apparent as the number of parallel connections increases, i.e., the longer the gate wiring 10 becomes.

[0017] Based on these findings, the inventors conducted further research and discovered that by connecting an impedance element to the gate wiring 10, it is possible to effectively utilize the behavior of the gate wiring 10 as a distributed constant line and improve MAG in a predetermined frequency band. The present embodiment was devised based on these findings, and its specific configuration will be described below.

[0018] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the description, the same elements are denoted by the same reference numerals, and duplicate descriptions will be omitted as appropriate.

[0019] 3 is a plan view showing the configuration of a field effect transistor 1 according to an embodiment of the present invention. The field effect transistor 1 can be used as an amplifying element in, for example, a power amplifier or a low noise amplifier.

[0020] The field-effect transistor 1 includes a first unit transistor 2a, a second unit transistor 2b, a third unit transistor 2c, a fourth unit transistor 2d, a fifth unit transistor 2e, a sixth unit transistor 2f, a seventh unit transistor 2g, an eighth unit transistor 2h, a ninth unit transistor 2i, a tenth unit transistor 2j, a gate wiring 10, a signal input electrode G1, a signal output electrode D1, a connecting conductor 24, an impedance element 18a, and an impedance element 18b. Hereinafter, the first unit transistor 2a through the tenth unit transistor 2j will be collectively referred to as the "unit transistors 2." Hereinafter, the impedance elements 18a and 18b will be collectively referred to as the "impedance elements 18." The configuration other than the impedance element 18 is the same as in the comparative example of FIG. 1(b), but other field-effect transistor configurations may also be used. The number of unit transistors 2 connected in parallel is "10" in the example of FIG. 3, but any number may be used. The unit transistor 2 can also be called a unit cell.

[0021] The field-effect transistor 1 has a multi-finger structure consisting of multiple unit transistors 2 connected in parallel. The multiple unit transistors 2 are arranged side by side in a direction d1 on a semiconductor substrate (not shown). The direction d1 is along the surface of the semiconductor substrate. The impedance element 18 is also arranged on the semiconductor substrate. The semiconductor substrate is not particularly limited, and may be, for example, a semiconductor substrate such as silicon, a compound semiconductor substrate, or a substrate including a compound semiconductor layer. The compound semiconductor is not particularly limited, and may be, for example, gallium arsenide (GaAs) or a nitride semiconductor such as gallium nitride (GaN). The field-effect transistor 1 is not particularly limited, and may be, for example, a high electron mobility transistor using gallium nitride, i.e., a GaN HEMT.

[0022] Each of the plurality of unit transistors 2 has a gate electrode 4, a source electrode S, and a drain electrode D.

[0023] The plurality of source electrodes S each extend in a direction d2, which is perpendicular to the direction d1 and extends along the surface of the semiconductor substrate.

[0024] The source electrode S at one end is connected to a via 20a. The via 20a is connected to a ground conductor (not shown) formed on the back surface of the semiconductor substrate. The source electrode S at the other end is connected to a via 20b. The via 20b is connected to the ground conductor.

[0025] These source electrodes S at both ends are connected by a connecting conductor 24 such as an air bridge. The source electrodes S of the unit transistors 2 other than those at both ends are also connected to the connecting conductor 24. In other words, the multiple source electrodes S are grounded. The connecting conductor 24 spans multiple unit transistors 2, but for clarity of illustration, FIG. 3 shows the state in which the connecting conductor 24 has been removed. Note that the multiple source electrodes S do not have to be grounded.

[0026] Each of the drain electrodes D extends in a direction d2. One end of each of the drain electrodes D is connected to a signal output electrode D1, which serves as a drain terminal, via an electrode extending in a direction d1. The signal output electrode D1 outputs a high-frequency signal.

[0027] Each of the gate electrodes 4 extends in direction d2. The gate wiring 10 extends in direction d1 and connects one end of each of the gate electrodes 4. In other words, the gate wiring 10 and the gate electrodes 4 form a comb-shaped gate electrode portion.

[0028] In the gate wiring 10, the portion that connects two adjacent gate electrodes 4 is called a gate connection portion. The gate connection portion can also be called a gate feed portion. In the example of Figure 3, each of the multiple gate connection portions has the same length.

[0029] A signal input electrode G1, which is a gate terminal, is connected to the gate wiring 10. A high-frequency signal is input to the signal input electrode G1. The signal input electrode G1 is connected between both ends of the gate wiring 10 in one direction d1. Here, the signal input electrode G1 is connected to the center of the gate wiring 10 in one direction d1.

[0030] One impedance element 18a is connected between one end of the gate wiring 10 in one direction d1 and the signal input electrode G1. The other impedance element 18b is connected between the other end of the gate wiring 10 and the signal input electrode G1. The two impedance elements 18 are arranged on both sides of the signal input electrode G1. The two impedance elements 18 may have the same configuration and the same impedance.

[0031] The impedance of the impedance element 18 as viewed from the connection point between the gate wiring 10 and the impedance element 18 is capacitive or inductive in the frequency band of the input signal to the signal input electrode G1. The impedance of the impedance element 18 is determined so that the maximum available power gain MAG of the field-effect transistor 1 has an upwardly convex frequency dependence in the frequency band of the input signal. Furthermore, the impedance of the impedance element 18 is an open circuit impedance in DC, i.e., is substantially infinite.

[0032] The impedance element 18a includes a transmission line 14a and a capacitance element 16a, which are connected in series between one end of the gate wiring 10 and the signal input electrode G1.

[0033] The transmission line 14a includes a transmission line 141a and a transmission line 142a. The transmission line 141a has one end connected to one end of the gate wiring 10, and the other end. The transmission line 141a extends in direction d2 from one end of the gate wiring 10. The transmission line 142a has one end connected to the signal input electrode G1, and the other end. The transmission line 142a extends in one direction d1 from the signal input electrode G1.

[0034] The capacitive element 16a is, for example, a MIM (Metal-Insulator-Metal) capacitor, and is connected between the other end of the transmission line 141a and the other end of the transmission line 142a. For example, an upper electrode of the capacitive element 16a is connected to the other end of the transmission line 142a, and a lower electrode of the capacitive element 16a is connected to the other end of the transmission line 141a.

[0035] The impedance element 18b includes a transmission line 14b and a capacitance element 16b, which are connected in series between the other end of the gate wiring 10 and the signal input electrode G1.

[0036] The transmission line 14b includes a transmission line 141b and a transmission line 142b. The transmission line 141b has one end connected to the other end of the gate wiring 10, and the other end. The transmission line 141b extends in direction d2 from the other end of the gate wiring 10. The transmission line 142b has one end connected to the signal input electrode G1, and the other end. The transmission line 142b is connected to the signal input electrode G1 on the opposite side from the connection position of the transmission line 142a. The transmission line 142b extends in one direction d1 from the signal input electrode G1.

[0037] The capacitive element 16b is, for example, an MIM capacitor, and is connected between the other end of the transmission line 141b and the other end of the transmission line 142b.

[0038] Hereinafter, transmission line 14a and transmission line 14b will be collectively referred to as "transmission line 14" where appropriate. Capacitance element 16a and capacitance element 16b will be collectively referred to as "capacitance element 16" where appropriate. The "length of transmission line 14" refers to the sum of the lengths of transmission lines 141a and 142a that constitute impedance element 18a, and the sum of the lengths of transmission lines 141b and 142b that constitute impedance element 18b.

[0039] The width and length of the transmission line 14 and the capacitance of the capacitive element 16 can be determined appropriately by experiment or simulation so that MAG becomes a desired value in the frequency band of the input signal. When the transmission line 14 and the capacitive element 16 are connected by a via (not shown), the inductance of the via may be included in the length of the transmission line 14.

[0040] The impedance of the impedance element 18 is not particularly limited, but for example, the absolute value of the impedance may be 0Ω or more and 10 kΩ or less in the frequency band of the input signal.

[0041] Next, we will explain the simulation results of the field-effect transistor 1. In the simulation circuit, the gate wiring 10 is represented by a distributed constant line in which multiple transmission lines are connected in series. One transmission line corresponds to one gate connection part of the gate wiring 10.

[0042] The input signal voltage of signal input electrode G1 is Vo. The voltage at one end of gate electrode 4 of fifth unit transistor 2e is V1. The voltage at one end of gate electrode 4 of fourth unit transistor 2d is V2. The voltage at one end of gate electrode 4 of third unit transistor 2c is V3. The voltage at one end of gate electrode 4 of second unit transistor 2b is V4. The voltage at one end of gate electrode 4 of first unit transistor 2a is V5. Voltages V1 to V5 are the voltages at each position within gate wiring 10.

[0043] The arrangement of the gate wiring 10 and the multiple unit transistors 2 is symmetrical with respect to the signal input electrode G1. Therefore, the voltage at one end of the gate electrode 4 of the sixth unit transistor 2f is equal to voltage V1, and similarly, the voltages at one end of the gate electrodes 4 of the seventh, eighth, ninth, and tenth unit transistors 2g, 2h, 2i, and 2j are equal to voltages V2, V3, V4, and V5, respectively. Therefore, the simulation results for voltages V1 to V5 will be explained below.

[0044] FIG. 4 shows simulation results of the high-frequency characteristics of the field-effect transistor 1 of the embodiment and the field-effect transistor 100 of the comparative example. Specifically, FIG. 4 shows simulation results of the frequency characteristics of the MAG of the embodiment and the comparative example, and the frequency characteristics of the normalized average voltage Vavn obtained by normalizing the average value Vav of the voltages V1 to V5 in the gate wiring 10 of the embodiment and the comparative example by the input signal voltage Vo. The simulations of the embodiment and the comparative example differ in the presence or absence of two impedance elements 18, but the other conditions are the same. The number of unit transistors 2 connected in parallel is "10". The normalized average voltage Vavn is expressed by the following equation (1). In the example of FIG. 4, n=5 in equation (1).

[0045]

number

[0046] As shown in FIG. 4, the MAG is improved compared to the comparative example in the frequency range from around 64 GHz to around 85 GHz. For example, at around 70 GHz, where the MAG is 0 dB in the comparative example, the MAG is improved to approximately 6.4 dB in the embodiment. The MAG in the embodiment has an upwardly convex frequency dependence at least in the frequency range higher than around 64 GHz. The MAG having an upwardly convex frequency dependence indicates that there is a region in which the MAG increases as the frequency increases. For example, the MAG at 70 GHz is larger than the MAG at 64 GHz. In the example of FIG. 4, the lower limit frequency of the frequency band of the input signal to the signal input electrode G1 is around 64 GHz. Furthermore, in the embodiment, the normalized average voltage Vavn of voltages V1 to V5 is larger than that of the comparative example in the frequency range higher than around 64 GHz.

[0047] The frequency at which the magnitude relationship of MAG reverses between the comparative example and the embodiment and the frequency at which the magnitude relationship of normalized average voltage Vavn of voltages V1 to V5 reverses between the comparative example and the embodiment are approximately 64 GHz, which is roughly the same. This shows that an increase in normalized average voltage Vavn of voltages V1 to V5 contributes to an improvement in MAG.

[0048] The output signal current is the product of the input voltages V1, V2, V3, V4, and V5 to each unit transistor 2 multiplied by the transconductance of the unit transistor 2, so the normalized average voltage Vavn and the output signal current are proportional. Because standing waves of signal voltages exist within the gate wiring 10, the input voltages V1, V2, V3, V4, and V5 are distributed. In other words, setting the impedance of the impedance element 18 so that the normalized average voltage Vavn is large in a given signal frequency band improves the maximum available power gain MAG. Because the impedance of the impedance element 18 is frequency-dependent, even if the normalized average voltage Vavn reaches a maximum at a certain frequency, it usually does not reach a maximum at a different frequency. This embodiment is characterized by the fact that the maximum available power gain MAG peaks in the signal frequency band, i.e., exhibits a convex frequency dependency. Thus, maximizing the normalized average voltage Vavn enhances the effect of this embodiment over the comparative example.

[0049] Although not shown, the MAG is also improved compared to the comparative example when the length of the transmission line 14 is changed under the same conditions as in Fig. 4. By adjusting the length of the transmission line 14, the frequency range in which the MAG is improved can be adjusted.

[0050] As described above, according to the embodiment, the impedance element 18 connected between the gate wiring 10 and the signal input electrode G1 can cause the voltage distribution in the gate wiring 10 to differ from that of the comparative example. This makes it possible to increase the normalized average voltage Vavn of the gate voltages input to the gate electrodes 4 of multiple unit transistors 2 in a predetermined frequency band compared to the comparative example. This therefore makes it possible to increase MAG in a predetermined frequency band compared to the comparative example. The greater the number of unit transistors 2 connected in parallel, the greater the improvement in MAG compared to the comparative example.

[0051] By using the transmission line 14 and the capacitance element 16 connected in series as the impedance element 18, the capacitance element 16 can be used to adjust the imaginary part of the impedance of the impedance element 18, thereby expanding the impedance adjustment range of the impedance element 18 and effectively increasing MAG. Here, if a transmission line 14 with a physical length shorter than the distance between the signal input electrode G1 and one end of the gate wiring 10 is required, it is difficult to physically connect it using only the transmission line 14. In this case, by using the capacitance element 16 to return the phase of the reflection coefficient, the transmission line 14 can be lengthened, making it physically possible to connect it. In this way, using the capacitance element 16 can also alleviate restrictions on the length of the transmission line 14.

[0052] Furthermore, if the absolute value of the impedance of the impedance element 18 is 0Ω or more and 10 kΩ or less in the frequency band of the input signal, the MAG can be increased more effectively.

[0053] The inventors believe that it is extremely difficult to improve MAG by, for example, about 5 dB by improving semiconductor process technology, such as by shortening the gate length. Improving semiconductor process technology requires a great deal of cost and time. In contrast, in the present embodiment, MAG can be improved by, for example, several dB simply by adding impedance element 18 to an existing field-effect transistor using existing semiconductor process technology, thereby suppressing cost increases and eliminating the need for a long development period.

[0054] Next, various configuration examples of the impedance element 18 will be described below. Any configuration can be adopted for the impedance element 18 as long as it can achieve the desired impedance. The following description will focus on differences from the configuration in FIG.

[0055] For example, the position of the capacitive element 16 may be closer to the signal input electrode G1 than in the example of Fig. 3. In other words, the length of one of the transmission lines 141a and 141b may be made longer, and the length of the other of the transmission lines 142a and 142b may be made shorter.

[0056] Furthermore, one of the transmission lines 141a, 141b in the impedance element 18 may be omitted, and the lower electrode of the capacitance element 16 may be directly connected to one end or the other end of the gate wiring 10. Alternatively, when the capacitance element 16 is disposed adjacent to the signal input electrode G1, the other of the transmission lines 142a, 142b may be omitted, and the upper electrode of the capacitance element 16 may be directly connected to the signal input electrode G1.

[0057] Furthermore, an inductor element may be connected in place of one of the transmission lines 142a, 142b in the impedance element 18. That is, the impedance element 18 may have an inductor element and a capacitance element 16 connected between the gate wiring 10 and the signal input electrode G1. The capacitance element 16 may be connected to the signal input electrode G1, and the inductor element may be connected to the gate wiring 10. The inductor element may be formed in a spiral shape or a meander shape on the semiconductor substrate 30.

[0058] According to these configuration examples, the degree of freedom in the configuration of the field effect transistor 1 can be improved.

[0059] Furthermore, as shown in Fig. 5, the capacitance element 16 may not be provided, and the impedance element 18 may be configured by a transmission line 14. Fig. 5 is a plan view showing another example of the configuration of the field-effect transistor 1 according to the embodiment.

[0060] The transmission line 14a has one end connected to one end of the gate wiring 10 and the other end connected to the signal input electrode G1. The transmission line 14b has one end connected to the other end of the gate wiring 10 and the other end connected to the signal input electrode G1. The transmission line 14 has an L-shape in plan view. The shape of the transmission line 14 in plan view can be determined appropriately depending on the required length of the transmission line 14. In this configuration example, the impedance of the impedance element 18 is not an open impedance in DC. In the configuration of FIG. 5, both ends of the impedance element 18 are at the same DC potential, so it does not affect the bias state of the field-effect transistor 1. In this configuration example, the impedance element 18 is formed using the transmission line 14 and does not use the capacitance element 16, thereby achieving a small and simple configuration of the impedance element 18.

[0061] Alternatively, the transmission line 14 may be omitted, and the capacitance element 16 may be directly connected between one end or the other end of the gate wiring 10 and the signal input electrode G1. That is, the impedance element 18 may be the capacitance element 16. In this case, the capacitance element 16 may be L-shaped in plan view. That is, the upper and lower electrodes of the capacitance element 16 each have an L-shape. Alternatively, a rectangular, elongated capacitance element 16 may be used, and one end or the other end of the gate wiring 10 may be linearly connected to the signal input electrode G1. For example, one end of the lower electrode of the capacitance element 16 may be directly connected to one end or the other end of the gate wiring 10, and one end of the upper electrode of the capacitance element 16 may be directly connected to the signal input electrode G1. This configuration example improves the flexibility of the configuration of the field-effect transistor 1.

[0062] Furthermore, in the configurations of Figures 3 and 5, one impedance element 18 is connected to each end of the gate wiring 10 in the longitudinal direction, but this is not limited to this, and the number of impedance elements 18 and their connection positions to the gate wiring 10 may be determined so as to obtain desired high-frequency characteristics.

[0063] 3 and 5, the gate wiring 10 is disposed at the end of multiple unit transistors 2, providing a high degree of freedom in the area in which the impedance elements 18 are disposed. This also provides a high degree of freedom in the number of impedance elements 18 and their connection positions to the gate wiring 10. This also provides a high degree of freedom in setting the frequency characteristics of the impedance elements 18, i.e., in the circuit configuration of the impedance elements 18. For example, the impedance elements 18 may be configured and their connection positions to the gate wiring 10 may be set so as to obtain desired high-frequency characteristics, such as significantly reducing MAG in a specific frequency band while improving MAG in a desired frequency band.

[0064] For example, each of the two impedance elements 18 may be connected to the gate line 10 at a position closer to the signal input electrode G1, rather than at both ends of the gate line 10.

[0065] It is also possible to omit one of the two impedance elements 18. In this case, one impedance element 18 may be connected to one end of the gate wiring 10, or may be connected to the gate wiring 10 at a position closer to the signal input electrode G1.

[0066] Alternatively, a plurality of impedance elements 18 may be connected in parallel between the signal input electrode G1 and the gate wiring 10 on at least one of both sides of the signal input electrode G1. That is, the field effect transistor 1 may include three or more impedance elements 18. The connection positions of the plurality of impedance elements 18 to the gate wiring 10 may be different. The connection positions of the plurality of impedance elements 18 to the signal input electrode G1 may be the same or different.

[0067] In this way, the field-effect transistor 1 may include at least one impedance element 18 that is connected between the gate wiring 10 and the signal input electrode G1 and whose connection position to the gate wiring 10 is closer to one end of the gate wiring 10 in one direction d1 than the signal input electrode G1. In this case, one of the at least one impedance element 18 may be connected between one end of the gate wiring 10 and the signal input electrode G1.

[0068] The field-effect transistor 1 may further include at least one other impedance element 18 that is connected between the gate wiring 10 and the signal input electrode G1 and whose connection position to the gate wiring 10 is closer to the other end of the gate wiring 10 than the signal input electrode G1. In this case, one of the at least one other impedance element 18 may be connected between the other end of the gate wiring 10 and the signal input electrode G1.

[0069] The connection positions of the multiple impedance elements 18 to the gate wiring 10 may be symmetrical or asymmetrical with respect to the signal input electrode G1. When connected to asymmetrical positions, the number of impedance elements 18 may differ on both sides of the signal input electrode G1.

[0070] When a plurality of impedance elements 18 are provided, the impedances of the impedance elements 18 may be different from each other so as to obtain desired high frequency characteristics.

[0071] Furthermore, the signal input electrode G1 does not have to be connected to the center of the gate line 10 in one direction d1, and may be connected to the gate line 10 at a position shifted in one direction d1 from the center.

[0072] The number of impedance elements 18 and the connection positions of the impedance elements 18 to the gate wiring 10 and the signal input electrode G1 can be determined appropriately through experiments or simulations so as to obtain desired high frequency characteristics.

[0073] These configurations also enable an improvement in MAG compared to the comparative example, and also increase the degree of freedom in the configuration of the field-effect transistor 1.

[0074] The present disclosure has been described above based on the embodiments. It will be understood by those skilled in the art that the present disclosure is not limited to the above embodiments, that various design changes are possible, and that various modifications are possible, and that such modifications are also within the scope of the present disclosure.

[0075] An overview of one aspect of the present disclosure is as follows: A field-effect transistor according to an aspect of the present disclosure includes: a plurality of unit transistors arranged side by side in one direction, each having a source electrode, a drain electrode, and a gate electrode, a gate wiring extending in the one direction and connecting the plurality of gate electrodes, a signal input electrode connected to the gate wiring, and at least one impedance element connected between the gate wiring and the signal input electrode, the connection position of which to the gate wiring being closer to one end of the gate wiring in the one direction than the signal input electrode.

[0076] According to this embodiment, the maximum available power gain can be improved in a predetermined frequency band.

[0077] One of the at least one impedance element may be connected between one end of the gate wiring and the signal input electrode, in which case the maximum available power gain can be further improved.

[0078] The signal input electrode may be connected between both ends of the gate wiring in the one direction. The field-effect transistor may further include at least one other impedance element connected between the gate wiring and the signal input electrode, and connected to the gate wiring at a position closer to the other end of the gate wiring than the signal input electrode. In this case, the maximum available power gain can be further improved.

[0079] One of the at least one impedance element may be connected between one end of the gate wiring and the signal input electrode, and another of the at least one impedance element may be connected between the other end of the gate wiring and the signal input electrode, in which case the maximum available power gain can be further improved.

[0080] The impedance element may be a capacitance element connected between the gate wiring and the signal input electrode, which improves the degree of freedom in the configuration of the field effect transistor.

[0081] The impedance element may be a transmission line connected between the gate wiring and the signal input electrode, in which case the impedance element can be realized with a small and simple configuration.

[0082] The impedance element may include a transmission line and a capacitance element connected in series between the gate wiring and the signal input electrode, which effectively increases the maximum available power gain in a predetermined frequency band.

[0083] The impedance element may include an inductor element and a capacitor element connected between the gate wiring and the signal input electrode, which improves the degree of freedom in the configuration of the field effect transistor.

[0084] The impedance of the impedance element may be an open circuit impedance in a direct current. In this case, the impedance element may include a capacitive element.

[0085] The impedance of the impedance element may be determined so that the maximum available power gain of the field-effect transistor has a convex frequency dependency in the frequency band of the signal input to the signal input electrode, thereby effectively increasing the maximum available power gain in the frequency band of the signal. [Explanation of symbols]

[0086] 1...field effect transistor, 2...unit transistor, 2a...first unit transistor, 2b...second unit transistor, 2c...third unit transistor, 2d...fourth unit transistor, 2e...fifth unit transistor, 2f...sixth unit transistor, 2g...seventh unit transistor, 2h...eighth unit transistor, 2i...ninth unit transistor, 2j...tenth unit transistor, 4...gate electrode, 10...gate wiring, 14, 14a, 14b...transmission lines, 16, 16a, 16b...capacitive element, 18, 18a, 18b...impedance element, 141a, 141b, 142a, 142b...transmission lines, S...source electrode, D...drain electrode, D1...signal output electrode, G1...signal input electrode.

Claims

1. a plurality of unit transistors arranged side by side in one direction, each having a source electrode, a drain electrode, and a gate electrode; a gate wiring extending in the one direction and connecting the plurality of gate electrodes; a signal input electrode connected to the gate wiring; at least one impedance element connected between the gate wiring and the signal input electrode, the connection position of which to the gate wiring is closer to one end of the gate wiring in the one direction than the signal input electrode; A field effect transistor comprising:

2. one of the at least one impedance element is connected between one end of the gate wiring and the signal input electrode; 2. The field effect transistor according to claim 1 .

3. the signal input electrode is connected between both ends of the gate wiring in the one direction, further comprising at least one other impedance element connected between the gate wiring and the signal input electrode, the connection position of which to the gate wiring is closer to the other end of the gate wiring than the signal input electrode; 2. The field effect transistor according to claim 1 .

4. one of the at least one impedance element is connected between one end of the gate wiring and the signal input electrode; one of the at least one other impedance element is connected between the other end of the gate wiring and the signal input electrode; 4. The field effect transistor according to claim 3.

5. the impedance element is a capacitance element connected between the gate wiring and the signal input electrode; 5. A field effect transistor according to claim 1.

6. the impedance element is a transmission line connected between the gate wiring and the signal input electrode; 5. A field effect transistor according to claim 1.

7. 5. The field effect transistor according to claim 1, wherein the impedance element comprises a transmission line and a capacitance element connected in series between the gate wiring and the signal input electrode.

8. the impedance element has an inductor element and a capacitive element connected between the gate wiring and the signal input electrode; 5. A field effect transistor according to claim 1.

9. The impedance of the impedance element is an open circuit impedance in DC.

5. A field effect transistor according to claim 1.

10. the impedance of the impedance element is determined so that the maximum available power gain of the field effect transistor has an upwardly convex frequency dependency in the frequency band of the signal input to the signal input electrode; 5. A field effect transistor according to claim 1.

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