Power source control device and switching power source device

Abstract

To perform suitable multi-phase control in an on-time control method.SOLUTION: Using output transistors (MH) for a plurality of channels, an input voltage is independently switched; thus, an output voltage is generated. A ramp voltage (Vramp) and an error voltage (Verr) according to an error between a feedback voltage (Vfb) and a reference voltage (Vref_fb) are generated and from these voltages, a comparison signal (Cout) is generated. Based on the comparison signal, the output transistors of the channels are controlled to be on sequentially for a predetermined on period. Every time the level of the comparison signal is changed to an active level, the change direction of the ramp voltage is changed from a first direction to a second direction and after an inverted trigger time elapses, the direction is returned to the first direction. The inverted trigger time is set to be less than or equal to the time obtained by dividing the predetermined on period by the number of channels.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to a power supply control device and a switching power supply device. [Background technology]

[0002] In switching power supplies, the on-time control method is known as a control method that can achieve high-speed load response characteristics (see Patent Document 1). This control method is often implemented in combination with a technology called ripple injection, which makes it possible to use multilayer ceramic capacitors with low equivalent series resistance (ESR) as output capacitors. On the other hand, switching power supplies equipped with multiple channels of DC / DC converters can perform multiphase control. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-108189

[0004] [overview] In order to apply multiphase control to a switching power supply device that employs an on-time control method, some ingenuity is required.

[0005] A power supply control device according to one aspect of the present disclosure is a power supply control device used in a switching power supply device configured to generate a plurality of rectangular wave-shaped switch voltages at switch terminals of a plurality of channels by individually switching an input voltage using output stage circuits for a plurality of channels, each including an output transistor, and to generate an output voltage by rectifying and smoothing the plurality of switch voltages, the power supply control device comprising: an error voltage generation circuit configured to generate an error voltage corresponding to the error between a feedback voltage corresponding to the output voltage and a predetermined reference voltage; a ramp voltage generation circuit configured to generate a ramp voltage that alternately rises and falls; a comparison circuit configured to generate a comparison signal having an active level or a non-active level based on the high-low relationship between two voltages based on the error voltage, the ramp voltage, and the feedback voltage; and a switching control circuit that sequentially controls the output transistors of the plurality of channels to be on for a specified on-time while shifting the on-times of the output transistors of the plurality of channels based on the switching control signal, wherein the switching control circuit switches the output transistor of any one of the channels from off to on and returns it to off after the specified on-time has elapsed every time the level of the comparison signal switches from the non-active level to the active level, and the ramp voltage generation circuit switches the direction of change of the ramp voltage from a first direction to a second direction every time the level of the comparison signal switches from the non-active level to the active level, and thereafter switches the direction of change of the ramp voltage from the second direction to the first direction after a reversal trigger time has elapsed that is set to be equal to or less than the time obtained by dividing the specified on-time by the number of channels. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing the overall configuration of a switching power supply device according to a first reference configuration. [Figure 2] FIG. 2 is a timing chart of the switching power supply device according to the first reference configuration. [Figure 3] FIG. 3 is a diagram showing the overall configuration of a power supply device according to a second reference configuration. [Figure 4]FIG. 4 is a timing chart of the switching power supply device according to the second reference configuration. [Figure 5] FIG. 5 is a timing chart of the switching power supply device according to the second reference configuration. [Figure 6] FIG. 6 is a diagram illustrating the overall configuration of a switching power supply device according to a first embodiment of the present disclosure. [Figure 7] FIG. 7 is a diagram illustrating the overall configuration of a switching power supply device according to the first embodiment of the present disclosure. [Figure 8] FIG. 8 is a timing chart of the switching power supply device according to the first embodiment of the present disclosure. [Figure 9] FIG. 9 is a timing chart of the switching power supply device according to the first embodiment of the present disclosure (n=2). [Figure 10] FIG. 10 is a diagram illustrating the overall configuration of a switching power supply device according to the second embodiment of the present disclosure. [Figure 11] FIG. 11 is an external perspective view of a semiconductor device that forms a power supply control device according to the second embodiment of the present disclosure. [Figure 12] FIG. 12 is a timing chart relating to generation of a comparison signal according to the second embodiment of the present disclosure. [Figure 13] FIG. 13 is a timing chart of an operation in response to an odd-numbered rising edge of a comparison signal according to the second embodiment of the present disclosure. [Figure 14] FIG. 14 is a timing chart of an operation in response to an odd-numbered rising edge of a comparison signal according to the second embodiment of the present disclosure. [Figure 15] FIG. 15 is a timing chart of an operation in response to an even-numbered rising edge of a comparison signal according to the second embodiment of the present disclosure. [Figure 16] FIG. 16 is a timing chart of an operation in response to an even-numbered rising edge of a comparison signal according to the second embodiment of the present disclosure. [Figure 17] FIG. 17 is a timing chart of the power supply control device according to the second embodiment of the present disclosure. [Figure 18]FIG. 18 relates to Example EX2_1 belonging to the second embodiment of the present disclosure, and is a diagram showing the connection relationship between drivers when the number of channels is three. [Figure 19] FIG. 19 is an explanatory diagram of a modified technique related to the gradient of the slope voltage, according to Example EX2_2 belonging to the second embodiment of the present disclosure. [Figure 20] FIG. 20 is an overall configuration diagram of a switching power supply device according to a third embodiment of the present disclosure. [Figure 21] FIG. 21 is an external perspective view of two semiconductor devices that form a power supply control device according to the third embodiment of the present disclosure. [Figure 22] FIG. 22 is a timing chart of an operation in response to an odd-numbered rising edge of a comparison signal according to the third embodiment of the present disclosure. [Figure 23] FIG. 23 is a timing chart of an operation in response to an odd-numbered rising edge of a comparison signal according to the third embodiment of the present disclosure. [Figure 24] FIG. 24 is a timing chart of an operation in response to an even-numbered rising edge of a comparison signal according to the third embodiment of the present disclosure. [Figure 25] FIG. 25 is a timing chart of an operation in response to an even-numbered rising edge of a comparison signal according to the third embodiment of the present disclosure. [Figure 26] FIG. 26 is a timing chart of the power supply control device according to the third embodiment of the present disclosure. [Figure 27] FIG. 27 relates to Example EX3_1 belonging to the third embodiment of the present disclosure and is a diagram showing the connection relationship between drivers when the number of channels is 3. [Figure 28] FIG. 28 is an explanatory diagram of a modified technique related to the gradient of the slope voltage, according to Example EX3_2 belonging to the third embodiment of the present disclosure. [Figure 29] FIG. 29 is an explanatory diagram of a modification technique relating to the direction of change in voltage according to the fourth embodiment of the present disclosure. [Figure 30] FIG. 30 is a modified configuration diagram of a switching power supply device according to the fourth embodiment of the present disclosure.

[0007] [Detailed explanation] Prior to describing the switching power supply device according to the embodiment of the present disclosure, switching power supply devices according to first and second reference configurations will be described.

[0008] FIG. 1 shows a switching power supply 910 according to a first reference configuration. The switching power supply 910 is a step-down switching power supply that employs an on-time control method. FIG. 2 shows a timing chart of the switching power supply 910. The switching power supply 910 includes an output stage circuit 911, which is a series circuit of a high-side transistor (output transistor) and a low-side transistor (synchronous rectification transistor). In the switching power supply 910, the output stage circuit 911 switches an input voltage Vin to generate a square-wave switching voltage Vsw, which is then rectified and smoothed by a coil 912 and an output capacitor 913 to obtain an output voltage Vout. In the switching power supply 910, an error amplifier 914 generates an error voltage Verr based on the error between a feedback voltage Vfb corresponding to the output voltage Vout and a reference voltage, while a ramp voltage generation circuit 915 generates a ramp voltage Vramp that fluctuates in synchronization with the switching voltage Vsw. In the switching power supply device 910, the ramp voltage Vramp increases monotonically during the high level period of the switch voltage Vsw (the period when the switch voltage Vsw is approximately at the level of the input voltage Vin), and decreases monotonically during the low level period of the switch voltage Vsw (the period when the switch voltage Vsw is approximately at the level of 0V).

[0009] In the switching power supply device 910, the comparator 916 generates a comparison signal Cout that has a low level during the period when "Vramp + Vfb > Verr" holds and has a high level during the period when "Vramp + Vfb < Verr" holds. In the switching power supply device 910, every time the level of the comparison signal Cout switches from a low level to a high level, the gate signal GH of the high-side transistor is set to a high level for an on-time Ton, so that the high-side transistor is on for the on-time Ton and the low-side transistor is off. In the switching power supply device 910, the on-time Ton may be determined according to the switching voltage Vsw.

[0010] The switching power supply device 910 operates so that the output voltage Vout is stabilized at a predetermined target voltage. In the switching power supply device 910, a variation from the target voltage of the output voltage Vout is detected, and when the variation occurs, the comparison signal Cout is generated so that the output voltage Vout promptly heads toward the target voltage. For the stable operation of the comparator 916, the ripple of the input voltage to the comparator 916 needs to be correspondingly large. If the ramp voltage generation circuit 915 is not provided and the output capacitor 913 is formed of a ceramic capacitor or the like having a sufficiently low equivalent series resistance, the above ripple becomes insufficient and the stable operation is impaired. By providing the ramp voltage generation circuit 915, even if the output capacitor 913 is formed of a ceramic capacitor or the like, the comparator 916 can be stably operated.

[0011] FIG. 3 shows a switching power supply 920 according to a second reference configuration. The switching power supply 920 is a step-down switching power supply employing an on-time control system, similar to the switching power supply 910 of FIG. 1. However, the switching power supply 920 is provided with two-channel output stage circuits 921_1 and 921_2, each of which is an output stage circuit configured with a series circuit of a high-side transistor (output transistor) and a low-side transistor (synchronous rectification transistor), for multiphase control. FIG. 4 shows a timing chart of the switching power supply 920. In the switching power supply 920, the input voltage Vin is individually switched by the output stage circuits 921_1 and 921_2 to generate rectangular-wave switch voltages Vsw1 and Vsw2, which are then rectified and smoothed by coils 922_1 and 922_2 and an output capacitor 923 to obtain the output voltage Vout. In the switching power supply device 920, an error amplifier 924 generates an error voltage Verr based on the error between a reference voltage and a feedback voltage Vfb corresponding to the output voltage Vout, while a ramp voltage generation circuit 925 generates a ramp voltage Vramp that fluctuates in synchronization with the switch voltage Vsw1 or Vsw2. The ramp voltage generation circuit 925 monotonically increases the ramp voltage Vramp during a period when at least one of the switch voltages Vsw1 and Vsw2 is at a high level (approximately the level of the input voltage Vin), and monotonically decreases the ramp voltage Vramp during a period when both the switch voltages Vsw1 and Vsw2 are at a low level (approximately 0 V).

[0012] In the switching power supply device 920, the comparator 926 generates a comparison signal Cout that has a low level during the period when "Vramp + Vfb > Verr" holds and has a high level during the period when "Vramp + Vfb < Verr" holds. In the switching power supply device 920, in response to the switching of the level of the comparison signal Cout from the low level to the high level, the operation of setting the gate signal GH1 of the high-side transistor of the output stage circuit 921_1 to the high level for the on-time Ton and the operation of setting the gate signal GH2 of the high-side transistor of the output stage circuit 921_2 to the high level for the on-time Ton are alternately performed.

[0013] FIG. 4 assumes a situation where the sum of the duty ratios of the first channel and the second channel is less than 100%. In the switching power supply device 920, the duty ratio of the first channel is the ratio of the on-time of the high-side transistor of the output stage circuit 921_1 to the sum of the on-time of the high-side transistor and the on-time of the low-side transistor of the output stage circuit 921_1. In the switching power supply device 920, the duty ratio of the second channel is the ratio of the on-time of the high-side transistor of the output stage circuit 921_2 to the sum of the on-time of the high-side transistor and the on-time of the low-side transistor of the output stage circuit 921_2.

[0014] The switching power supply 920 does not operate correctly in a hypothetical case where the sum of the on-duty of the first channel and the on-duty of the second channel is greater than 100%. FIG. 5 shows a hypothetical timing chart of the switching power supply 920 for this hypothetical case. In this hypothetical case, the on-duty of both the first and second channels is greater than 50%. The dashed waveforms 931 and 932 in FIG. 5 represent the waveforms of the switch voltage Vsw2 and the gate signal GH2 that would be observed if the switching power supply 920 operated correctly in this hypothetical case. However, in this hypothetical case, the ramp voltage Vramp actually continues to rise during the high-level period of the switch voltage Vsw1, so the comparison signal Cout does not become high when the gate signal GH2 should switch to high (the dashed waveform 933 in the comparison signal Cout does not occur in FIG. 5). As a result, the switching power supply 920 does not perform correct control when the sum of the on-duty of the first channel and the on-duty of the second channel is greater than 100%.

[0015] In consideration of these circumstances, an embodiment of the present disclosure is described below. In each drawing referred to in the embodiment of the present disclosure, the same parts are denoted by the same reference numerals, and duplicated explanations of the same parts are generally omitted. For the sake of simplicity, this specification may use symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components, and may omit or abbreviate the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs. For example, the comparison signal referred to by "Cout" (see FIG. 6), described below, may be written as the comparison signal Cout or abbreviated as the signal Cout, but they all refer to the same thing.

[0016] Some terms used in describing the embodiments of the present disclosure will be explained below. Ground refers to a reference conductor having a reference potential of 0V (zero volts), or refers to the 0V potential itself. The reference conductor may be formed using a conductor such as metal. The 0V potential may also be referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a specific reference represents the potential seen from ground. Level refers to the level (height) of potential, and for any given signal or voltage, a high level has a higher potential than a low level. For any given signal or voltage, a transition from a low level to a high level may be referred to as a rising edge, and a transition from a high level to a low level may be referred to as a falling edge.

[0017] For any transistor configured as a FET (field-effect transistor), such as a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Additionally, unless otherwise specified, the back gate of any MOSFET can be considered shorted to the source.

[0018] Hereinafter, the on and off states of any transistor may be simply referred to as on and off. Furthermore, for any transistor, the period during which the transistor is in the on state will be referred to as the on period, and the period during which the transistor is in the off state will be referred to as the off period.

[0019] For any signal having a high-level or low-level signal level, the period during which the level of the signal is high is referred to as the high-level period, and the period during which the level of the signal is low is referred to as the low-level period. The same applies to any voltage having a high-level or low-level voltage level.

[0020] The connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection unless otherwise specified.

[0021] When any two voltages to be compared are voltage v1 and v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0022] <<First Embodiment>> The first embodiment of the present disclosure will be described. FIG. 6 shows the overall configuration of the switching power supply device 1 according to the first embodiment of the present disclosure. The switching power supply device 1 receives a positive input voltage Vin from a voltage source not shown and generates an output voltage Vout by power conversion of the input voltage Vin. Here, it is assumed that the switching power supply device 1 is a step-down switching power supply device, and thus the output voltage Vout is lower than the input voltage Vin. The switching power supply device 1 stabilizes the output voltage Vout at a target voltage Vtg having a predetermined positive DC voltage value. Therefore, in the steady state, the output voltage Vout substantially coincides with the target voltage Vtg. The switching power supply device 1 has n DC / DC converters. The n DC / DC converters are composed of the first to nth channel DC / DC converters. n represents an arbitrary integer of 2 or more.

[0023] The switching power supply 1 comprises a power supply control device 2 that controls the operation of the switching power supply 1, and a plurality of discrete components externally connected to the power supply control device 2, and the power supply control device 2 and the plurality of discrete components form DC / DC converters of first to n-th channels. The plurality of discrete components include n-channel coils L, an output capacitor C1, and feedback resistors R1 and R2. The output capacitor C1 may be any type of capacitor, and may be formed using a ceramic capacitor or the like with a sufficiently small equivalent series resistance.

[0024] The power supply control device 2 is provided with an error voltage generation circuit 3, a ramp voltage generation circuit 4, a comparison circuit 5, and a switching control circuit 6. The power supply control device 2 is also provided with output stage circuits MM for n channels. However, the output stage circuits MM for n channels may be provided outside the power supply control device 2 and connected to the power supply control device 2.

[0025] The DC / DC converter of each channel has one output stage circuit MM and one coil L. The error voltage generating circuit 3, ramp voltage generating circuit 4, and comparison circuit 5 are shared among the first to n-th channels (shared by the DC / DC converters of the first to n-th channels). The switching control circuit 6 controls the state of the output stage circuit MM of each channel.

[0026] The power supply control device 2 has an input terminal IN, a ground terminal GND, and a feedback terminal FB, as well as a switch terminal SW provided for each channel. Therefore, the power supply control device 2 has a total of n switch terminals SW corresponding to the first to nth channels. An input voltage Vin is supplied to the input terminal IN from a voltage source (not shown). The ground terminal GND is connected to ground.

[0027] In each channel, the output stage circuit MM has a series circuit of a high-side transistor MH and a low-side transistor ML. In each channel, the first end of the coil L is connected to the corresponding switch terminal SW. The second ends of the coils L in all channels are commonly connected to the output terminal OUT. The voltage generated at the output terminal OUT is the output voltage Vout.

[0028] An output capacitor C1 is inserted between the output terminal OUT and ground. That is, a first terminal of the output capacitor C1 is connected to the output terminal OUT, and a second terminal of the output capacitor C1 is connected to ground. A load LD is connected to the output terminal OUT. The load LD is any load that is driven based on the output voltage Vout. The current supplied from the output terminal OUT to the load LD (i.e., the output current of the switching power supply device 1) is called the load current. Furthermore, the current flowing through each coil L is called the coil current IL.

[0029] A first terminal of the feedback resistor R1 is connected to the output terminal OUT, a second terminal of the feedback resistor R1 is connected to a first terminal of the feedback resistor R2, and a second terminal of the feedback resistor R2 is connected to ground. A feedback voltage Vfb corresponding to the output voltage Vout is generated at the connection node between the feedback resistors R1 and R2. A feedback terminal FB is connected to the connection node between the feedback resistors R1 and R2 and receives the feedback voltage Vfb. The feedback voltage Vfb is a divided voltage of the output voltage Vout and is therefore proportional to the output voltage Vout. The feedback resistors R1 and R2 form a feedback voltage generation circuit that generates the feedback voltage Vfb. The feedback resistors R1 and R2 may be built into the power supply control device 2. The output voltage Vout itself may be used as the feedback voltage Vfb. In either case, the feedback voltage Vfb is a voltage corresponding to the output voltage Vout.

[0030] A feedback voltage Vfb is input to the error voltage generating circuit 3. A reference voltage Vref_fb for feedback control is also input to the error voltage generating circuit 3. The reference voltage Vref_fb is generated within the power supply control device 2 based on the input voltage Vin, and has a predetermined positive DC voltage value. The reference voltage Vref_fb may be generated by a voltage source within the error voltage generating circuit 3. The error voltage generating circuit 3 compares the feedback voltage Vfb with the reference voltage Vref_fb, and generates and outputs an error voltage Verr, which is a voltage signal corresponding to the error between the feedback voltage Vfb and the reference voltage Vref_fb.

[0031] The ramp voltage generating circuit 4 generates and outputs a ramp voltage Vramp that alternately rises and falls. That is, the voltage value of the ramp voltage Vramp alternately rises and falls. The ramp voltage generating circuit 4 monotonically increases the ramp voltage Vramp at a predetermined constant rate during the ramp voltage Vramp's rising period (i.e., the period during which the ramp voltage Vramp is increased), and monotonically decreases the ramp voltage Vramp at a predetermined constant rate during the ramp voltage Vramp's falling period (i.e., the period during which the ramp voltage Vramp is decreased). The timing of switching the direction of change of the ramp voltage Vramp is controlled by a switching control circuit 6 (details will be described later).

[0032] The comparator circuit 5 generates and outputs a comparison signal Cout based on the relationship between the error voltage Verr, the ramp voltage Vramp, and the feedback voltage Vfb. The comparison signal Cout is a binary signal having an active level or a non-active level.

[0033] The switching control circuit 6 performs switching control for each output stage circuit MM based on the comparison signal Cout. At this time, the switching control circuit 6 performs multi-phase control in which the phase of the switching control is shifted among a plurality of channels.

[0034] Hereinafter, when the n output stage circuits MM are to be distinguished from one another as shown in Fig. 7, the n output stage circuits MM will be referred to as output stage circuits MM[1] to MM[n]. Similarly, the n switch terminals SW may be referred to as switch terminals SW[1] to SW[n], and the n coils L may be referred to as coils L[1] to L[n]. The output stage circuit MM[i], switch terminal SW[i], and coil L[i] are the output stage circuit MM, switch terminal SW, and coil L in the DC / DC converter of the i-th channel. i represents any integer, and when i is used as a variable indicating any channel, i represents any natural number equal to or less than n.

[0035] The output stage circuits MM of all channels have the same configuration. As described above, each output stage circuit MM includes transistors MH and ML. The transistors MH and ML are N-channel MOSFETs. In each output stage circuit MM, the transistors MH and ML are a pair of switching elements connected in series between the input terminal IN and the ground terminal GND (i.e., ground). The transistor MH is located at a higher potential than the transistor ML. Specifically, in each output stage circuit MM, the drain of the transistor MH is connected to the input terminal IN and receives the input voltage Vin. In each output stage circuit MM, the source of the transistor MH and the drain of the transistor ML are commonly connected to the corresponding switch terminal SW. Therefore, in the output stage circuit MM[i], the source of the transistor MH and the drain of the transistor ML are commonly connected to the switch terminal SW[i]. In each output stage circuit MM, the source of the transistor ML is connected to the ground terminal GND (and therefore to ground). Note that a current detection resistor may be inserted between the source of the transistor ML and the ground terminal GND.

[0036] The transistor MH functions as an output element (output transistor), and the transistor ML functions as a rectifier element (synchronous rectifier transistor). In the switching control of the output stage circuit MM, the output element (MH) and the rectifier element (ML) are alternately turned on and off.

[0037] In each output stage circuit MM, the transistors MH and ML are alternately turned on and off by switching control to switch the input voltage Vin, resulting in a square-wave switch voltage Vsw appearing at the corresponding switch terminal SW. The switch voltage Vsw at the switch terminal SW[i] is specifically referred to as the switch voltage Vsw[i]. That is, the switching control circuit 6 generates switch voltages Vsw[1] to Vsw[n] at the switch terminals SW[1] to SW[n] by individually switching the input voltage Vin using the output stage circuits MM[1] to MM[n]. In each channel, the coil L[i] and output capacitor C1 rectify and smooth the switch voltage Vsw[i]. The coils L[1] to L[n] and output capacitor C1 form a rectifying and smoothing circuit that rectifies and smoothes the switch voltages Vsw[1] to Vsw[n] to generate the output voltage Vout. In each channel, the switch terminal SW is connected to the first end of the corresponding coil L. That is, 、 The switch terminal SW[i] is connected to the first terminal of the coil L[i]. The second terminals of all of the coils L[1] to L[n] are commonly connected to the output terminal OUT. The coils L[1] to L[n] have the same inductance value (however, differences due to errors may occur).

[0038] In each channel, while the transistor MH is on, the coil current IL flows through the channel (between the drain and source) of the transistor MH, and then, while the transistor MH is off, the coil current IL flows through the channel of the transistor ML or the parasitic diode of the transistor ML.

[0039] In each channel, the switching control circuit 6 controls the on / off state of the transistors MH and ML by supplying gate signals GH and GL as drive signals to the gates of the transistors MH and ML, respectively. The transistors MH and ML are turned on and off in response to the gate signals GH and GL. The gate signal GH for the transistor MH of the output stage circuit MM[i] is specifically referred to as the gate signal GH[i], and the gate signal GL for the transistor ML of the output stage circuit MM[i] is specifically referred to as the gate signal GL[i]. The transistor MH of the output stage circuit MM[i] is turned on during a high-level period of the gate signal GH[i] and turned off during a low-level period of the gate signal GH[i]. Similarly, the transistor ML of the output stage circuit MM[i] is turned on during a high-level period of the gate signal GL[i] and turned off during a low-level period of the gate signal GL[i].

[0040] In the output stage circuit MM[i] of any channel, a state in which the transistor MH is turned on and the transistor ML is turned off is called an output high state, a state in which the transistor MH is turned off and the transistor ML is turned on is called an output low state, and a state in which the transistors MH and ML are both turned off is called a both off state. In the output stage circuit MM[i] of any channel, the transistors MH and ML are never turned on at the same time. In each channel, the transistors MH and ML are basically turned on and off alternately, but there are also cases in which both the transistors MH and ML are maintained in an off state.

[0041] The switching control circuit 6 can switch the output stage circuit MM[i] of each of the output stage circuits MM[1] to MM[n] from a low output state to a high output state and from a high output state to a low output state. In switching the output stage circuit MM[i] from a low output state to a high output state, the switching control circuit 6 first switches the transistor ML of the output stage circuit MM[i] from on to off using a falling edge of the gate GL[i], then generates a rising edge of the gate GH[i] after a dead time to switch the transistor MH of the output stage circuit MM[i] from off to on. In switching the output stage circuit MM[i] from a high output state to a low output state, the switching control circuit 6 first switches the transistor MH of the output stage circuit MM[i] from on to off using a falling edge of the gate GH[i], then generates a rising edge of the gate GL[i] after a dead time to switch the transistor ML of the output stage circuit MM[i] from off to on. The dead time is a very short time inserted to ensure that the transistors MH and ML in the same channel are not turned on at the same time. In the following, unless otherwise necessary, the existence of the dead time will be ignored, and it will be considered that in the output stage circuit MM[i] of any channel, the gate signal GL[i] is at a low level during the high level period of the gate signal GH[i], and the gate signal GL[i] is at a high level during the low level period of the gate signal GH[i].

[0042] Although not shown, the power supply control device 2 is provided with an internal power supply circuit that generates various internal power supply voltages based on the input voltage Vin, and each circuit within the power supply control device 2 is driven by the input voltage Vin or the internal power supply voltage. In each output stage circuit MM, the gate signal GL is a signal referenced to the ground potential, while the gate signal GH is a signal referenced to the potential of the switch terminal SW. A low-level gate signal GH has the potential of the switch terminal SW, and a high-level gate signal GH is a predetermined voltage higher than the potential of the switch terminal SW. This predetermined voltage is greater than the gate threshold voltage of the transistor MH. A well-known bootstrap circuit (not shown) can be used to generate a boost power supply for generating the gate signal GH. The transistor MH may be configured as a P-channel MOSFET, in which case a boost power supply is not required.

[0043] Alternatively, a diode rectification system may be adopted in the DC / DC converter of each channel. In this case, instead of the transistor ML, a synchronous rectification diode having an anode connected to ground and a cathode connected to the switch terminal SW is used as the rectification element. In this case, only the transistor MH (output transistor) is turned on and off in the switching control of the output stage circuit MM.

[0044] The switching control circuit 6 performs multi-phase control using an on-time control method. That is, based on the comparison signal Cout, the switching control circuit 6 controls the transistors MH of the output stage circuits MM[1] to MM[n] to be turned on for a prescribed on-time Ton in sequence while shifting the on-periods of the transistors MH of the output stage circuits MM[1] to MM[n] from each other. At this time, every time the level of the comparison signal Cout switches from the non-active level to the active level, the switching control circuit 6 switches the transistor MH of any one channel from off to on and returns it to off after the elapse of the on-time Ton. For the sake of concreteness of explanation here, it is assumed that in the comparison signal Cout, the non-active level is the low level and the active level is the high level (however, a modification in which the high level is the non-active level and the low level is the active level is also possible).

[0045] Refer to FIG. 8. In FIG. 8, the waveform of the error voltage Verr is shown as a broken line segment, and the waveform of the combined voltage (Vramp + Vfb) of the lamp voltage Vramp and the feedback voltage Vfb is shown as a solid triangular wave. The combined voltage (Vramp + Vfb) is the sum voltage of the lamp voltage Vramp and the feedback voltage Vfb. Also shown in FIG. 8 are the waveforms of the comparison signal Cout and the gate signals GH[1] to GH[n]. The comparison circuit 5 outputs a high-level comparison signal Cout during the period when "Vramp + Vfb < Verr" holds, and outputs a low-level comparison signal Cout during the period when "Vramp + Vfb > Verr" holds. The comparison signal Cout during the period when "Vramp + Vfb = Verr" holds has a high level or a low level.

[0046] As shown in FIG. 8, the switching control circuit 6 generates a rising edge in the gate signal GH[1] in response to the (1+n×m)th rising edge in the comparison signal Cout, and then generates a falling edge in the gate signal GH[1] after the on-time Ton has elapsed. Therefore, the switching control circuit 6 switches the transistor MH of the output stage circuit MM[1] from off to on in response to the (1+n×m)th rising edge in the comparison signal Cout, and then switches it back to off after the on-time Ton has elapsed. In other words, the switching control circuit 6 switches the state of the output stage circuit MM[1] from an output low state to an output high state in response to the (1+n×m)th rising edge in the comparison signal Cout, and then switches it back to the output low state after the on-time Ton has elapsed. Similarly, the switching control circuit 6 generates a rising edge in the gate signal GH[2] in response to the (2+n×m)th rising edge in the comparison signal Cout, and then generates a falling edge in the gate signal GH[2] after the on-time Ton has elapsed. Therefore, the switching control circuit 6 switches the transistor MH of the output stage circuit MM[2] from off to on in response to the (2+n×m)th rising edge of the comparison signal Cout, and switches it back to off after the on-time Ton has elapsed. In other words, the switching control circuit 6 switches the state of the output stage circuit MM[2] from the output low state to the output high state in response to the (2+n×m)th rising edge of the comparison signal Cout, and switches it back to the output low state after the on-time Ton has elapsed. The same operation is performed in response to other rising edges of the comparison signal Cout.

[0047] In general, the switching control circuit 6 generates a rising edge in the gate signal GH[j] in response to the (j+n×m)th rising edge in the comparison signal Cout, and then generates a falling edge in the gate signal GH[j] after the on-time Ton has elapsed. Therefore, the switching control circuit 6 switches the transistor MH of the output stage circuit MM[j] from off to on in response to the (j+n×m)th rising edge in the comparison signal Cout, and then switches it back to off after the on-time Ton has elapsed. In other words, the switching control circuit 6 switches the state of the output stage circuit MM[j] from an output low state to an output high state in response to the (j+n×m)th rising edge in the comparison signal Cout, and then switches it back to the output low state after the on-time Ton has elapsed. In (j+n×m), j represents any natural number equal to or less than n, and m represents any integer equal to or greater than 0. In addition, Figure 8 illustrates how a rising edge occurs in the gate signal GH[j] after a very short time has passed since the timing of the (j+n×m)th rising edge in the comparison signal Cout, and this very short time is a delay time that occurs within the switching control circuit 6 (the same applies to Figure 9 described later).

[0048] Under the control of the switching control circuit 6, the ramp voltage generating circuit 4 switches the ramp voltage Vramp from decreasing to increasing each time a rising edge occurs in the comparison signal Cout. Then, when the reversal trigger time Trvs has elapsed since the switching, the ramp voltage generating circuit 4 switches the ramp voltage Vramp from increasing to decreasing. Here, "Trvs = Ton / n" holds. That is, the reversal trigger time Trvs is equal to the time (Ton / n) obtained by dividing the on-time Ton by n. However, the reversal trigger time Trvs may be slightly shorter than the time (Ton / n) (for example, it may be shorter by a predetermined small amount).

[0049] In a steady state where the output voltage Vout is stabilized at the target voltage Vtg (i.e., in a state where "Vout = Vtg"), the on-time Ton has a fixed length according to the ratio of the input voltage Vin to the output voltage Vout. Except for a short period during a transient response (at least in a steady state), the on-time Ton of the first to nth channels is the same as one another, and the on-duties of the first to nth channels are also the same as one another. In the following, unless otherwise required, it is assumed that the on-time Ton of the first to nth channels is the same as one another, and the on-duties of the first to nth channels are also the same as one another.

[0050] The on-time Ton of the i-th channel refers to the length of the on-period of the transistor MH of the output stage circuit MM[i] in one cycle of the switching control of the output stage circuit MM[i] (i.e., the period from when the transistor MH of the output stage circuit MM[i] is switched from off to on until it is switched back to off). One cycle of the switching control of the output stage circuit MM[i] is the period from when the transistor MH is switched from off to on in the output stage circuit MM[i], through the switching of the transistor MH from on to off, to just before the transistor MH is switched on again. The on-duty of the i-th channel is also sometimes referred to as the on-duty of the output stage circuit MM[i]. The on-duty of the i-th channel (the on-duty of the output stage circuit MM[i]) is the ratio of the on-period of the transistor MH of the output stage circuit MM[i] to the sum of the on-period of the transistor MH and the on-period of the transistor ML of the output stage circuit MM[i].

[0051] A steady state in which the load current has a certain current value is referred to as a reference steady state. Here, it is assumed that the establishment of "Vfb < Vref_fb" results in an increase in the error voltage Verr, while the establishment of "Vfb > Vref_fb" results in a decrease in the error voltage Verr. Starting from the reference steady state, when the load current increases and the output voltage Vout becomes lower than the target voltage Vtg, the generation interval of the rising edge of the comparison signal Cout becomes narrower than that in the reference steady state through the decrease in the feedback voltage Vfb and the increase in the error voltage Verr. As a result, the on-duty of the first to nth channels becomes larger than that in the reference steady state, and the output voltage Vout increases toward the target voltage Vtg. Conversely, starting from the reference steady state, when the load current decreases and the output voltage Vout becomes higher than the target voltage Vtg, the generation interval of the rising edge of the comparison signal Cout becomes larger than that in the reference steady state through the increase in the feedback voltage Vfb and the decrease in the error voltage Verr. As a result, the on-duty of the first to nth channels becomes smaller than that in the reference steady state, and the output voltage Vout decreases toward the target voltage Vtg. Such feedback control can provide high responsiveness to fluctuations in the load current.

[0052] FIG. 9 shows waveforms of several voltages and signals when "n = 2". In FIG. 9, the waveform of the error voltage Verr is shown as a broken line segment, and the waveform of the combined voltage (Vramp + Vfb) of the ramp voltage Vramp and the feedback voltage Vfb is shown as a solid triangular wave. In addition to the waveforms of the comparison signal Cout, the gate signals GH[1] and GH[2], the waveforms of the switch voltages Vsw[1] and Vsw[2] are also shown in FIG. 9 (dead time is ignored in FIG. 9).

[0053] When "n=2," the switching control circuit 6 generates a rising edge in the gate signal GH[1] in response to odd-numbered rising edges in the comparison signal Cout, and then generates a falling edge in the gate signal GH[1] after the on-time Ton has elapsed. In other words, the switching control circuit 6 switches the state of the output stage circuit MM[1] from an output low state to an output high state in response to odd-numbered rising edges in the comparison signal Cout, and returns it to the output low state after the on-time Ton has elapsed. When "n=2," the switching control circuit 6 generates a rising edge in the gate signal GH[2] in response to even-numbered rising edges in the comparison signal Cout, and then generates a falling edge in the gate signal GH[2] after the on-time Ton has elapsed. In other words, the switching control circuit 6 switches the state of the output stage circuit MM[2] from an output low state to an output high state in response to even-numbered rising edges in the comparison signal Cout, and then returns it to the output low state after the on-time Ton has elapsed. When "n=2", the reversal trigger time Trvs coincides with half the on-time Ton (Ton / 2) (however, it may be slightly smaller than half the on-time Ton).

[0054] 9 assumes that the sum of the on-duty of the first channel and the on-duty of the second channel is 100% or more. As can be seen from FIG. 9, unlike the switching power supply 920 of FIG. 3, the switching power supply 1 can perform desired multi-phase control even when the sum of the on-duty of the first channel and the on-duty of the second channel is 100% or more. That is, in the switching power supply 1 when "n=2," desired multi-phase control can be performed even in cases where two output stage circuits MM simultaneously enter the output high state. In the switching power supply 1 when "n≧3," desired multi-phase control can be performed even in cases where two or more output stage circuits MM simultaneously enter the output high state.

[0055] <<Second embodiment>> A second embodiment of the present disclosure will be described. The second embodiment and the third and fourth embodiments described below are based on the first embodiment, and for matters not specifically mentioned in the second to fourth embodiments, the description of the first embodiment also applies to the second to fourth embodiments unless there is a contradiction. However, when interpreting the description of the second embodiment, the description of the second embodiment may take precedence for matters that contradict between the first and second embodiments (the same applies to the third and fourth embodiments described below). As long as there is no contradiction, any two or more of the first to fourth embodiments may be combined.

[0056] 10 shows the configuration of a switching device 1A, which is a switching device 1 according to the second embodiment. The switching device 1A includes a power supply control device 2A as the power supply control device 2 (see FIG. 7). In the second embodiment, it is assumed that "n=2" unless otherwise specified.

[0057] FIG. 11 is a perspective view of the appearance of a semiconductor device SD used as a power supply control device 2A. The semiconductor device SD is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and multiple external terminals exposed from the housing to the outside of the semiconductor device SD. The semiconductor device SD is formed by encapsulating the semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the semiconductor device SD and the type of housing of the semiconductor device SD shown in FIG. 11 are merely examples and can be designed as desired. FIG. 10 shows an input terminal IN, switch terminals SW[1] and SW[2], a ground terminal GND, and a feedback terminal FB as some of the multiple external terminals provided on the semiconductor device SD. Other external terminals may also be provided on the semiconductor device SD.

[0058] The switching device 1A is provided with coils L[1] and L[2], an output capacitor C1, and feedback resistors R1 and R2, as shown in the first embodiment. The connections between the coils L[1] and L[2], the output capacitor C1, the feedback resistors R1 and R2, the switch terminals SW[1] and SW[2], the feedback terminal FB, the output terminal OUT, and the ground are the same as those shown in the first embodiment.

[0059] The power supply control device 2A includes output stage circuits MM[1] and MM[2], an error amplifier 31, a phase compensation circuit 32, a reference power supply 33, a ramp circuit 41, an OR circuit 42, a comparator 51, drivers 61[1] and 61[2], and on-timer circuits 62[1] and 62[2]. However, the output stage circuits MM[1] and MM[2] may be provided outside the power supply control device 2A (outside the semiconductor device SD). The phase compensation circuit 32 may also be provided outside the power supply control device 2A (outside the semiconductor device SD). The driver 61[1] and on-timer circuit 62[1] are the driver and on-timer circuit for the first channel (CH1), and the driver 61[2] and on-timer circuit 62[2] are the driver and on-timer circuit for the second channel (CH2).

[0060] The error amplifier 31 and phase compensation circuit 32 form the error voltage generation circuit 3 in Fig. 7. However, it may be understood that the reference voltage source 33 is also included in the components of the error voltage generation circuit 3. The ramp circuit 41 and OR circuit 42 form the ramp voltage generation circuit 4 in Fig. 7. The comparator 51 corresponds to the comparison circuit 5 in Fig. 7. The drivers 61[1] and 61[2] and the on-timer circuits 62[1] and 62[2] form the switching control circuit 6 in Fig. 7.

[0061] The error amplifier 31 is a current output type transconductance amplifier. The error amplifier 31 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal of the error amplifier 31 is connected to a feedback terminal FB and receives a feedback voltage Vfb. A reference voltage Vref_fb is supplied to the non-inverting input terminal of the error amplifier 31 from a reference voltage source 33. The reference voltage Vref_fb is a DC voltage having a predetermined positive voltage value. The output terminal of the error amplifier 31 is connected to a wiring WR31 (error output wiring).

[0062] The error amplifier 31 outputs a current signal I31 corresponding to the difference between the feedback voltage Vfb and the reference voltage Vref_fb from its output terminal, thereby generating a voltage corresponding to the difference between the feedback voltage Vfb and the reference voltage Vref_fb on the line WR31. The voltage applied to the line WR31 is the error voltage Verr. Charge generated by the current signal I31 is input to and output from the line WR31. Specifically, when the feedback voltage Vfb is lower than the reference voltage Vref_fb, the error amplifier 31 outputs a current generated by the current signal I31 from the error amplifier 31 to the line WR31 so that the potential of the line WR31 increases (i.e., the error voltage Verr increases). When the feedback voltage Vfb is higher than the reference voltage Vref_fb, the error amplifier 31 draws a current generated by the current signal I31 from the line WR31 to the error amplifier 31 so that the potential of the line WR31 decreases (i.e., the error voltage Verr decreases). As the absolute value of the difference between the feedback voltage Vfb and the reference voltage Vref_fb increases, the magnitude of the current by the current signal I31 also increases.

[0063] When the power supply control device 2A starts up, a soft-start voltage that gradually rises from 0 V to a voltage exceeding the reference voltage Vref_fb may be generated within the power supply control device 2A. In this case, the error amplifier 31 compares the lower of the reference voltage Vref_fb and the soft-start voltage with the feedback voltage Vfb and generates a current signal I31 based on the comparison result. However, here we consider the state after the soft-start voltage becomes higher than the reference voltage Vref_fb, and hereinafter the existence of the soft-start voltage will be ignored.

[0064] The phase compensation circuit 32 is provided between the wiring WR31 and ground, and receives the input of the current signal I31 to compensate for the phase of the voltage on the wiring WR31 (the phase of the error voltage Verr). The phase compensation circuit 32 has a series circuit of a resistor 32a (phase compensation resistor) and a capacitor 32b (phase compensation capacitor). Specifically, one end of the resistor 32a is connected to the wiring WR31, and the other end of the resistor 32a is connected to ground via the capacitor 32b. By appropriately setting the resistance value of the resistor 32a and the capacitance value of the capacitor 32b, it is possible to compensate for the phase of the voltage on the wiring WR31 (the phase of the error voltage Verr) and prevent oscillation of the output feedback loop.

[0065] The OR circuit 42 is a two-input logical sum circuit. A signal T_Vramp[1] (first ramp command signal) is supplied from the driver circuit 61[1] to a first input terminal of the OR circuit 42, and a signal T_Vramp[2] (second ramp command signal) is supplied from the driver circuit 61[2] to a second input terminal of the OR circuit 42. The OR circuit 42 outputs a signal Vramp_CTL based on the signals T_Vramp[1] and T_Vramp[2] to the ramp circuit 41. The signals T_Vramp[1], T_Vramp[2], and Vramp_CTL are all binary signals having a high level or a low level. The OR circuit 42 outputs a high-level signal Vramp_CTL during a period when at least one of the signals T_Vramp[1] and T_Vramp[2] is at a high level. The OR circuit 42 outputs a low-level signal Vramp_CTL during a period when both the signals T_Vramp[1] and T_Vramp[2] are at a low level.

[0066] The ramp circuit 41 generates and outputs a ramp voltage Vramp that alternately increases and decreases in response to a signal Vramp_CTL supplied from an OR circuit 42. The ramp circuit 41 monotonically increases the ramp voltage Vramp at a predetermined constant rate of increase during a high-level period of the signal Vramp_CTL, and monotonically decreases the ramp voltage Vramp at a predetermined constant rate of decrease during a low-level period of the signal Vramp_CTL (see FIG. 12).

[0067] Specifically, the lamp voltage generation circuit 41 outputs voltages Vr1 and Vr2. The voltage Vr1 is the sum voltage of the lamp voltage Vramp and the voltage Vr2. The voltage Vr2 has a predetermined positive DC voltage value. The voltage Vr1 is a pulsating DC voltage, and the voltage Vr2 corresponds to the DC component of the voltage Vr1. That is, "Vramp = Vr1 - Vr2".

[0068] Voltages Vr1, Vr2, error voltage Verr, and feedback voltage Vfb are input to the comparator 51 (therefore, the lamp voltage Vramp, error voltage Verr, and feedback voltage Vfb are input). The comparator 51 generates and outputs a comparison signal Cout having a high level or a low level according to the high - low relationship of two voltages based on the lamp voltage Vramp, error voltage Verr, and feedback voltage Vfb. Of these two voltages, one is the combined voltage (Vramp + Vfb), and the other is the error voltage Verr. The combined voltage (Vramp + Vfb) is the sum voltage of the lamp voltage Vramp and the feedback voltage Vfb.

[0069] FIG. 12 shows the relationship between the signal Vramp_CTL, the error voltage Verr, the combined voltage (Vramp + Vfb), and the comparison signal Cout. The comparator 51 outputs a high - level comparison signal Cout during the period when "Vramp + Vfb < Verr" holds, and outputs a low - level comparison signal Cout during the period when "Vramp + Vfb > Verr" holds. The comparison signal Cout during the period when "Vramp + Vfb = Verr" holds has a high level or a low level. As described in the first embodiment, the low - level comparison signal Cout corresponds to the non - active level, and the high - level comparison signal Cout corresponds to the active level. The comparison signal Cout from the comparator 51 is input to the drivers 61[1] and 61[2].

[0070] The driver 61[1] supplies gate signals GH[1] and GL[1] to the gates of the transistors MH and ML in the output stage circuit MM[1], respectively, to turn on and off the transistors MH and ML in the output stage circuit MM[1]. The driver 61[1] also outputs a signal Ton_SET[1] to the on-timer circuit 62[1] and a signal T_Vramp[1] to the OR circuit 42.

[0071] Similar to the driver 61[1], the driver 61[2] supplies gate signals GH[2] and GL[2] to the gates of the transistors MH and ML in the output stage circuit MM[2], respectively, thereby individually turning on and off the transistors MH and ML in the output stage circuit MM[2]. The driver 61[2] also outputs a signal Ton_SET[2] to the on-timer circuit 62[2] and a signal T_Vramp[2] to the OR circuit 42.

[0072] The on-timer circuit 62[1] has a first measurement function for measuring the on-time Ton of the first channel (i.e., a function for measuring whether the elapsed time since the transistor MH of the output stage circuit MM[1] switched from off to on has reached the specified on-time Ton), and outputs a signal Ton_RST[1] indicating the measurement result of the first measurement function to the driver 61[1]. The on-timer circuit 62[1] is connected to the switch terminal SW[1]. The on-timer circuit 62[1] determines the on-duty of the output stage circuit MM[1] from the average voltage of the switch voltage Vsw[1] and the input voltage Vin, and can set the on-time Ton of the first channel according to the on-duty of the output stage circuit MM[1]. The on-timer circuit 62[1] also has a second measurement function for measuring the inversion trigger time Trvs (see FIG. 9), and outputs a signal T_Vramp_RST[1] indicating the measurement result of the second measurement function to the driver 61[1]. The second measurement function of the on-timer circuit 62[1] is a function to measure whether the elapsed time since the transistor MH of the output stage circuit MM[1] switched from off to on has reached the inversion trigger time Trvs. In other words, it is a function to measure whether the length of the rising period of the ramp voltage Vramp has reached the inversion trigger time Trvs.

[0073] Like the on-timer circuit 62[1], the on-timer circuit 62[2] has a first measurement function for measuring the on-time Ton of the second channel (i.e., a function for measuring whether the elapsed time since the transistor MH of the output stage circuit MM[2] switched from off to on has reached the specified on-time Ton). The on-timer circuit 62[2] outputs a signal Ton_RST[2] indicating the measurement result of the first measurement function to the driver 61[2]. The on-timer circuit 62[2] is connected to the switch terminal SW[2]. The on-timer circuit 62[2] determines the on-duty of the output stage circuit MM[2] from the average voltage of the switch voltage Vsw[2] and the input voltage Vin, and can set the on-time Ton of the second channel according to the on-duty of the output stage circuit MM[2]. The on-timer circuit 62[2] also has a second measurement function for measuring the inversion trigger time Trvs (see FIG. 9) and outputs a signal T_Vramp_RST[2] indicating the measurement result of the second measurement function to the driver 61[2]. The second measurement function of the on-timer circuit 62[2] is a function to measure whether the elapsed time since the transistor MH of the output stage circuit MM[2] was switched from off to on has reached the inversion trigger time Trvs. In other words, it is a function to measure whether the length of the rising period of the ramp voltage Vramp has reached the inversion trigger time Trvs.

[0074] The sequence control signals Sa and Sb are transmitted and received between the drivers 61[1] and 62[2]. Through the transmission and reception of the sequence control signals Sa and Sb, the driver 61[1] responds only to odd-numbered rising edges in a group of rising edges in the comparison signal Cout, and the driver 61[2] responds only to even-numbered rising edges in a group of rising edges in the comparison signal Cout. In the power supply control device 2A shown in FIG. 10, the sequence control signal Sa is output from the driver 61[1] to the driver 61[2], and the sequence control signal Sb is output from the driver 61[2] to the driver 61[1]. The signals Ton_SET[i], Ton_RST[i], T_Vramp_RST[i], Sa, and Sb are all binary signals having a high level or a low level.

[0075] 13, the operation in response to the odd-numbered rising edge of the comparison signal Cout will be described. A0 , t A1 , t A2 , t A3 , t A4 occur in this order. In this specification, any time may be understood as a concept having a certain time width. Except for a very short time in a transient state where the levels of the sequence control signals Sa and Sb are switched, one of the sequence control signals Sa and Sb has a high level and the other has a low level, and the levels of the sequence control signals Sa and Sb are switched every time a rising edge of the comparison signal Cout occurs. In the initial state of the power supply control device 2A, the sequence control signal Sb has a high level and the sequence control signal Sa has a low level. At time t A0 At time t A0 At time t, the signals Cout, GH[1], T_Vramp[1], Ton_SET[1], Ton_RST[1] and T_Vramp_RST[1] all have a low level. A0 The time t immediately after A1 In this case, an odd-numbered rising edge occurs in the comparison signal Cout.

[0076] When the sequence control signal input to the driver 61[1] is at a high level, and a rising edge occurs in the comparison signal Cout, the driver 61[1] performs a response operation RES A In the power supply control device 2A shown in FIG. 10, the sequence control signal input to the driver 61[1] is the sequence control signal Sb, and is input at time t A1 Therefore, at time t A1 In response to the rising edge of the comparison signal Cout at time t A2 Response operation at RES A [1] is performed. At time t A2 is time t A1 Although this is a time that is later than the circuit delay time, it is actually time t A1 is equal to.

[0077] Response operation RES A In [1], the driver 61[1] generates a rising edge in the gate signal GH[1] to switch the state of the output stage circuit MM[1] from the output low state or both off state to the output high state. A In [1], the driver 61[1] generates a rising edge in each of the signals T_Vramp[1] and Ton_SET[1], and also generates a rising edge in the sequence control signal (here, signal Sa) that it outputs. Note that even if a rising edge occurs in the comparison signal Cout when the sequence control signal (here, signal Sb) input to the driver 61[1] has a low level, the driver 61[1] does not perform the response operation RES A Do not execute [1].

[0078] The on-timer circuit 62[1] is a response operation RES A In response to the rising edge of the signal Ton_SET[1] based on [1], the time elapsed from the timing of the rising edge of the signal Ton_SET[1] (hereinafter referred to as the elapsed time t EA [1]) is measured as the elapsed time t EA [1] is time t A2 The on-timer circuit 62[1] measures the elapsed time t EA [1] The time t when the reversal trigger time Trvs is reached A3 At time t A3 A falling edge is generated in the signal T_Vramp[1] in response to the rising edge of the signal T_Vramp_RST[1] at time t A3 It ends with.

[0079] The on-timer circuit 62[1] also detects the elapsed time t EA [1] The time t when the on-time Ton (the on-time Ton of the first channel) is reached A4At time t A4 At time t, the driver 61[1] generates a falling edge in the gate signal GH[1] in response to the rising edge of the signal Ton_RST[1]. This causes the state of the output stage circuit MM[1] to switch from an output high state to an output low state (strictly speaking, by generating a rising edge in the gate signal GL[1] via the falling edge of the gate signal GH[1], the state of the output stage circuit MM[1] switches from an output high state to an output low state via both OFF states). The driver 61[1] also generates a falling edge in the gate signal GL[1] at time t A4 Immediately after generating a fall edge in the gate signal GH[1] (or approximately simultaneously with the fall edge of the gate signal GH[1]), the on-timer circuit 62[1] generates a fall edge in the signal Ton_SET[1]. In response to the fall edge of the signal Ton_SET[1], the on-timer circuit 62[1] generates a fall edge in the signal Ton_RST[1]. The on-timer circuit 62[1] sets the inversion trigger time Trvs to half (or slightly shorter than half) of the on-time Ton of the transistor MH in the output stage circuit MM[1].

[0080] FIG. 14 shows the waveforms of signals and voltages in the on-timer circuit 62[1]. Slope voltages Vslp_a[1] and Vslp_b[1] are generated inside the on-timer circuit 62[1], and a reference voltage Vref[1] for determining the on-time Ton is also generated. The reference voltage Vref[1] has a positive DC voltage value. The on-timer circuit 62[1] can adjust the on-time Ton of the first channel by adjusting the reference voltage Vref[1]. The slope voltages Vslp_a[1] and Vslp_b[1] are, in principle, 0V. The on-timer circuit 62[1] determines the time t when the rising edge of the signal Ton_SET[1] occurs. A2 (see FIG. 13), the slope voltages Vslp_a[1] and Vslp_b[1] are each monotonically increased at a common and constant rate of increase from 0V.

[0081] time t A2 After that, at time tA3 In the figure, the on-timer circuit 62[1] generates a rising edge in the signal T_Vramp_RST[1], and then, after a short time has elapsed, causes the slope voltage Vslp_b[1] to drop sharply to 0 V. The signal T_Vramp_RST[1] represents the relationship between the slope voltage Vslp_b[1] and the voltage (Vref[1] / 2), and a falling edge occurs in the signal T_Vramp_RST[1] when the slope voltage Vslp_b[1] falls below the voltage (Vref[1] / 2) in the process of the slope voltage Vslp_b[1] dropping to 0 V.

[0082] time t A2 After that, at time t A4 In this example, the on-timer circuit 62[1] generates a rising edge in the signal Ton_RST[1], and then, after a short time has elapsed, the slope voltage Vslp_a[1] is rapidly reduced to 0 V. The reduction in the slope voltage Vslp_a[1] may be triggered by a falling edge in the signal Ton_SET[1]. The signal Ton_RST[1] represents the relationship between the slope voltage Vslp_a[1] and the reference voltage Vref[1], and a falling edge occurs in the signal Ton_RST[1] when the slope voltage Vslp_a[1] falls below the reference voltage Vref[1] during the reduction of the slope voltage Vslp_a[1] to 0 V.

[0083] The voltage (Vref[1] / 2) is half the voltage of the reference voltage Vref[1]. The slope voltages Vslp_a[1] and Vslp_b[1] rise at the same rate. A2 and t A3 The inversion trigger time Trvs, which corresponds to the time difference between the two, is half the on-time Ton of the first channel. The slope voltage Vslp_a[1] can be generated by a constant current circuit and a capacitor charged by the constant current from the constant current circuit. The slope voltage Vslp_b[1] is generated in the same way.

[0084] 15, the operation in response to an even-numbered rising edge of the comparison signal Cout will be described.A10 , t A11 , t A12 , t A13 , t A14 occurs in this order. At time t A10 At time t A10 At time t, the signals Cout, GH[2], T_Vramp[2], Ton_SET[2], Ton_RST[2], and T_Vramp_RST[2] all have a low level. A10 The time t immediately after A11 In this case, an even-numbered rising edge occurs in the comparison signal Cout.

[0085] When the sequence control signal input to the driver 61[2] is at a high level, and a rising edge occurs in the comparison signal Cout, the driver 61[2] performs a response operation RES A In the power supply control device 2A shown in FIG. 10, the sequence control signal input to the driver 61[2] is the sequence control signal Sa, which is input at time t A11 Therefore, at time t A11 In response to the rising edge of the comparison signal Cout at time t A12 Response operation at RES A [2] is performed. At time t A12 is time t A11 Although this is a time that is later than the circuit delay time, it is actually time t A11 is equal to.

[0086] Response operation RES A In [2], the driver 61[2] generates a rising edge in the gate signal GH[2] to switch the state of the output stage circuit MM[2] from the output low state or both off state to the output high state. AIn [2], the driver 61[2] generates a rising edge in each of the signals T_Vramp[2] and Ton_SET[2], and also generates a rising edge in the sequence control signal (here, signal Sb) that it outputs. Note that even if a rising edge occurs in the comparison signal Cout when the sequence control signal (here, signal Sa) input to the driver 61[2] has a low level, the driver 61[2] does not perform the response operation RES A Do not perform [2].

[0087] The on-timer circuit 62[2] is a response operation RES A In response to the rising edge of the signal Ton_SET[2] based on [2], the elapsed time from the timing of the rising edge of the signal Ton_SET[2] (hereinafter referred to as the elapsed time t EA [2]) is measured as the elapsed time t EA [2] is time t A12 The on-timer circuit 62[2] measures the elapsed time t EA [2] The time t when the reversal trigger time Trvs is reached A13 At time t A13 In response to the rising edge of the signal T_Vramp_RST[2] at time t A13 It ends with.

[0088] The on-timer circuit 62[2] also detects the elapsed time t EA [2] The time t when the on-time Ton (the on-time Ton of the second channel) is reached A14 At time t A14At time t, the driver 61[2] generates a falling edge in the gate signal GH[2] in response to the rising edge of the signal Ton_RST[2]. This causes the state of the output stage circuit MM[2] to switch from an output high state to an output low state (strictly speaking, by generating a rising edge in the gate signal GL[2] via the falling edge of the gate signal GH[2], the state of the output stage circuit MM[2] switches from an output high state to an output low state via both OFF states). The driver 61[2] also generates a falling edge in the gate signal GL[2] at time t A14 Immediately after generating a fall edge in the gate signal GH[2] (or approximately simultaneously with the fall edge of the gate signal GH[2]), the on-timer circuit 62[2] generates a fall edge in the signal Ton_SET[2]. In response to the fall edge of the signal Ton_SET[2], the on-timer circuit 62[2] generates a fall edge in the signal Ton_RST[2]. The on-timer circuit 62[2] sets the inversion trigger time Trvs to half (or slightly shorter than half) of the on-time Ton of the transistor MH in the output stage circuit MM[2].

[0089] FIG. 16 shows the waveforms of signals and voltages in the on-timer circuit 62[2]. Slope voltages Vslp_a[2] and Vslp_b[2] are generated inside the on-timer circuit 62[2], and a reference voltage Vref[2] for determining the on-time Ton is also generated. The reference voltage Vref[2] has a positive DC voltage value. The on-timer circuit 62[2] can adjust the on-time Ton of the second channel by adjusting the reference voltage Vref[2]. The slope voltages Vslp_a[2] and Vslp_b[2] are, in principle, 0V. The on-timer circuit 62[2] determines the time t when the rising edge of the signal Ton_SET[2] occurs. A12 (see FIG. 15), the slope voltages Vslp_a[2] and Vslp_b[2] are each monotonically increased at a common constant rate of increase from 0V.

[0090] time t A12 After that, at time t A13In the signal T_Vramp_RST[2], the on-timer circuit 62[2] generates a rising edge in the signal T_Vramp_RST[2], and then, after a short time has elapsed, causes the slope voltage Vslp_b[2] to drop sharply to 0 V. The signal T_Vramp_RST[2] represents the relationship between the slope voltage Vslp_b[2] and the voltage (Vref[2] / 2), and when the slope voltage Vslp_b[2] falls below the voltage (Vref[2] / 2) in the process of the slope voltage Vslp_b[2] dropping to 0 V, a falling edge occurs in the signal T_Vramp_RST[2].

[0091] time t A12 After that, at time t A14 In this example, the on-timer circuit 62[2] generates a rising edge in the signal Ton_RST[2], and then, after a short time has elapsed, the slope voltage Vslp_a[2] is rapidly reduced to 0 V. The reduction in the slope voltage Vslp_a[2] may be triggered by a falling edge in the signal Ton_SET[2]. The signal Ton_RST[2] represents the relationship between the slope voltage Vslp_a[2] and the reference voltage Vref[2], and a falling edge occurs in the signal Ton_RST[2] when the slope voltage Vslp_a[2] falls below the reference voltage Vref[2] during the reduction of the slope voltage Vslp_a[2] to 0 V.

[0092] The voltage (Vref[2] / 2) is half the voltage of the reference voltage Vref[2]. The slope voltages Vslp_a[2] and Vslp_b[2] rise at the same rate. A12 and t A13 The inversion trigger time Trvs, which corresponds to the time difference between the two, is half the on-time Ton of the second channel. The slope voltage Vslp_a[2] can be generated using a constant current circuit and a capacitor charged by the constant current from the constant current circuit. The same is true for the slope voltage Vslp_b[2]. Note that the rate of rise for all slope voltages (Vslp_a[1], Vslp_b[1], Vslp_a[2], and Vslp_b[2]) is equal to one another.

[0093] Except for a short period during transient response (at least in steady state), "Vref[1] = Vref[2]" or "Vref[1] = Vref[2]" can be considered, so the on-time Ton of the first channel and the on-time Ton of the second channel are equal. A single reference voltage may be shared as the reference voltages Vref[1] and Vref[2].

[0094] FIG. 17 shows a timing chart of the switching power supply device 1A. Note that FIG. 17 shows the switch voltages Vsw[1] and Vsw[2] while ignoring the existence of dead time. From top to bottom in FIG. 17, the switch voltage Vsw[1], switch voltage Vsw[2], composite voltage (Vramp+Vfb), comparison signal Cout, gate signal GH[1], gate signal GH[2], signal Vramp_CTL, signal T_Vramp[1], signal Ton_SET[1], signal Ton_RST[1], slope voltage Vslp_a[1], signal T_Vramp_RST[1], slope voltage Vslp_b[1], signal T_Vramp[2], signal Ton_SET[2], signal Ton_RST[2], slope voltage Vslp_a[2], signal T_Vramp_RST[2], and slope voltage Vslp_b[2] are shown as solid line waveforms. In FIG. 17, the error voltage Verr, the reference voltage Vref[1], the voltage (Vref[1] / 2), the reference voltage Vref[2], and the voltage (Vref[2] / 2) are indicated by five dashed waveforms extending horizontally in the drawing.

[0095] 17, a case is assumed in which the output voltage Vout is stabilized at the target voltage Vtg when the sum of the on-duty of the first channel and the on-duty of the second channel exceeds 100%. In the steady state in which the output voltage Vout is stabilized at the target voltage Vtg, the feedback voltage Vfb and the error voltage Verr are maintained constant. In response to the rising edge of the comparison signal Cout, the ramp voltage Vramp increases only for a time (Ton / 2) after a rising edge occurs in the signal T_Vramp[1] or T_Vramp[2], and decreases otherwise.

[0096] Starting from the state shown in Figure 17, if the load current increases and the output voltage Vout falls below the target voltage Vtg, the feedback voltage Vfb decreases and the error voltage Verr increases, causing the interval between rising edges of the comparison signal Cout to become shorter than in Figure 17. As a result, the on-duties of the first and second channels become larger than in Figure 17, and the output voltage Vout increases toward the target voltage Vtg. Conversely, starting from the state shown in Figure 17, if the load current decreases and the output voltage Vout becomes higher than the target voltage Vtg, the feedback voltage Vfb increases and the error voltage Verr decreases, causing the interval between rising edges of the comparison signal Cout to become longer than in Figure 17. As a result, the on-duties of the first and second channels become smaller than in Figure 17, and the output voltage Vout decreases toward the target voltage Vtg. This feedback control ensures high responsiveness to fluctuations in the load current.

[0097] The signal T_Vramp[i] functions as a ramp command signal that specifies the direction of change of the ramp voltage Vramp. The state of the signal T_Vramp[i] is either negated or asserted. The asserted signal T_Vramp[i] specifies that the ramp voltage Vramp should change in an upward direction. The ramp circuit 41 outputs the ramp voltage Vramp according to the contents of the ramp command signals (T_Vramp[1] and T_Vramp[2]). The negated signal T_Vramp[i] does not specify that the ramp voltage Vramp should change in an upward direction. In this embodiment, the negated state corresponds to a low-level signal T_Vramp[i], and the asserted state corresponds to a high-level signal T_Vramp[i] (however, these correspondences can be reversed).

[0098] The switching control circuits (61[1], 62[1], 61[2], 62[2]) according to the second embodiment supply first and second ramp command signals (T_Vramp[1], T_Vramp[2]) to the ramp voltage generating circuits (41, 42) (see FIG. 10). In response to the level of the comparison signal Cout switching from a non-active level (low level) to an active level (high level), the switching control circuits (61[1], 62[1], 61[2], 62[2]) switch the i-th ramp command signal (T_Vramp[i]) from a negated state (low level) to an asserted state (high level) when switching the transistor MH of the i-th channel from off to on, and then switch the i-th ramp command signal (T_Vramp[i]) from the asserted state to the negated state when the inversion trigger time Trvs has elapsed (see FIGS. 13 and 15; i is a natural number equal to or less than n). The ramp voltage generating circuits (41, 42) set the ramp voltage Vramp to a first direction during a period when both the first and second ramp command signals are negated, and set the ramp voltage Vramp to a second direction during a period when either the first or second ramp command signal is asserted. In this embodiment, the first direction is a downward direction and the second direction is an upward direction.

[0099] The second embodiment includes the following examples EX2_1 and EX2_2.

[0100] [Example EX2_1] Example EX2_1 will be described. In FIG. 10, the switching power supply device 1 when "n=2" is shown as switching power supply device 1A, but as described above, the value of n (number of channels) is any value equal to or greater than 2. For example, when "n=3" in the second embodiment, a circuit group for a third channel is added to the switching device 1A shown in FIG. 10. The circuit group for the third channel includes a coil L[3], and a driver 61[3], an on-timer circuit 62[3], and an output stage circuit MM[3] that are added to the power supply control device 2A of FIG. 10 (see FIG. 18).

[0101] 18 shows a partial configuration of the power supply control device 2 (2A) when "n=3". The operation of the driver 61[3] and the on-timer circuit 62[3] is the same as the operation of the driver 61[1] and the on-timer circuit 62[1]. Regarding the operation of the driver 61[1] and the on-timer circuit 62[1], the symbol "[1]" in the above description and the symbol "[1]" associated with the input / output signals of the driver 61[1] and the on-timer circuit 62[1] can be replaced with the symbol "[i]", and it is sufficient to consider that the variable i is 1, 2, or 3.

[0102] However, when "n=3", the sequence control signals Sa, Sb, and Sc are transmitted and received between the drivers 61[1] to 61[3]. The sequence control signal Sc is a binary signal having a high level or a low level, just like the sequence control signals Sa and Sb. When "n=3", through the transmission and reception of the sequence control signals Sa to Sc, the driver 61[1] performs a response operation RES in response to only the (1+3×m)th rising edge of the group of rising edges in the comparison signal Cout. A [1] is performed (see FIG. 13), and the driver 61 [2] performs a response operation RES in response to only the (2+3×m)th rising edge of the group of rising edges in the comparison signal Cout. A [2] is performed (see FIG. 15), and the driver 61[3] performs a response operation RES in response to only the (3+3×m)th rising edge of the group of rising edges in the comparison signal Cout. A [3] is performed, where m represents any integer equal to or greater than 0. When "n=3", the sequence control signal Sa is supplied from the driver 61[1] to the driver 61[2], the sequence control signal Sb is supplied from the driver 61[2] to the driver 61[3], and the sequence control signal Sc is supplied from the driver 61[3] to the driver 61[1].

[0103] Except for a short time in a transient state when the levels of the sequence control signals Sa to Sc are switched, only one of the sequence control signals Sa to Sc has a high level, and the remaining two sequence control signals have a low level. Then, every time a rising edge of the comparison signal Cout occurs, the sequence control signal having a high level is alternated between the sequence control signals Sa to Sc. In the initial state of the power supply control device 2 (2A) when "n=3", the sequence control signal Sc has a high level, and the sequence control signals Sa and Sb have low levels.

[0104] When a rising edge occurs in the comparison signal Cout while the sequence control signal input to the driver 61[1] (signal Sc in the configuration of FIG. 18) is at a high level, the driver 61[1] performs a response operation RES A When a rising edge occurs in the comparison signal Cout while the sequence control signal input to the driver 61 (signal Sa in the configuration of FIG. 18) is at a high level, the driver 61 [2] performs a response operation RES A When a rising edge occurs in the comparison signal Cout while the sequence control signal (signal Sb in the configuration of FIG. 18) input to the driver 61[3] is at a high level, the driver 61[3] performs a response operation RES A [3] is performed. Response operation RES A The response action RES is obtained by replacing the symbol "[1]" in the above explanation with the symbol "[3]". A Equivalent to [3].

[0105] Therefore, the response action RES AIn [3], the driver 61[3] generates a rising edge in the signal T_Vramp[3] that it outputs. After that, when the inversion trigger time Trvs has elapsed, the driver 61[3] generates a falling edge in the signal T_Vramp[3] based on the output of the on-timer circuit 62[3]. When "n=3", the logical sum signal of the signals T_Vramp[1] to T_Vramp[3] is input to the ramp circuit 41 as the signal Vramp_CTL. The ramp circuit 41 sets the change direction of the ramp voltage Vramp to an upward direction during a period when any of the signals T_Vramp[1] to T_Vramp[3] is at a high level, and sets the change direction of the ramp voltage Vramp to a downward direction during a period when all of the signals T_Vramp[1] to T_Vramp[3] are at a low level.

[0106] When "n=3", the drivers 61[1] to 61[3] and the on-timer circuits 62[1] to 62[3] form the switching control circuit 6 in Fig. 7. The same applies when "n≧4".

[0107] Generalizing the case where n represents an arbitrary integer equal to or greater than 2, the switching control circuit 6 and ramp voltage generating circuit 4 (see FIG. 7) according to the second embodiment can be said to operate as follows. That is, each time the level of the comparison signal Cout switches from a non-active level (low level) to an active level (high level), the switching control circuit 6 according to the second embodiment switches one of the transistors MH of the first to n-th channels from off to on, maintains the on state for a specified on-time Ton, and then switches the transistor MH back to off. At this time, the switching control circuit 6 sequentially switches the transistor MH to be switched from off to on among the transistors MH of the first to n-th channels. That is, assuming that the active level is high, the switching control circuit 6 switches the transistor MH of the j-th channel from off to on in response to the (j+n×m)-th rising edge of the comparison signal Cout (j represents an arbitrary natural number equal to or less than n, and m represents an arbitrary integer equal to or greater than 0). A switching control circuit 6, which is composed of drivers 61[1] to 61[n] and on-timer circuits 62[1] to 62[n], supplies signals T_Vramp[1] to T_Vramp[n], which are first to n-th ramp command signals, to the ramp voltage generation circuit 4 (41, 42). When the level of the comparison signal Cout switches from a non-active level (low level) to an active level (high level), the switching control circuit 6 switches the i-th ramp command signal (T_Vramp[i]) from a negated state (low level) to an asserted state (high level) when the transistor MH of the i-th channel switches from off to on. After that, when a reversal trigger time Trvs has elapsed, the switching control circuit 6 switches the i-th ramp command signal from the asserted state to the negated state (see FIGS. 13 and 15). The reversal trigger time Trvs is set to be equal to or shorter than the time (Ton / n). The ramp voltage generating circuit 4 (41, 42) of the second embodiment sets the direction of change of the ramp voltage Vramp to a first direction (decreasing direction) during a period when the first to nth ramp command signals (T_Vramp[1] to T_Vramp[n]) are all in a negated state, and sets the direction of change of the ramp voltage Vramp to a second direction (increasing direction) during a period when any of the first to nth ramp command signals is in an asserted state.

[0108] The signal Vramp_CTL may be interpreted as a ramp command signal (single ramp command signal). The switching control circuit 6 switches the signal Vramp_CTL from a negated state (low level) to an asserted state (high level) when switching the transistor MH of any channel from off to on in response to the level of the comparison signal Cout switching from a non-active level (low level) to an active level (high level), and then switches the signal Vramp_CTL from the asserted state to the negated state when the inversion trigger time Trvs has elapsed.

[0109] [Example EX2_2] An example EX2_2 will be described. The method for measuring the inversion trigger time Trvs is arbitrary. For example, as shown in FIG. 19, the rate of increase of the slope voltage Vslp_b[1] is set to twice the rate of increase of the slope voltage Vslp_a[1], and the slope voltage Vslp_b[1] is increased at time t A2 The slope voltage Vslp_b[1] starts rising from 0V and reaches the reference voltage Vref[1] at time t A3 The on-timer circuit 62[1] may generate a rising edge in the signal T_Vramp_RST[1]. This allows the inversion trigger time Trvs to be set to half the on-time Ton of the first channel. The same applies to the second channel.

[0110] Generalizing n as an arbitrary integer equal to or greater than 2, for any natural number i equal to or less than n (see FIGS. 13 and 14), the on-timer circuit 62[i] may operate as follows: That is, the on-timer circuit 62[i] may make the slope voltages Vslp_a[i] and Vslp_b[i] rise at a common rate, start the slope voltages Vslp_a[i] and Vslp_b[i] from 0 V at the timing of the rising edge of the signal Ton_SET[i], set the on-time Ton to the time from the rise start timing until the slope voltage Vslp_a[i] reaches the reference voltage Vref[i], and set the inversion trigger time Trvs to the time from the rise start timing until the slope voltage Vslp_b[i] reaches a voltage (Vref[i] / n) or a voltage that is a small voltage lower than the voltage (Vref[i] / n).

[0111] Alternatively, for any natural number i less than or equal to n (see Figures 13 and 19), the on-timer circuit 62[i] sets the rate of rise of the slope voltage Vslp_b[i] to n times the rate of rise of the slope voltage Vslp_a[i], and then causes the slope voltages Vslp_a[i] and Vslp_b[i] to start rising from 0 V at the timing of the rising edge of the signal Ton_SET[i], sets the time from the timing at which the rise starts until the slope voltage Vslp_a[i] reaches the reference voltage Vref[i] to the on-time Ton, and sets the time from the timing at which the rise starts until the slope voltage Vslp_b[i] reaches the reference voltage Vref[i] or until it reaches a voltage that is a small voltage lower than the reference voltage Vref[i] to the inversion trigger time Trvs.

[0112] <<Third Embodiment>> A third embodiment of the present disclosure will now be described. FIG. 20 shows the configuration of a switching device 1B, which is a switching device 1 according to the third embodiment. The switching device 1B includes a power supply control device 2B as a power supply control device 2 (see FIG. 7). In the third embodiment, unless otherwise specified, it is assumed that "n=2". The power supply control device 2B includes semiconductor devices SD[1] and SD[2], which are two electronic components separated from each other.

[0113] FIG. 21 is a perspective view of the semiconductor devices SD[1] and SD[2]. The semiconductor device SD[i] is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) for accommodating the semiconductor chip, and multiple external terminals exposed from the housing to the outside of the semiconductor device SD[i]. The semiconductor device SD[i] is formed by encapsulating the semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the semiconductor device SD[i] and the type of housing for the semiconductor device SD[i] shown in FIG. 21 are merely examples and can be designed arbitrarily. The multiple external terminals provided on the semiconductor device SD[1] include an input terminal IN, a switch terminal SW[1], a ground terminal GND, and a feedback terminal FB, as well as link terminals TI[1], TO[1], and TC[1]. Other external terminals may also be provided on the semiconductor device SD[1]. The semiconductor device SD[2] has a plurality of external terminals including an input terminal IN, a switch terminal SW[2], and a ground terminal GND, as well as interconnection terminals TI[2], TO[2], and TC[2]. Other external terminals may also be provided in the semiconductor device SD[2].

[0114] The switching device 1B includes coils L[1] and L[2], an output capacitor C1, and feedback resistors R1 and R2, as shown in the first embodiment. The connections between the coils L[1] and L[2], the output capacitor C1, the feedback resistors R1 and R2, the switch terminals SW[1] and SW[2], the feedback terminal FB, the output terminal OUT, and the ground are the same as those shown in the first embodiment.

[0115] A common input voltage Vin is supplied to the input terminals IN of the semiconductor devices SD[1] and SD[2]. The ground terminals GND of the semiconductor devices SD[1] and SD[2] are connected to ground. The wiring WRa, WRb, and WRcmp are external wiring provided outside the semiconductor devices SD[1] and SD[2]. The interconnection terminal TO[1] is connected to the interconnection terminal TI[2] through the external wiring WRa. The interconnection terminal TI[1] is connected to the interconnection terminal TO[2] through the external wiring WRb. The interconnection terminal TC[1] is connected to the interconnection terminal TC[2] through the external wiring WRcmp.

[0116] The semiconductor device SD[1] includes an output stage circuit MM[1], an error amplifier 31, a phase compensation circuit 32, a reference power supply 33, a ramp circuit 41, a comparator 51, a driver 66[1], an on-timer circuit 67[1], and a ramp timer circuit 68. However, the output stage circuit MM[1] may be provided outside the semiconductor device SD[1]. The phase compensation circuit 32 may also be provided outside the semiconductor device SD[1]. The semiconductor device SD[2] includes an output stage circuit MM[2], a driver 66[2], and an on-timer circuit 67[2]. However, the output stage circuit MM[2] may be provided outside the semiconductor device SD[2]. The driver 66[1] and the on-timer circuit 67[1] are the driver and on-timer circuit for the first channel (CH1), and the driver 66[2] and the on-timer circuit 67[2] are the driver and on-timer circuit for the second channel (CH2).

[0117] The error amplifier 31 and the phase compensation circuit 32 form the error voltage generation circuit 3 in Fig. 7. However, it may be understood that the reference voltage source 33 is also included in the components of the error voltage generation circuit 3. The ramp circuit 41 forms the ramp voltage generation circuit 4 in Fig. 7. The comparator 51 corresponds to the comparison circuit 5 in Fig. 7. The drivers 66[1] and 66[2], the on-timer circuits 67[1] and 67[2], and the ramp timer circuit 68 form the switching control circuit 6 in Fig. 7.

[0118] The semiconductor device SD[1] functions as a controller-side device in multiphase control, and the semiconductor device SD[2] functions as a target-side device in multiphase control. The first or second configuration method can be used to configure the semiconductor devices SD[1] and SD[2]. In the first configuration method, the semiconductor devices SD[1] and SD[2] are different types of semiconductor devices with different configurations. In the second configuration method, two semiconductor devices with the same configuration are used as the semiconductor devices SD[1] and SD[2]. In the second configuration method, each semiconductor device has the components of the semiconductor device SD[1] in FIG. 20, but the semiconductor device functioning as the semiconductor device SD[2] has a circuit group consisting of the error amplifier 31, phase compensation circuit 32, reference voltage source 33, ramp circuit 41, comparator 51, and ramp timer circuit 68 that stops operating. In the second configuration method, the semiconductor device that receives the first setting signal functions as the semiconductor device SD[1], and the semiconductor device that receives the second setting signal functions as the semiconductor device SD[2]. For example, each semiconductor device according to the second configuration method may be provided with a setting terminal, and of the two semiconductor devices, the semiconductor device having the setting terminal receiving the first setting signal (e.g., a high-level setting signal) may function as the semiconductor device SD[1], and the semiconductor device having the setting terminal receiving the second setting signal (e.g., a low-level setting signal) may function as the semiconductor device SD[2]. The first setting signal may be supplied to one of the two semiconductor devices, and the second setting signal may be supplied to the other, from a microcomputer or the like provided outside the two semiconductor devices.

[0119] The configurations and operations of the error amplifier 31, phase compensation circuit 32, reference voltage source 33, ramp circuit 41, and comparator 51 in the power supply control device 2B are the same as those of the error amplifier 31, phase compensation circuit 32, reference voltage source 33, ramp circuit 41, and comparator 51 shown in the second embodiment. Therefore, the power supply control device 2B also obtains the comparison signal Cout according to the signal relationship shown in FIG. 12. However, in the power supply control device 2B, a signal Vramp_CTL is supplied from a driver 66[1] to the ramp circuit 41. Also in the power supply control device 2B, the comparison signal Cout output from the comparator 51 is supplied to drivers 66[1] and 66[2].

[0120] The driver 66[1] supplies gate signals GH[1] and GL[1] to the gates of the transistors MH and ML in the output stage circuit MM[1], respectively, to turn on and off the transistors MH and ML in the output stage circuit MM[1]. The driver 66[1] also outputs a signal Ton_SET[1] to the on timer circuit 67[1], a signal T_Vramp_SET to the ramp timer circuit 68, and a signal Vramp_CTL to the ramp circuit 41.

[0121] Similar to the driver 66[1], the driver 66[2] supplies gate signals GH[2] and GL[2] to the gates of the transistors MH and ML in the output stage circuit MM[2], respectively, to turn on and off the transistors MH and ML in the output stage circuit MM[2]. The driver 66[2] also outputs a signal Ton_SET[2] to the on-timer circuit 67[2].

[0122] The on-timer circuit 67[1] has a first measurement function for measuring the on-time Ton of the first channel (i.e., a function for measuring whether the elapsed time since the transistor MH of the output stage circuit MM[1] switched from off to on has reached the specified on-time Ton), and outputs a signal Ton_RST[1] indicating the measurement result of the first measurement function to the driver 66[1]. The on-timer circuit 67[1] is connected to the switch terminal SW[1]. The on-timer circuit 67[1] determines the on-duty of the output stage circuit MM[1] from the average voltage of the switch voltage Vsw[1] and the input voltage Vin, and can set the on-time Ton of the first channel according to the on-duty of the output stage circuit MM[1].

[0123] Like the on-timer circuit 67[1], the on-timer circuit 67[2] has a first measurement function for measuring the on-time Ton of the second channel (i.e., a function for measuring whether the elapsed time since the transistor MH of the output stage circuit MM[2] switched from off to on has reached the specified on-time Ton), and outputs a signal Ton_RST[2] indicating the measurement result of the first measurement function to the driver 66[2]. The on-timer circuit 67[2] is connected to the switch terminal SW[2]. The on-timer circuit 67[2] determines the on-duty of the output stage circuit MM[2] from the average voltage of the switch voltage Vsw[2] and the input voltage Vin, and can set the on-time Ton of the second channel according to the on-duty of the output stage circuit MM[2].

[0124] The ramp timer circuit 68 has a second measurement function of measuring the reversal trigger time Trvs (see FIG. 9), and outputs a signal T_Vramp_RST indicating the measurement result of the second measurement function to the driver 66[1]. The second measurement function of the ramp timer circuit 68 is a function of measuring whether the elapsed time from when the transistor MH of the output stage circuit MM[1] or MM[2] switches from off to on has reached the reversal trigger time Trvs, in other words, a function of measuring whether the length of the rising period of the ramp voltage Vramp has reached the reversal trigger time Trvs.

[0125] Queue control signals Sa and Sb are transmitted and received between the drivers 66[1] and 66[2]. Inside the semiconductor device SD[1], the driver 66[1] is connected to the link terminals TO[1] and TI[1], and inside the semiconductor device SD[2], the driver 66[2] is connected to the link terminals TO[2] and TI[2]. The driver 66[1] outputs the queue control signal Sa to the link terminal TO[1]. Therefore, the queue control signal Sa from the driver 66[1] is input to the driver 66[2] via the link terminal TO[1], external wiring WRa, and link terminal TI[2]. The driver 66[2] outputs the queue control signal Sb to the link terminal TO[2]. Therefore, the queue control signal Sb from the driver 66[2] is input to the driver 66[1] via the link terminal TO[2], external wiring WRb, and link terminal TI[1]. The signals Ton_SET[i], Ton_RST[i], T_Vramp_SET, T_Vramp_RST, Vramp_CTL, Sa, and Sb are all binary signals having a high level or a low level.

[0126] In the power supply control device 2B, the comparison signal Cout output from the comparator 51 is supplied to the driver 66[1] in the semiconductor device SD[1] and also to the linking terminal TC[1]. Since the linking terminal TC[1] is connected to the linking terminal TC[2] by the external wiring WRcmp, the comparison signal Cout output from the comparator 51 is also supplied to the driver 66[2] via the linking terminal TC[1], the external wiring WRcmp, and the linking terminal TC[2].

[0127] 22, the operation in response to the odd-numbered rising edge of the comparison signal Cout will be described. B0 , t B1 , t B2 , t B3 , t B4occur in this order. Except for a short time in a transient state where the levels of the sequence control signals Sa and Sb are switched, one of the sequence control signals Sa and Sb has a high level and the other has a low level, and the levels of the sequence control signals Sa and Sb are switched every time a rising edge of the comparison signal Cout occurs. In the initial state of the power supply control device 2B, the sequence control signal Sb has a high level and the sequence control signal Sa has a low level. At time t B0 At time t B0 At time t, the signals Cout, GH[1], Vramp_CTL, Ton_SET[1], T_VRAMP_SET, Ton_RST[1], and T_Vramp_RST all have a low level. B0 The time t immediately after B1 In this case, an odd-numbered rising edge occurs in the comparison signal Cout.

[0128] When the sequence control signal input to the driver 66[1] has a high level, and a rising edge occurs in the comparison signal Cout, the driver 66[1] performs a response operation RES B In the power supply control device 2B shown in FIG. 20, the sequence control signal input to the driver 66[1] is the sequence control signal Sb, and is input at time t B1 Therefore, at time t B1 In response to the rising edge of the comparison signal Cout at time t B2 Response operation at RES B [1] is performed. At time t B2 is time t B1 Although this is a time that is later than the circuit delay time, it is actually time t B1 is equal to.

[0129] Response operation RES B In [1], the driver 66[1] generates a rising edge in the gate signal GH[1] to switch the state of the output stage circuit MM[1] from the output low state or both off state to the output high state. BIn [1], the driver 66[1] generates a rising edge in each of the signals Vramp_CTL, Ton_SET[1], and T_Vramp_SET, and also generates a rising edge in the sequence control signal (here, signal Sa) that it outputs. Note that even if a rising edge occurs in the comparison signal Cout when the sequence control signal (here, signal Sb) input to the driver 66[1] has a low level, the driver 66[1] does not respond with a response operation RES B Do not execute [1].

[0130] The on-timer circuit 67[1] is the response operation RES B In response to the rising edge of the signal Ton_SET[1] based on [1], the ramp timer circuit 68 measures the elapsed time from the timing of the rising edge of the signal Ton_SET[1]. B In response to the rising edge of the signal T_Vramp_SET based on [1], the elapsed time from the timing of the rising edge of the signal T_Vramp_SET is measured. B [1], the rising edges of the signals Ton_SET[1] and T_Vramp_SET occur at time t B2 Therefore, both the on-timer circuit 67[1] and the lamp timer circuit 68 are turned on at time t B2 The time elapsed since (hereinafter referred to as the elapsed time t EB [1]) will be measured.

[0131] The ramp timer circuit 68 detects the elapsed time t EB [1] The time t when the reversal trigger time Trvs is reached B3 The driver 66[1] generates a rising edge in the signal T_Vramp_RST at time t B3 In response to the rising edge of the signal T_Vramp_RST at time t B2 The ramp voltage Vramp rises at time t B3 The driver 66[1] also ends at time t B3When the ramp timer circuit 68 receives a rising edge of the signal T_Vramp_RST, it generates a falling edge of the signal T_Vramp_SET after a predetermined short time has elapsed. In response to the falling edge of the signal T_Vramp_SET, the ramp timer circuit 68 generates a falling edge of the signal T_Vramp_RST.

[0132] The on-timer circuit 67[1] also detects the elapsed time t EB [1] The time t when the on-time Ton (the on-time Ton of the first channel) is reached B4 At time t B4 At time t, the driver 66[1] generates a falling edge in the gate signal GH[1] in response to the rising edge of the signal Ton_RST[1]. This causes the state of the output stage circuit MM[1] to switch from an output high state to an output low state (strictly speaking, by generating a rising edge in the gate signal GL[1] via the falling edge of the gate signal GH[1], the state of the output stage circuit MM[1] switches from an output high state to an output low state via both OFF states). The driver 66[1] also generates a falling edge in the gate signal GL[1] at time t B4 Immediately after generating a fall edge in the gate signal GH[1] (or approximately simultaneously with the fall edge of the gate signal GH[1]), the on-timer circuit 67[1] generates a fall edge in the signal Ton_SET[1] in response to the fall edge of the signal Ton_SET[1]. The ramp timer circuit 68 sets the inversion trigger time Trvs to half (or slightly shorter than half) of the on-time Ton of the transistor MH in the output stage circuit MM[1].

[0133] FIG. 23 shows the waveforms of signals and voltages in the on timer circuit 67[1] and the ramp timer circuit 68. A slope voltage Vslp_a[1] is generated inside the on timer circuit 67[1], and a slope voltage Vslp_b[1] is generated inside the ramp timer circuit 68. The on timer circuit 67[1] also generates and sets a reference voltage Vref[1]. The reference voltage Vref[1] has a positive DC voltage value. The on timer circuit 67[1] can adjust the on time Ton of the first channel by adjusting the reference voltage Vref[1]. A voltage (Vref[1] / 2) that is half the reference voltage Vref[1] set by the on timer circuit 67[1] is supplied to the ramp timer circuit 68. The slope voltages Vslp_a[1] and Vslp_b[1] are, in principle, 0V. The on timer circuit 67[1] and the ramp timer circuit 68 generate and set a slope voltage Vslp_a[1] and a slope voltage Vslp_b[1] based on the time t when the rising edge of the signal Ton_SET[1] occurs. B2 (See FIG. 22), the slope voltages Vslp_a[1] and Vslp_b[1] are monotonically increased at a common and constant rate of increase starting from 0V.

[0134] time t B2 After that, at time t B3 At , the ramp timer circuit 68 generates a rising edge in the signal T_Vramp_RST, and then, after a short time has elapsed, causes the slope voltage Vslp_b[1] to drop sharply to 0V. The drop of the slope voltage Vslp_b[1] to 0V is triggered by the falling edge of the signal T_Vramp_SET (see also FIG. 22). The signal T_Vramp_RST represents the high / low relationship between the slope voltage Vslp_b[1] and the voltage (Vref[1] / 2), and a falling edge occurs in the signal T_Vramp_RST when the slope voltage Vslp_b[1] falls below the voltage (Vref[1] / 2) during the process of the slope voltage Vslp_b[1] dropping to 0V.

[0135] time t B2 After that, at time t B4In this example, the on-timer circuit 67[1] generates a rising edge in the signal Ton_RST[1], and then, after a short time has elapsed, it sharply reduces the slope voltage Vslp_a[1] to 0V. The reduction of the slope voltage Vslp_a[1] to 0V is triggered by the falling edge of the signal Ton_SET[1] (see also FIG. 22). The signal Ton_RST[1] represents the relationship between the slope voltage Vslp_a[1] and the reference voltage Vref[1], and a falling edge occurs in the signal Ton_RST[1] when the slope voltage Vslp_a[1] falls below the reference voltage Vref[1] during the reduction of the slope voltage Vslp_a[1] to 0V.

[0136] The voltage (Vref[1] / 2) is half the voltage of the reference voltage Vref[1]. The slope voltages Vslp_a[1] and Vslp_b[1] rise at the same rate. B2 and t B3 The inversion trigger time Trvs, which corresponds to the time difference between the two, is half the on-time Ton of the first channel. The slope voltage Vslp_a[1] can be generated by a constant current circuit and a capacitor charged by the constant current from the constant current circuit. The slope voltage Vslp_b[1] is generated in the same way.

[0137] 24, the operation in response to the even-numbered rising edges of the comparison signal Cout will be described. B10 , t B11 , t B12 , t B13 , t B14 occurs in this order. At time t B10 At time t B10 At time t, the signals Cout, GH[2], Vramp_CTL, Ton_SET[2], T_VRAMP_SET, Ton_RST[2], and T_Vramp_RST all have a low level. B10 The time t immediately after B11 In this case, an even-numbered rising edge occurs in the comparison signal Cout.

[0138] time t B11 In response to the rising edge of the comparison signal Cout at time t B12 Response operation at RES B [2] is performed. At time t B12 is time t B11 Although this is a time that is later than the circuit delay time, it is actually time t B11 Equal to . Response action RES B [2] is partly performed by driver 66[2], and the response action RES B The rest of [2] is executed by the driver 66[1]. When the sequence control signal input to the driver 66[2] has a high level and a rising edge occurs in the comparison signal Cout, the driver 66[2] performs a response operation RES B In the power supply control device 2B shown in FIG. 20, the sequence control signal input to the driver 66[2] is the sequence control signal Sa, which is input at time t B11 Therefore, at time t B11 Responsive operation RES in response to the rising edge of the comparison signal Cout B A part of the operation of [2] is performed by the driver 66[2]. When the sequence control signal input to the driver 66[1] has a low level and a rising edge occurs in the comparison signal Cout, the driver 66[1] performs a response operation RES B In the power supply control device 2B shown in FIG. 20, the sequence control signal input to the driver 66[1] is the sequence control signal Sb, and the remaining operation of [2] is performed. B11 At time t B11 Responsive operation RES in response to the rising edge of the comparison signal Cout B The remaining operations of [2] are performed by the driver 66[1].

[0139] Response operation RES B In a partial operation of [2], the driver 66[2] generates a rising edge in the gate signal GH[2] to switch the state of the output stage circuit MM[2] from the output low state or both off state to the output high state.B In a partial operation of [2], the driver 66[2] generates a rising edge in the signal Ton_SET[2] and also generates a rising edge in the sequence control signal (here, the signal Sb) that it outputs. B In the remaining operation of [2], the driver 66[1] generates a rising edge in each of the signals Vramp_CTL and T_Vramp_SET. Note that even if a rising edge occurs in the comparison signal Cout when the sequence control signal (here, the signal Sa) input to the driver 66[2] has a low level, the driver 66[2] continues the response operation RES B [2] Some operations are not performed.

[0140] The on-timer circuit 67[2] is the response operation RES B In response to the rising edge of the signal Ton_SET[2] based on [2], the ramp timer circuit 68 measures the elapsed time from the timing of the rising edge of the signal Ton_SET[2]. B In response to the rising edge of the signal T_Vramp_SET based on [2], the time elapsed from the timing of the rising edge of the signal T_Vramp_SET is measured. B [2], the rising edges of the signals Ton_SET[2] and T_Vramp_SET occur at time t B12 Therefore, both the on-timer circuit 67[2] and the lamp timer circuit 68 are turned on at time t B12 The time elapsed since (hereinafter referred to as the elapsed time t EB [2]) will be measured.

[0141] The ramp timer circuit 68 detects the elapsed time t EB [2] The time t when the reversal trigger time Trvs is reached B13 The driver 66[1] generates a rising edge in the signal T_Vramp_RST at time t B13 In response to the rising edge of the signal T_Vramp_RST at time t B12The ramp voltage Vramp rises at time t B13 The driver 66[1] also ends at time t B13 When the ramp timer circuit 68 receives a rising edge of the signal T_Vramp_RST, it generates a falling edge of the signal T_Vramp_SET after a predetermined short time has elapsed. In response to the falling edge of the signal T_Vramp_SET, the ramp timer circuit 68 generates a falling edge of the signal T_Vramp_RST.

[0142] The on-timer circuit 67[2] also detects the elapsed time t EB [2] The time t when the on-time Ton (the on-time Ton of the second channel) is reached B14 At time t B14 At time t, the driver 66[2] generates a falling edge in the gate signal GH[2] in response to the rising edge of the signal Ton_RST[2]. This causes the state of the output stage circuit MM[2] to switch from an output high state to an output low state (strictly speaking, by generating a rising edge in the gate signal GL[2] via the falling edge of the gate signal GH[2], the state of the output stage circuit MM[2] switches from an output high state to an output low state via both OFF states). The driver 66[2] also generates a falling edge in the gate signal GL[2] at time t B14 Immediately after generating a fall edge in the gate signal GH[2] (or approximately simultaneously with the fall edge of the gate signal GH[2]), the on-timer circuit 67[2] generates a fall edge in the signal Ton_SET[2]. In response to the fall edge of the signal Ton_SET[2], the on-timer circuit 67[2] generates a fall edge in the signal Ton_RST[2]. The ramp timer circuit 68 sets the inversion trigger time Trvs to half (or slightly shorter than half) of the on-time Ton of the transistor MH in the output stage circuit MM[2].

[0143] FIG. 25 shows the waveforms of signals and voltages in the on-timer circuit 67[2] and ramp timer circuit 68. A slope voltage Vslp_a[2] is generated inside the on-timer circuit 67[2], and a slope voltage Vslp_b[1] is generated inside the ramp timer circuit 68. The on-timer circuit 67[2] also generates and sets a reference voltage Vref[2]. The reference voltage Vref[2] has a positive DC voltage value. The on-timer circuit 67[2] can adjust the on-time Ton of the second channel by adjusting the reference voltage Vref[2]. The slope voltages Vslp_a[2] and Vslp_b[1] are, in principle, 0V. The on-timer circuit 67[2] and ramp timer circuit 68 generate a signal and a voltage waveform based on the rising edge occurrence time t of the signals Ton_SET[2] and T_Vramp_SET. B12 (See FIG. 24), the slope voltages Vslp_a[2] and Vslp_b[1] are monotonically increased at a common and constant rate of increase from 0V as a starting point.

[0144] time t B12 After that, at time t B13 At , the ramp timer circuit 68 generates a rising edge in the signal T_Vramp_RST, and then, after a short time has elapsed, causes the slope voltage Vslp_b[1] to drop sharply to 0V. The drop of the slope voltage Vslp_b[1] to 0V is triggered by the falling edge of the signal T_Vramp_SET (see also FIG. 24). The signal T_Vramp_RST represents the high / low relationship between the slope voltage Vslp_b[1] and the voltage (Vref[1] / 2), and a falling edge occurs in the signal T_Vramp_RST when the slope voltage Vslp_b[1] falls below the voltage (Vref[1] / 2) during the process of the slope voltage Vslp_b[1] dropping to 0V.

[0145] time t B12 After that, at time t B14In this example, the on-timer circuit 67[2] generates a rising edge in the signal Ton_RST[2], and then, after a short time has elapsed, it sharply reduces the slope voltage Vslp_a[2] to 0V. The reduction of the slope voltage Vslp_a[2] to 0V is triggered by the falling edge of the signal Ton_SET[2] (see also FIG. 24). The signal Ton_RST[2] represents the relationship between the slope voltage Vslp_a[2] and the reference voltage Vref[2], and a falling edge occurs in the signal Ton_RST[2] when the slope voltage Vslp_a[2] falls below the reference voltage Vref[2] during the reduction of the slope voltage Vslp_a[2] to 0V.

[0146] The rates of rise of the slope voltages Vslp_a[1], Vslp_a[2], and Vslp_b[1] are equal to each other (see Figures 23 and 25). Except for a short period during transient response (at least in the steady state), "Vref[1] = Vref[2]" or "Vref[1] = Vref[2]" can be considered, so the voltage (Vref[1] / 2) is half the voltage of the reference voltage Vref[2]. Therefore, at time t B12 and t B13 The inversion trigger time Trvs, which corresponds to the time difference between these two, is half the on-time Ton of the second channel. Also, when "Vref[1] = Vref[2]", the on-time Ton of the first channel and the on-time Ton of the second channel are equal. A single reference voltage may be shared as the reference voltages Vref[1] and Vref[2]. The slope voltage Vslp_a[2] can be generated using a constant current circuit and a capacitor charged by the constant current from the constant current circuit. The same applies to the slope voltage Vslp_b[1].

[0147] FIG. 26 shows a timing chart for the switching power supply device 1B. Note that in FIG. 26, the switch voltages Vsw[1] and Vsw[2] are shown ignoring the existence of dead time. From top to bottom in FIG. 26, the switch voltage Vsw[1], switch voltage Vsw[2], composite voltage (Vramp+Vfb), comparison signal Cout, gate signal GH[1], gate signal GH[2], signal Vramp_CTL, signal Ton_SET[1], signal Ton_RST[1], slope voltage Vslp_a[1], signal T_Vramp_SET, signal T_Vramp_RST, slope voltage Vslp_b[1], signal Ton_SET[2], signal Ton_RST[2], and slope voltage Vslp_a[2] are shown as solid line waveforms. In FIG. 26, the error voltage Verr, the reference voltage Vref[1], the voltage (Vref[1] / 2), and the reference voltage Vref[2] are indicated by four dashed waveforms extending in the horizontal direction of the drawing.

[0148] 26, a case is assumed in which the output voltage Vout is stabilized at the target voltage Vtg when the sum of the on-duty of the first channel and the on-duty of the second channel exceeds 100%. In the steady state in which the output voltage Vout is stabilized at the target voltage Vtg, the feedback voltage Vfb and the error voltage Verr are maintained constant. In response to the rising edge of the comparison signal Cout, the ramp voltage Vramp rises for a period of time (Ton / 2) after the rising edge of the signal Vramp_CTL appears, and otherwise the ramp voltage Vramp falls.

[0149] Starting from the state shown in Figure 26, if the load current increases and the output voltage Vout falls below the target voltage Vtg, the feedback voltage Vfb decreases and the error voltage Verr increases, causing the interval between rising edges of the comparison signal Cout to become shorter than in Figure 26. As a result, the on-duties of the first and second channels become larger than in Figure 26, and the output voltage Vout increases toward the target voltage Vtg. Conversely, starting from the state shown in Figure 26, if the load current decreases and the output voltage Vout becomes higher than the target voltage Vtg, the feedback voltage Vfb increases and the error voltage Verr decreases, causing the interval between rising edges of the comparison signal Cout to become longer than in Figure 26. As a result, the on-duties of the first and second channels become smaller than in Figure 26, and the output voltage Vout decreases toward the target voltage Vtg. This feedback control enables high responsiveness to fluctuations in the load current.

[0150] The signal Vramp_CTL functions as a ramp command signal that specifies the direction of change of the ramp voltage Vramp. The signal Vramp_CTL is in either a negated state or an asserted state. An asserted signal Vramp_CTL specifies that the ramp voltage Vramp should change in an upward direction. The ramp circuit 41 outputs the ramp voltage Vramp according to the contents specified by the ramp command signal (Vramp_CTL). A negated signal Vramp_CTL does not specify that the ramp voltage Vramp should change in an upward direction. In this embodiment, a low-level signal Vramp_CTL corresponds to a negated state, and a high-level signal Vramp_CTL corresponds to an asserted state (however, these correspondences can be reversed).

[0151] The switching control circuits (66[1], 67[1], 66[2], 67[2], and 68) according to the third embodiment supply a ramp command signal (Vramp_CTL) to the ramp voltage generating circuit (41) (see FIG. 20). In response to the level of the comparison signal Cout switching from a non-active level (low level) to an active level (high level), the switching control circuits (66[1], 67[1], 66[2], 67[2], and 68) switch the ramp command signal (Vramp_CTL) from a negated state (low level) to an asserted state (high level) when switching the transistor MH of any channel from off to on, and then switch the ramp command signal from the asserted state to the negated state after the inversion trigger time Trvs has elapsed (see FIGS. 22 and 24). The ramp voltage generating circuit (41) sets the ramp voltage Vramp to change in a first direction during a period when the ramp command signals are in a negated state, and sets the ramp voltage Vramp to change in a second direction during a period when any of the ramp command signals is in an asserted state. In this embodiment, the first direction is a decreasing direction, and the second direction is an increasing direction.

[0152] The third embodiment includes the following Examples EX3_1 to EX3_3.

[0153] [Example EX3_1] Example EX3_1 will be described. In FIG. 20, the switching power supply device 1 when "n=2" is shown as switching power supply device 1B, but as described above, the value of n (number of channels) is any value equal to or greater than 2. For example, when "n=3" in the third embodiment, a circuit group for a third channel is added to the switching device 1B shown in FIG. 20. The circuit group for the third channel includes a coil L[3], and a driver 66[3], an on-timer circuit 67[3], and an output stage circuit MM[3] that are added to the power supply control device 2B of FIG. 20 (see FIG. 27).

[0154] FIG. 27 shows a partial configuration of the power supply control device 2 (2B) when "n=3". When "n=3", the power supply control device 2 (2B) is formed by three semiconductor devices SD[1] to SD[3], which are separate electronic components. The semiconductor device SD[3] has the same configuration as the semiconductor device SD[2]. The driver and on-timer circuit provided in the semiconductor device SD[3] corresponding to the driver 66[2] and on-timer circuit 67[2] of the semiconductor device SD[2] are the driver 66[3] and on-timer circuit 67[3]. The three linking terminals (three external terminals) provided in the semiconductor device SD[3] corresponding to the linking terminals TI[2], TO[2], and TC[2] of the semiconductor device SD[2] are the linking terminals TI[3], TO[3], and TC[3]. When "n=3", external wiring provided outside the semiconductor devices SD[1] to SD[3] connects the interconnection terminals TO[1] and TI[2], connects the interconnection terminals TO[2] and TI[3], and connects the interconnection terminals TO[3] and TI[1], and also connects the interconnection terminals TC[1], TC[2], and TC[3] to each other. The comparison signal Cout generated in the semiconductor device SD[1] is supplied to the driver 66[1] and is also supplied to the interconnection terminal TC[1]. The comparison signal Cout generated in the semiconductor device SD[1] is also supplied to the drivers 66[2] and 66[3] via the interconnection terminals TC[1], TC[2], and TC[3].

[0155] The operation of the driver 66[3] and the on-timer circuit 67[3] is similar to that of the driver 66[2] and the on-timer circuit 67[2], and the above description of the operation of the driver 66[2] and the on-timer circuit 67[2] also applies to the driver 66[3] and the on-timer circuit 67[3]. In this application, the symbol "[2]" in the above description of the operation of the driver 66[2] and the on-timer circuit 67[2], as well as the symbol "[2]" associated with the input / output signals of the driver 66[2] and the on-timer circuit 67[2], should be replaced with the symbol "[3]".

[0156] However, when "n=3", the sequence control signals Sa, Sb, and Sc are transmitted and received between the drivers 66[1] to 66[3]. The sequence control signal Sc is a binary signal having a high level or a low level, just like the sequence control signals Sa and Sb. When "n=3", through the transmission and reception of the sequence control signals Sa to Sc, the driver 66[1] performs a response operation RES in response to only the (1+3×m)th rising edge of the group of rising edges in the comparison signal Cout. B The driver 66[2] performs the response operation RES in response to only the (2+3×m)th rising edge of the group of rising edges in the comparison signal Cout (see FIG. 22). B The driver 66[3] performs a partial operation of [2] (see FIG. 24), and performs a response operation RES in response to only the (3+3×m)th rising edge of the group of rising edges in the comparison signal Cout. B The driver 66[1] performs a part of the operation of [3] in response to the (2+3×m)th rising edge of the group of rising edges in the comparison signal Cout. B The remaining operation of [2] is performed (see Figure 24), and the response operation RES is performed in response to the (3+3×m)th rising edge. B The remaining operations of [3] are performed. m represents any integer equal to or greater than 0. When "n=3", the sequence control signal Sa is supplied from the driver 66[1] to the driver 66[2] via the linking terminals TO[1] and TI[2], the sequence control signal Sb is supplied from the driver 66[2] to the driver 66[3] via the linking terminals TO[2] and TI[3], and the sequence control signal Sc is supplied from the driver 66[3] to the driver 66[1] via the linking terminals TO[3] and TI[1].

[0157] Except for a short time in a transient state when the levels of the sequence control signals Sa to Sc are switched, only one of the sequence control signals Sa to Sc has a high level, and the remaining two sequence control signals have a low level. Then, every time a rising edge of the comparison signal Cout occurs, the sequence control signal having a high level is alternated between the sequence control signals Sa to Sc. In the initial state of the power supply control device 2 (2B) when "n=3", the sequence control signal Sc has a high level, and the sequence control signals Sa and Sb have low levels.

[0158] When a rising edge occurs in the comparison signal Cout while the sequence control signal input to the driver 66[1] (signal Sc in the configuration of FIG. 27) is at a high level, the driver 66[1] performs a response operation RES B When a rising edge occurs in the comparison signal Cout while the sequence control signal input to the driver 66 (signal Sa in the configuration of FIG. 27) is at a high level, the driver 66 [2] performs a response operation RES B When a rising edge occurs in the comparison signal Cout while the sequence control signal (signal Sb in the configuration of FIG. 27) input to the driver 66[3] is at a high level, the driver 66[3] performs a response operation RES B Part of the operation in [3] is performed. Response operation RES B Regarding the partial operation of [2], the operation obtained by replacing the symbol "[2]" in the above explanation with the symbol "[3]" is the response operation RES B When a rising edge occurs in the comparison signal Cout while the sequence control signal (signal Sc in the configuration of FIG. 27) input to the driver 66[1] is at a low level, the driver 66[1] performs a response operation RES B [2] Residual action or response action RES B [3] Perform the remaining operations. Response operation RES B The remaining action of [3] is the response action RES B This is the same operation as the remaining part of [2].

[0159] When "n=3", the drivers 66[1] to 66[3], the on-timer circuits 67[1] to 67[3], and the ramp timer circuit 68 form the switching control circuit 6 in Fig. 7. The same applies when "n≧4".

[0160] Generalizing the operation of n as an integer equal to or greater than 2, the switching control circuit 6 and ramp voltage generating circuit 4 according to the third embodiment can be said to operate as follows. Specifically, the switching control circuit 6 according to the third embodiment switches one of the transistors MH of the first to n-th channels from off to on each time the level of the comparison signal Cout switches from a non-active level (low level) to an active level (high level), maintains the transistor MH on for a specified on-time Ton, and then switches the transistor MH back to off. At this time, the switching control circuit 6 sequentially switches the transistor MH to be switched on from off among the transistors MH of the first to n-th channels. In other words, assuming that the active level is high, the switching control circuit 6 switches the transistor MH of the j-th channel from off to on in response to the (j+n×m)-th rising edge of the comparison signal Cout (j represents any natural number equal to or less than n, and m represents any integer equal to or greater than 0). The switching control circuit 6, which is composed of drivers 66[1] to 66[n], on-timer circuits 67[1] to 67[n], and a ramp timer circuit 68, supplies a signal Vramp_CTL, which is a ramp command signal, to the ramp voltage generation circuit 4 (41). When the level of the comparison signal Cout switches from a non-active level (low level) to an active level (high level), the switching control circuit 6 switches the ramp command signal (Vramp_CTL) from a negated state (low level) to an asserted state (high level) when switching the transistor MH of any channel from off to on. After that, when the reversal trigger time Trvs has elapsed, the switching control circuit 6 switches the ramp command signal from the asserted state to the negated state (see FIGS. 22 and 24). The reversal trigger time Trvs is set to be equal to or less than the time (Ton / n). The ramp voltage generating circuit 4 (41) of the third embodiment sets the direction of change of the ramp voltage Vramp to a first direction (decreasing direction) during the period when the ramp command signal is in a negated state, and sets the direction of change of the ramp voltage Vramp to a second direction (increasing direction) during the period when the ramp command signal is in an asserted state.

[0161] [Example EX3_2] An example EX3_2 will be described. The method for measuring the inversion trigger time Trvs is arbitrary. For example, as shown in FIG. 28, the rate of increase of the slope voltage Vslp_b[1] is set to twice the rate of increase of the slope voltage Vslp_a[1], and the slope voltage Vslp_b[1] is increased at time t B2 The slope voltage Vslp_b[1] starts rising from 0V and reaches the reference voltage Vref[1] at time t B3 In this case, the ramp timer circuit 68 may generate a rising edge in the signal T_Vramp_RST. This allows half the on-time Ton of the first channel to be set as the inversion trigger time Trvs. The same applies to the second channel. That is, by setting the rate of rise of the slope voltage Vslp_b[1] to twice the rate of rise of the slope voltages Vslp_a[1] and Vslp_a[2], half the on-time Ton may be set as the inversion trigger time Trvs.

[0162] Generalizing the case where n represents any integer equal to or greater than 2, the ramp timer circuit 68 may operate as follows: That is, the ramp timer circuit 68 sets the rate of increase of the slope voltage Vslp_b[1] to the rate of increase of the slope voltages Vslp_a[1] to Vslp_a[n] equal to the rate of increase of the slope voltages Vslp_b[1], starts increasing the slope voltage Vslp_b[1] from the timing of occurrence of the rising edge of the signal T_Vramp_SET, and sets the inversion trigger time Trvs to the time from the timing of start of the increase until the slope voltage Vslp_b[1] reaches the voltage (Vref[1] / n) or the time until it reaches a voltage that is a small voltage lower than the voltage (Vref[1] / n).

[0163] Alternatively, the ramp timer circuit 68 may set the rate of rise of the slope voltage Vslp_b[1] to n times the rate of rise of the slope voltages Vslp_a[1] to Vslp_a[n], and then start rising the slope voltage Vslp_b[1] from the timing when the rising edge of the signal T_Vramp_SET occurs, and set the inversion trigger time Trvs to the time from the timing when the slope voltage Vslp_b[1] starts to rise until it reaches the reference voltage Vref[1] or until it reaches a voltage that is a small voltage lower than the reference voltage Vref[1].

[0164] [Example EX3_3] An example EX3_3 will be described. The power supply control device 2B shown in FIG. 20 may be configured with a single semiconductor device SD (see FIG. 11), which is a single electronic component. In this case, all of the components described as being provided in the semiconductor devices SD[1] and SD[2] with reference to FIG. 20 are provided in the single semiconductor device SD, and in this case, the link terminals TO[1], TI[1], TC[1], TO[2], TI[2], and TC[2] are interpreted as internal nodes provided in the single semiconductor device SD, and the external wiring WRa, WRb, and WRcmp are interpreted as internal wiring provided in the single semiconductor device SD. The same applies to the case where "n≧3".

[0165] <<Fourth Embodiment>> A fourth embodiment of the present disclosure will be described. In the fourth embodiment, some modified techniques or supplementary matters to the above-described embodiments will be described.

[0166] A modified version MOD4_1 in which the direction of change of the lamp voltage Vramp is opposite to that of the above-described example may be applied to the power supply control device 2A or 2B. When the modified version MOD4_1 is applied, as shown in FIG. 29, the lamp circuit 41 sets the direction of change of the lamp voltage Vramp to the rising direction during the period when the signal Vramp_CTL is in the negative state (low level), and sets the direction of change of the lamp voltage Vramp to the falling direction during the period when the signal Vramp_CTL is in the asserted state (high level). However, when the modified version MOD4_1 is applied, the error amplifier 31 is modified such that the error voltage Verr rises in response to the establishment of "Vfb > Vref_fb" and the error voltage Verr falls in response to the establishment of "Vfb < Vref_fb", and the comparator 51 is modified such that the comparison signal Cout has a non-active level (low level) during the period when "Vramp + Vfb < Verr" is established and the comparison signal Cout has an active level (high level) during the period when "Vramp + Vfb > Verr" is established. Note that either the low level or the high level of the signal Vramp_CTL can be arbitrarily assigned to the negative state and the asserted state. Similarly, either the low level or the high level of the comparison signal Cout can be arbitrarily assigned to the non-active level and the active level.

[0167] In addition, regarding any signal or voltage, the relationship between their high level and low level can be reversed in a form that does not impair the above-mentioned gist.

[0168] Although it duplicates what has already been described, as shown in FIG. 30, the output stage circuits MM[1] to MM[n] may be provided outside the power supply control device 2 and connected to the power supply control device 2. That is, in the switching power supply device 1A of FIG. 10, the output stage circuits MM[1] and MM[2] may be provided outside the semiconductor device SD, and in the switching power supply device 1B of FIG. 20, the output stage circuits MM[1] and MM[2] may be provided outside the semiconductor devices SD[1] and SD[2].

[0169] The switching power supply device (1, 1A, 1B) shown in each embodiment can be mounted in any electrical device, such as an electrical component mounted in a vehicle such as an automobile, a computer, a home appliance, or an industrial device.

[0170] The channel types of the FETs (field effect transistors) shown in the above-described embodiments are merely examples. The channel type of any FET may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0171] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0172] In the present disclosure, any first physical quantity and any second physical quantity being "the same" is understood as a concept that includes errors. In other words, a first physical quantity and a second physical quantity being "the same" means that they are designed or manufactured with the aim of making the first physical quantity and the second physical quantity "the same." Even if there is a slight error between the first and second physical quantities, the first physical quantity and the second physical quantity should be understood as being "the same." This applies not only to physical quantities, but also to expressions similar to "the same" (e.g., "identical" or "matching"), and should be interpreted in the same way.

[0173] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0174] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0175] A power supply control device according to one aspect of the present disclosure is a power supply control device (2, 2A, 2B) used in a switching power supply device (1, 1A, 1B) configured to generate a plurality of rectangular wave switch voltages (Vsw[1] to Vsw[n]) at switch terminals (SW[1] to SW[n]) for a plurality of channels by individually switching an input voltage (Vin) using output stage circuits (MM[1] to MM[n]) for a plurality of channels, each including an output transistor (MH), and to generate an output voltage (Vout) by rectifying and smoothing the plurality of switch voltages, the power supply control device comprising: an error voltage generation circuit (3) configured to generate an error voltage (Verr) corresponding to an error between a feedback voltage (Vfb) corresponding to the output voltage and a predetermined reference voltage (Vref_fb); a ramp voltage generation circuit (4) configured to generate a ramp voltage (Vramp) that alternately rises and falls; and a voltage control circuit (5) configured to have an active level or a non-active level based on the high-low relationship between two voltages based on the error voltage, the ramp voltage, and the feedback voltage. and a switching control circuit (6) that sequentially controls the output transistors of the plurality of channels to be on for a specified on-time (Ton) while shifting the on-times of the output transistors of the plurality of channels based on the comparison signal, wherein the switching control circuit switches the output transistor of any one of the channels from off to on and returns it to off after the specified on-time has elapsed every time the level of the comparison signal switches from the non-active level to the active level, and the ramp voltage generation circuit switches the direction of change of the ramp voltage from a first direction to a second direction every time the level of the comparison signal switches from the non-active level to the active level, and thereafter switches the direction of change of the ramp voltage from the second direction to the first direction after a reversal trigger time (Trvs) has elapsed that is set to be equal to or less than the time (Ton / n) obtained by dividing the specified on-time by the number of channels (first configuration).

[0176] This makes it possible to perform desired multiphase control even in cases where output transistors of two or more channels are simultaneously turned on.

[0177] The power supply control device according to the first configuration may be configured (second configuration) such that the level of the comparison signal switches between the active level and the non-active level each time the relationship between the combined voltage (Vramp+Vfb) of the ramp voltage and the feedback voltage and the error voltage (Verr) in the comparator circuit is reversed.

[0178] In the power supply control device according to the second configuration (see FIG. 12), the error voltage generating circuit may be configured to lower the error voltage when the feedback voltage is higher than the reference voltage and to raise the error voltage when the feedback voltage is lower than the reference voltage, the comparison signal may have the inactive level when the composite voltage is higher than the error voltage and the active level when the composite voltage is lower than the error voltage, and the first direction may be a lowering direction and the second direction may be an ascending direction (third configuration).

[0179] In the power supply control device according to the second configuration (see FIG. 29), the error voltage generating circuit may be configured so that it increases the error voltage when the feedback voltage is higher than the reference voltage and decreases the error voltage when the feedback voltage is lower than the reference voltage, the comparison signal has the inactive level when the composite voltage is lower than the error voltage and the active level when the composite voltage is higher than the error voltage, and the first direction is an increasing direction and the second direction is a decreasing direction (fourth configuration).

[0180] In the power supply control devices according to the first to fourth configurations (see FIG. 10), the multiple channels are first to n-th channels, n represents an integer equal to or greater than 2, the output stage circuits for the multiple channels are first to n-th channel output stage circuits (MM[1] to MM[n]), and the switching control circuit switches one of the output transistors of the first to n-th channels from off to on and maintains it on for the specified on-time every time the level of the comparison signal switches from the non-active level to the active level, and the switching control circuit supplies first to n-th ramp command signals (T_Vramp[1] to T_Vramp[n]), each having an asserted state or a negated state, to the ramp voltage generation circuits (41, 42), and is switched from the non-active level to the active level, the ith ramp command signal (T_Vramp[i]) is switched from the negated state to the asserted state when the output transistor of the ith channel is switched from off to on, and thereafter, when the inversion trigger time has elapsed, the ith ramp command signal is switched from the asserted state to the negated state, where i represents a natural number equal to or less than n, and the ramp voltage generation circuit may be configured to set the change direction of the ramp voltage to the first direction during a period when all of the first to nth ramp command signals are in the negated state, and to set the change direction of the ramp voltage to the second direction during a period when any of the first to nth ramp command signals is in the asserted state (fifth configuration).

[0181] In the power supply control devices according to the first to fourth configurations (see FIG. 20), the multiple channels are first to n-th channels, n represents an integer equal to or greater than 2, the output stage circuits for the multiple channels are first to n-th channel output stage circuits (MM[1] to MM[n]), the switching control circuit switches any of the output transistors of the first to n-th channels from off to on and maintains the on state for the specified on-time every time the level of the comparison signal switches from the non-active level to the active level, and the switching control circuit supplies a ramp command signal (T_Vramp_CTL) having an asserted state or a negated state to the ramp voltage generation circuit (41); The ramp command signal may be switched from the negated state to the asserted state when an output transistor of any channel is switched from off to on in response to the level of the comparison signal switching from the non-active level to the active level, and then, when the inversion trigger time has elapsed, the ramp command signal is switched from the asserted state to the negated state, and the ramp voltage generating circuit may be configured to set the change direction of the ramp voltage to the first direction during the period when the ramp command signal is in the negated state, and to set the change direction of the ramp voltage to the second direction during the period when the ramp command signal is in the asserted state (sixth configuration).

[0182] The power supply control device according to any one of the first to sixth configurations (see FIG. 7) may have a configuration (seventh configuration) in which output stage circuits for the plurality of channels are provided in the power supply control device.

[0183] In the power supply control device according to any of the first to sixth configurations (see FIG. 30), the power supply control device may be configured (eighth configuration) in which the output stage circuits for the multiple channels provided outside the power supply control device are connected to the power supply control device.

[0184] A switching power supply device according to one aspect of the present disclosure (see FIG. 7) includes a power supply control device according to any one of the first to sixth configurations described above, and a rectifying and smoothing circuit configured to generate the output voltage by rectifying and smoothing the multiple switch voltages, and has a configuration (ninth configuration) in which output stage circuits for the multiple channels are provided in the power supply control device.

[0185] A switching power supply device according to another aspect of the present disclosure (see FIG. 30) has a configuration (tenth configuration) including a power supply control device according to any one of the first to sixth configurations described above, output stage circuits for the multiple channels connected to the power supply control device, and a rectifying and smoothing circuit configured to generate the output voltage by rectifying and smoothing the multiple switch voltages. [Explanation of symbols]

[0186] 910, 920 Switching source device 914, 924 Error amplifier 915, 925 Lamp voltage generation circuit 911, 921_1, 921_2 output stage circuit 912, 922_1, 922_2 coils 913, 923 Output capacitor 1, 1A, 1B Switching Power Supply 2, 2A, 2B power control device 3 Error voltage generation circuit 4. Lamp voltage generation circuit 5 Comparison circuit 6 Switching control circuit Vin Input voltage Vout Output voltage L, L[1]~L[n] coils C1 Output capacitor OUT output terminal LD load R1, R2 feedback resistors FB Feedback terminal IN input terminal GND Ground terminal SW, SW[1]~SW[n] Switch terminals MM, MM[1]~MM[n] output stage circuit MH transistor (output transistor) ML transistor (synchronous rectification transistor) Vfb Feedback voltage Vref_fb Reference voltage Verr error voltage Vramp Ramp voltage Cout comparison voltage GH, GH[1]~GH[n], GL, GL[1]~GL[n] Gate signals Ton On time Trvs Reverse trigger time 31 Error amplifier 32 Phase compensation circuit 33 Reference voltage source 41 Lamp circuit 42 OR circuit 51 Comparator 61[1]~61[3], 66[1]~66[3] drivers 62[1]~62[3], 67[1]~67[3] On-timer circuit 68 Lamp timer circuit SD, SD[1]~SD[3] Semiconductor device TO[1]~TO[3], TI[1]~TI[3], TC[1]~TC[3] Linkage terminals WRa, WRb, WRcmp external wiring

Claims

1. A power supply control device used in a switching power supply device configured to generate a plurality of rectangular wave switch voltages at switch terminals for a plurality of channels by individually switching an input voltage using output stage circuits for a plurality of channels, each including an output transistor, and to generate an output voltage by rectifying and smoothing the plurality of switch voltages, an error voltage generating circuit configured to generate an error voltage corresponding to an error between a feedback voltage corresponding to the output voltage and a predetermined reference voltage; a ramp voltage generating circuit configured to generate a ramp voltage that alternately rises and falls; a comparison circuit configured to generate a comparison signal having an active level or a non-active level based on a high-low relationship between two voltages based on the error voltage, the ramp voltage, and the feedback voltage; a switching control circuit that sequentially controls the output transistors of the plurality of channels to be turned on for a specified on-time while shifting the on-times of the output transistors of the plurality of channels based on the comparison signal, the switching control circuit switches the output transistor of any one of the channels from off to on and returns it to off after the specified on-time has elapsed every time the level of the comparison signal switches from the non-active level to the active level; The ramp voltage generating circuit switches the direction of change of the ramp voltage from a first direction to a second direction every time the level of the comparison signal switches from the non-active level to the active level, and thereafter, when an inversion trigger time has elapsed that is set to be equal to or less than the time obtained by dividing the specified on-time by the number of channels, switches the direction of change of the ramp voltage from the second direction to the first direction. , power control device.

2. In the comparator circuit, the level of the comparison signal is switched between the active level and the non-active level every time the level relationship between the composite voltage of the ramp voltage and the feedback voltage and the error voltage is reversed. The power supply control device according to claim 1 .

3. the error voltage generating circuit reduces the error voltage when the feedback voltage is higher than the reference voltage and increases the error voltage when the feedback voltage is lower than the reference voltage; the comparison signal has the inactive level when the composite voltage is higher than the error voltage and the active level when the composite voltage is lower than the error voltage; The first direction is a downward direction and the second direction is an upward direction. The power supply control device according to claim 2 .

4. the error voltage generating circuit increases the error voltage when the feedback voltage is higher than the reference voltage and decreases the error voltage when the feedback voltage is lower than the reference voltage; the comparison signal has the inactive level when the composite voltage is lower than the error voltage and the active level when the composite voltage is higher than the error voltage; The first direction is an upward direction and the second direction is a downward direction. The power supply control device according to claim 2 .

5. the plurality of channels are first to n-th channels, where n is an integer of 2 or more; the output stage circuits for the plurality of channels are output stage circuits for first to n-th channels, the switching control circuit switches any one of the output transistors of the first to n-th channels from off to on and maintains it on for the specified on-time every time the level of the comparison signal switches from the non-active level to the active level; the switching control circuit supplies first to n-th ramp command signals, each having an asserted state or a negated state, to the ramp voltage generating circuit, switches the i-th ramp command signal from the negated state to the asserted state when switching the output transistor of the i-th channel from off to on in response to the level of the comparison signal switching from the non-active level to the active level, and thereafter switches the i-th ramp command signal from the asserted state to the negated state when the inversion trigger time has elapsed, where i represents a natural number equal to or less than n; The ramp voltage generating circuit sets the change direction of the ramp voltage to the first direction during a period when all of the first to n-th ramp command signals are in the negated state, and sets the change direction of the ramp voltage to the second direction during a period when any of the first to n-th ramp command signals is in the asserted state.

5. The power supply control device according to claim 1.

6. the plurality of channels are first to n-th channels, where n is an integer of 2 or more; the output stage circuits for the plurality of channels are output stage circuits for first to n-th channels, the switching control circuit switches any one of the output transistors of the first to n-th channels from off to on and maintains it on for the specified on-time every time the level of the comparison signal switches from the non-active level to the active level; the switching control circuit supplies a ramp command signal having an asserted state or a negated state to the ramp voltage generating circuit, switches the ramp command signal from the negated state to the asserted state when switching an output transistor of any one of the channels from off to on in response to the level of the comparison signal switching from the non-active level to the active level, and thereafter switches the ramp command signal from the asserted state to the negated state when the inversion trigger time has elapsed; The ramp voltage generating circuit sets the change direction of the ramp voltage to the first direction during a period in which the ramp command signal is in the negated state, and sets the change direction of the ramp voltage to the second direction during a period in which the ramp command signal is in the asserted state.

5. The power supply control device according to claim 1.

7. The power supply control device is provided with an output stage circuit for each of the plurality of channels.

5. The power supply control device according to claim 1.

8. The output stage circuits for the plurality of channels provided outside the power supply control device are connected to the power supply control device.

5. The power supply control device according to claim 1.

9. A power supply control device according to any one of claims 1 to 4, a rectifying and smoothing circuit configured to rectify and smooth the plurality of switch voltages to generate the output voltage; Equipped with The output stage circuits for the plurality of channels are provided in the power supply control device. , switching power supply.

10. A power supply control device according to any one of claims 1 to 4, an output stage circuit for the plurality of channels connected to the power supply control device; a rectifying and smoothing circuit configured to rectify and smooth the plurality of switch voltages to generate the output voltage. , switching power supply.

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