Laminate structure, semiconductor device and method for manufacturing semiconductor device

Abstract

To provide a laminate structure capable of suppressing warpage, a semiconductor device, and a method for manufacturing the semiconductor device.SOLUTION: A laminate structure according to the present embodiment comprises: a first wafer having a first semiconductor element; a second wafer having a second semiconductor element and bonded to one surface side of the first wafer; and a third wafer having a third semiconductor element and bonded to the opposite side of the first wafer, the second semiconductor element and the third semiconductor element are of the same type, and the second wafer and third wafer are arranged facing each other with the first wafer sandwiched therebetween.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a stacked structure, a semiconductor device, and a method for manufacturing a semiconductor device. [Background technology]

[0002] When wafers are stacked in multiple stages to increase the number of layers, warpage of the stack may increase. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2019 / 0043836 Summary of the Invention [Problem to be solved by the invention]

[0004] A stacked structure, a semiconductor device, and a method for manufacturing a semiconductor device that can suppress warpage are provided. [Means for solving the problem]

[0005] The laminated structure according to this embodiment comprises a first wafer having a first semiconductor element, a second wafer having a second semiconductor element and bonded to one side of the first wafer, and a third wafer having a third semiconductor element and bonded to the other side of the first wafer, wherein the second semiconductor element and the third semiconductor element are of the same type, and the second wafer and the third wafer are arranged facing each other with the first wafer sandwiched between them.

[0006] The semiconductor device according to this embodiment comprises a first chip having a first semiconductor element, a second chip having a second semiconductor element and attached to one side of the first chip, and a third chip having a third semiconductor element and attached to the other side of the first chip, wherein the second semiconductor element and the third semiconductor element are the same type of element, and the second chip and the third chip are arranged facing each other with the first chip sandwiched between them.

[0007] The method for manufacturing a semiconductor device according to this embodiment involves bonding a first wafer having a first semiconductor element formed on its first surface and warped so that the first surface is convex to a second wafer having a second semiconductor element formed on its second surface and warped so that the second surface is convex, with the first surface facing the second surface, and bonding a third wafer having a third semiconductor element formed on its third surface and warped so that the third surface faces the first back surface, which is the surface opposite the first surface of the first wafer. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a diagram showing an example of the configuration of a laminated structure according to a first embodiment. [Figure 2A] 1 is a cross-sectional view showing an example of the configuration of a laminated structure according to a first embodiment. [Figure 2B] 1 is a cross-sectional view showing an example of the configuration of a laminated structure according to a first embodiment. [Figure 3A] 3A to 3C are diagrams illustrating an example of a method for manufacturing the laminated structure according to the first embodiment. [Figure 3B] 3B is a diagram showing an example of a method for manufacturing a laminated structure, following FIG. 3A. FIG. [Figure 3C] 3B, which is a diagram showing an example of a method for manufacturing a laminated structure. [Figure 3D] 3D is a diagram showing an example of a method for manufacturing a laminated structure, following FIG. 3C. [Figure 3E] 3D, which is a diagram showing an example of a method for manufacturing a laminated structure. [Figure 4] FIG. 10 is a diagram showing an example of the configuration of a laminated structure according to a comparative example. [Figure 5] FIG. 10 is a cross-sectional view showing an example of the configuration of a laminated structure according to a comparative example. [Figure 6A] 10A to 10C are diagrams illustrating an example of a method for manufacturing a laminated structure according to a comparative example. [Figure 6B] 3B is a diagram showing an example of a method for manufacturing a laminated structure, following FIG. 3A. FIG. [Figure 6C] 3B, which is a diagram showing an example of a method for manufacturing a laminated structure. [Figure 7] FIG. 10 is a diagram showing an example of the configuration of a laminated structure according to a second embodiment. [Figure 8] FIG. 10 is a diagram showing an example of the configuration of a laminated structure according to a third embodiment. [Figure 9] FIG. 10 is a diagram showing an example of the configuration of a laminated structure according to a fourth embodiment. [Figure 10] FIG. 10 is a diagram showing an example of the configuration of a laminated structure according to a fifth embodiment. [Figure 11] FIG. 13 is a diagram showing an example of the configuration of a laminated structure according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiment. The drawings are schematic or conceptual, and the proportions of the various parts are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0010] (First embodiment) Fig. 1 is a diagram showing an example of the configuration of a stacked structure 1 according to the first embodiment. Fig. 1 also shows one semiconductor device 2 after the stacked structure 1 is separated into a plurality of semiconductor devices 2.

[0011] The laminated structure 1 includes three wafers W1, W2, and W3 that are laminated together.

[0012] The wafer W1 is, for example, a logic wafer. The wafer W1 has a surface F11 and a surface F12 opposite to the surface F12. The wafer W1 has a semiconductor element E1 and a semiconductor substrate S1 on which the semiconductor element E1 is provided. In the example shown in FIG. 1, the semiconductor element E1 is provided on the surface F11 side. The semiconductor substrate S1 is provided on the surface F12 side. The semiconductor element E1 is, for example, a readout circuit. In the example shown in FIG. 1, the semiconductor element E1 of the wafer W1 is, for example, a controller that controls a memory cell array, which will be described later. The controller is, for example, a CMOS (Complementary Metal Oxide Semiconductor) circuit.

[0013] The wafer W2 is, for example, a memory array wafer. The wafer W2 is provided on one surface (for example, surface F11) of the wafer W1. The wafer W2 has a semiconductor element E2 and a semiconductor substrate S2 on which the semiconductor element E2 is provided. Note that, as in the example shown in FIG. 1, the semiconductor substrate S2 does not necessarily have to be provided. The semiconductor element E2 is, for example, a memory element. In the example shown in FIG. 1, the semiconductor element E2 of the wafer W2 is, for example, a memory cell array. The memory cell array may be a three-dimensional memory cell array in which a plurality of memory cells are arranged three-dimensionally. The memory cell array is, for example, a three-dimensional NAND memory, but may also be a DRAM (Dynamic Random Access Memory) array or the like.

[0014] The wafer W3 is, for example, a memory array wafer. The wafer W3 is provided on the other surface (for example, surface F12) of the wafer W1. The wafer W3 has a semiconductor element E3 and a semiconductor substrate S3 on which the semiconductor element E3 is provided. The semiconductor element E3 is, for example, a memory element. In the example shown in FIG. 1, the semiconductor element E3 of the wafer W3 is a memory cell array. The memory cell array may be a three-dimensional memory cell array in which a plurality of memory cells are arranged three-dimensionally. The memory cell array is, for example, a three-dimensional NAND memory, but may also be a DRAM (Dynamic Random Access Memory) array or the like.

[0015] The wafers W2 and W3 are the same type of wafer, that is, the semiconductor elements E2 and E3 are the same type of elements.

[0016] Depending on the semiconductor element, such as when the semiconductor element has a transistor, a certain thickness may be required for the semiconductor substrate to operate. The semiconductor substrate S1 has a thickness according to the operating limits of the semiconductor element E1, which is a CMOS circuit. The thickness of the semiconductor substrate S1 is, for example, 5 μm or more. The thickness of the first semiconductor substrate S1 may be smaller than the thickness of one or both of the second semiconductor substrate S2 and the third semiconductor substrate S3.

[0017] The semiconductor device 2 includes three stacked chips CH1, CH2, and CH3.

[0018] The chip CH1 is, for example, a logic chip. The chip CH1 is one chip obtained after the wafer W1 included in the stacked structure 1 is diced into a plurality of chips. The chip CH1 has a semiconductor element E1 and a semiconductor substrate S1.

[0019] The chip CH2 is, for example, a memory chip. The chip CH2 is one chip obtained after the wafer W2 included in the stacked structure 1 is diced into a plurality of chips. The chip CH2 has a semiconductor element E2 and a semiconductor substrate S2.

[0020] The chip CH3 is, for example, a memory chip. The chip CH3 is one chip obtained after the wafer W3 included in the stacked structure 1 is diced into multiple chips. The chip CH3 has a semiconductor element E3 and a semiconductor substrate S3.

[0021] Chips CH2 and CH3 are the same type of chips.

[0022] Here, wafers W1, W2, and W3 may have warpage. The warpage of a wafer occurs, for example, due to the difference in thermal expansion coefficient between the material of the semiconductor substrate (e.g., silicon (Si)) and the material of the laminated film (semiconductor element) formed at a film formation temperature of several hundred degrees Celsius.

[0023] Therefore, wafers W2 and W3 are arranged so as to sandwich wafer W1 therebetween. More specifically, wafers W2 and W3 are arranged so as to face each other with wafer W1 sandwiched therebetween (face to face). That is, wafers W2 and W3 are arranged upside down relative to each other. Note that in the example shown in FIG. 1, the word "Array" in semiconductor elements E2 and E3 is written upside down.

[0024] By arranging the wafers W2 and W3 of the same type so that the wafer W1 is sandwiched between them, the warpage of the wafers W2 and W3 can be canceled (offset), and as a result, the warpage of the stacked structure 1 and the semiconductor device 2 can be suppressed.

[0025] 2A and 2B are cross-sectional views showing an example of the configuration of the multilayer structure 1 according to the first embodiment. 2A and 2B are cross-sectional views of the multilayer structure 1 shown in FIG.

[0026] The wafers W1 and W2 are bonded together at the bonding surface S. Similarly, the wafers W1 and W3 are bonded together at the bonding surface S.

[0027] The semiconductor element E1 includes, for example, a transistor provided on a semiconductor substrate S1.

[0028] The semiconductor element E2 includes, for example, a memory cell array. The bit lines BL of the semiconductor element E2 are provided on the lower surface side of the wafer W2, that is, on the wafer W1 side of the wafer W2.

[0029] The semiconductor element E3 includes, for example, a memory cell array. The bit lines BL of the semiconductor element E3 are provided on the upper surface side of the wafer W3, i.e., on the wafer W1 side of the wafer W3. A through electrode pad penetrating the semiconductor substrate S1 is directly bonded (attached) to an electrode pad formed on the surface of the semiconductor element E3 (the upper surface of the wafer W3). An electrode pad formed on the surface of the semiconductor element E1 (the upper surface of the wafer W1) is directly bonded (attached) to an electrode pad formed on the surface of the semiconductor element E2 (the lower surface of the wafer W2). The semiconductor elements E2 and E3 may be electrically connected directly without going through a transistor of the semiconductor element E1.

[0030] Therefore, as shown in Figures 2A and 2B, wafers W2 and W3 are arranged upside down. Pads for connecting to the outside are formed on the wafer W3 side, as an example. At this time, at least a part or all of semiconductor substrate S3 may be removed. Alternatively, pads for connecting to the outside may be formed on the wafer W2 side. At this time, at least a part or all of semiconductor substrate S2 may be removed. The semiconductor substrate is removed by polishing, grinding, etching, or the like.

[0031] Although FIG. 2A shows the semiconductor substrate S2 of the wafer W2, the semiconductor substrate S2 may not be provided, as in FIG.

[0032] The stepped portion of the memory cell array included in semiconductor element E2 is formed so that the steps increase from the upper left to the lower right in Fig. 2A. The stepped portion of the memory cell array included in semiconductor element E3 is formed so that the steps increase from the lower right to the upper left in Fig. 2A. In other words, the stepped portion of the memory cell array included in semiconductor element E2 and the stepped portion of the memory cell array included in semiconductor element E3 are in a point-symmetric relationship.

[0033] The stepped portion of the memory cell array included in semiconductor element E2 is formed so that the steps increase from the upper left to the lower right in Fig. 2B. The stepped portion of the memory cell array included in semiconductor element E3 is formed so that the steps increase from the lower left to the upper right in Fig. 2B. In other words, the stepped portion of the memory cell array included in semiconductor element E2 and the stepped portion of the memory cell array included in semiconductor element E3 are in an axisymmetric relationship.

[0034] Next, a method for manufacturing the laminated structure 1 will be described.

[0035] 3A to 3E are diagrams showing an example of a method for manufacturing the laminated structure 1 according to the first embodiment.

[0036] First, as shown in FIG. 3A, wafers W1 and W2 are prepared. Each of wafers W1 and W2 has a semiconductor substrate S1 or S2. Because semiconductor elements E1 and E2 are thin films, it is difficult to transport each of semiconductor elements E1 and E2 individually without the semiconductor substrates S1 and S2. The semiconductor substrates S1 and S2 that support semiconductor elements E1 and E2 make wafers W1 and W2 easier to handle.

[0037] Each of wafers W1 and W2 shown in FIG. 3A has a convex warpage. More specifically, wafer W1, which is a logic wafer, has a convex warpage of convex a. Wafer W2, which is a memory array wafer, has a convex warpage of convex b. That is, the amounts of warpage of wafer W1 and wafer W2 are different. The magnitude of warpage is convex a<convex b.

[0038] 3B, the wafer W1 and the wafer W2 are bonded together such that the surface of the wafer W1 on the semiconductor element E1 side and the surface of the wafer W2 on the semiconductor element E2 side are bonded together.

[0039] Next, as shown in Figure 3C, the stacked structure of wafers W1 and W2 is turned upside down, and at least a portion of semiconductor substrate S1 is removed to thin it. Wafer W3 shown in Figure 3C is prepared at the same time as wafer W2, for example, in the process shown in Figure 3A. The entire semiconductor substrate S1 may be removed by polishing, grinding, etching, or the like.

[0040] The stacked structure of wafers W1 and W2 shown in Figure 3C has a convex warp. More specifically, the stacked structure of wafers W1 and W2 has a warp caused by a concave a, which is an upside-down inversion of convex a, and a convex b. As described above, convex a < convex b, so the stacked structure of wafers W1 and W2 has a convex warp.

[0041] 3D, the stacked structure of wafers W1 and W2 is bonded to wafer W3, with the surface of wafer W1 facing the semiconductor substrate S1 being bonded to the surface of wafer W3 facing the semiconductor element E3.

[0042] Next, as shown in Fig. 3E, the wafers W1, W2, and W3 are turned upside down, and the semiconductor substrate S2 is thinned. In the example shown in Fig. 3E, the semiconductor substrate S2 is removed. This completes the stacked structure 1 shown in Fig. 1.

[0043] Note that even after removing semiconductor substrate S2, semiconductor substrates S1 and S3 remain, so the stacked structure of wafers W1, W2, and W3 remains easy to handle. Therefore, the thickness of second semiconductor substrate S2 may be different from the thickness of third semiconductor substrate S3. In the example shown in FIG. 3E, the thickness of second semiconductor substrate S2 is 0 μm.

[0044] The stacked structure of wafers W1, W2, and W3 shown in Figure 3E has a convex warp. More specifically, the stacked structure of wafers W1, W2, and W3 has a warp caused by a convex a, a concave b which is the inverse of the convex b, and a convex b. Because the concave b and the convex b cancel each other out, the stacked structure of wafers W1, W2, and W3 has a warp caused by a convex a.

[0045] Thereafter, the stacked structure 1 is diced into individual pieces to complete the semiconductor device 2. The semiconductor substrate S3 may be removed before the semiconductor device 2 is completed. Pads for connecting to the outside may be formed after removing the semiconductor substrate S3, or may be formed on the semiconductor substrate S3 without removing the semiconductor substrate S3. Pads for connecting to the outside may be formed on the semiconductor substrate S2 side.

[0046] As described above, according to the first embodiment, the wafers W2 and W3 are arranged so as to sandwich the wafer W1 therebetween. This makes it possible to cancel warpage of the wafers W2 and W3. As a result, it is possible to suppress warpage of the stacked structure 1 and the semiconductor device 2.

[0047] Note that warpage of the semiconductor substrate itself may affect the warpage of the stacked structure 1 and the semiconductor device 2. If the warpage of the wafers W1 and W3 is canceled out and negligible, the warpage of the stacked structure 1 is almost entirely due to the warpage of the wafer W1. Wafer warpage is determined by stress and thickness. In the example shown in FIG. 3E, the semiconductor element E1 has an upward convex warpage, the semiconductor substrate S1 has a downward convex warpage, and the wafer W1 as a whole has an upward convex warpage of a convex a. The thicker the semiconductor substrate S1, the greater the downward convex warpage of the semiconductor substrate S1. Therefore, the thickness of the semiconductor substrate S1 may be adjusted so that the warpage of the semiconductor element E1 and the semiconductor substrate S1 are balanced. This can further suppress the warpage of the stacked structure 1 and the semiconductor device 2.

[0048] Furthermore, for example, if the semiconductor elements E2 and E3 each have a vertically symmetrical structure internally, the warpage of the wafers W2 and W3 will not change even if the wafers W2 and W3 are inverted upside down. In this case, the wafers W2 and W3 may not be arranged so as to face each other. In other words, the wafers W2 and W3 may be arranged in the same orientation without being inverted upside down.

[0049] (Comparative Example) 4 is a diagram showing an example of the configuration of a stacked structure 1a according to a comparative example. In the comparative example, the arrangement of stacked wafers is different from that of the first embodiment. Note that some semiconductor substrates are omitted in FIG. 4.

[0050] The stacked structure 1a includes three stacked wafers W1a, W2a, and W3a. The wafer W1a is, for example, a logic wafer. The wafers W2a and W3a are, for example, memory array wafers.

[0051] 5 is a cross-sectional view of the laminated structure 1 shown in FIG. 4, showing an example of the configuration of the laminated structure 1a according to the comparative example.

[0052] The wafers W1a and W3a, which are arranged so as to sandwich the wafer W2a therebetween, are different types of wafers and are arranged in the same orientation.

[0053] 6A to 6C are diagrams showing an example of a method for manufacturing a laminated structure 1a according to a comparative example. The steps shown in FIGS. 6A to 6C are performed after the same steps as those shown in FIGS. 3A and 3B. Note that the wafers W1 and W2 shown in FIGS. 3A and 3B are the same as the wafers W1a and W2a.

[0054] After wafer W1a and wafer W2a are bonded together (see FIG. 3B), semiconductor substrate S2 is thinned as shown in FIG. 6A. In the example shown in FIG. 6A, semiconductor substrate S2 is removed. Wafer W3a shown in FIG. 6A is prepared at the same time as wafer W2a, for example, in the process shown in FIG. 3A.

[0055] The stacked structure of wafers W1a and W2a shown in Figure 6A has a concave warpage. More specifically, the stacked structure of wafers W1a and W2a has a warpage caused by a convex portion a and a concave portion b, which is the inverse of the convex portion b. As described above, since convex portion a is smaller than convex portion b, the stacked structure of wafers W1a and W2a has a concave warpage.

[0056] Next, as shown in FIG. 6B, the stacked structure of the wafers W1a and W2a and the wafer W3a are bonded together.

[0057] Next, the semiconductor substrate S3 is thinned as shown in Figure 6C. In the example shown in Figure 6C, the semiconductor substrate S3 is removed.

[0058] The stacked structure of wafers W1a, W2a, and W3a shown in Figure 6C has a concave warpage. More specifically, the stacked structure of wafers W1a, W2a, and W3a has a warpage caused by a convex portion a and two concave portions b that are the inverse of the two convex portions b. As described above, since convex portion a is smaller than convex portion b, the stacked structure of wafers W1a, W2a, and W3a has a concave warpage.

[0059] 6C, the warpage of the two recesses b caused by the wafers W2a and W3a, which are memory array wafers, overlaps with each other, further strengthening the warpage of the recesses b, resulting in a larger warpage of the stacked structure 1a.

[0060] In contrast, in the first embodiment, wafers W2 and W3 of the same type are arranged to sandwich wafer W1. This makes it possible to cancel warpage of wafers W2 and W3. As a result, warpage of stacked structure 1 and semiconductor device 2 can be suppressed.

[0061] (Second embodiment) 7 is a diagram showing an example of the configuration of a stacked structure 1 according to the second embodiment. The second embodiment differs from the first embodiment in that the wafers W2 and W3 are arranged upside down. Note that the semiconductor substrate is omitted from FIG. 7.

[0062] Both wafers W2 and W3 are upside down compared to FIG. 1 according to the first embodiment. In this case, wafers W2 and W3 are also arranged facing each other with wafer W1 sandwiched therebetween. Therefore, warpage of wafers W2 and W3 can be canceled.

[0063] A detailed description of the semiconductor device 2 including chips CH1, CH2, and CH3 obtained by dividing the wafers W1, W2, and W3 will be omitted.

[0064] The wafers W2 and W3 may be arranged upside down as in the second embodiment. The stacked structure 1 according to the second embodiment can obtain the same effects as the first embodiment.

[0065] (Third embodiment) 8 is a diagram showing an example of the configuration of a stacked structure 1 according to the third embodiment. The third embodiment differs from the first embodiment in that the wafer W1 is arranged upside down. Note that semiconductor substrates S1, S2, and S3 are omitted from FIG. 8.

[0066] The wafer W1 is upside down compared to FIG. 1 according to the first embodiment. In this case, the wafers W2 and W3 are also arranged facing each other with the wafer W1 sandwiched therebetween. Therefore, warpage of the wafers W2 and W3 can be canceled.

[0067] A detailed description of the semiconductor device 2 including chips CH1, CH2, and CH3 obtained by dividing the wafers W1, W2, and W3 will be omitted.

[0068] The wafer W1 may be arranged upside down as in the third embodiment. The stacked structure 1 according to the third embodiment can obtain the same effects as the first embodiment.

[0069] (Fourth embodiment) Fig. 9 is a diagram showing an example of the configuration of a stacked structure 1 according to the fourth embodiment. The fourth embodiment differs from the first embodiment in that two logic wafers are arranged to sandwich a memory array wafer. Note that the semiconductor substrate is omitted from Fig. 9.

[0070] Wafer W1 is, for example, a memory array wafer, and wafers W2 and W3 are, for example, logic wafers.

[0071] In this case as well, the wafers W2 and W3 are arranged to face each other with the wafer W1 sandwiched therebetween, thereby canceling out any warpage of the wafers W2 and W3.

[0072] A detailed description of the semiconductor device 2 including chips CH1, CH2, and CH3 obtained by dividing the wafers W1, W2, and W3 will be omitted.

[0073] As in the fourth embodiment, two logic wafers may be arranged to sandwich a memory array wafer. The stacked structure 1 according to the fourth embodiment can achieve the same effects as the first embodiment. Furthermore, the stacked structure 1 according to the second embodiment may be combined with at least one of the second and third embodiments. That is, both wafers W2 and W3 may be arranged upside down, and wafer W1 may also be arranged upside down.

[0074] (Fifth embodiment) Fig. 10 is a diagram showing an example of the configuration of a stacked structure 1 according to a fifth embodiment. The fifth embodiment differs from the first embodiment in that four wafers are stacked. Note that the semiconductor substrate is omitted from Fig. 10.

[0075] The laminated structure 1 further includes a wafer W4.

[0076] Wafer W4 is a logic wafer. Wafer W4 is disposed between one surface (e.g., surface F11) of wafer W1 and wafer W2. Wafer W4 has semiconductor element E4 and a semiconductor substrate S4 on which semiconductor element E4 is disposed. Note that semiconductor substrate S4 is omitted in FIG. 10.

[0077] The wafer W4 is bonded to the wafer W1 at its lower bonding surface, and similarly, the wafer W4 is bonded to the wafer W2 at its upper bonding surface.

[0078] The wafers W1 and W4 are the same type of wafer, that is, the semiconductor elements E1 and E4 are the same type of elements.

[0079] Wafer W4 is disposed so as to face wafer W1. That is, wafers W1 and W4 are disposed upside down. This makes it possible to cancel warpage of wafers W1 and W4. As a result, warpage of stacked structure 1 and semiconductor device 2 can be suppressed.

[0080] Both wafers W1 and W4 may be placed upside down.

[0081] The wafers W2 and W3 are arranged so as to sandwich the two wafers W1 and W4 therebetween. The wafers W2 and W3 are arranged so as to face each other with the two wafers W1 and W4 sandwiched therebetween. This makes it possible to cancel warpage of the wafers W2 and W3. As a result, warpage of the stacked structure 1 and the semiconductor device 2 can be suppressed.

[0082] A detailed description of the semiconductor device 2 including chips CH1, CH2, CH3, and CH4 obtained by dividing the wafers W1, W2, W3, and W4 will be omitted.

[0083] Five or more wafers may be stacked. In this case, wafers W2 and W3 are also arranged so as to sandwich three or more wafers therebetween.

[0084] As in the fifth embodiment, four wafers may be stacked. The stacked structure 1 according to the fifth embodiment can obtain the same effects as the first embodiment. The stacked structure 1 according to the fifth embodiment may also be combined with the second embodiment. That is, both wafers W2 and W3 may be arranged upside down.

[0085] (Sixth embodiment) FIG. 11 is a diagram showing an example of the configuration of a stacked structure 1 according to the sixth embodiment. The sixth embodiment differs from the fifth embodiment in that two logic wafers are arranged to sandwich two memory array wafers. That is, the sixth embodiment is also a combination of the fourth and fifth embodiments. Note that the semiconductor substrate is omitted from FIG. 11.

[0086] Wafers W1 and W4 are, for example, memory array wafers, and wafers W2 and W3 are, for example, logic wafers.

[0087] As in the fifth embodiment, the wafer W4 is disposed so as to face the wafer W1, thereby canceling out the warpage of the wafers W1 and W4.

[0088] As in the fifth embodiment, the wafers W2 and W3 are arranged to face each other with the two wafers W1 and W4 sandwiched therebetween, thereby canceling out the warpage of the wafers W2 and W3.

[0089] A detailed description of the semiconductor device 2 including chips CH1, CH2, CH3, and CH4 obtained by dividing the wafers W1, W2, W3, and W4 will be omitted.

[0090] Two logic wafers may be arranged to sandwich two memory array wafers, as in the sixth embodiment. The stacked structure 1 according to the sixth embodiment can achieve the same effects as the fifth embodiment.

[0091] In this embodiment, wafer W1 is a logic wafer, and wafers W2 and W3 are memory array wafers, but this is not limiting. For example, the combination of wafers W1, W2, and W3 may be any combination that can mitigate wafer warpage, and may be any element formed on the wafer, such as logic, passive elements such as capacitors, pixel sensors, or power semiconductors. In an embodiment using three or more wafers, any combination may be used as long as it can mitigate wafer warpage.

[0092] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0093] 1 stacked structure, 2 semiconductor device, CH1 to CH4 chips, E1 to E4 semiconductor elements, W1 to W4 wafers

Claims

1. a first wafer having a first semiconductor device; a second wafer having a second semiconductor element and bonded to one surface of the first wafer; a third wafer having a third semiconductor element and bonded to the other surface side of the first wafer; Equipped with the second semiconductor element and the third semiconductor element are elements of the same type, A stacked structure in which the second wafer and the third wafer are arranged facing each other with the first wafer sandwiched therebetween.

2. a fourth wafer having a fourth semiconductor element and bonded between the first wafer and the second wafer; The stacked structure according to claim 1 , wherein the second wafer and the third wafer are arranged to sandwich the first wafer and the fourth wafer therebetween.

3. the second semiconductor element and the third semiconductor element are elements of the same type, The stacked structure according to claim 2 , wherein the first semiconductor element and the fourth semiconductor element are elements of the same type.

4. the second semiconductor device and the third semiconductor device each have a memory cell array; The stacked structure according to claim 1 , wherein the first semiconductor element includes a CMOS control circuit that controls the memory cell array.

5. The stacked structure of claim 1, wherein the second wafer further has a second semiconductor substrate on which the second semiconductor element is provided, or the third wafer further has a third semiconductor substrate on which the third semiconductor element is provided.

6. The stacked structure of claim 5 , wherein the thickness of the second semiconductor substrate is different from the thickness of the third semiconductor substrate.

7. The stacked structure according to claim 6 , wherein a thickness of a first semiconductor substrate on which the first semiconductor element is provided is smaller than a thickness of one or both of the second semiconductor substrate and the third semiconductor substrate.

8. a first chip having a first semiconductor element; a second chip having a second semiconductor element and attached to one surface side of the first chip; a third chip having a third semiconductor element and attached to the other surface side of the first chip; Equipped with the second semiconductor element and the third semiconductor element are elements of the same type, The second chip and the third chip are disposed facing each other with the first chip sandwiched therebetween.

9. a first wafer having a first semiconductor element formed on a first surface and warped so that the first surface is convex, and a second wafer having a second semiconductor element formed on a second surface and warped so that the second surface is convex, are bonded together so that the first surface faces the second surface; a third wafer having a third semiconductor element formed on a third surface and warped so that the third surface is convex is bonded to a first back surface of the first wafer, the first back surface being the surface opposite to the first surface of the first wafer, so that the third surface faces the first back surface; A method for manufacturing a semiconductor device, comprising:

10. 10. The method for manufacturing a semiconductor device according to claim 9, further comprising removing at least a portion of said first back surface after said first surface and said second surface are bonded together so as to face each other.

11. 10. The method for manufacturing a semiconductor device according to claim 9, further comprising forming external connection pads on a second back surface side of the second wafer, which is the surface opposite to the second front surface, or on a third back surface side of the third wafer, which is the surface opposite to the third front surface.

12. 12. The method for manufacturing a semiconductor device according to claim 11, further comprising removing at least a portion of the second wafer from the second rear surface side or removing at least a portion of the third wafer from the third rear surface side before forming external connection pads.

13. 10. The method for manufacturing a semiconductor device according to claim 9, wherein the first semiconductor element is a CMOS control circuit, and the second semiconductor element and the third semiconductor element are a memory cell array controlled by the CMOS control circuit.

14. 10. The method for manufacturing a semiconductor device according to claim 9, wherein the magnitude of warpage of the first wafer is smaller than the magnitude of warpage of the second wafer.

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