Semiconductor devices for RF integrated circuits

Abstract

To reduce the cost of certain RF circuits and dissipate heat effectively. A semiconductor device of an RF circuit may include one or more active devices, such as transistors, diodes, and / or varactors, formed from a first semiconductor material structure integrated (e.g., bonded) with a base substrate formed from a second semiconductor material structure that includes other circuit components. The first semiconductor material structure may be, for example, a III-V or III-N semiconductor material structure, and the second semiconductor material structure may be, for example, silicon.

Description

[Technical field]

[0001] The present disclosure relates to semiconductor devices, and in particular to devices that can be configured to operate as RF integrated circuits. [Background technology]

[0002] Silicon integrated circuit (IC) processes, which monolithically integrate all circuit components onto a silicon substrate, are commonly used to fabricate a variety of circuits. In certain radio frequency (RF) electronics applications, III-V semiconductors may perform better than silicon for some active devices of the circuit based on their superior material properties. However, for III-V RF integrated circuits, many passive components (e.g., capacitors, inductors, interconnects, etc.) take up significant space on the III-V substrate and do not provide significant performance advantages compared to similar devices fabricated on silicon, resulting in significantly increased cost compared to silicon ICs. Summary of the Invention

[0003] In a first aspect of the present disclosure, a semiconductor device may include a base substrate and a transistor connected to the base substrate. The base substrate may include a substrate layer including a semiconductor or insulator material, the substrate layer having a front surface and a back surface opposite the front surface. The base substrate may further include a first plurality of vias each extending through the entire thickness of the substrate layer, a first metal material in each of the first plurality of vias, a back surface metal material covering the back surface of the substrate layer and contacting the first metal material in each of the first plurality of vias, and an interconnect metal on the front surface of the substrate layer. The transistor may include a III-N material structure. The III-N material structure may include a III-N barrier layer, a III-N channel layer on an N-face of the III-N barrier layer, the III-N barrier layer having a larger band gap than the III-N channel layer, and a two-dimensional electron gas (2DEG) channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the III-N barrier layer. The transistor may further include a plurality of contacts, the plurality of contacts including a source contact, a drain contact, and a gate contact. The source contact, the gate contact, and the drain contact may be on an opposite side of the III-N channel layer from the III-N barrier layer, and the source contact and the drain contact may be electrically connected to the 2DEG channel. The transistor may be on the front surface of the base substrate with the substrate layer of the base substrate between the backside metal and the transistor, and the first metal material in a first via of the first plurality of vias may be electrically connected to a first contact of the plurality of contacts by one or more bonding materials.

[0004] In a second aspect, the semiconductor device may include a base substrate and a transistor connected to the base substrate. The base substrate may include a substrate layer including a semiconductor or insulator material, the substrate layer having a front surface and a back surface opposite the front surface. The base substrate may further include a first plurality of vias each extending through the entire thickness of the substrate layer, a first metal material in each of the first plurality of vias, a back metal material covering the back surface of the substrate layer and contacting the first metal material in each of the first plurality of vias, and an interconnect metal on the front surface of the substrate layer. The transistor may include a III-N material structure. The III-N material structure may include a III-N barrier layer, a III-N channel layer on an N-face of the III-N barrier layer, the III-N barrier layer having a larger band gap than the III-N channel layer, and a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the III-N barrier layer. The transistor may further include a plurality of contacts. The plurality of contacts may include a source contact, a drain contact, and a gate contact. The source contact, the gate contact, and the drain contact may be on an opposite side of the III-N channel layer from the III-N barrier layer, and the source contact and the drain contact may be electrically connected to the 2DEG channel. The transistor may further include a thermal contact that is thermally coupled to the III-N material structure and electrically isolated from the 2DEG channel. The transistor may be on the front surface of the base substrate with the substrate layer of the base substrate between the backside metal and the transistor, and the first metal material in a first via of the first plurality of vias may be electrically connected to the thermal contact of the transistor.

[0005] In a third aspect, the semiconductor device may include a base substrate and a transistor connected to the base substrate. The base substrate may include a substrate layer including a semiconductor or insulator material, the substrate layer having a front surface and a back surface opposite the front surface. The base substrate may further include a first plurality of vias each extending through the entire thickness of the substrate layer, a first metal material in each of the first plurality of vias, a back surface metal material covering the back surface of the substrate layer and contacting the first metal material in each of the first plurality of vias, and an interconnect metal on the front surface of the substrate layer. The transistor may include a III-N material structure. The III-N material structure may include a III-N barrier layer, a III-N channel layer on an N-face of the III-N barrier layer, the III-N barrier layer having a larger band gap than the III-N channel layer, and a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the III-N barrier layer. The transistor may further include a plurality of contacts. The plurality of contacts may include a source contact, a drain contact, and a gate contact. The source contact, the gate contact, and the drain contact may be on an opposite side of the III-N channel layer from the III-N barrier layer, and the source contact and the drain contact may be electrically connected to the 2DEG channel. The transistor may be on the front surface of the base substrate with the substrate layer of the base substrate between the backside metal and the transistor. A first end of an impedance element may be electrically connected to a first contact of the plurality of contacts, and a second end of the impedance element may be electrically connected to the first metal material.

[0006] In a fourth aspect, a semiconductor device may include a base substrate and a transistor connected to the base substrate. The base substrate may include a substrate layer including a semiconductor or insulator material, the substrate layer having a front surface and a back surface opposite the front surface. The base substrate may include a plurality of vias each extending through the entire thickness of the substrate layer and a first metal material in each of the vias. The base substrate may further include a back metal layer patterned to form a first plurality of segments on the back side of the substrate layer, each segment of the first plurality of segments contacting the first metal material in at least one of the vias. The base substrate may further include a front metal layer patterned to form a second plurality of segments on the front surface of the substrate layer, each segment of the second plurality of segments contacting the first metal material in at least one of the vias. The transistor may include a III-N material structure. The III-N material structure may include a III-N barrier layer, a III-N channel layer on an N-face of the III-N barrier layer, the III-N barrier layer having a larger bandgap than the III-N channel layer, and a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the III-N barrier layer. The transistor may further include a plurality of contacts. The plurality of contacts may include a source contact, a drain contact, and a gate contact. The source contact, the gate contact, and the drain contact may be on an opposite side of the III-N channel layer from the III-N barrier layer, and the source contact and the drain contact may be electrically connected to the 2DEG channel. The transistor may be on the front surface of the base substrate with the substrate layer of the base substrate between the back metal and the transistor. A first segment of the second plurality of segments may be electrically connected to a first contact of the plurality of contacts.

[0007] In a fifth aspect, a semiconductor device may include a base substrate and a structure. The base substrate may include a substrate layer including a semiconductor or insulator material, the substrate layer having a front surface and a back surface opposite the front surface, and a front metal layer patterned to form a first plurality of segments on the front surface of the substrate layer. The structure may include a semiconductor or insulator layer and a first metal layer on the semiconductor layer. The first metal layer is patterned to form a second plurality of segments. Each segment of the first plurality of segments may be connected to at least one segment of the second plurality of segments by a bonding material. Furthermore, the front metal layer, the first metal layer, and the bonding material may each be part of an inductive element.

[0008] Any of the semiconductor devices described herein may include one or more of the following features, either alone or in combination with each other. At least one of the one or more bonding materials may include or be formed from gold, silver, copper, and indium-containing compounds, tin-containing compounds, AuSn, AuSi, CuSn, AuGe, AlGe, AlSi, or combinations thereof. The one or more bonding materials may be directly between the first contact and the first metallic material. The first contact may be the source contact. The substrate layer may include a material selected from the group consisting of silicon, gallium arsenide, silicon carbide, sapphire, germanium, indium phosphide, silicon oxide, and aluminum nitride. The base substrate may further include a second plurality of vias each extending partially through the substrate layer without extending through the entire thickness of the substrate layer. The base substrate may further include the first metallic material within each via of the second plurality of vias. A second via of the second plurality of vias may be directly beneath a second contact of the plurality of contacts. The thermal conductivity of the first metallic material may be greater than the thermal conductivity of the semiconductor or the insulator material of the substrate layer. The base substrate may further include an insulating material within each via of the first plurality of vias. And, optionally, the thermal conductivity of the insulating material may be less than the semiconductor or the insulator material of the substrate layer. The insulating material may be between the first metallic material and the substrate layer. The insulating material may electrically isolate the first metallic material from the substrate layer. The semiconductor device may further include a circuit element connected to the base substrate, the circuit element being selected from the group consisting of a capacitor, an inductor, a transformer, a resistor, a waveguide, an antenna, an electrical resonator, an acoustic component, a piezoelectric component, a diode, and a silicon-based transistor. The first metallic material may include or be formed from a material selected from the group consisting of copper, gold, aluminum, silver, and tungsten. The semiconductor device may be a circuit, and optionally a maximum operating frequency of the transistor may be at least twice an operating frequency of the circuit.The semiconductor device may be a circuit, and optionally, the total thickness of the one or more bonding materials may be less than 0.4% of a free space wavelength corresponding to a maximum operating frequency of the circuit. The total thickness of the one or more bonding materials may be less than 20 micrometers. The interconnect metal may be in direct contact with the first metal material in the first via of the first plurality of vias. The interconnect metal may be between the source contact and the first metal material in the first via of the first plurality of vias. The contacts of the transistor may be between the III-N channel layer and the base substrate. At least a portion of the transistor may be contained within a device cell, and the distance between any two points within the device cell may be less than 15 percent of a free space wavelength of radiation at a maximum operating frequency of the semiconductor device. The back metal layer, the front metal layer, and the first metal material in each of the vias may be part of an inductive element.

[0009] Any of the semiconductor devices described herein may include a second III-N barrier layer and a second III-N channel layer on an N-face of the second III-N barrier layer, the second III-N barrier layer having a larger bandgap than the second III-N channel layer. The second transistor may further include a second 2DEG channel in the second III-N channel layer adjacent to an interface between the second III-N channel layer and the second III-N barrier layer. The second transistor may further include a second plurality of contacts, including a second source contact, a second drain contact, and a second gate contact, the second source contact, the second gate contact, and the second drain contact each being on an opposite side of the second III-N channel layer from the second III-N barrier layer, and the second source contact and the second drain contact being electrically connected to the second 2DEG channel. The second transistor may be at least partially connected to the base substrate by the one or more bonding materials, the one or more bonding materials further being directly between a second contact of the second plurality of contacts and the first metal material in a second via of the first plurality of vias.

[0010] In a sixth aspect, a method for forming a semiconductor device may include (i) providing a base substrate; and (ii) connecting a transistor to the base substrate. The base substrate may include a substrate layer including a semiconductor or insulator material, the substrate layer having a front surface and a back surface opposite the front surface, a first plurality of vias each extending through a thickness of the substrate layer, a first metal material in each of the first plurality of vias, a back metal material covering the back surface of the substrate layer and contacting the first metal material in each of the first plurality of vias, and an interconnect metal on the front surface of the substrate layer. The transistor may include a III-N barrier layer and a III-N channel layer on an N-face of the III-N barrier layer, the III-N barrier layer having a larger band gap than the III-N channel layer. The transistor may further include a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the III-N barrier layer. The transistor may further include a plurality of contacts, including a source contact, a drain contact, and a gate contact, the source contact, the gate contact, and the drain contact being on an opposite side of the III-N channel layer from the III-N barrier layer, and the source contact and the drain contact being electrically connected to the 2DEG channel. After connecting the transistor to the base substrate, the transistor may be on the front surface of the base substrate with the substrate layer of the base substrate between the back metal and the transistor. Furthermore, a first end of an impedance element may be electrically connected to a first contact of the plurality of contacts, and a second end of the impedance element may be electrically connected to the first metal material.

[0011] In a seventh aspect, a method for forming a semiconductor device may include (i) providing a base substrate; and (ii) connecting a transistor to the base substrate. The base substrate may include a substrate layer including a semiconductor or insulator material, the substrate layer having a front surface and a back surface opposite the front surface, a first plurality of vias each extending through a thickness of the substrate layer, a first metal material in each of the first plurality of vias, a back metal material covering the back surface of the substrate layer and contacting the first metal material in each of the first plurality of vias, and an interconnect metal on the front surface of the substrate layer. The transistor may include a III-N barrier layer and a III-N channel layer on an N-face of the III-N barrier layer, the III-N barrier layer having a larger band gap than the III-N channel layer. The transistor may further include a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the III-N barrier layer. The transistor may further include a plurality of contacts, including a source contact, a drain contact, and a gate contact, the source contact, the gate contact, and the drain contact being on an opposite side of the III-N channel layer from the III-N barrier layer, and the source contact and the drain contact being electrically connected to the 2DEG channel. After connecting the transistor to the base substrate, the transistor may be on the front surface of the base substrate with the substrate layer of the base substrate between the backside metal and the transistor. Additionally, the first metal material in a first via of the first plurality of vias may be electrically connected to a first contact of the plurality of contacts by one or more bonding materials.

[0012] In any of the methods described herein, the source contact may include a plurality of source fingers, which may be electrically isolated from one another prior to connecting the transistor to the base substrate, and which may be electrically connected to one another after connecting the transistor to the base substrate. [Brief description of the drawings]

[0013] [Figure 1] 1 is a schematic diagram of an example semiconductor device.

[0014] [Figure 2A] FIG. 1 is a cross-sectional view of an example of an N-polarity III-N transistor. [Figure 2B] FIG. 1 is a cross-sectional view of an example of an N-polarity III-N transistor.

[0015] [Diagram 3] FIG. 1 is a plan view of an example of an N-polarity III-N transistor structure.

[0016] [Figure 4] 2 is a cross-sectional view of an embodiment of the semiconductor device of FIG. 1.

[0017] [Diagram 5] FIG. 13 is a plan view of an N-polarity III-N transistor structure with junction material deposited on the source and drain contacts.

[0018] [Figure 6] 2 is a cross-sectional view of another embodiment of the semiconductor device of FIG. 1. [Figure 7] 2 is a cross-sectional view of another embodiment of the semiconductor device of FIG. 1.

[0019] [Figure 8A] FIG. 1 is a plan view of an N-polar III-N transistor structure including thermal contacts. [Figure 8B] FIG. 1 is a plan view of an N-polar III-N transistor structure including thermal contacts.

[0020] [Figure 9] 8B is a cross-sectional view of one embodiment of a semiconductor device including the transistor structure of FIG. 8A connected to a base substrate.

[0021] [Figure 10]1 is a cross-sectional view of one embodiment of a semiconductor device including an impedance element between a contact of a transistor structure and an interconnect metal of a base substrate.

[0022] [Figure 11] 1 is a cross-sectional view of an embodiment of a semiconductor device including an inductive element integrated with a base substrate.

[0023] [Figure 12] FIG. 12 is a plan view of the inductive element of FIG.

[0024] [Figure 13] FIG. 13 is a cross-sectional view of a portion of another inductive element. [Figure 14] FIG. 13 is a plan view of a portion of another inductive element.

[0025] [Figure 15] FIG. 13 is a diagram illustrating a configuration example of another inductive element. [Figure 16] FIG. 13 is a diagram illustrating a configuration example of another inductive element. [Figure 17] FIG. 13 is a diagram illustrating a configuration example of another inductive element. [Figure 18] FIG. 13 is a diagram illustrating a configuration example of another inductive element.

[0026] [Figure 19] FIG. 1 is a diagram illustrating a configuration example of a toroidal transformer. [Figure 20] FIG. 1 is a diagram illustrating a configuration example of a toroidal transformer.

[0027] [Figure 21A] FIG. 1 illustrates a cross-sectional view of an embodiment of a semiconductor device including a diode connected to a base substrate. [Figure 21B] FIG. 1 illustrates a cross-sectional view of an embodiment of a semiconductor device including a diode connected to a base substrate. [Figure 21C] FIG. 1 illustrates a cross-sectional view of an embodiment of a semiconductor device including a diode connected to a base substrate.

[0028] [Figure 22] 1 is a cross-sectional view of one embodiment of a semiconductor device in which backside metal material of a substrate layer in a base substrate is patterned to form a portion of an inductor.

[0029] [Figure 23A] 2 is a cross-sectional view of another embodiment of a semiconductor device.

[0030] [Figure 23B] FIG. 23B is a circuit diagram of the semiconductor device of FIG. 23A.

[0031] [Figure 24] 1 is a cross-sectional view of yet another embodiment of a semiconductor device.

[0032] [Diagram 25] 1A-1D illustrate a method of forming a semiconductor device.

[0033] Like numbers in the drawings represent similar elements. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] Detailed Description Described herein is a semiconductor device in which one or more active devices, such as transistors, diodes, and / or varactors, formed from a first semiconductor material structure (e.g., a III-V semiconductor structure such as III-N material) are integrated (e.g., connected) with a base substrate formed from a second semiconductor material structure (e.g., silicon) that includes other circuit components. The base substrate provides electrical connections between the active devices and other circuit components as well as dissipates heat generated during operation of the active devices. This configuration of the semiconductor device can also minimize parasitic impedances and / or provide accurate impedances at each terminal of the active devices, thereby improving the performance of the semiconductor device. Because the cross-sectional area of ​​the III-V materials used to form this configuration is reduced compared to the cross-sectional area of ​​conventional III-V integrated circuits, devices formed with this configuration can achieve the performance advantages provided by III-V devices without many of the additional costs associated with some of the other circuit components of conventional III-V integrated circuits.

[0035] FIG. 1 is a schematic plan view (i.e., top view) of an example semiconductor device 100 formed on a base substrate 104. The semiconductor device 100 can be operated as a transmit / receive module (general RF circuit). The semiconductor device 100 includes several circuit subcomponents, such as a two-stage power amplifier having a first stage 112 and a second stage 114, a transmit / receive (T / R) switch 116, and a low noise amplifier (LNA) 118. The semiconductor device 100 further includes several passive devices that are integrated with or part of the base substrate 104, such as a transmission line 122, a capacitor (e.g., also called a metal-insulator-metal capacitor, MIM capacitor) 124, a thin film resistor 126, and an inductor 128. The semiconductor device 100 is further configured to receive a transmit input signal at node 142, transmit and receive signals to and from an antenna at node 144, and transmit a receive output signal at node 146.

[0036] The semiconductor device 100 further includes active device chiplets 132, 134, 136, and 138. Each active device chiplet includes one or more active devices, such as transistors, diodes, and / or varactors. In many applications, the devices have very high power densities during operation (e.g., 250 mW or more per millimeter of gate perimeter), and therefore may dissipate large amounts of heat. For the transmit / receive module shown in FIG. 1, the chiplets 132, 134, 136, and 138 may each include one or more nitrogen-polarity III-nitride transistors, as described in more detail below. The transistors of the chiplet 132 are part of the first stage 112 of the power amplifier, the transistors of the chiplet 134 are part of the second stage 114 of the power amplifier, the transistors of the chiplet 136 are part of the T / R switch 116, and the transistors of the chiplet 138 are part of the LNA 118. Each of the transistors in chiplets 132, 134, 136, and 138 is coupled to its respective circuit subcomponent in a manner that provides electrical connections between the transistors and other components of semiconductor device 100 and that effectively dissipates heat generated during operation of the transistors, as described further below.

[0037] Although chiplets 132, 134, 136, and 138 are each provided as separate components and individually coupled to their own circuit subcomponents on base substrate 104, in some cases, one or more of chiplets 132, 134, 136, and 138 may be very small and difficult to handle. Thus, two or more of chiplets 132, 134, 136, and 138 may be provided as a single component (e.g., on a common substrate) and all the transistors of the single-component chiplet may be coupled to their own circuit subcomponents.

[0038] As used herein, the term III-nitride or III-N materials, layers, devices, etc. refer to materials having the stoichiometric formula Sc vB w Al x In y Ga z N a (D) b Refers to a material or device composed of a compound semiconductor material that follows, where v + w + x + y + z is approximately 1, 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, a + b is approximately 1, 0.9 < a ≦ 1, 0 ≦ b < 0.1, and (D) is any Group V element other than nitrogen. In III-nitride devices or III-N devices such as high electron mobility transistors (HEMTs), the conductive channel may be partially or fully contained within the III-N material layer.

[0039] A cross-sectional view of an example of a nitrogen-polarity (N-polarity) III-N transistor 200 that can be used as a transistor in dielets 132, 134, 136, and 138 is shown in FIG. 2A. The transistor 200 configured as a HEMT includes a III-N material structure 218 grown on a suitable substrate 210 (such as silicon, silicon carbide, sapphire, AlN, or GaN). This III-N material structure includes a first III-N layer 212 on the substrate 210, a III-N barrier layer 214 on the first III-N layer 212, and a III-N channel layer 216 on the III-N barrier layer 214. The first III-N layer 212 can be formed of, for example, GaN or can include GaN and can function as a buffer layer to enable the growth of a high-quality III-N active device layer thereon. The III-N barrier layer 214 can be formed of, for example, Al x Ga 1-x N or can include Al x Ga 1-xThe III-N barrier layer 214 may include GaN. The bandgap of the III-N barrier layer 214 may be larger than the bandgap of the first III-N layer 212. The III-N channel layer 216 may be, for example, GaN. The III-N channel layer 216 has a different composition than the III-N barrier layer 214, the bandgap of the III-N barrier layer 214 is larger than the bandgap of the III-N channel layer 216, and the thicknesses of the layers 214 and 216 are selected such that a two-dimensional electron gas (2DEG) channel 219 (shown in dashed lines in FIG. 2 ) is induced in the III-N channel layer 216 adjacent the interface between the III-N barrier layer 214 and the III-N channel layer 216.

[0040] Transistor 200 further includes a source contact 224, a drain contact 225, and a gate contact 226, with source contact 224 and drain contact 225 each electrically connected to 2DEG channel 219. As used herein, two or more contacts or other items, such as conductive layers or components, are "electrically connected" to mean that they are connected by a material that is sufficiently conductive so that the electrical potential of each of the contacts or other items is always the same, or nearly the same, under all bias conditions.

[0041] The III-N layers 212, 214, and 216 are then heated to 400° C., as indicated by arrows 220. JPEG2025501019000002.jpg9170 2. The III-N layer 212 is an N-polar III-N layer oriented in the direction. Thus, the III-N channel layer 216 is on the N-face of the III-N barrier layer 214, and the source, drain, and gate contacts 224-226 are on the N-face of the III-N material structure 218 and on the III-N channel layer 216 opposite the III-N barrier layer 214, respectively. In some embodiments, it may be preferred that the first III-N layer 212 is at least 5 micrometers thick (e.g., at least 7 micrometers or at least 10 micrometers thick). For example, if the substrate 210 is conductive, it may be desirable for the first III-N layer 212 to be semi-insulating and at least 10 micrometers thick to electrically isolate the substrate 210 from the 2DEG channel 219. Optionally, the substrate 210 can be removed after forming the III-N layers 212, 214, and 216, so that the substrate 210 is not included in the final transistor structure. Additionally, optionally, after formation of the III-N layers 212, 214, and 216, some or all of the III-N layers underlying the III-N barrier layer 214 (e.g., III-N layer 212) can also be removed.

[0042] FIG. 2B illustrates another embodiment of a nitrogen-polarity (N-polarity) III-N transistor 200′ that is similar to the transistor 200 of FIG. 2A, but further includes a III-N transition layer 211 between the substrate 210 and the N-polarity III-N material structure 218. In some cases, it may be difficult to grow a high-quality N-polarity III-N layer directly on a foreign substrate (e.g., a substrate not formed of III-N material). In the transistor 200′ of FIG. 2B, this problem is addressed by first growing the III-N transition layer 211. This transition layer 211 is initially grown as a III-polarity layer, but is inverted to an N-polarity layer during the growth of the layer, for example, by doping with magnesium. That is, an initial portion of the III-N transition layer 211 (i.e., the portion close to the substrate 210) is formed as a III-polarity layer, and after this initial portion is formed, the growth conditions are adjusted so that the portion of the layer 211 above this initial portion is inverted and formed to have a nitrogen-polarity orientation. Similar to transistor 200 in FIG. 2A, optionally, the substrate can be removed, and optionally, after formation of III-N layers 212, 214, and 216, at least a portion of the III-N layers underlying III-N barrier layer 214 (e.g., III-N layers 211 and 212) can also be removed.

[0043] 3 is a plan view of an N-polarity III-N transistor structure 300 similar to the transistor 200 of FIG. 2, but implemented as a multi-finger device. The source contacts of the transistor structure 300 (corresponding to the source contacts 224 of the transistor 200) are implemented as a plurality of source fingers 324. The drain contacts of the transistor structure 300 (corresponding to the drain contacts 225 of the transistor 200) are implemented as a plurality of drain fingers 325. The gate contacts of the transistor structure 300 (corresponding to the gate contacts 226 of the transistor 200) are implemented as a plurality of gate fingers 326, with each gate finger 326 being between one of the source fingers 324 and one of the drain fingers 325, as shown. The gate fingers 326 are primarily on the active area 350 of the transistor structure 300, with the metal connecting each gate finger 326 being on the non-active area 360 of the transistor structure 300. In the active region 350, the III-N layer of the transistor structure 300 is the same as the III-N material structure 218 of the transistor 200 of FIG. 2, and in this region, the 2DEG channel 219 is present. In the non-active region 360, the III-N layer is modified (e.g., by ion implantation or by at least partially etching the III-N material structure 218) to remove the 2DEG channel 219 or to make all the material in the non-active region 360 non-conductive. The source fingers 324 are configured to be electrically isolated from each other (i.e., not electrically connected to each other), and the drain fingers are also configured to be electrically isolated from each other (i.e., not electrically connected to each other) in the transistor structure 300, as shown. However, when the III-N transistor structure 300 is connected to the base substrate 104 of FIG. 1 via the interconnect metal on the base substrate, the source fingers 324 are electrically connected to each other (as will be described below). Similarly, when the III-N transistor structure 300 is connected to the base substrate 104 of FIG. 1 through interconnect metal on the base substrate, the drain fingers 325 are also electrically connected to each other.In some embodiments, the source fingers 324 are electrically connected to each other but the drain fingers 325 are electrically isolated from each other before connecting the transistor structure 300 to the base substrate 104. In other embodiments, the drain fingers 325 are electrically connected to each other but the source fingers 324 are electrically isolated from each other before connecting the transistor structure 300 to the base substrate 104.

[0044] In some embodiments, at least a portion of the III-N transistor structure 300 is contained within a device cell, where the distance between any two points within the device cell is less than 15 percent of the free-space wavelength of radiation at the highest operating frequency of the semiconductor device. As used herein, the term "device cell" refers to a semiconductor device with a collection of two or more types of electrodes, e.g., the gate, source, and drain of a field effect transistor, or the anode and cathode of a diode, where each electrode of a given type is connected in parallel through conductive connections. There may be multiple active semiconductor regions accessed by these electrodes. The device cell is further constrained to be electrically small such that the phase of a continuous wave sinusoidal signal varies by no more than 10 percent of the period between all parallel-connected electrodes. At a minimum, the physical extent of a device cell must be within an area on the wafer surface where any two points on the perimeter of the cell are no more than 34 wavelengths of free space at the highest operating frequency. Electrodes may extend beyond what is considered a device cell. For example, an important feature of an ohmic contact is understood to be the portion within three transfer lengths of the current carrying end of the electrode, although the electrode may physically extend any distance beyond this. Multiple device cells may be further interconnected in parallel in a circuit.

[0045] FIG. 4 is a cross-sectional view 400 illustrating one embodiment of the semiconductor device 100 of FIG. 1 in which the transistor structure 300 of FIG. 3 is used as each transistor in the chiplets 132 and 134. Specifically, FIG. 4 illustrates the connection between the transistor structure 300 and the underlying base substrate 104 along dashed line 370 of FIG. 3, as well as illustrating additional features of the base substrate 104. As shown in FIG. 4, the base substrate 104 includes a substrate layer 436 that includes or is formed from a semiconductor or insulator material, such as silicon, gallium arsenide, silicon carbide, sapphire, germanium, indium phosphide, silicon oxide, and aluminum nitride. The substrate layer 436 has a front surface adjacent the transistor structure 300 and a back surface opposite the front surface. The substrate layer 436 has a first plurality of vias 472 formed therein, with each via 472 of the first plurality of vias extending through the entire thickness of the substrate layer 436 (i.e., from the front surface to the back surface). Each via 472 of the first plurality of vias has a first metal material 432 embedded therein. The first metal material may include or be formed from a material selected from the group consisting of copper, gold, aluminum, silver, and tungsten. The base substrate 104 further includes a backside metal material 438 covering a backside of the substrate layer 436 and in contact with the first metal material 432 in each via 472 of the first plurality of vias. The base substrate 104 further includes an interconnect metal 435 / 437 on a surface of the substrate layer 436, the interconnect metal 435 being in direct contact with the first metal material 432 in each via 472 of the first plurality of vias. The interconnect metal 435 may electrically connect each source finger 324 to one another, and the interconnect metal 437 may electrically connect each drain finger to one another when the transistor structure 300 is connected (e.g., bonded) to the base substrate 104. The interconnect metal 435 / 437 may also form electrical connections between contacts of the transistor structure 300 and other components of the semiconductor device 100 when the transistor structure 300 is connected (e.g., bonded) to the base substrate 104. Optionally, a dielectric material 439 is included on the surface of the substrate layer 436.

[0046] As shown in FIG. 4, the transistor structure 300 is connected to the base substrate 104 in a configuration in which the plurality of contacts 324-326 of the transistor structure 300 are between the III-N channel layer of the material structure 218 and the base substrate 104. The transistor structure 300 can be connected to the base substrate 104 using the following process. Prior to connection, a first bonding material 444 / 445 is deposited on a portion of the source contact 324 and the drain contact 325 of the transistor structure 300, respectively, as shown in FIG. 5. As shown in FIGS. 4 and 5, a portion of the first bonding material 444 is deposited on the portion of the source contact 324, and a portion of the first bonding material 445 is deposited on the portion of the drain contact 325. A second bonding material 454 / 455 (shown in FIG. 4) is deposited on the portion of the base substrate 104 in a pattern that mirrors the pattern of the first bonding material 444 / 445. The location of the second bonding material portion 454 corresponds to the location of the first bonding material portion 444, and the location of the second bonding material portion 455 corresponds to the location of the first bonding material portion 445. The second bonding material portion 454 may be in direct contact with the interconnect metal 435, and the second bonding material portion 455 may be in direct contact with the interconnect metal 437. The transistor structure 300 is then placed on the surface of the base substrate 104 with the substrate layer 436 oriented between the backside metal 438 and the transistor 300, such that the first bonding material portion 444 is in direct contact with the second bonding material portion 454, and the first bonding material portion 445 is in direct contact with the second bonding material portion 455. 4, in this configuration, the bonding material 444 / 454 resides directly between the source contact 324 and the first metal material 432 in each via 472 of the first plurality of vias, and the interconnect metal 435 resides between the source contact 324 and the first metal material 432 in each via 472 of the first plurality of vias. The entire semiconductor device 100 is then exposed to heat and / or pressure to cause the bonding material to form an electrical and thermal connection between the source / drain contacts 324 / 325 and the corresponding interconnect metal 435 / 437.Because the interconnect metal 435 is directly connected (and electrically connected) to the first metal material 432 in each via 472 of the first plurality of vias, after the thermal bonding process is completed, the first metal material 432 in each via 472 of the first plurality of vias is electrically connected to the source contact 324 by the bonding materials 444 and 454.

[0047] The bonding materials 444 / 445 and 454 / 455 may each be formed of the same material or different materials. For example, either of the bonding materials 444 / 445 or 454 / 455 may include or be formed of gold, silver, copper, and indium-containing compounds, tin-containing compounds, AuSn, AuSi, CuSn, AuGe, AlGe, AlSi, or combinations thereof. In some cases, the bonding material 444 / 445 is applied to the transistor structure 300, but the bonding material 454 / 455 is not applied to the base substrate 104, and thus is omitted from the semiconductor device 100, and only a single bonding material is used in the device 100. In other cases, the bonding material 454 / 455 is applied to the base substrate 104, but the bonding material 444 / 445 is not applied to the transistor structure 300, and thus is omitted from the semiconductor device 100, and only a single bonding material is used in the device 100.

[0048] The first metal material 432 in each via 472 of the first plurality of vias shown in FIG. 4 can serve several purposes. First, the first metal material 432 in each via 472 provides a conductive path between the source contacts (fingers) 324 of the transistor 300 and the backside metal material 438, thereby electrically connecting the source fingers 324 to one another and also allowing a voltage (e.g., a ground voltage) to be applied to the source contacts 324 through the backside metal material 438. Second, the first metal material 432 in each via 472 provides a thermally conductive path for dissipating heat generated during operation of the transistor 300, e.g., transferring heat from the transistor 300 to the backside metal material 438. To effectively transfer heat from the transistor 300, the composition of the first metal material 432 can be selected such that the thermal conductivity of the first metal material 432 is higher than the thermal conductivity of the semiconductor or insulator material of the substrate layer 436. To further improve thermal management of the semiconductor device 100, the device 100 may optionally be attached to a metal plate 480. As shown in Figure 4, the metal plate 480 is in direct contact with the backside metal material 438. The metal plate 480 can act as both a ground plate and a heat sink.

[0049] To further improve dissipation of heat from the transistor 300, the base substrate 104 may further include a second plurality of vias 474, where each via 474 of the second plurality of vias may also include a first metal material 432 therein. As shown in FIG. 4, each via 474 of the second plurality of vias may be disposed beneath one of the contacts 324-326 that is not beneath a via 472 of the first plurality of vias. For example, for the configuration 400 shown in FIG. 4, each via 472 of the first plurality of vias is beneath a source finger 324, and each via 474 of the second plurality of vias is beneath a drain finger 325. Each via 474 extends to the backside of the substrate layer 436, such that the first metal material 432 within the via 474 of the second plurality of vias is in contact with the backside metal material 438. However, to prevent the source contact 324 and the drain contact 325 from shorting (i.e., electrically connecting) each other, the first metal material 432 in the vias 474 of the second plurality of vias must be electrically isolated from the drain contact 325. Thus, as shown in FIG. 4, each via 474 of the second plurality of vias does not extend through the entire thickness of the substrate layer 436, but rather only partially penetrates the substrate layer 436. As such, a portion of the substrate layer 436 remains between the via 474 and the interconnect metal 437.

[0050] Because the first metal material 432 in each via 472 of the first plurality of vias is electrically connected to both the backside metal material 438 and the source contact 324, the source contact can be fixed to a ground voltage by attaching the semiconductor device 100 to a ground plate 480 that directly contacts the backside metal material 438, as shown in FIG. 4. However, in some cases, it may be desirable to contact the drain contact 325, rather than the source contact 324, to the backside metal material 438. FIG. 6 illustrates an alternative embodiment 600 of the semiconductor device 100 in which the transistor 300 is bonded to a base substrate 604. The base substrate 604 is similar to the base substrate 104 of FIG. 4, but is configured such that the vias 472 of the first plurality of vias (i.e., vias that extend through the entire thickness of the substrate layer 436) are under the drain fingers (i.e., drain contacts) 325 and the vias 474 of the second plurality of vias are under the source fingers (i.e., source contacts) 324. Thus, when the transistor 300 is connected (e.g., bonded) to the base substrate 604, the drain contact 325 of the transistor 300 is electrically connected to the first metal material 432 in the first plurality of vias 472, and the via 474 of the second plurality of vias is below the source contact 324.

[0051] In some cases, it may be desirable to electrically isolate the first metal material 432 in the vias 472 and 474 from the substrate layer 436 to inhibit leakage currents through the first metal material 432. Accordingly, FIG. 7 is a cross-sectional view of a portion of the semiconductor device 100 of FIG. 1, illustrating an embodiment 700 in which the transistor 300 is connected (e.g., bonded) to a base substrate 704. The base substrate 704 is similar to the base substrate 104 illustrated in FIG. 4, but further includes an insulating material 740 in the vias 472 and 474 between the first metal material 432 and the substrate layer 436. The insulating material 740 electrically isolates the first metal material 432 from the substrate layer 436. The insulating material 740 may have a higher thermal conductivity than the semiconductor or insulating material of the substrate layer 436, which may further improve heat dissipation from the transistor 300. However, many materials that provide sufficient electrical insulation also have poor thermal conductivity. Thus, the insulating material 740 may have a lower thermal conductivity than the semiconductor or insulator material of the substrate layer 436 .

[0052] In some embodiments of the semiconductor device 100, it may be desirable for the source contact 324, the drain contact 325, and the gate contact 326, respectively, to all be electrically isolated (i.e., not electrically connected) from the backside metal material 438. However, such a structure may make it difficult to adequately dissipate heat from the N-polar III-N transistor during operation. Figures 8A and 8B show embodiments of N-polar III-N transistor structures 800A and 800B, respectively, which are similar to the transistor structure 300 of Figure 3, but further include a thermal contact 827 that is electrically isolated from the 2DEG channel (2DEG 219 shown in Figure 2) and thermally coupled to the III-N material structure in the active region 350 and / or non-active region 360 of the transistor structure. In the transistor structure 800A, the thermal contact is partially on the material of the active region 350 and partially on the material of the non-active region 370. In transistor structure 800B, the thermal contact is divided into multiple regions and is entirely on the material of the non-active region 370. The transistor structures 800A and 800B may be connected to a base substrate 904 in a configuration 900 shown in FIG. 9 (transistor structure 800A is shown in FIG. 9) to allow sufficient heat dissipation during operation. FIG. 9 is a cross-sectional view of a semiconductor device along dashed line 870 in FIG. 8A when the transistor structure 800 is bonded to the base substrate 904. The base substrate 904 is similar to the base substrate 104 in FIG. 4, but is configured such that the via 472 of the first plurality of vias (i.e., vias that extend through the entire thickness of the substrate layer 436) is below the thermal contact 827 and the via 474 of the second plurality of vias is below the source contact 324 and the drain contact 325, respectively. Thus, when the transistor 300 is connected (e.g., bonded) to the base substrate 604, the thermal contacts 827 of the transistor structure 800 are electrically connected to the first metal material 432 of the first plurality of vias 472, which are located below the source contacts 324 and the drain contacts 325, respectively.In this configuration, a significant amount of heat generated in the transistor structure 800 is transferred to the backside metal 438 through the thermal contact 827, the interconnect metal 835, and the first metal material 432 in the first plurality of vias 472. Excess heat is also transferred to the backside metal 438 through the source and drain contacts 324 and 325, and through the first metal material 432 in the second plurality of vias 474.

[0053] 1 shows a semiconductor device 100 configured as a transmit / receive module, other types of devices and circuits can be formed using III-N N-polarity transistors bonded to a base substrate using the processes described above for a variety of applications. For example, devices and circuits that can be formed using III-N N-polarity transistors bonded to a base substrate using the structures and processes described herein include power amplifiers (e.g., switch mode power amplifiers such as class A power amplifiers, class B power amplifiers, class C power amplifiers, outphasing power amplifiers, Doherty power amplifiers, class D, E, F, or inverted class F power amplifiers, stacked power amplifiers, or envelope tracking power amplifiers), low noise amplifiers, buffer or drive amplifiers, distributed amplifiers, transimpedance amplifiers, operational amplifiers, laser drivers or light emitting diode drivers, piezoelectric drivers, analog predistorters, switches such as single-pole single-throw switches and single-pole double-throw switches, other switch embodiments with one or more poles and one or more throws, discrete transistors, cascode amplifiers, Darlington pair amplifiers, differential pairs, mixers, frequency multipliers, frequency These may include frequency dividers, phase detectors, phase locked loops, oscillators, voltage controlled oscillators, variable gain amplifiers, variable attenuators, phase shifters, modulators, vector modulators, voltage regulators, pulse modulators, pulse generators, power detectors, time delays, couplers, isolators, circulators, filters, limiters, as well as any of the above circuits in either a differential or single-ended input and differential or single-ended output configuration, linear voltage regulators, half bridges, full bridges, rectifiers, switching power converters (such as buck converters, boost converters, buck-boost converters, Cuk converters, single-ended primary inductor converters, flyback converters, forward converters, push-pull converters, half bridge converters or full bridge converters, or envelope tracking power supplies), and the like.Many of these other types of devices and circuits can include other circuit components in addition to, or in place of, the components described above for semiconductor device 100. These other components can include, for example, capacitors, inductors, transformers, resistors, waveguides, antennas, electrical resonators, acoustic components, piezoelectric components, diodes, silicon-based transistors, or combinations thereof.

[0054] When the semiconductor device 100 is configured as a circuit (e.g., an RF circuit), various components and functions can be configured to optimize the performance of the circuit. Especially for high power and high frequency operation, various functions and design elements may play a significant role in the performance of the circuit. Thus, the transistor 300 may be configured such that its maximum operating frequency is at least twice (e.g., at least 2.5 times, at least 3 times, at least 4 times, or at least 5 times) the operating frequency of the circuit. For a high frequency amplifier, the most relevant maximum operating frequency is the maximum oscillation frequency, and for a switch, the most relevant maximum operating frequency is the cutoff frequency of the switch. Also, some circuits, such as frequency multipliers, do not have a clearly defined maximum operating frequency. Furthermore, to minimize parasitic impedances at the source and gate terminals of the transistor 300, the total thickness of the bonding materials 444 / 454 or 445 / 455 may be less than 0.4% (e.g., less than 0.3% or less than 0.2%) of the free space wavelength corresponding to the maximum operating frequency of the circuit. For example, the total thickness of the bonding materials 444 / 454 or 445 / 455 may be less than 30 micrometers, less than 25 micrometers, less than 20 micrometers, less than 15 micrometers, or less than 10 micrometers.

[0055] The term "maximum operating frequency" as used herein refers to the highest frequency at which any significant voltage, current, or power of the signal is present. In applications using bandwidth-limited signals, such as most digitally modulated communications, this is considered the upper frequency limit of the signal's channel. In applications without a clearly defined upper frequency limit, for example when the signal is a frequency modulated analog signal or a pulse train, the upper limit is usually interpreted as the highest frequency below which 99% of the significant signal power is contained, excluding any DC component of the power. Harmonics of the signal frequency are usually excluded from the maximum operating frequency, except in applications where the harmonic components of the signal are used as output, such as in the case of a frequency multiplier.

[0056] In some embodiments of the semiconductor device 100, it is preferable to add a precise impedance to the source contact 324, drain contact 325, or gate contact 326, respectively, to improve impedance matching in various RF circuit applications. For example, in a low noise amplifier with HEMT transistors connected to a common source, it may be desirable to add a small inductive impedance between the HEMT source and circuit ground, and provide gain and low noise matching impedance to the drain and gate, respectively. When the device terminals are also used as the main points of heat transfer to the base substrate, at least one terminal will often be directly connected to the back metal of the base substrate by the metal material 432 in multiple vias 472 (e.g., source contact 324 in embodiments 400 and 700, drain contact 325 in embodiment 600). The size (e.g., average diameter) and number of vias can be adjusted to control the series inductance between the back metal 438 and the contact connected to the metal material 432 in the vias 472. However, the range of impedance values ​​that can be obtained in this manner may be limited (the magnitude of the impedance of an inductor is equal to the product of the frequency and inductance of the current flowing through the inductor). For example, the product of the transistor inductance and gate width may be limited to a range of 0.01 to 100 pH-mm (where the transistor gate width refers to the dimension of the gate perpendicular to the gate length). This may limit the range of impedance values ​​that can be obtained. Another approach is to pattern the backside metal 438 to include various passive circuit elements, rather than providing it as a uniform ground plate. However, this approach may be less desirable when attaching a semiconductor device to the ground plate 480. Yet another approach is to implement the structure shown in FIG. 9 and place an impedance element (e.g., a metal strip having a desired impedance) in series with the interconnect metals 435 and 437 connected to the source contact 324 and drain contact 325, respectively.

[0057] Another approach is to include an impedance element between the source contact 324 and the source interconnect metal 435 and / or between the drain contact 325 and the drain interconnect metal 437. The impedance element may be, for example, a metal strip deposited on a dielectric material 439 (shown in FIG. 4) at the surface of the substrate layer 436. FIG. 10 is a cross-sectional view illustrating a source junction of a semiconductor device configuration 1000 similar to the configuration 400 of FIG. 4, but further including an impedance element 1002 between the source contact 324 and the source interconnect metal 435. As shown, a first end of the impedance element 1002 is electrically connected to the source contact 324 by the junction materials 444 and 454, and a second end of the impedance element 1002 is electrically connected to the first metal material 432 in the via 472 by the source interconnect metal 435. Optionally, further source interconnect metal 435' may be electrically connected to the first end of impedance element 1002, with all of the source fingers electrically connected to each other by further source interconnect metal 435. Similar modifications may be made to the connection between the drain contact and the drain interconnect metal to insert an impedance element therebetween.

[0058] 10 illustrates the impedance element 1002 as being formed on the dielectric material 439 and / or on a surface of the base substrate 104, other configurations are possible. For example, the impedance element 1002 may be formed within (e.g., within) the dielectric material 439. That is, the dielectric material 439 may be formed from two (or more) dielectric layers, and the impedance element 1002 may be formed between the two dielectric layers. Also, the source interconnect metal 435 may include multiple metal wiring layers.

[0059] 11 is a cross-sectional view of another semiconductor device 1100 similar to that shown in FIG. 10, but having an inductive element 1102 (a type of impedance element) integrated with a base substrate 1104. That is, the base substrate 1104 includes an integrated inductive element 1102 that includes a front metal layer 1162, a back metal layer 1138, and a first metal material 432 in a via 472. The view shown in FIG. 11 corresponds to a cross-section along dashed line 1270 in FIG.

[0060] FIG. 12 is a plan view of the entire inductive element 1102 (with the substrate layer 436 omitted for clarity). As shown in FIG. 12, the front metal layer 1162 is patterned into a number of segments 1162A-1162L, and the back metal layer 1138 is patterned into a number of segments 1138A-1138K. Segment 1162A is conductively connected to segment 1138A through a first metal material 432 in a first via 472 common to the two segments. Segment 1138A is conductively connected to segment 1162B through a first metal material 432 in a second via 472 common to the two segments, and so on. Thus, current entering inductive element 1102 at contact 324 first passes through segment 1162A, then down through the first via 472 to segment 1138A, then up through segment 1138A through the second via 472 to segment 1162B, and so on until the current passes through segment 1162L and exits inductive element 1102. The configuration of inductive element 1102 shown in Figure 12 is in the form of a toroidal inductor, although alternative configurations may form other types of inductors, as will be described in more detail below.

[0061] FIG. 13 is a cross-sectional view of a portion of another inductive element 1302 that may be used with or integrated into a semiconductor device described herein. Additional components of the overall inductive element 1302 are shown in plan view in FIG. 14. What is shown in FIG. 13 corresponds to a cross-section along dashed line 1470 in FIG. 14. The inductive element 1302 is formed from materials 210 and 218 of the chiplet structure 1360, bonding materials 444 / 454, and a first metal layer 1364 that overlies the surface metal layer 1335 of the base substrate 1304. Thus, the complete structure of the inductive element 1302 is formed only after the chiplet structure 1360 is connected (e.g., bonded) to the base substrate 1304.

[0062] Figure 14 is a plan view of the essential portion of the inductive element 1302. As shown in Figure 14, the first metal layer 1364 is patterned into a number of segments 1364A-1364L, and the surface metal layer 1335 is patterned into a number of segments 1335A-1335K. Segment 1364A is conductively connected to segment 1335A via a first bonding material stack 444 / 454, segment 1335A is conductively connected to segment 1364B via a second bonding material stack 444 / 454, and so on. Thus, current entering inductive element 1302 first passes through segment 1364A, then through the first stack of joining materials 444 / 454 into segment 1335A, then through segment 1335A through the second stack of joining materials 444 / 454 into segment 1364B, and so on, until the current passes through segment 1364L and exits inductive element 1302. The configuration of inductive element 1302 shown in Figure 14 is in the form of a toroidal inductor, although alternative configurations may form other types of inductors, as will be described in more detail below.

[0063] 15-16 show the configurations of inductive elements 1502 and 1602, respectively, which can be formed using the same materials and manufacturing techniques as inductive element 1102 of FIGS. 11-12 and 13-14. FIG. 17-18 show the configurations of inductive elements 1702 and 1802, respectively, which can be formed using the same materials and manufacturing techniques as inductive element 1302 of FIGS. 13-14. FIG. 15 and FIG. 17 are plan views showing an axial inductor, and FIG. 16 and FIG. 18 are plan views showing a conical axial inductor. FIG. 19-20 show the configurations of toroidal transformers 1902 and 2002, respectively. Transformer 1902 can be formed using the same materials and manufacturing techniques as inductive element 1102 of FIGS. 11-12, and transformer 2002 can be formed using the same materials and manufacturing techniques as inductive element 1302 of FIGS. 13-14.

[0064] As mentioned above, each chiplet may include a plurality of N-polarity III-N transistors bonded to a base substrate. Thus, any of the semiconductor devices described herein may include, in addition to the single N-polarity III-N transistor shown in Figures 4, 6, 7, 10, and 11 as bonded to a base substrate, a second transistor also connected to the base substrate, the second transistor including a second III-N barrier layer and a second III-N channel layer on the N-face of the second III-N barrier layer. The band gap of the second III-N barrier layer is larger than that of the second III-N channel layer. The second transistor may further include a second 2DEG channel in the second III-N channel layer adjacent to the interface between the second III-N channel layer and the second III-N barrier layer, and a second plurality of contacts. The second plurality of contacts includes a second source contact, a second drain contact, and a second gate contact. The second source contact, the second gate contact, and the second drain contact are each on an opposite side of the second III-N channel layer from the second III-N barrier layer, and the second source contact and the second drain contact are electrically connected to the second 2DEG channel.

[0065] 21A is a cross-sectional view illustrating a semiconductor device embodiment 2100 in which a two-terminal device structure, such as a diode structure 2102, is connected to a base substrate 2104. The diode structure 2102 includes an anode contact (e.g., an anode finger) 396 and a cathode contact (e.g., a cathode finger) 394. Each cathode finger 394 is electrically connected (through bonding material 444 / 454 and interconnect metal 495) to metal material 432 in a number of vias 472. As with other embodiments described herein, each via 472 extends through the entire thickness of the substrate layer 436, and the metal material 432 contacts the backside metal material 438.

[0066] 21B is a cross-sectional view illustrating another embodiment 2100' of a semiconductor device in which a two-terminal device structure, such as a diode structure 2102, is connected to a base substrate 2104'. In the embodiment illustrated in FIG. 21B, each anode finger 396 is electrically connected (through bonding material 444 / 454 and interconnect metal 495) to metal material 432 in a plurality of vias 472.

[0067] FIG. 21C is a cross-sectional view illustrating yet another embodiment 2100″ of a semiconductor device in which a two-terminal device structure, such as a diode structure 2102, is connected to a base substrate 2104″. In the embodiment illustrated in FIG. 21C, the anode finger 396 and the cathode finger 394 are each electrically isolated from the metal material 432 within the via 474 because the via 474 does not penetrate the entire thickness of the substrate layer 436. Although not shown in FIG. 21C, similar to the structures illustrated in FIGS. 8A, 8B, and 9, the diode structure 2102 may further include one or more thermal contacts (such as thermal contact 827 in FIGS. 8A, 8B, and 9) electrically connected to the metal material 438.

[0068] Figure 22 is a cross-sectional view of another embodiment 2200 of a semiconductor device similar to device 400 of Figure 4, except that metal material 438 on the backside of substrate layer 436 of base substrate 1204 is patterned to form a portion of an inductor. The source interconnect metal 435 may all be electrically connected to each other, and the drain interconnect metal 437 may all be electrically connected to each other.

[0069] 23A is a cross-sectional view of another embodiment 2300 of a semiconductor device similar to device 900 of FIG. 9, except that base substrate 2304 further includes a semiconductor component 2310 formed in substrate layer 436 of base substrate 2304, and at least one contact (e.g., source 324, drain 325, or gate 326) of transistor structure 800 is electrically connected (e.g., coupled) to a contact of semiconductor component 2310. In the configuration shown in FIG. 23A, semiconductor component 2310 is a bipolar junction transistor and includes emitter contact 2312, base contact 2314, and collector contact 2316. Emitter contact 2312 is electrically connected to backside metal 438 via interconnect metal 835 and first metal material 432 in at least one of vias 472. The collector contact 2316 is electrically connected to the source finger 324 of the transistor structure 800 via the bonding material 445 / 455.

[0070] FIG. 23B is a circuit diagram showing the connection between the contacts of the transistor structure 800 and the bipolar junction transistor 2310 when the metal plate 480 (electrically connected to the emitter contact 2312) is connected to ground. The configuration shown in FIG. 23B is commonly known as a cascode configuration. Although not shown in FIG. 23A and FIG. 23B, the gate finger 326 may optionally be connected to ground and / or the emitter contact 2312, for example, by coupling the gate finger 326 to an interconnect metal 835 that contacts the first metal material 432 in at least one of the vias 472, thereby electrically connecting the gate finger 326 to the backside metal 438. In some embodiments, the transistor structure 800 may have a higher breakdown voltage than the semiconductor component (e.g., bipolar transistor structure) 2310. In some embodiments, transistor structure 800 may be a depletion mode device with a threshold voltage less than zero, and optionally semiconductor component 2310 may be an enhancement mode device with a threshold voltage greater than zero. By coupling devices 800 and 2310 in a cascode configuration using the coupling technique shown in Figure 23A, the impedance of connecting the contacts of one device to the contacts of the other device can be minimized while effectively dissipating heat from the devices during operation.

[0071] FIG. 24 is a cross-sectional view of another embodiment 2400 of the cascode configuration shown in FIG. 23B. In the configuration 2400, the backside metal material 438 and the metal plate 480 are on the backside of the transistor structure 800′, rather than on the backside of the material structure 2484 that has the semiconductor component 2310 in part (e.g., formed therein). That is, the backside metal material 438 and the metal plate 480 are on the opposite side of the substrate 210 from the III-N material structure 218. In this configuration, the substrate 210 and the III-N material structure 218 can form a base substrate upon which a circuit can be fabricated / assembled, and the semiconductor component 2310 is provided as one or more chiplets bonded to the base structure. Thus, the substrate 210, III-N material structure 218, backside metal material 438, and the metal plate 480 can extend laterally beyond the extent shown in FIG. 24 and can further include additional circuit components connected on or formed within the III-N material structure. The base substrate including the transistor structure 800' may optionally include vias 2472 / 2482 including metal material 432 similar to the vias shown above for other devices, except that the vias 2472 / 2482 pass through the material of the transistor structure 800' rather than through the material of a device bonded to the transistor structure 800'. The vias 2472 and the metal material 432 therein electrically connect the emitter contact 2312 to the metal plate 480, which may be a useful configuration to provide a low impedance electrical connection from the emitter contact 2312 to ground when the metal plate 480 is grounded and serves as a ground plate. Optionally, thermal vias 2482 may also be included to improve heat dissipation, but are often not required. Although not shown, an additional via may optionally be included to electrically connect the gate finger 326 to the metal plate 480 to provide a low impedance electrical connection from the gate finger 326 to the metal plate 480. Alternatively, the gate fingers 326 may optionally be directly bonded to the emitter contacts 2312 or may be electrically connected to the emitter contacts 2312 by metal traces on the surface of the transistor structure 800'.The configuration 2400 shown in FIG. 24 may be more costly to implement than other embodiments described herein, but may be more effective at dissipating heat from the transistor structure 800′, thereby improving overall circuit performance.

[0072] A method 2500 of forming one or more of the semiconductor devices described herein is shown in FIG. 25. The method 2500 includes providing a base substrate 2510. The base substrate may be, for example, the base substrate 104 shown in FIG. 4 and FIG. 10. The method 2500 further includes connecting a transistor to the base substrate 2520 (e.g., connecting the transistor 300 to the base substrate 104 as shown in FIG. 4 and FIG. 10). In some embodiments, the method 2500 includes, after connecting the transistor to the base substrate, the transistor is on a front surface of the base substrate with a substrate layer of the base substrate between a backside metal and the transistor, and a first metal material in a first via of a first plurality of vias is electrically connected to a first contact of a plurality of contacts by one or more bonding materials (e.g., as in FIG. 4). In another embodiment of method 2500, after connecting the transistor to the base substrate, the transistor is on the surface of the base substrate with a substrate layer of the base substrate between a backside metal and the transistor, a first end of an impedance element is electrically connected to a first contact of a plurality of contacts, and a second end of the impedance element is electrically connected to a first metal material (e.g., as in FIG. 10). The source contact of the transistor connected to the base substrate may include a plurality of source fingers. Before connecting the transistor to the base substrate, the source fingers may be electrically isolated from one another. After connecting the transistor to the base substrate, the source fingers may all be electrically connected to a common conductor, whereby the source fingers are electrically connected to one another.

[0073] Any of the semiconductor devices described herein may be part of or integrated with electronic components such as a cellular phone, a mobile or satellite base station, a radar module, a backhaul system, or a wireless access point, or any of the semiconductor devices described herein may be part of or integrated with a land, sea, or airborne transmitter, receiver, or transceiver that communicates with a satellite.

[0074] Various semiconductor devices and methods of forming the semiconductor devices have been described above. However, it should be understood that these are presented by way of example only and not limitation. Where the above methods and steps show particular events occurring in a particular order, those skilled in the art will recognize that the order of certain steps can be modified and that such modifications are in keeping with the variations of the disclosure. While embodiments have been specifically shown and described, it will be understood that various changes in form and detail can be made. Accordingly, other embodiments are within the scope of the following claims.

Claims

1. 1. A semiconductor device comprising: A base substrate, a substrate layer including a semiconductor or insulating material, the substrate layer having a front surface and a back surface opposite the front surface; a first plurality of vias each extending through a thickness of the substrate layer; a first metallic material within each via of the first plurality of vias; a backside metal material covering the backside surface of the substrate layer and in contact with the first metal material in each via of the first plurality of vias; an interconnect metal on the surface of the substrate layer; A base substrate including: A transistor connected to the base substrate, 1. A III-N material structure comprising: a III-N barrier layer; and a III-N channel layer on an N-face of the III-N barrier layer, the III-N barrier layer having a larger bandgap than the III-N channel layer; and a 2DEG channel in the III-N channel layer adjacent an interface between the III-N channel layer and the III-N barrier layer; a III-N material structure comprising: a plurality of contacts, the plurality of contacts including a source contact, a drain contact, and a gate contact, the source contact, the gate contact, and the drain contact being on an opposite side of the III-N channel layer from the III-N barrier layer, the source contact and the drain contact being electrically connected to the 2DEG channel; A transistor including Including, a first via of the first plurality of vias electrically connected to a first contact of the plurality of contacts by one or more bonding materials;

2. 10. The semiconductor device of claim 1, wherein at least one of the one or more bonding materials comprises gold, silver, copper, and indium-containing compounds, tin-containing compounds, AuSn, AuSi, CuSn, AuGe, AlGe, AlSi, or combinations thereof.

3. The semiconductor device of claim 1 , wherein the one or more bonding materials are directly between the first contact and the first metallic material.

4. The semiconductor device of claim 1 , wherein the first contact is the source contact.

5. 1. A semiconductor device comprising: A base substrate, a substrate layer including a semiconductor or insulating material, the substrate layer having a front surface and a back surface opposite the front surface; a first plurality of vias each extending through a thickness of the substrate layer; a first metallic material within each via of the first plurality of vias; a backside metal material covering the backside surface of the substrate layer and in contact with the first metal material in each via of the first plurality of vias; an interconnect metal on the surface of the substrate layer; A base substrate including: A transistor connected to the base substrate, 1. A III-N material structure comprising: a III-N barrier layer; and a III-N channel layer on an N-face of the III-N barrier layer, the III-N barrier layer having a larger bandgap than the III-N channel layer; and a 2DEG channel in the III-N channel layer adjacent an interface between the III-N channel layer and the III-N barrier layer; a III-N material structure comprising: a plurality of contacts including a source contact, a drain contact, and a gate contact, the source contact, the gate contact, and the drain contact being on an opposite side of the III-N channel layer from the III-N barrier layer, and the source contact and the drain contact being electrically connected to the 2DEG channel; a thermal contact thermally coupled to the III-N material structure and electrically isolated from the 2DEG channel; A transistor including Including, a semiconductor device, the transistor being on the front surface of the base substrate with the substrate layer of the base substrate between the back surface metal and the transistor, and the first metal material in a first via of the first plurality of vias being electrically connected to the thermal contact of the transistor.

6. 1. A semiconductor device comprising: A base substrate, a substrate layer including a semiconductor or insulating material, the substrate layer having a front surface and a back surface opposite the front surface; a first plurality of vias each extending through a thickness of the substrate layer; a first metallic material within each via of the first plurality of vias; a backside metal material covering the backside surface of the substrate layer and in contact with the first metal material in each via of the first plurality of vias; an interconnect metal on the surface of the substrate layer; A base substrate including: A transistor connected to the base substrate, 1. A III-N material structure comprising: a III-N barrier layer; and a III-N channel layer on an N-face of the III-N barrier layer, the III-N barrier layer having a larger bandgap than the III-N channel layer; and a 2DEG channel in the III-N channel layer adjacent an interface between the III-N channel layer and the III-N barrier layer; a III-N material structure comprising: a plurality of contacts including a source contact, a drain contact, and a gate contact, the source contact, the gate contact, and the drain contact being on an opposite side of the III-N channel layer from the III-N barrier layer, and the source contact and the drain contact being electrically connected to the 2DEG channel; a thermal contact thermally coupled to the III-N material structure and electrically isolated from the 2DEG channel; A transistor including Including, the transistor is on the front surface of the base substrate with the substrate layer of the base substrate between the backside metal and the transistor; A semiconductor device, wherein a first end of an impedance element is electrically connected to a first contact of the plurality of contacts and a second end of the impedance element is electrically connected to the first metallic material.

7. The method further includes the step of: a second III-N barrier layer; and a second III-N channel layer on the N-face of the second III-N barrier layer, the second III-N barrier layer having a larger bandgap than the second III-N channel layer; and a second 2DEG channel in the second III-N channel layer adjacent an interface between the second III-N channel layer and the second III-N barrier layer; a second plurality of contacts including a second source contact, a second drain contact, and a second gate contact, the second source contact, the second gate contact, and the second drain contact each being on an opposite side of the second III-N channel layer from the second III-N barrier layer, and the second source contact and the second drain contact electrically connected to the second 2DEG channel; Including, 7. The semiconductor device of claim 1, wherein the second transistor is at least partially connected to the base substrate by the one or more bonding materials, the one or more bonding materials further being directly between a second contact of the second plurality of contacts and the first metal material in a second via of the first plurality of vias.

8. The semiconductor device of any one of claims 1 to 6, wherein the substrate layer comprises a material selected from the group consisting of silicon, gallium arsenide, silicon carbide, sapphire, germanium, indium phosphide, silicon oxide, and aluminum nitride.

9. The semiconductor device of any one of claims 1 to 6, wherein the base substrate further comprises a second plurality of vias each extending partially through the substrate layer without extending through the entire thickness of the substrate layer.

10. 10. The semiconductor device of claim 9, wherein the base substrate further comprises the first metallic material within each via of the second plurality of vias.

11. The semiconductor device of claim 10 , wherein a second via of the second plurality of vias is directly beneath a second contact of the plurality of contacts.

12. The semiconductor device according to any one of claims 1 to 6, wherein the thermal conductivity of the first metallic material is greater than the thermal conductivity of the semiconductor or insulator material of the substrate layer.

13. The semiconductor device of any preceding claim, wherein the base substrate further comprises an insulating material within each via of the first plurality of vias.

14. The semiconductor device of claim 13 , wherein the insulating material has a lower thermal conductivity than the semiconductor or the insulating material of the substrate layer.

15. The semiconductor device of claim 13 , wherein the insulating material is between the first metallic material and the substrate layer.

16. 16. The semiconductor device of claim 15, wherein the insulating material electrically isolates the first metallic material from the substrate layer.

17. 7. The semiconductor device of claim 1, further comprising a circuit element connected to the base substrate, the circuit element being selected from the group consisting of a capacitor, an inductor, a transformer, a resistor, a waveguide, an antenna, an electrical resonator, an acoustic component, a piezoelectric component, a diode, and a silicon-based transistor.

18. The semiconductor device of any one of claims 1 to 6, wherein the first metallic material comprises a material selected from the group consisting of copper, gold, aluminum, silver, and tungsten.

19. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device is a circuit, and a maximum operating frequency of the transistor is at least twice the operating frequency of the circuit.

20. 7. The semiconductor device of claim 1, wherein the semiconductor device is a circuit and the total thickness of the one or more bonding materials is less than 0.4% of a free space wavelength corresponding to a maximum operating frequency of the circuit.

21. The semiconductor device of any one of claims 1 to 6, wherein a total thickness of the one or more bonding materials is less than 20 micrometers.

22. The semiconductor device of any preceding claim, wherein the interconnect metal is in direct contact with the first metal material in the first via of the first plurality of vias.

23. 23. The semiconductor device of claim 22, wherein the interconnect metal is between the source contact and the first metal material in the first via of the first plurality of vias.

24. The semiconductor device of any one of claims 1 to 6, wherein the contacts of the transistor are between the III-N channel layer and the base substrate.

25. 7. The semiconductor device of claim 1, wherein at least a portion of the transistor is contained within a device cell, and the distance between any two points within the device cell is less than 15 percent of the free space wavelength of radiation at a highest operating frequency of the semiconductor device.

26. 1. A semiconductor device comprising: A base substrate, a substrate layer including a semiconductor or insulating material, the substrate layer having a front surface and a back surface opposite the front surface; a plurality of vias each extending through the entire thickness of the substrate layer; a first metallic material within each of said vias; a backside metal layer patterned to form a first plurality of segments on a backside side of the substrate layer, each segment of the first plurality of segments in contact with the first metal material in at least one of the vias; a surface metal layer patterned to form a second plurality of segments on the surface of the substrate layer, each segment of the second plurality of segments contacting the first metal material in at least one of the vias; A base substrate including: A transistor, 1. A III-N material structure comprising: a III-N barrier layer; and a III-N channel layer on an N-face of the III-N barrier layer, the III-N barrier layer having a larger bandgap than the III-N channel layer; and a 2DEG channel in the III-N channel layer adjacent an interface between the III-N channel layer and the III-N barrier layer; a III-N material structure comprising: a plurality of contacts, including a source contact, a drain contact, and a gate contact, the source contact, the gate contact, and the drain contact being on an opposite side of the III-N channel layer from the III-N barrier layer, the source contact and the drain contact being electrically connected to the 2DEG channel; A transistor including Including, the transistor is on the front surface of the base substrate with the substrate layer of the base substrate between the backside metal and the transistor; A semiconductor device, wherein a first segment of the second plurality of segments is electrically connected to a first contact of the plurality of contacts.

27. 27. The semiconductor device of claim 26, wherein the back metal layer, the front metal layer, and the first metal material in each of the vias are part of an inductive element.

28. a substrate layer including a semiconductor or insulating material, the substrate layer having a front surface and a back surface opposite the front surface; a surface metal layer patterned to form a first plurality of segments on the surface of the substrate layer; A base substrate including: a semiconductor or insulator layer; a first metal layer on the semiconductor layer; wherein the first metal layer is patterned to form a second plurality of segments; Including, each segment of the first plurality of segments is connected to at least one segment of the second plurality of segments by a bonding material; The surface metal layer, the first metal layer, and the bonding material are part of an inductive element.

29. 1. A method of forming a semiconductor device, comprising: A base substrate is prepared, the base substrate having a substrate layer including a semiconductor or insulating material, the substrate layer having a front surface and a back surface opposite the front surface; a first plurality of vias each extending through a thickness of the substrate layer; a first metallic material within each via of the first plurality of vias; a backside metal material covering the backside surface of the substrate layer and in contact with the first metal material in each via of the first plurality of vias; an interconnect metal on the surface of the substrate layer; and A transistor is connected to the base substrate, the transistor being a III-N barrier layer; and a III-N channel layer on an N-face of the III-N barrier layer, the III-N barrier layer having a larger bandgap than the III-N channel layer; and a 2DEG channel in the III-N channel layer adjacent an interface between the III-N channel layer and the III-N barrier layer; a plurality of contacts, the plurality of contacts including a source contact, a drain contact, and a gate contact, the source contact, the gate contact, and the drain contact being on an opposite side of the III-N channel layer from the III-N barrier layer, the source contact and the drain contact being electrically connected to the 2DEG channel; Including Including, after connecting the transistor to the base substrate, the transistor is on a front surface of the base substrate with the substrate layer of the base substrate between the backside metal and the transistor; A method, wherein a first end of an impedance element is electrically connected to a first contact of the plurality of contacts and a second end of the impedance element is electrically connected to the first metallic material.

30. 1. A method of forming a semiconductor device, comprising: A base substrate is prepared, the base substrate having a substrate layer including a semiconductor or insulating material, the substrate layer having a front surface and a back surface opposite the front surface; a first plurality of vias each extending through a thickness of the substrate layer; a first metallic material within each via of the first plurality of vias; a backside metal material covering the backside surface of the substrate layer and in contact with the first metal material in each via of the first plurality of vias; an interconnect metal on the surface of the substrate layer; Including, A transistor is connected to the base substrate, the transistor being a III-N barrier layer; and a III-N channel layer on an N-face of the III-N barrier layer, the III-N barrier layer having a larger bandgap than the III-N channel layer; and a 2DEG channel in the III-N channel layer adjacent an interface between the III-N channel layer and the III-N barrier layer; a plurality of contacts, the plurality of contacts including a source contact, a drain contact, and a gate contact, the source contact, the gate contact, and the drain contact being on an opposite side of the III-N channel layer from the III-N barrier layer, the source contact and the drain contact being electrically connected to the 2DEG channel; Including, the transistor is on the front surface of the base substrate with the substrate layer of the base substrate between the backside metal and the transistor after connecting the transistor to a base substrate, and the first metal material in a first via of the first plurality of vias is electrically connected to a first contact of the plurality of contacts by one or more bonding materials.

31. the source contact comprises a plurality of source fingers; prior to connecting the transistor to the base substrate, the source fingers are electrically isolated from one another; The method according to any one of claims 29 to 30, wherein after connecting the transistor to the base substrate, the source fingers are electrically connected to each other.

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