Stacked FETs with non-shared work function metals

Abstract

A semiconductor structure is provided that includes a first FET device stacked on a second FET device, the first FET device including a first functional gate structure including a first work function metal and the second FET device including a second functional gate structure including a second work function metal. In the structure, the first work function metal is absent in areas including the second work function metal and vice versa. Thus, there is no shared work function metal in the semiconductor structure.

Description

[Technical field]

[0001] This application relates to semiconductor technology, and more particularly to stacked field effect transistors (FETs) and methods of forming same. [Background technology]

[0002] A stacked FET involves a first FET device stacked vertically on top of a second FET device. Although stacking allows for miniaturized devices, it is very difficult to achieve independent gates for stacked devices. Summary of the Invention

[0003] A semiconductor structure is provided that includes a first FET device stacked on a second FET device, the first FET device including a first functional gate structure including a first work function metal and the second FET device including a second functional gate structure including a second work function metal. In the structure, the first work function metal is absent in areas including the second work function metal and vice versa. Thus, there is no shared work function metal in the semiconductor structure.

[0004] In one aspect of the present application, a semiconductor structure is provided. In one embodiment, the semiconductor structure includes a first FET device stacked on a second FET device, the first FET device includes a first functional gate structure including a first work function metal, and the second FET device includes a second functional gate structure including a second work function metal. A stacked device isolation dielectric material layer is located between the first FET device and the second FET device. A first gate cut dielectric structure is located laterally adjacent to the first FET device, and a second gate cut dielectric structure is located laterally adjacent to the second FET device. In the present application, a portion of the first gate cut dielectric structure passes through an opening in the stacked device isolation dielectric material layer and is laterally adjacent to the second FET device.

[0005] In an embodiment, the portion of the first gate cut dielectric structure that penetrates the opening has an expanded width compared to the width of the remaining portion of the first gate cut dielectric structure that does not penetrate the opening and is laterally adjacent to the first FET device. This expanded width ensures that the first FET device and the second FET device do not include a shared workfunction metal. In an embodiment, the portion of the first gate cut dielectric structure that penetrates the opening directly contacts a surface of the second gate cut dielectric structure.

[0006] In an embodiment, the first FET device comprises at least one semiconducting nanosheet and the second FET device comprises at least one semiconducting fin, in other embodiments, the first FET device comprises at least one semiconducting nanosheet and the second FET device comprises at least one semiconducting nanosheet.

[0007] In an embodiment, another first FET device is located laterally adjacent to the first FET device and separated by a first gate cut dielectric structure, the another first FET device including a third functional gate structure having a third work function metal. In an embodiment, another second FET device is located laterally adjacent to the second FET device and separated by a second gate cut dielectric structure and a portion of the first gate cut dielectric structure that passes through the opening, the another second FET device including a fourth functional gate structure having a fourth work function metal. The third and fourth work function metals are not shared by different device regions.

[0008] In an embodiment, the first gate cut dielectric structure contacts a first surface of a first conductive-contact-containing interlayer dielectric (ILD) material layer, the first conductive-contact-containing ILD material layer including a first source / drain contact structure contacting a source / drain region of the first FET device. In an embodiment, a backside power delivery network is located on a second surface of the first conductive-contact-containing ILD material layer opposite the first surface of the first conductive-contact-containing ILD material layer.

[0009] In an embodiment, the second gate-cut dielectric structure contacts a first surface of a second conductive-contact-containing ILD material layer, the second conductive-contact-containing ILD material layer including a second source / drain contact structure contacting a source / drain region of the second FET device, a second gate contact structure contacting the second functional gate structure, a shared gate contact structure contacting both the first functional gate structure and the second functional gate structure, and a second gate contact structure contacting the first functional gate structure but not the second functional gate structure.

[0010] In an embodiment, the back-end-of-the-line structure is located on a second surface of the second conductive-contact-containing ILD material layer opposite the first surface of the second conductive-contact-containing ILD material layer.

[0011] In an embodiment, the stacked device isolation dielectric material layer is laterally adjacent to a dielectric isolation layer located between the first and second FET devices. In an embodiment, the dielectric isolation layer is separated from the spacer dielectric material by a sacrificial dielectric liner portion. In an embodiment, another dielectric isolation layer is positioned above the first FET device.

[0012] In an embodiment, a first source / drain region of a first FET device is separated from a second source / drain region of a second FET device by an inner spacer dielectric material and a dielectric material structure.

[0013] In addition to providing a semiconductor structure, the present application also provides a method for forming the same, which will become more apparent in the drawings and detailed discussion section hereinafter. [Brief description of the drawings]

[0014] [Figure 1]FIG. 1 illustrates a layout including a pair of spaced apart active device regions with a gate structure disposed vertically and present in each of the active device regions, with cut lines XX (which is a cross section through one of the active device regions), Y1-Y1 (which is a cross section through the gate structure), and Y2-Y2 (which is a cross section through the source / drain regions) shown in FIG. [Figure 2A] FIG. 2 is a cross-sectional view taken along line XX of an exemplary structure that can be employed in the present application, the exemplary structure including a pair of spaced apart nanosheet material stacks located on a surface of a dielectric material layer present on a surface of a semiconductor substrate, each nanosheet material stack including a sacrificial semiconductor material layer and a semiconductor channel material layer stacked one on top of the other. [Figure 2B] FIG. 2 is a cross-sectional view taken along line Y1-Y1 of the exemplary structure. [Figure 2C] FIG. 2 is a cross-sectional view taken along line Y2-Y2 of the exemplary structure. [Figure 3A] FIG. 2B is a cross-sectional view of the exemplary structure shown in FIG. 2A after forming a first sacrificial gate structure, a first dielectric spacer, patterning each nanosheet material stack using the first sacrificial gate structure and second dielectric spacer as an etch mask to provide a nanosheet stack of alternating sacrificial semiconductor material nanosheets and semiconducting channel material nanosheets, recessing each sacrificial semiconductor material nanosheet, forming internal spacers in gaps created by the recesses, forming first source / drain regions, and forming a first interlayer dielectric (ILD) material layer. [Figure 3B] FIG. 2C is a cross-sectional view of the example structure shown in FIG. 2B after the above formation. [Figure 3C] FIG. 2D is a cross-sectional view of the example structure shown in FIG. 2C after the above formation. [Figure 4A] 3B is a cross-sectional view of the example structure shown in FIG. 3A after bonding the upper semiconducting channel layer using a dielectric-to-dielectric bonding process. [Figure 4B] FIG. 3C is a cross-sectional view of the example structure shown in FIG. 3B after bonding. [Figure 4C] FIG. 3D is a cross-sectional view of the example structure shown in FIG. 3C after bonding. [Figure 5A] FIG. 4B is a cross-sectional view of the exemplary structure shown in FIG. 4A after patterning the semiconducting channel material layer to form a semiconducting fin on each nanosheet stack of alternating sacrificial semiconductor material nanosheets and semiconducting channel material nanosheets. [Figure 5B] FIG. 4C is a cross-sectional view of the example structure shown in FIG. 4B after the above formation. [Figure 5C] FIG. 4D is a cross-sectional view of the example structure shown in FIG. 4C after the above formation. [Figure 6A] FIG. 5B is a cross-sectional view of the example structure shown in FIG. 5A after forming a second sacrificial gate structure and a second dielectric spacer on a portion of each semiconductor fin, forming second source / drain regions, and forming a second ILD material layer. [Figure 6B] FIG. 5C is a cross-sectional view of the example structure shown in FIG. 5B after the above formation. [Figure 6C] FIG. 5D is a cross-sectional view of the example structure shown in FIG. 5C after the above formation. [Figure 7A] FIG. 6B is a cross-sectional view of the exemplary structure shown in FIG. 6A after forming an opening that passes entirely through the second sacrificial gate structure and the stacked device isolation dielectric material layer and partially into the first sacrificial gate structure. [Figure 7B] FIG. 6C is a cross-sectional view of the example structure shown in FIG. 6B after the above formation. [Figure 7C] FIG. 6D is a cross-sectional view of the example structure shown in FIG. 6C after the above formation. [Figure 8A] FIG. 7B is a cross-sectional view of the example structure shown in FIG. 7A after removing the first sacrificial gate structure and the second sacrificial gate structure, exposing each semiconductor fin by removing the second sacrificial gate structure, exposing each sacrificial semiconductor material nano-sheet by removing the first sacrificial gate structure, and then removing the exposed sacrificial semiconductor material nano-sheet. [Figure 8B] FIG. 7C is a cross-sectional view of the example structure shown in FIG. 7B after the above removal. [Figure 8C] FIG. 7D is a cross-sectional view of the example structure shown in FIG. 7C after the removal. [Figure 9A]FIG. 8B is a cross-sectional view of the exemplary structure shown in FIG. 8A after forming a high-k dielectric material layer on the physically exposed surfaces of each semiconductor fin and each semiconductor channel material nanosheet, followed by forming an amorphous silicon (a-Si) layer. [Figure 9B] FIG. 8C is a cross-sectional view of the example structure shown in FIG. 8B after the above formation. [Figure 9C] FIG. 8D is a cross-sectional view of the example structure shown in FIG. 8C after the above formation. [Figure 10A] FIG. 9B is a cross-sectional view of the example structure shown in FIG. 9A after forming a gate kerf (CT) generally through the a-Si layer and partially into a portion of the dielectric material layer. [Figure 10B] FIG. 9C is a cross-sectional view of the example structure shown in FIG. 9B after the above formation. [Figure 10C] FIG. 9D is a cross-sectional view of the example structure shown in FIG. 9C after the above formation. [Figure 11A] FIG. 10B is a cross-sectional view of the example structure shown in FIG. 10A after forming a protective material in a lower portion of the gate cut groove, the protective material having a top surface located between the top and bottom surfaces of the stacked device isolation dielectric material layers. [Figure 11B] FIG. 10C is a cross-sectional view of the exemplary structure shown in FIG. 10B after the above formation. [Figure 11C] FIG. 10D is a cross-sectional view of the example structure shown in FIG. 10C after the above formation. [Figure 12A] FIG. 11B is a cross-sectional view of the example structure shown in FIG. 11A after trimming the a-Si layer located along the sidewalls of an upper portion of the gate kerf groove to increase the width of the upper portion of the gate kerf groove relative to the lower portion of the gate kerf groove. [Figure 12B] FIG. 11C is a cross-sectional view of the example structure shown in FIG. 11B after the hemming. [Figure 12C] FIG. 11D is a cross-sectional view of the example structure shown in FIG. 11C after the hemming. [Figure 13A]FIG. 12B is a cross-sectional view of the example structure shown in FIG. 12A after removing protective material from a lower portion of the gate kerf to expose a modified gate kerf having a first portion having the width of the original gate kerf and a second portion having an increased width. [Figure 13B] FIG. 12C is a cross-sectional view of the example structure shown in FIG. 12B after the above exposure. [Figure 13C] FIG. 12D is a cross-sectional view of the example structure shown in FIG. 12C after the above exposure. [Figure 14A] FIG. 13B is a cross-sectional view of the example structure shown in FIG. 13A after a first gate cut dielectric structure has been formed in a first portion of the modified gate cut groove and partially into a second portion of the modified gate groove. [Figure 14B] FIG. 13C is a cross-sectional view of the example structure shown in FIG. 13B after the above formation. [Figure 14C] FIG. 13D is a cross-sectional view of the example structure shown in FIG. 13C after the above formation. [Figure 15A] FIG. 14B is a cross-sectional view of the example structure shown in FIG. 14A after forming additional a-Si on top of the first gate cut dielectric structure to completely fill the remaining second portion of the modified gate cut trench. [Figure 15B] FIG. 14C is a cross-sectional view of the example structure shown in FIG. 14B after forming and filling. [Figure 15C] FIG. 14D is a cross-sectional view of the example structure shown in FIG. 14C after forming and filling. [Figure 16A] FIG. 15B is a cross-sectional view of the example structure shown in FIG. 15A after a second gate cut dielectric structure is formed in the a-Si layer and contacts a surface of the first gate cut dielectric structure. [Figure 16B] FIG. 15C is a cross-sectional view of the exemplary structure shown in FIG. 15B after forming and contacting. [Figure 16C] FIG. 15D is a cross-sectional view of the exemplary structure shown in FIG. 15C after forming and contacting. [Figure 17A] FIG. 16B is a cross-sectional view of the example structure shown in FIG. 16A after removing a top portion of the a-Si layer to expose high-k gate dielectric material located on each semiconductor fin. [Figure 17B]FIG. 16C is a cross-sectional view of the example structure shown in FIG. 16B after the above removal and exposure. [Figure 17C] FIG. 16D is a cross-sectional view of the example structure shown in FIG. 16C after the above removal and exposure. [Figure 18A] FIG. 17B is a cross-sectional view of the exemplary structure shown in FIG. 17A after forming a second gate electrode on the physically exposed surface of the high-k gate dielectric material layer located on the first set of semiconductor fins and forming another second gate electrode on the physically exposed surface of the high-k gate dielectric material layer located on the second set of semiconductor fins, the first and second sets of semiconductor fins being separated by a second gate cut dielectric structure and an enlarged width portion of the first gate cut dielectric structure that penetrates an opening present in the stacked device isolation dielectric material layer. [Figure 18B] FIG. 17C is a cross-sectional view of the exemplary structure shown in FIG. 17B after the above formation. [Figure 18C] FIG. 17D is a cross-sectional view of the example structure shown in FIG. 17C after the above formation. [Figure 19A] FIG. 18B is a cross-sectional view of the example structure shown in FIG. 18A after forming a second conductive-contact-containing ILD material layer, the second conductive-contact-containing ILD material layer including a second source / drain contact structure contacting the second source / drain region, a second gate contact structure contacting the second gate electrode, a first gate contact structure, a shared gate contact structure, and a first source / drain contact structure having a dielectric cap embedded therein. [Figure 19B] FIG. 18C is a cross-sectional view of the exemplary structure shown in FIG. 18B after the above formation. [Figure 19C] FIG. 18D is a cross-sectional view of the example structure shown in FIG. 18C after the above formation. [Figure 20A] 19B is a cross-sectional view of the example structure shown in FIG. 19A after forming back-end-of-the-line (BEOL) structures and a carrier wafer on the second conductive-contact-containing ILD material layer. [Figure 20B] FIG. 19C is a cross-sectional view of the example structure shown in FIG. 19B after the above formation. [Figure 20C]FIG. 19D is a cross-sectional view of the exemplary structure shown in FIG. 19C after the above formation. [Figure 21A] 20B is a cross-sectional view of the example structure shown in FIG. 20A after flipping the example structure 180 degrees, removing the semiconductor substrate, removing the dielectric material layer, and removing the physically exposed portions of the high-k gate dielectric material previously located on the dielectric material layer. [Figure 21B] FIG. 20C is a cross-sectional view of the example structure shown in FIG. 20B after the above removal. [Figure 21C] FIG. 20D is a cross-sectional view of the example structure shown in FIG. 20C after the above removal. [Figure 22A] FIG. 21B is a cross-sectional view of the example structure shown in FIG. 21A after removing the physically exposed portion of the a-Si layer. [Figure 22B] FIG. 21C is a cross-sectional view of the example structure shown in FIG. 21B after the above removal. [Figure 22C] FIG. 21D is a cross-sectional view of the example structure shown in FIG. 21C after the above removal. [Figure 23A] FIG. 22B is a cross-sectional view of the exemplary structure shown in FIG. 22A after forming a first gate electrode on a physically exposed surface of the high-k gate dielectric material layer located on a first set of suspended semiconducting channel material nanosheets and forming another first gate electrode on a physically exposed surface of the high-k gate dielectric material layer located on a second set of suspended semiconducting channel material nanosheets. [Figure 23B] 22C is a cross-sectional view of the exemplary structure shown in FIG. 22B after the above formation. [Figure 23C] 22D is a cross-sectional view of the example structure shown in FIG. 22C after being formed as described above. [Figure 24A] FIG. 23B is a cross-sectional view of the example structure shown in FIG. 23A after forming a first conductive-contact-containing ILD material layer, the first conductive-contact-containing ILD material layer including a first source / drain contact structure contacting the first source / drain region. [Figure 24B] FIG. 23C is a cross-sectional view of the exemplary structure shown in FIG. 23B after the above formation. [Figure 24C]FIG. 23D is a cross-sectional view of the example structure shown in FIG. 23C after the above formation. [Figure 25A] 24B is a cross-sectional view of the example structure shown in FIG. 24A after forming a backside power distribution network (BSPDN) structure on the first conductive-contact-containing ILD material layer. [Figure 25B] FIG. 24C is a cross-sectional view of the exemplary structure shown in FIG. 24B after the above formation. [Figure 25C] FIG. 24D is a cross-sectional view of the example structure shown in FIG. 24C after the above formation. [Figure 26A] FIG. 2 is a cross-sectional view of an exemplary structure taken through XX shown in FIG. 1 that can be employed in another embodiment of the present application, the exemplary structure including a semiconductor substrate, a dielectric material layer, a first sacrificial semiconductor material layer, a first nanosheet material stack, a second sacrificial semiconductor material layer, and a second nanosheet material stack, each nanosheet material stack including alternating sacrificial semiconductor material layers and semiconductor channel material layers. [Figure 26B] 2 is a cross-sectional view of an example structure taken along line Y1-Y1 of FIG. 1. [Figure 27A] FIG. 26B is a cross-sectional view of the example structure shown in FIG. 26A after first patterning a first sacrificial semiconductor material layer, a first nanosheet material stack, a second sacrificial semiconductor material layer, and a second nanosheet material stack to provide a patterned structure. [Figure 27B] FIG. 26C is a cross-sectional view of the exemplary structure shown in FIG. 26B after providing the above patterned structure. [Figure 28A] 27B is a cross-sectional view of the example structure shown in FIG. 27A after a dielectric liner has been formed along the sidewalls of the patterned structure and a dielectric fill material has been formed laterally adjacent to the dielectric liner. [Figure 28B] FIG. 27C is a cross-sectional view of the example structure shown in FIG. 27B after the above formation. [Figure 29A] 28B is a cross-sectional view of the exemplary structure shown in FIG. 28A after patterning the patterned structure to provide a pair of patterned vertically stacked structures. [Figure 29B] FIG. 28C is a cross-sectional view of the example structure shown in FIG. 28B after providing the above structure. [Figure 30A] 29B is a cross-sectional view of the example structure shown in FIG. 29A after removing remaining portions of the first and second sacrificial semiconductor material layers from each patterned vertically stacked structure. [Figure 30B] FIG. 29C is a cross-sectional view of the example structure shown in FIG. 29B after the above removal. [Figure 31A] 30B is a cross-sectional view of the example structure shown in FIG. 30A after forming a dielectric material within a volume that previously contained remaining portions of the first and second sacrificial semiconductor material layers. [Figure 31B] FIG. 30C is a cross-sectional view of the exemplary structure shown in FIG. 30B after the above formation. [Figure 32A] FIG. 31B is a cross-sectional view of the example structure shown in FIG. 31A after removing the dielectric fill material and the dielectric liner. [Figure 32B] FIG. 31C is a cross-sectional view of the example structure shown in FIG. 31B after the above removal. [Figure 33A] FIG. 32B is a cross-sectional view of the example structure shown in FIG. 32A after forming a sacrificial dielectric liner. [Figure 33B] FIG. 32C is a cross-sectional view of the example structure shown in FIG. 32B after the above formation. [Figure 34A] FIG. 33B is a cross-sectional view of the example structure shown in FIG. 33A after forming a first sacrificial gate material. [Figure 34B] FIG. 33C is a cross-sectional view of the exemplary structure shown in FIG. 33B after the above formation. [Figure 35A] FIG. 34B is a cross-sectional view of the exemplary structure shown in FIG. 34A after recessing the first sacrificial gate material. [Figure 35B] FIG. 34C is a cross-sectional view of the exemplary structure shown in FIG. 34B after providing the recesses. [Figure 36A] FIG. 35B is a cross-sectional view of the example structure shown in FIG. 35A after forming a sacrificial material over the recessed sacrificial gate material. [Figure 36B] FIG. 35C is a cross-sectional view of the exemplary structure shown in FIG. 35B after the above formation. [Figure 37A] FIG. 36B is a cross-sectional view of the example structure shown in FIG. 36A after forming a second sacrificial gate material and a hard mask layer. [Figure 37B] FIG. 36C is a cross-sectional view of the exemplary structure shown in FIG. 36B after the above formation. [Figure 38A] FIG. 37B is a cross-sectional view of the example structure shown in FIG. 37A after patterning the hard mask layer, the second sacrificial gate material, the sacrificial dielectric liner, the sacrificial material, and the sacrificial first gate material to provide at least one sacrificial gate structure topped by remaining portions of the hard mask layer. [Figure 38B] FIG. 37C is a cross-sectional view of the example structure shown in FIG. 37B after providing the above structure. [Figure 38C] 38A and 38B and is a cross-sectional view of the example structure taken through cut line Y2-Y2 shown in FIG. 1. [Figure 39A] A cross-sectional view of the exemplary structure shown in Figure 38A after removing remaining portions of the sacrificial material to form a gap laterally adjacent to the second dielectric insulating layer and between the remaining portions of the first and second sacrificial gate materials. [Figure 39B] FIG. 38C is a cross-sectional view of the exemplary structure shown in FIG. 38B after the above formation. [Figure 39C] FIG. 38D is a cross-sectional view of the exemplary structure shown in FIG. 38C after the above formation. [Figure 40A] A cross-sectional view of the exemplary structure shown in FIG. 39A after forming a dielectric spacer along the sidewall of each sacrificial structure and, during the formation of the dielectric spacers, filling the gaps with dielectric spacer material to provide a layer of spacer dielectric material between remaining portions of the first and second sacrificial gate materials. [Figure 40B] FIG. 39C is a cross-sectional view of the exemplary structure shown in FIG. 39B after providing the above layers. [Figure 40C] FIG. 39D is a cross-sectional view of the exemplary structure shown in FIG. 39C after providing the above layers. [Figure 41A]FIG. 40B is a cross-sectional view of the exemplary structure shown in FIG. 40A after patterning each patterned vertical stack structure utilizing the at least one hard mask-topped sacrificial gate structure and the dielectric spacer as a combination etch mask to provide a vertical nanosheet stack structure including at least a first nanosheet stack and a second nanosheet stack, each of the first and second nanosheet stacks including alternating stacked sacrificial semiconductor material nanosheets and semiconducting channel material nanosheets, recessing and providing gaps in each sacrificial semiconductor material nanosheet of the first and second nanosheet stacks, filling each gap, and forming an internal spacer dielectric material along the sidewalls of each vertical nanosheet stack structure and along the sidewalls of the at least one hard mask-topped sacrificial gate structure. [Figure 41B] FIG. 40C is a cross-sectional view of the exemplary structure shown in FIG. 40B after the above formation. [Figure 41C] FIG. 40D is a cross-sectional view of the exemplary structure shown in FIG. 40C after the above formation. [Figure 42A] A cross-sectional view of the exemplary structure shown in Figure 41A after forming a dielectric material structure in the gaps located between each vertical nanosheet stack structure and below the internal spacer dielectric material present along the sidewalls of each vertical nanosheet. [Figure 42B] FIG. 41C is a cross-sectional view of the exemplary structure shown in FIG. 41B after the above formation. [Figure 42C] FIG. 41D is a cross-sectional view of the exemplary structure shown in FIG. 41C after the above formation. [Figure 43A] A cross-sectional view of the exemplary structure shown in Figure 42A after removing an upper portion of the internal spacer dielectric material present along the sidewall of the second nanosheet stack, forming a second source / drain region on the dielectric material structure and adjacent to the second nanosheet stack, and forming a second ILD material layer on the second source / drain region. [Figure 43B] FIG. 42C is a cross-sectional view of the example structure shown in FIG. 42B after the above formation. [Figure 43C] FIG. 42D is a cross-sectional view of the example structure shown in FIG. 42C after the above formation. [Figure 44A] A cross-sectional view of the exemplary structure shown in Figure 43A after forming an opening generally through the remaining portion of the second sacrificial gate material and the layer of spacer dielectric material into a portion of the remaining first sacrificial gate material. [Figure 44B] FIG. 43C is a cross-sectional view of the exemplary structure shown in FIG. 43B after the above formation. [Figure 44C] FIG. 43D is a cross-sectional view of the exemplary structure shown in FIG. 43C after the above formation. [Figure 45A] A cross-sectional view of the exemplary structure shown in Figure 44A after removing remaining portions of the first and second sacrificial gate materials, physically exposed portions of the sacrificial dielectric liner, and each recessed sacrificial semiconductor nanosheet of the first and second nanosheet stacks to provide suspended nanosheets of semiconductor channel material within the first and second nanosheet stacks. [Figure 45B] FIG. 44C is a cross-sectional view of the exemplary structure shown in FIG. 44B after providing the nanosheets. [Figure 45C] FIG. 44D is a cross-sectional view of the exemplary structure shown in FIG. 44C after providing the nanosheets. [Figure 46A] FIG. 45B is a cross-sectional view of the example structure shown in FIG. 45A after forming a high-k gate dielectric material and an a-Si layer. [Figure 46B] FIG. 45C is a cross-sectional view of the exemplary structure shown in FIG. 45B after the above formation. [Figure 46C] FIG. 45D is a cross-sectional view of the exemplary structure shown in FIG. 45C after the above formation. [Figure 47A] FIG. 46B is a cross-sectional view of the example structure shown in FIG. 46A after a first gate cut dielectric structure is formed in a first portion of the modified gate cut groove and partially formed into a second portion of the modified gate cut groove. [Figure 47B] FIG. 46C is a cross-sectional view of the exemplary structure shown in FIG. 46B after the above formation. [Figure 47C] FIG. 46D is a cross-sectional view of the exemplary structure shown in FIG. 46C after the above formation. [Figure 48A]FIG. 47B is a cross-sectional view of the example structure shown in FIG. 47A after additional a-Si is formed over the first gate cut dielectric structure to fill the remaining volume of the modified gate cut trench. [Figure 48B] FIG. 47C is a cross-sectional view of the example structure shown in FIG. 47B after filling. [Figure 48C] FIG. 47D is a cross-sectional view of the example structure shown in FIG. 47C after filling. [Figure 49A] FIG. 48B is a cross-sectional view of the example structure shown in FIG. 48A after forming a second gate cut dielectric structure on the first gate cut dielectric structure. [Figure 49B] FIG. 48C is a cross-sectional view of the exemplary structure shown in FIG. 48B after the above formation. [Figure 49C] FIG. 48D is a cross-sectional view of the exemplary structure shown in FIG. 48C after the above formation. [Figure 50A] FIG. 49B is a cross-sectional view of the example structure shown in FIG. 49A after removing an upper portion of the a-Si layer located above the spacer dielectric material layer to provide a gate cavity. [Figure 50B] FIG. 49C is a cross-sectional view of the example structure shown in FIG. 49B after providing the cavity. [Figure 50C] FIG. 49D is a cross-sectional view of the example structure shown in FIG. 49C after providing the cavity. [Figure 51A] FIG. 50B is a cross-sectional view of the exemplary structure shown in FIG. 50A after forming a second gate electrode on the physically exposed surface of the high-k gate dielectric material layer located on a first set of suspended semiconducting channel material nanosheets of the second nanosheet stack and forming another second gate electrode on the physically exposed surface of the high-k gate dielectric material layer located on a second set of suspended semiconducting channel material nanosheets of another second nanosheet stack, the device regions being separated by an enlarged portion of the first gate cut dielectric structure that penetrates the second gate cut dielectric structure and an opening in the spacer dielectric material. [Figure 51B] FIG. 50C is a cross-sectional view of the exemplary structure shown in FIG. 50B after the above formation. [Figure 51C] FIG. 50D is a cross-sectional view of the exemplary structure shown in FIG. 50C after the above formation. [Figure 52A] FIG. 51B is a cross-sectional view of the exemplary structure shown in FIG. 51A after forming a second conductive-contact-containing ILD material layer, the second conductive-contact-containing ILD material layer including a second source / drain contact structure contacting the second source / drain region, a second gate contact structure contacting the second gate electrode, the first gate contact structure, and a shared gate contact structure embedded therein. [Figure 52B] FIG. 51C is a cross-sectional view of the exemplary structure shown in FIG. 51B after the above formation. [Figure 52C] FIG. 51D is a cross-sectional view of the exemplary structure shown in FIG. 51C after the above formation. [Figure 53A] FIG. 52B is a cross-sectional view of the example structure shown in FIG. 52A after forming back-end-of-the-line (BEOL) structures and a carrier wafer on the second conductive-contact-containing ILD material layer. [Figure 53B] FIG. 52C is a cross-sectional view of the exemplary structure shown in FIG. 52B after the above formation. [Figure 53C] FIG. 52D is a cross-sectional view of the example structure shown in FIG. 52C after the above formation. [Figure 54A] FIG. 53B is a cross-sectional view of the example structure shown in FIG. 53A after flipping the example structure 180°, removing the semiconductor substrate, removing the dielectric material layer, and removing the physically exposed portions of the high dielectric constant dielectric material layer that are located in the remaining portions of the a-Si layer. [Figure 54B] FIG. 53C is a cross-sectional view of the example structure shown in FIG. 53B after the above removal. [Fig. 54C] FIG. 53D is a cross-sectional view of the example structure shown in FIG. 53C after the above removal. [Figure 55A] FIG. 54B is a cross-sectional view of the example structure shown in FIG. 54A after removing the a-Si layer. [Figure 55B] FIG. 54C is a cross-sectional view of the example structure shown in FIG. 54B after the above removal. [Figure 55C] FIG. 54D is a cross-sectional view of the example structure shown in FIG. 54C after the above removal. [Figure 56A]FIG. 55B is a cross-sectional view of the exemplary structure shown in FIG. 55A after forming a first gate electrode on a physically exposed surface of a high-k gate dielectric material layer located on a first set of suspended semiconducting channel material nanosheets of a first nanosheet stack and forming another first gate electrode on a physically exposed surface of a high-k gate dielectric material layer located on a second set of suspended semiconducting channel material nanosheets of another first nanosheet stack, the device regions being separated by a first gate cut dielectric structure. [Figure 56B] FIG. 55C is a cross-sectional view of the exemplary structure shown in FIG. 55B after the above formation. [Figure 56C] FIG. 55D is a cross-sectional view of the exemplary structure shown in FIG. 55C after the above formation. [Figure 57A] FIG. 56B is a cross-sectional view of the example structure shown in FIG. 56A after forming a back gate dielectric cap layer. [Figure 57B] FIG. 56C is a cross-sectional view of the exemplary structure shown in FIG. 56B after the above formation. [Figure 57C] FIG. 56D is a cross-sectional view of the exemplary structure shown in FIG. 56C after the above formation. [Figure 58A] FIG. 57B is a cross-sectional view of the exemplary structure shown in FIG. 57A after providing a recess in the dielectric material structure. [Figure 58B] FIG. 57C is a cross-sectional view of the exemplary structure shown in FIG. 57B after providing the recesses. [Figure 58C] FIG. 57D is a cross-sectional view of the exemplary structure shown in FIG. 57C after providing the recesses. [Figure 59A] FIG. 58B is a cross-sectional view of the example structure shown in FIG. 58A after forming first source / drain regions. [Figure 59B] FIG. 58C is a cross-sectional view of the exemplary structure shown in FIG. 58B after the above formation. [Figure 59C] FIG. 58D is a cross-sectional view of the exemplary structure shown in FIG. 58C after the above formation. [Figure 60A]FIG. 59B is a cross-sectional view of the example structure shown in FIG. 59A after forming a first conductive-contact-containing ILD material layer, the first conductive-contact-containing ILD material layer including a first source / drain contact structure contacting the first source / drain region. [Figure 60B] FIG. 59C is a cross-sectional view of the exemplary structure shown in FIG. 59B after the above formation. [Figure 60C] FIG. 59D is a cross-sectional view of the exemplary structure shown in FIG. 59C after the above formation. [Figure 61A] FIG. 60B is a cross-sectional view of the example structure shown in FIG. 60A after forming backside interconnect and backside power distribution network (BSPDN) structures on the first conductive-contact-containing ILD material layer. [Figure 61B] FIG. 60C is a cross-sectional view of the exemplary structure shown in FIG. 60B after the above formation. [Figure 61C] FIG. 60D is a cross-sectional view of the exemplary structure shown in FIG. 60C after the above formation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The present application will now be described in more detail with reference to the following discussion and drawings that accompany this application. It should be noted that the drawings in this application are provided for illustrative purposes only, and therefore the drawings are not drawn to scale. It should also be noted that like and corresponding elements are referred to by like reference numerals.

[0016] In the following description, numerous specific details are set forth, such as specific structures, components, materials, dimensions, processing steps, techniques, etc., in order to understand various embodiments of the present application. However, those skilled in the art will understand that various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps are not described in detail to avoid obscuring the present application.

[0017] When an element is referred to as being "on" or "on" another element, as a layer, region, or substrate, it will be understood that it may be directly on the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly on" another element, there are no intervening elements. Also, when an element is referred to as being "under" or "below" another element, it will be understood that it may be below or directly below the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly under" or "directly under" another element, there are no intervening elements. It should be noted that terms such as "first," "second," "third," "fourth," etc. are used throughout this application as a way of identifying similar elements, e.g., a first FET device and a second FET device, and do not imply an order in which those similar elements are formed.

[0018] Referring initially to FIG. 1, a diagram is provided illustrating a layout including a pair of spaced apart active device regions RX1 and RX2 with a gate structure GS perpendicular to each of the active device regions, which will be used in the present application in describing the exemplary structures of the present application. The layout includes a cut line XX that is a cross section through one of the active device regions (i.e., the first active device region RX1), a cut line Y1-Y1 that is a cross section through the gate structure GS, and a cut line Y2-Y2 that is a cross section through the source / drain regions. In the present application, the active device regions, e.g., RX1 and RX2, include stacked semiconductor devices (i.e., stacked FETs) that include semiconductor channel material structures including, for example, semiconductor nanosheets, semiconductor fins, semiconductor nanowires, or any combination thereof. In one example, the stacked FETs of the present application include a nanosheet FET device stacked with a semiconductor finFET (or simply finFET) device. Such stacked FETs are illustrated in FIGS. 2A-26C. In yet another example, the stacked FETs of the present application include a first nanosheet FET device stacked with a second nanosheet FET device. Such stacked FETs are shown in Figures 27A-61C, in which a first FET device is stacked above a second FET device.

[0019] In each of the exemplary stacked FETs, there is a first FET device stacked above a second FET device, the first FET device including a first functional gate structure including a first work function metal, and the second FET device including a second functional gate structure including a second work function metal that may be different from the first work function metal. Each stacked FET also includes a stacked device isolation dielectric material layer located between the first FET device and the second FET device. The first gate cut dielectric structure is located laterally adjacent to the first FET device, and the second gate cut dielectric structure is located laterally adjacent to the second FET device. In the present application, the first gate cut dielectric structure passes through an opening in the stacked device isolation dielectric material layer and is laterally adjacent to the second FET device. The first gate cut dielectric structure laterally adjacent to the second FET device has an enlarged portion that seals the opening, ensuring that no shared work function metal is used. These and other aspects of the present application will become apparent from the drawings and their detailed description hereinafter.

[0020] First, referring to Figures 2A, 2B and 2C, various views through XX, Y1-Y1 and Y2-Y2, respectively, of an exemplary structure that can be employed in the present application are illustrated. The exemplary structure includes a pair of spaced apart nanosheet material stacks MS located on the surface of a dielectric material layer 102 that is present on the surface of a semiconductor substrate 100. According to the present application, each nanosheet material stack MS is located in a different active device region (e.g., RX1 and RX2 described above in Figure 1) that includes a sacrificial semiconductor material layer 104L and a semiconductor channel material layer 106L stacked one after the other.

[0021] The semiconductor substrate 100 can be composed of at least one semiconductor material having semiconducting properties. Examples of semiconductor materials that can be used in the present application include, but are not limited to, silicon (Si), silicon germanium (SiGe) alloys, silicon germanium carbide (SiGeC) alloys, germanium (Ge), III / V compound semiconductors, II / VI compound semiconductors, or multi-layer stacks including at least two semiconductor materials (e.g., multi-layer stacks of Si and SiGe). In one embodiment (shown in the drawings of the present application), the semiconductor substrate 100 is composed entirely of at least one semiconductor material.

[0022] The dielectric material layer 102 is comprised of any dielectric material having electrical insulating properties. Exemplary dielectric materials that may be employed in providing the dielectric material layer 102 include, but are not limited to, silicon dioxide, silicon nitride, silicon oxynitride, or boron nitride. In some embodiments, the dielectric material layer 102 may be formed on the surface of the semiconductor substrate 100 using a deposition process, such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In yet other embodiments, the dielectric material layer 102 may be formed on the surface of the semiconductor substrate 100 using a thermal process, such as, for example, thermal oxidation and / or thermal nitridation. The dielectric material layer 102 may have a thickness of 5 nm to 50 nm, although other thicknesses are contemplated and may be employed as the thickness of the dielectric material. In some embodiments, the dielectric material layer 102 is a component of an SOI substrate, the semiconductor substrate 100 is a first semiconductor material layer of the SOI substrate, the dielectric material layer 102 is a buried insulating layer of the SOI substrate, and the second semiconductor material layer is thinned and converted to a first sacrificial semiconductor material layer 104L, such as SiGe, by a SiGe condensation process.

[0023] As described above, each nanosheet material stack MS includes alternating sacrificial semiconductor material layers 104L and semiconducting channel material layers 106L. In this embodiment of the present application, the number of semiconductor material layers 104L and semiconducting channel material layers 106L is equal. That is, each nanosheet material stack MS in this embodiment of the present application includes "n" semiconducting channel material layers 106L and "n" sacrificial semiconductor material layers, where n is an integer starting from 1. According to one example, the nanosheet material stack MS includes three sacrificial semiconductor material layers 104L and three semiconducting channel material layers 106L. Each sacrificial semiconductor material 104L is composed of a first semiconductor material, and each semiconducting channel material layer 106L is composed of a second semiconductor material that is compositionally different from the first semiconductor material. In some embodiments, the second semiconductor material that composes each semiconducting channel material layer 106L is a semiconductor material that can provide high channel mobility to an n-type FET device. In another embodiment, the second semiconductor material making up each semiconductor channel material 106L is a semiconductor material capable of providing high channel mobility for a p-type FET device.

[0024] The first semiconductor material constituting each sacrificial semiconductor material layer 104L and the second semiconductor material constituting each semiconductor channel material layer 106L may include one of the semiconductor materials described above for the semiconductor substrate 100. In the present application, the first semiconductor material constituting each sacrificial semiconductor material layer 104L may be compositionally the same as or different from at least the top semiconductor material portion of the semiconductor substrate 100. The second semiconductor material constituting each semiconductor channel material layer 106L may be compositionally the same as or different from at least the top semiconductor material portion of the semiconductor substrate 100. Typically, the second semiconductor material constituting each semiconductor channel material layer 106L is compositionally the same as at least the top semiconductor material portion of the semiconductor substrate 100. In one example, the semiconductor substrate 100 is composed of silicon, the first semiconductor material constituting each sacrificial semiconductor material layer 104L is composed of a silicon germanium alloy, and the second semiconductor material constituting each semiconductor channel material layer 106L is composed of silicon. Other combinations of semiconductor materials are possible so long as the first semiconductor material making up each sacrificial semiconductor material layer 104L is compositionally different from the second semiconductor material making up each semiconductor channel material layer 106L.

[0025] The material stack MS can be formed by growing blanket layers of alternating semiconductor channel material and sacrificial semiconductor material on a first sacrificial semiconductor material. The alternating blanket layers of semiconductor channel material and sacrificial semiconductor material can be deposited using epitaxial growth. The alternating blanket layers of sacrificial semiconductor material and semiconductor channel material are then patterned by lithography and etching to form the nanosheet material stack MS.

[0026] 3A, 3B and 3C, there is illustrated the exemplary structures shown in FIGS. 2A, 2B and 2C, respectively, after forming a first sacrificial gate structure 108, a first dielectric spacer 110, patterning each nanosheet material stack MS using the first sacrificial gate structure 108 and the second dielectric spacer 110 as an etch mask to provide a nanosheet stack NS of alternating sacrificial semiconductor material nanosheets 104 and semiconductor channel material nanosheets 106, recessing each sacrificial semiconductor material nanosheet 104, forming internal spacers 112 in the gaps created by the recessing, forming first source / drain regions 116, and forming a first ILD material layer 118.

[0027] The first sacrificial gate structure 108 includes at least a sacrificial gate material. In some embodiments, the first sacrificial gate structure 108 may include a sacrificial gate dielectric material located below the sacrificial gate material. A sacrificial gate cap may be located above the sacrificial gate material. The first sacrificial gate structure 108 may be formed by depositing blanket layers of a sacrificial gate dielectric material (e.g., silicon dioxide, etc.), a sacrificial gate material (e.g., polysilicon or metal, etc.), and a dielectric hard mask material (e.g., silicon nitride, etc.), with the dielectric hard mask material constituting the sacrificial gate cap. In some embodiments, the deposition of the blanket layers of the sacrificial gate dielectric material and / or dielectric hard mask material may be omitted. The deposition of the blanket layers of the dielectric hard mask material, the sacrificial gate material, and the sacrificial gate dielectric material may include, but is not limited to, CVD, PECVD, PVD, ALD, or any combination of these deposition processes. After forming the sacrificial gate dielectric material, the sacrificial gate material, and the blanket layer of hard mask material, a patterning process (including lithography and etching) is used to convert the blanket layer of hard mask material into a sacrificial gate cap, and to convert the sacrificial gate dielectric material and the blanket layer of sacrificial gate dielectric material into a first sacrificial gate structure 108.

[0028] After forming the first sacrificial gate structure 108, the first dielectric spacer 110 is formed by deposition of a dielectric spacer material followed by etching of the spacer. The dielectric spacer material constituting the first dielectric spacer 110 may include silicon dioxide, silicon nitride, SiBCN, SiOCN, etc. The first dielectric spacer 110 is present along the sidewalls of the first sacrificial gate structure 108 and along the sidewalls of the nanosheet material stack MS. In an embodiment, the first dielectric spacer 110 may be I-shaped and may have a top surface that is coplanar with the top surface of the first sacrificial gate structure 108.

[0029] After forming the first sacrificial gate structure 108 and the first dielectric spacer 110, the nanosheet material stack is patterned. In the patterning step, the first sacrificial gate structure 108 and the first dielectric spacer 110 are used as a combination etch mask to convert the nanosheet material stack MS into a nanosheet stack NS including alternating stacks of sacrificial semiconductor material nanosheets 104 and semiconducting channel material nanosheets 106. Each sacrificial semiconductor material nanosheet 104 and semiconducting channel material nanosheet 106 may have a width of 5 nm to 100 nm and a vertical thickness of 1 nm to 15 nm, which is the same as the deposition thickness of the sacrificial semiconductor material layer 104L and the semiconducting channel material layer 106L. The patterning step includes an etch to remove the physically exposed portions of the nanosheet material stack MS that are not protected by the etch masks while maintaining a portion of the nanosheet material stack MS under each etch mask. The retained portion of the nanosheet material stack MS is a nanosheet stack NS of alternating sacrificial semiconductor material nanosheets 104 (i.e., the remaining portions of each sacrificial semiconductor material layer 104L) and semiconductor channel material nanosheets 106 (the remaining portions of each semiconductor channel material layer 106L). Etching can include a dry etching process, such as reactive ion etching (RIE). The nanosheet stack NS has an outermost wall vertically aligned with the outermost wall of the first dielectric spacer 110. At this point in the application, each sacrificial semiconductor material nanosheet 104 has an outermost wall vertically aligned with the outermost wall of each semiconductor channel material nanosheet 106.

[0030] Next, each sacrificial semiconductor material nanosheet 104 is recessed to form a gap. Each gap is formed above and below one of the semiconductor channel material nanosheets 106. After this recessing step, the remaining (i.e. recessed) sacrificial semiconductor material nanosheet 104 has a reduced width compared to the width of the original sacrificial semiconductor material nanosheet 104. Recessing includes a lateral etching step selected in removing the sacrificial semiconductor material nanosheet 104 relative to the semiconductor channel material nanosheet 106. Next, an internal spacer 112 is formed in each gap created during recessing each sacrificial semiconductor material nanosheet 104. The formation of the internal spacer 112 includes a conformal deposition of another dielectric spacer material, followed by an isotropic etch. The other dielectric spacer material may be compositionally the same or compositionally different from the dielectric spacer material constituting the first dielectric spacer 110. The exposed dielectric material layer 102 may then be subjected to an isotropic etch step to form a recess that also extends below the bottom internal spacer 112. A dielectric material 114 may be deposited and recessed to fill the recesses. The dielectric material 114 is different from the dielectric material layer 102, such as SiC, SiCO, etc.

[0031] The first source / drain regions 116 are of a first conductivity type (i.e., n-type or p-type) and are formed by an epitaxial growth process defined below. The first source / drain regions 116 grow outward from the physically exposed sidewalls of each semiconductor channel material nanosheet 106. A dopant, defined below, is typically present during the epitaxial growth process or during a subsequent implant. A recess etch can be optionally employed to reduce the height of the first source / drain regions 116. The term "epitaxial growth" or "epitaxially growing" refers to the growth of a second semiconductor material on a growth surface of a first semiconductor material, where the second semiconductor material grown has the same crystalline characteristics as the first semiconductor material. In an epitaxial deposition process, chemical reactants, comprised of source gases, are controlled and system parameters are set such that the deposited atoms reach the growth surface of the first semiconductor material with sufficient energy to move around on the growth surface and orient themselves relative to the crystalline arrangement of the atoms of the growth surface. Examples of various epitaxial growth process equipment that can be employed in the present application include, for example, rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The temperature of epitaxial deposition typically ranges from 550°C to 900°C. Typically, higher temperatures result in faster deposition, but faster deposition can result in crystal defects and film cracking.

[0032] As used herein, a "source / drain" region may be a source region or a drain region, depending on the subsequent wiring and application of voltage during operation of the FET. The first source / drain region 116 is composed of a semiconductor material and a dopant. The semiconductor material that comprises the first source / drain region 116 may include one of the semiconductor materials described above for the semiconductor substrate 100. The semiconductor material that comprises the first source / drain region 116 may be compositionally the same as or compositionally different from each semiconductor channel material nanosheet 106. However, the semiconductor material that comprises the first source / drain region 116 is compositionally different from each recessed sacrificial semiconductor material nanosheet 104. The dopant present in the first source / drain region 116 may be a p-type dopant or an n-type dopant. The term "p-type" refers to the addition of an impurity to an intrinsic semiconductor that creates a deficiency of valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, phosphorus, and indium. "N-type" refers to the addition of an impurity that provides free electrons to an intrinsic semiconductor. In silicon-containing semiconductor materials, examples of n-type dopants, or impurities, include, but are not limited to, antimony, arsenic, and phosphorus. In one example, the first source / drain region 116 is 4x10 20 atoms / cm 3 From 3x10 21 atoms / cm 3 In one example, the first source / drain region 116 is made of silicon doped with phosphorous.

[0033] A first ILD material layer 118 is then formed on the first source / drain regions 116. The first ILD material layer 118 can be composed of a dielectric material including, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. The term "low-k" as used throughout this application refers to a dielectric material having a dielectric constant less than 4.0 (all dielectric constants referred to herein are relative to a vacuum unless otherwise noted). Although not shown, the first ILD material layer 118 can include a multi-layer structure of at least two different dielectric materials, such as, for example, silicon nitride and silicon dioxide, stacked one on top of the other. The first ILD material layer 118 can be formed by a deposition process, such as, for example, CVD, PECVD, or spin-on coating. A planarization step (including, for example, chemical mechanical polishing (CMP)) may be performed after deposition of the dielectric material that constitutes the first ILD material layer 118. The first ILD material layer 118 typically has a top surface that is coplanar with the top surface of the first sacrificial gate structure 108 and the top surface of the first dielectric spacer 110. Note that if a sacrificial gate cap is present, the aforementioned planarization step removes the sacrificial gate cap and exposes the sacrificial gate material of the first sacrificial gate structure 108. An upper portion of the first dielectric spacer 110 may also be removed by this planarization step.

[0034] 4A, 4B, and 4C, the exemplary structures shown in FIGS. 3A, 3B, and 3C, respectively, are illustrated after bonding the top semiconductor channel layer 122 using a dielectric-to-dielectric bonding process. This forms a multi-layer structure including a stacked device isolation dielectric material (hereinafter SDSDM) layer 120 and a semiconductor channel material layer 122. The SDSDM layer 120 can be composed of any dielectric material including, for example, silicon dioxide, silicon nitride, or a combination thereof. In one embodiment, the SDSDM layer 120 is composed entirely of silicon dioxide. The SDSDM layer 120 may have a thickness of 20 nm to 100 nm, although other thicknesses of the SDSDM layer 120 are also contemplated and can be used as the thickness of the SDSDM layer 120. The semiconductor channel material layer 122 is composed of one of the aforementioned semiconductor materials of the semiconductor substrate 100. Typically, but not always, the semiconductor channel material layer 122 is composed of a single semiconductor material such as, for example, silicon. The semiconductor channel material layer 122 may have a thickness of 10 nm to 100 nm, although other thicknesses of the semiconductor channel material layer 122 are contemplated and can be used as the thickness of the semiconductor channel material layer 122. A bonding oxide forming a multi-layer structure including the SDSDM layer 120 is typically first formed on the exposed surface of the exemplary structure shown in Figures 3A, 3B, and 3C and another semiconductor wafer. The other wafer is then flipped and bonded to the device wafer shown in Figures 3A, 3B, and 3C, followed by thinning the semiconductor material wafer to form the semiconductor channel material layer.

[0035] 5A, 5B and 5C, there is illustrated the exemplary structures shown in Figures 4A, 4B and 4C, respectively, after the semiconductor channel material layer 122 has been patterned to form semiconductor fins 122F above each nanosheet stack NS of alternating sacrificial semiconductor material nanosheets 104 and semiconductor channel material nanosheets 106. Although the figures illustrate a pair of semiconductor fins 122F formed above each nanosheet material stack NS, the present application works when only a single semiconductor fin or multiple, such as two semiconductor fins 122F, are formed above each nanosheet stack NS.

[0036] The semiconductor fins 122F can be formed by lithography and etching, a sidewall image transfer (SIT) process, or a direct self-assembly (DSA) patterning process in which a copolymer capable of self-assembly is used. Each semiconductor fin 122F formed includes a pair of vertical sidewalls that are parallel to each other. As used herein, a surface is "vertical" if there is a vertical surface that does not deviate by more than three times the root mean square roughness of the surface. Each semiconductor fin 122F formed includes a pair of sidewalls that are parallel to each other. Each semiconductor fin 122F has a width of 5 nm to 30 nm and a length of 100 nm to 2000 nm. Other widths and lengths are possible and can be used in the present application for each semiconductor fin 122F.

[0037] 6A, 6B, and 6C, the exemplary structures shown in FIGS. 5A, 5B, and 5C, respectively, are illustrated after forming a second sacrificial gate structure 124 and a second dielectric spacer 126 on a portion of each semiconductor fin 122F, forming second source / drain regions 128, and forming a second ILD material layer 130. The second sacrificial gate structure 124 straddles each of the semiconductor fins 122F as shown in FIG. 6B, so that it is located on the top surface and along the vertical sidewalls of the semiconductor fins 122F. The second sacrificial gate structure 124 may include any sacrificial gate dielectric material and sacrificial gate material as defined above for the first sacrificial gate structure 108. A sacrificial gate cap may be present on the second sacrificial gate structure 108. With or without a sacrificial gate cap, the second sacrificial gate structure 124 may be formed utilizing the processing techniques described above in forming the first sacrificial gate structure 108, with or without a sacrificial gate cap.

[0038] The second dielectric spacer 126 may include one of the dielectric spacer materials described above for the first dielectric spacer 110. The dielectric spacer material making up the second dielectric spacer 126 may be compositionally the same as or compositionally different from the dielectric spacer making up the first dielectric spacer 110. The second dielectric spacer 126 may be formed utilizing the techniques described above in forming the first dielectric spacer 110.

[0039] Second source / drain regions 128 are formed on the exposed surface of the semiconductor fin 122F that does not include the second dielectric spacer 126 or the second sacrificial gate dielectric material, and the second source / drain regions 128 are also formed on the surface of the SDSDM layer 120. The second source / drain regions 128 can be composed of a semiconductor material and a dopant that can be of opposite (or same) conductivity type compared to the dopant present in the first source / drain regions 116. In an embodiment, the second source / drain regions 128 can be formed by in situ doped epitaxial growth.

[0040] The second ILD material layer 130 may include one of the dielectric materials described above for the first ILD material layer 118. The dielectric material that makes up the second ILD material layer 130 may be compositionally the same as or different from the dielectric material that makes up the first ILD material layer 118. The second ILD material layer 130 may be formed utilizing one of the deposition processes described above for forming the first ILD material layer 118. A planarization process may be performed after the deposition step. This planarization process may remove the sacrificial cap from above the second sacrificial gate structure 124 and reduce the height of the second dielectric spacer 126. As shown, the second ILD material layer 130 has a top surface that is coplanar with the top surfaces of the second dielectric spacer 126 and the second sacrificial gate structure 124.

[0041] 7A, 7B, and 7C, the exemplary structures shown in FIGS. 6A, 6B, and 6C, respectively, are illustrated after an opening 132 has been formed generally in the second sacrificial gate structure 124 and the SDSDM layer 120, and partially into the first sacrificial gate structure 108. The opening 132 defines where a gate cut groove will subsequently be formed. The opening 132 may be formed by lithography and etching. Note that the opening 132 has a first width w1 (i.e., critical dimension) larger than the gate opening to facilitate subsequent filling with a high-k gate dielectric material layer and a-Si. The opening 132 extends through the SDSDM layer 120, as shown in FIG. 7B.

[0042] 8A, 8B and 8C, the exemplary structures shown in FIGS. 7A, 7B and 7C, respectively, are illustrated after removing the first sacrificial gate structure 108 and the second sacrificial gate structure 124, exposing each semiconductor fin 122F by removing the second sacrificial gate structure 124, exposing each sacrificial semiconductor material nanosheet 104 by removing the first sacrificial gate structure 108, and then removing the exposed sacrificial semiconductor material nanosheet 104. The removal of the sacrificial semiconductor material nanosheet 104 constitutes a nanosheet stack including at least one suspended semiconductor channel material nanosheet 106. The removal of the first sacrificial gate structure 108 and the second sacrificial gate structure 124 may include one or more (dry and / or wet) etching steps selected in removing the first sacrificial gate structure 108 and the second sacrificial gate structure 124. Removing the sacrificial semiconductor material nano-sheets 104 includes an etch that is selective in removing the sacrificial semiconductor material nano-sheets 104 relative to the semiconductor channel material nano-sheets 106 .

[0043] 9A, 9B, and 9C, the exemplary structures shown in FIGS. 8A, 8B, and 8C, respectively, are illustrated after forming a high-k dielectric material layer 134 on the physically exposed surfaces of each semiconductor fin 122F and each semiconductor channel material nanosheet 106, and then forming an a-Si layer 136. Although not illustrated, a thin deoxidized layer (i.e., a TiN layer) can be formed (e.g., by a deposition process such as ALD, CVD, PECVD, etc.) on the high-k dielectric material layer 134 before forming the a-Si layer 136. In addition to being formed on the physically exposed surfaces of the semiconductor fin 122F and the semiconductor channel material nanosheet 106, the high-k gate dielectric material 134 is also formed on the top, bottom, and sidewalls of the SDSDM layer 120, on the top surface of the dielectric material 102, on the top surface of the second ILD material layer 130, and on the top and sidewalls of the second dielectric spacer 126.

[0044] The term "high-k dielectric material" refers to a dielectric material having a dielectric constant greater than 4.0. Examples of high-k gate dielectric materials from which the high-k dielectric material layer 134 can be constructed include, for example, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO4), zirconium silicon oxynitride (ZrSiO x N y ), tantalum oxide (TaO xThe high-k dielectric material layer 134 may include metal oxides such as titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3), or lead zinc niobium oxide (Pb(Zn,Nb)O), or combinations thereof. The high-k gate dielectric material constituting the high-k dielectric material layer 134 may further include dopants such as lanthanum (La), aluminum (Al) or magnesium (Mg), or combinations thereof. The high-k dielectric material layer 134 may be formed utilizing a deposition process such as ALD, CVD, PECVD, or PVD. The high-k dielectric material layer 134 is a conformal layer having a thickness in the range of 1 nm to 10 nm.

[0045] The a-Si layer 136 may be formed by a deposition process including, but not limited to, ALD, CVD, or PECVD. An anneal may be performed after deposition of the a-Si layer 136. The anneal may be a rapid thermal anneal at a temperature between 700° C. and 1200° C. for a time period between a few nanoseconds to about a minute. The anneal is performed to ensure that defects in the high-k dielectric are repaired and to improve the integrity of the gate dielectric.

[0046] 10A, 10B, and 10C, the exemplary structures shown in FIGS. 9A, 9B, and 9C, respectively, are illustrated after forming a gate kerf groove (CT) 138 generally through the a-Si layer 136 and partially into a portion of the dielectric material layer 102. At the bottom of the gate kerf groove 138, the lower surface of the dielectric material layer 102 is physically exposed. The term "lower surface" is used throughout this application to refer to the surface of the material / structure that is located between the top surface of the material / structure and the bottom surface of the material / structure. A portion of the gate kerf groove 138 is formed in the same area where the opening 132 was formed. The gate kerf groove 138 can be formed by lithography and etching. The etching is selected to remove the physically exposed portion of the a-Si layer 136 that rests on the lower surface of the dielectric material layer 102.

[0047] 11A, 11B, and 11C, the exemplary structures shown in FIGS. 10A, 10B, and 10C, respectively, are illustrated after forming a protective material 140 in the lower portion of the gate cut groove 138, the protective material 140 having a top surface located between the top and bottom surfaces of the SDSDM layer 120. In one embodiment, the protective material 140 is comprised of an organic planarization layer (OPL). The protective material 140 can be formed by a deposition process (e.g., CVD, PECVD, or PVD, etc.), followed by a recess etch. Note that the recess etch does not have to be precise, as long as the recess etch stops somewhere between the top and bottom surfaces of the SDSDM layer 120.

[0048] 12A, 12B, and 12C, the exemplary structure shown in FIGS. 11A, 11B, and 11C, respectively, are illustrated after trimming the a-Si layer 136 located along the sidewalls of the upper portion of the gate kerf groove 138 to increase the width of the upper portion of the gate kerf groove 138 relative to the lower portion of the gate kerf groove 138. The increased width has a second width w2 that is greater than the original width w0 of the gate kerf groove 138. The trimming expands the critical dimension, i.e., the width of the original gate kerf groove 138 that is not protected by the protective material 140. This trimming step can expose the high-k gate dielectric material layer 134 that is present along the sidewalls of the previously cut SDSDM layer 120. This trimming step can be performed by an isotropic Si / TiN etch.

[0049] 13A, 13B, and 13C, the exemplary structures shown in FIGS. 12A, 12B, and 12C, respectively, are illustrated after removing protective material 140 from a lower portion of gate kerf groove 138 to expose a modified gate kerf groove 139 having a first portion having the width of the original gate kerf groove (this width is shown as w0 in FIG. 13B) and a second portion having an increased width (i.e., second width w2). Protective material 140 can be removed utilizing an etch selected to remove protective material 140 from modified gate kerf groove 139, such as N2 / H2 ash.

[0050] 14A, 14B and 14C, the exemplary structure shown in FIG. 13A, 13B and 13C, respectively, is illustrated after the first gate cut dielectric structure 142 has been formed in a first portion of the modified gate cut groove 139 and partially formed into a second portion of the modified gate groove 139. As shown, the first gate cut dielectric structure 142 has a surface that directly contacts the lower surface of the dielectric material layer 102 and has a portion that penetrates an opening present in the SDSDM layer 120 having an enlarged width, i.e., w3, compared to the width w4 of the portion of the first gate cut dielectric structure 142 that is present in the lower portion of the modified gate cut groove 139 without penetrating the opening. In the present application, w4 is equal to w0 as described above, and w3 is equal to w2 as described above. The first gate cut dielectric structure 142 has a top surface that extends above the top surface of the SDSDM layer 120 and thus is present in the region that includes the semiconductor fin 122F (i.e., the second device region). The first gate cut dielectric structure 142 may be composed of a dielectric material that is compositionally different than the dielectric material that comprises the dielectric material layer 102. In one embodiment, the first gate cut dielectric structure 142 is composed of silicon nitride. The first gate cut dielectric structure 142 may be formed by a deposition process, such as, for example, CVD or PECVD, followed by a recess etch.

[0051] 15A, 15B, and 15C, there is shown the exemplary structure shown in FIG. 14A, 14B, and 14C, respectively, after forming additional a-Si on top of the first gate cut dielectric structure 142 to completely fill the remaining second portion of the modified gate cut groove 139. The additional a-Si re-establishes the integrity of the original a-Si layer 136. The additional a-Si can be formed by deposition and planarization. The additional a-Si layer is not separately shown in the drawings of this application.

[0052] 16A, 16B, and 16C, there is shown the example structures shown in FIGS. 15A, 15B, and 15C, respectively, after a second gate cut dielectric structure 144 is formed in the a-Si layer 136 and contacts the surface of the first gate cut dielectric structure 142. The second gate cut dielectric structure 144 can be composed of a dielectric material that is compositionally the same or compositionally different than the first gate cut dielectric structure 142. The second gate cut dielectric structure 144 is formed by lithography, etching, deposition, and planarization processes.

[0053] 17A, 17B, and 17C, the example structures shown in FIGS. 16A, 16B, and 16C, respectively, are illustrated after removing the top portion of the a-Si layer 136 to expose the high-k gate dielectric material layer 134 located on each semiconductor fin 122F and on the top surface of the SDSDM layer 120. This step also includes removing the deoxidization layer present on the high-k gate dielectric material layer 134. Removing the top portion of the a-Si layer 136 may include an etch selected in removing the a-Si, while removing the deoxidization layer may include a different etch selected in removing the deoxidization layer.

[0054] 18A, 18B and 18C, the exemplary structures shown in Figs. 17A, 17B and 17C, respectively, are illustrated after forming a second gate electrode 145 on the physically exposed surface of the high-k gate dielectric material layer 134 located on the first set of semiconductor fins 122F (left side of Fig. 18B) and forming another second gate electrode 146 on the physically exposed surface of the high-k gate dielectric material layer 134 located on the second set of semiconductor fins 122F (right side of Fig. 18B), where the first and second sets of semiconductor fins are separated by the second gate cut dielectric structure 144 and an increased width portion of the first gate cut dielectric structure 142 that penetrates an opening present in the SDSDM layer 120. It should be noted that the first gate electrode is formed in a subsequent processing step of the present application.

[0055] According to the present application, the second gate electrode 145 and the gate dielectric material layer 134 formed on the first set of semiconductor fins 122F constitute a second functional gate structure of a second FET device, while another gate electrode 146 and the gate dielectric material layer 134 formed on the second set of semiconductor fins 122F constitute another second FET device. In some embodiments, the second FET device and the another second FET device may have the same threshold voltage Vt. In other embodiments, the second FET device may have a different Vt from the Vt of the another second FET device. In the illustrated embodiment, the second FET device and the another second FET device are finFET devices. The second FET device and the another second FET device may be of the same conductivity type (p-FET device or n-FET device). The second FET device and the another second FET device may be of different conductivity types.

[0056] The second gate electrode 145 and the further second gate electrode 146 include at least a work function metal (WFM) and an optional gate electrode material. Depending on the technique used to form the second gate electrode 145 and the further second gate electrode 146, the second gate electrode 145 and the further second gate electrode 146 may include a compositionally identical WFM or a compositionally different WFM. In an embodiment, the gate electrode 145 and the further second gate electrode 146 may include a gate electrode material that is compositionally identical or a gate electrode material that is compositionally different. When an optional gate electrode material is present, the WFM is located between the gate electrode material and the high-k gate dielectric material layer. The WFM is used in this application to set the threshold voltage of the FET device to a desired value. In some embodiments, the WFM can be selected to provide an n-type threshold voltage shift. As used herein, "n-type threshold voltage shift" refers to a shift in the effective work function of the work function metal-containing material toward the conduction band of silicon in the silicon-containing material. In one embodiment, the work function of the n-type work function metal ranges from 4.1 eV to 4.3 eV. Examples of materials that can provide such an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations thereof. In other embodiments, the WFM may be selected to provide a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal ranges from 4.9 eV to 5.2 eV. As used herein, "threshold voltage" is the lowest gate voltage attainable that turns on a semiconductor device, e.g., a transistor, by making the channel of the device conductive. The term "p-type threshold voltage shift" as used herein refers to a shift in the effective work function of a work function metal-containing material toward the valence band of silicon in a silicon-containing material. Examples of such materials that can provide a p-type threshold voltage shift include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof. The WFM can be formed by a deposition process, e.g., ALD, CVD, or PECVD.

[0057] The optional gate electrode material may be tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), zirconium (Zr), cobalt (Co), copper (Cu), aluminum (Al), lead (Pb), platinum (Pt), tin (Sn), silver (Ag), or gold (Au), or tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), or tantalum carbide (TbC). X The gate electrode material may include, but is not limited to, a conductive metal-containing material, such as, but not limited to, titanium carbide (TiC), titanium aluminum carbide, tungsten silicide (WSi2), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide, or nickel silicide. Any of the gate electrode materials may be formed using a deposition process, such as, for example, ALD, CVD, PECVD, PVD, plating, or sputtering. A reflow anneal or silicide anneal may be used in some embodiments of the present application after the conductive metal-containing material deposition.

[0058] The second gate electrode 145 and the further second gate electrode 146 may be formed at the same time or at different times using block mask techniques. In either embodiment, the second gate electrode 145 and the further second gate electrode 146 are formed by deposition followed by a planarization step. The planarization step removes any gate electrode material, WFM, and high-k dielectric material 134 present on the second dielectric spacer 126 and second ILD material layer 130, resulting in the planar structure shown in Figures 18A, 18B, and 18C.

[0059] 19A, 19B, and 19C, the exemplary structures shown in FIGS. 18A, 18B, and 18C, respectively, are illustrated after forming a second conductive-contact-containing ILD material layer 148 (a first conductive-contact-containing ILD material layer is formed in a subsequent processing step of the present application). The second conductive-contact-containing ILD material layer 148 includes a second source / drain contact structure 150 contacting the second source / drain region 128, a second gate contact structure 152 contacting the second gate electrode 145, a first gate contact structure 156 (which contact structure then contacts a first gate electrode of a first FET device), and a shared gate contact structure 154 (which contact structure contacts another second gate electrode 146 of another second FET device, which then contacts another first gate electrode of another first FET device). During the formation of the aforementioned contact structures, a shared source / drain contact structure 158 can be formed. The shared source / drain contact structure 158 contacts both the second source / drain region 128 and the first source / drain region 116 of the pair of stacked FET devices of the present application.

[0060] The second conductive-contact-containing ILD material layer 148 is comprised of one of the dielectric materials described above for the first ILD material layer 118. The second conductive-contact-containing ILD material layer 148 can be comprised of a dielectric material that is compositionally the same or compositionally different than the dielectric material that comprises the second ILD material layer 130. The second conductive-contact-containing ILD material layer 148 can be formed using one of the deposition processes described above for forming the first ILD material layer 118.

[0061] Each contact structure, i.e., second source / drain contact structure 150, second gate contact structure 152, first gate contact structure 156, shared gate contact structure 154, and shared source / drain contact structure 158, can be formed by forming contact openings into at least the second conductive-contact-containing ILD material layer 148 (some of these openings extend downward through various other material layers of the exemplary structure to allow contact to the surface of the desired structure / region). The contact openings are formed by lithography and etching. An optional diffusion barrier material and a conductive contact material are then formed (i.e., deposited) into each of the contact openings. Planarization can be performed after deposition of the optional diffusion barrier material and the conductive contact material. In one or more embodiments in which a contact liner is present, the contact liner (not shown) may include a silicide liner, such as Ti, Ni, NiPt, and a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof, such as Ti / TiN and Ti / WC. The contact liners can be formed using conformal deposition processes including PVD, RFPVD, CVD, or ALD. The formed contact liners can have a thickness ranging from 1 nm to 8 nm, although lesser and greater thicknesses can be employed. The contact conductor material comprising each contact structure can include, but is not limited to, W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or alloys thereof. The contact conductor material can be formed by any suitable deposition method, such as, for example, ALD, CVD, PVD, or plating. Each contact structure has a top surface that is coplanar with at least the second conductive contact-containing ILD material layer 148 after contact metal planarization.

[0062] 20A, 20B, and 20C, the exemplary structures shown in FIGS. 19A, 19B, and 19C, respectively, are illustrated after forming a BEOL structure 162 and a carrier wafer 164 on the second conductive-contact-containing ILD material layer 148. However, the BEOL structure 162 has a first side that forms and interfaces with the second conductive-contact-containing ILD material layer 148, and a second side that forms and interfaces with the carrier wafer 164 opposite the first side. The BEOL structure 162 includes conductive structures (i.e., interconnect lines and / or vias) embedded in one or more interconnect dielectric material layers. The conductive structures may include Cu, Al, W, or any combination thereof. The BEOL structure 162 may be formed utilizing techniques well known to those skilled in the art, including, for example, damascene techniques. The carrier wafer 164 on top of the BEOL structure 162 may include one of the semiconductor materials described above for the semiconductor substrate 100. A carrier wafer 164 is bonded to the BEOL structures 162 after the BEOL structures 162 are formed on the second conductive-contact-containing ILD material layer 148 .

[0063] 21A, 21B, and 21C, the exemplary structure shown in FIG. 20A, 20B, and 20C, respectively, is illustrated after flipping the exemplary structure 180°, removing the semiconductor substrate 100, removing the dielectric material layer 102, and removing the physically exposed portions of the high-k gate dielectric material 134 previously located on the dielectric material layer 102. The flipping can be performed by conventional means well known to those skilled in the art. For example, the flipping can be performed by manual or mechanical means (i.e., a robotic arm). This flipping physically exposes the surface of the semiconductor substrate 100 for further processing. The removal of the semiconductor substrate 100 includes an etch that stops on the surface of the dielectric material layer 102. The etch used in removing the semiconductor substrate 100 is typically a combination of wafer grinding, CMP, followed by dry or chemical wet etch steps. The removal of the dielectric material layer 102 includes an etch selected to remove the dielectric material that makes up the dielectric material layer 102. This etch does not remove the first gate cut structure 142, the bottom dielectric isolation structure 114, or the high-k gate dielectric material 134. Note that after the etch, a portion of the first gate cut dielectric structure 142 is physically exposed and a portion of the bottom dielectric isolation structure 114 is also physically exposed. The removal of the physically exposed portion of the high-k gate dielectric material 134 includes an etch that stops on the underlying a-Si layer 136. This etch does not etch any portion of the bottom dielectric isolation structure 114 or the first gate cut dielectric structure 142.

[0064] 22A, 22B, and 22C, the exemplary structures shown in FIGS. 21A, 21B, and 21C, respectively, are illustrated after removal of the physically exposed portions of the a-Si layer 136. Removal of the a-Si layer 136 includes an etch selected to remove the a-Si, which does not etch the bottom dielectric insulating structure 114, the deoxidized layer present on the high-k gate dielectric material 134 formed on the semiconductor channel material nano-sheet 106, and any portion of the first gate cut dielectric structure 142. After removal of the a-Si layer 136, another etch can be used to remove the deoxidized layer from the high-k gate dielectric material 134 present on the semiconductor material nano-sheet 106.

[0065] 23A, 23B and 23C, the exemplary structures shown in Fig. 22A, 22B and 22C, respectively, are illustrated after forming a first gate electrode 165 on a physically exposed surface of the high-k gate dielectric material layer 134 located on the first set of suspended semiconductor channel material nanosheets 106 (e.g., see the right side of Fig. 23B) and forming another first gate electrode 166 on a physically exposed surface of the high-k gate dielectric material layer located on the second set of suspended semiconductor channel material nanosheets 106 (e.g., see the left side of Fig. 23B). According to the present application, the first gate electrode 165 and the gate dielectric material layer 134 formed on the first set of semiconductor channel material nanosheets 106 constitute a first functional gate structure of a first FET device, while the another first gate electrode 166 and the gate dielectric material layer 134 formed on the second set of semiconductor channel material nanosheets 106 constitute another first FET device. In some embodiments, the first FET device and the other first FET device may have the same threshold voltage Vt. In other embodiments, the first FET device may have a different Vt than the other first FET device. The Vt of the first FET device may be the same or different from the Vt of the second FET device, and the Vt of the other first FET device may be the same or different from the VT of the other second FET device. In the illustrated embodiment, the first FET device and the other first FET device are nanosheet FET devices. In an embodiment, the first FET device and the other first FET device are the same conductivity type (p-FET device or n-FET device), but the conductivity type of the first FET device and the other first FET device is different from the second FET device and the other second FET device. Thus, in the present application, the first FET device is stacked above the second FET device, and the other first FET device is stacked above the other second FET device, and these devices are vertically separated by the SDSDM layer 120.The first FET device and the further first FET device are separated by a first gate cut dielectric structure 142, while the second FET device and the further second FET device are separated by a second gate cut dielectric structure 144, as shown in FIG. 26B.

[0066] The first gate electrode 165 and the further second gate electrode 166 include at least a work function metal (WFM) and any gate electrode material. Depending on the technique used to form the first gate electrode 165 and the further first gate electrode 166, the first gate electrode 165 and the further first gate electrode 166 may include compositionally the same WFM or compositionally different WFM. It should be noted that the WFM constituting the first gate electrode 165 is not present in the area of ​​the exemplary structure including the second gate electrode 145 due to the presence of the first gate cut dielectric structure 142 filling the opening between the SDSDM layers 120. Similarly, for the same reason, the WFM constituting the further first gate electrode 166 is not present in the area of ​​the exemplary structure including the further second gate electrode 146. In an embodiment, the first gate electrode 165 and the further first gate electrode 166 may include compositionally the same gate electrode material or compositionally different gate electrode material. The WFMs constituting the first gate electrode 165 and the further second gate electrode 166 include one of the WFMs described above for the second gate electrode 145 and the further second gate electrode 146. Any gate electrode material that can also be used in constructing the first gate electrode 165 and the further first gate electrode 166 includes one of the gate electrode materials described above for the second gate electrode 145 and the further second gate electrode 146. The first gate electrode 165 and the further second gate electrode 166 can be formed utilizing the techniques described above for forming the second gate electrode 145 and the further second gate electrode 146.

[0067] 24A, 24B, and 24C, the exemplary structures shown in FIGS. 23A, 23B, and 23C, respectively, are illustrated after forming a first conductive-contact-containing ILD material layer 168, which includes a first source / drain contact structure 170 that contacts (in the illustrated example contacts) a first source / drain region 116 of one of the first FET devices. The first conductive-contact-containing ILD material layer 168 includes one of the dielectric materials described above for the first ILD material layer 118. The first conductive-contact-containing ILD material layer 168 can be formed utilizing one of the deposition processes described above for forming the first ILD material layer 118. The first source / drain contact structure 116 can include materials and be formed as described above for the other contact structures.

[0068] 25A, 25B, and 25C, there is shown the example structure shown in Figures 24A, 24B, and 24C, respectively, after forming a BSPDN structure 122 on a first conductive-contact-containing ILD material layer 168. BSPDN includes materials / components well known to those skilled in the art.

[0069] In the example illustrated in Figures 2A-25C, a semiconductor structure including a nanosheet FET device stacked on a FinFET device is described and illustrated. The processing steps illustrated in Figures 2A-25C can be modified by one skilled in the art to form a semiconductor structure including a FinFET device stacked on a nanosheet FET device, a FinFET device stacked on another FinFET device, or a nanosheet FET device stacked on another nanosheet FET device. In the following example (see Figures 26A-61C), a semiconductor structure is described in which a first nanosheet FET device is stacked with a second nanosheet FET device. The processing steps used in this embodiment can be readily alternating by one skilled in the art to form other types of stacked FET devices.

[0070] 26A and 26B, an exemplary structure through XX and Y1-Y1 shown in FIG. 1 that can be employed in another embodiment of the present application is illustrated. The exemplary structure of this another embodiment includes a semiconductor substrate 200, a dielectric material layer 202, a first sacrificial semiconductor material layer 204L, a first nanosheet material stack MS1, a second sacrificial semiconductor material layer 205L, and a second nanosheet material stack MS2. Each nanosheet material stack includes an alternating sacrificial semiconductor material layer 206L and a semiconductor channel material layer 208L.

[0071] The semiconductor substrate 200 includes one of the semiconductor materials described above for the semiconductor substrate 100. The dielectric material layer 202 includes one of the dielectric materials described above for the dielectric material layer 102. The dielectric material layer 202 can be formed using one of the deposition processes described above for the dielectric material layer 102. Alternatively, the dielectric material layer 202 and the semiconductor substrate 200 are components of an SOI substrate in which the top semiconductor layer is the first sacrificial semiconductor material layer 204L. In some embodiments, the initial semiconductor layer above the dielectric material layer 202 is Si and can be converted to SiGe by epitaxially growing SiGe and performing SiGe condensation. The dielectric material layer 202 can have a thickness within the thickness ranges described above for the dielectric material layer 102.

[0072] The sacrificial semiconductor material layers 206L of the first and second nanosheet material stacks MS1 and MS2 each include a first semiconductor material as described above for the sacrificial semiconductor material layer 104L. The semiconductor channel material layers 208L of the first and second nanosheet material stacks MS1 and MS2 each include a second semiconductor material as described above for the semiconductor channel material layer 106L. The first and second sacrificial semiconductor material layers 204L and 205L each are composed of a third semiconductor material that is compositionally different from both the first semiconductor material constituting each sacrificial semiconductor material layer 206L and the second semiconductor material constituting each semiconductor channel material layer 208L. In one example, the sacrificial semiconductor material layer 206L is composed of a silicon germanium alloy having 30 atomic % germanium, the semiconductor channel material layer 208L is composed of silicon, and the first and second sacrificial semiconductor material layers 204L and 205L are composed of a silicon germanium alloy having a germanium content of 55 atomic %. Each of the first and second sacrificial semiconductor material layers 204L and 205L may have a thickness within a range of 10 nm to 40 nm, although other thicknesses are contemplated and may be used as the thickness of the first and second sacrificial semiconductor material layers 204L and 205L, respectively.

[0073] In this embodiment, the first nanosheet material stack MS1 and the second nanosheet material stack MS2 include "n" semiconductor channel material layers 208L and "n+1" sacrificial semiconductor material layers 206L, where n is at least 1. Thus, each semiconductor channel material layer 208L in the first nanosheet material stack MS1 and the second nanosheet material stack MS2 is sandwiched between a bottom sacrificial semiconductor material layer 206L and a top sacrificial semiconductor material layer 206L. According to an example, each of the first nanosheet material stack MS1 and the second nanosheet material stack MS2 includes three semiconductor channel material layers 208L and four sacrificial semiconductor material layers 206L. Although the present application illustrates that the first nanosheet material stack MS1 and the second nanosheet material stack MS2 include the same number of sacrificial semiconductor material layers 206L and semiconductor channel material layers 208L, the present application contemplates an embodiment when the first nanosheet material stack MS1 includes a different number of sacrificial semiconductor material layers 206L and semiconductor channel material layers 208L than the second nanosheet material stack MS2. For example, the first nanosheet material stack MS1 may include two semiconductor channel material layers 208L and three sacrificial semiconductor material layers 206L, while the second nanosheet material stack MS2 may include three semiconductor channel material layers 208L and four sacrificial semiconductor material layers 206L. Typically, but not always, the sacrificial semiconductor material layers 206L in the first nanosheet material stack MS1 are compositionally the same as the sacrificial semiconductor material layers 206L in the second nanosheet material stack MS2. Also typically, but not necessarily always, the semiconductor channel material layer 208L in the first nanosheet material stack MS1 is compositionally the same as the semiconductor channel material layer 208L in the second nanosheet material stack MS2. For example, in some embodiments, the semiconductor channel material layer 208L present in the first nanosheet material stack MS1 is composed of a second semiconductor material capable of imparting high channel mobility to an NFET device and the semiconductor channel material layer 208L present in the second nanosheet stack MS2 is composed of a second semiconductor material capable of imparting high channel mobility to a PFET device, or vice versa.The first nanosheet material stack MS1, the second sacrificial semiconductor material layer 205L, and the second nanosheet material stack MS2 may be formed by depositing (e.g., by epitaxial growth) a suitable semiconductor material on top of the first sacrificial semiconductor material layer 204L.

[0074] 27A and 27B, the exemplary structures shown in FIG. 26A and FIG. 26B, respectively, are illustrated after a first patterning of the first sacrificial semiconductor material layer 204L, the first nanosheet material stack MS1, the second sacrificial semiconductor material layer 205L, and the second nanosheet material stack MS2. This patterning includes depositing a layer of hard mask material on the top surface of the second nanosheet material stack MS2. The deposition of the layer of hard material may include CVD, PECVD, or PVD, and the hard mask material may include, for example, silicon dioxide, silicon nitride, or silicon oxynitride. The layer of hard mask material is then patterned by lithography and etching to form a patterned hard mask 210 on the top surface of the second nanosheet material stack MS2. With the patterned hard mask 210 in place, a second etch is used to etch the second nanosheet material stack MS2, the second sacrificial semiconductor material layer 205L, the first nanosheet material stack MS1, and the first sacrificial semiconductor material layer 204L. The etch stops at the surface of the dielectric material layer 202 to form a patterned structure as shown in Figures 27A and 27B. The patterned structure includes the patterned (i.e., unremoved) portions of the first sacrificial semiconductor material layer 204L (hereafter, patterned sacrificial semiconductor material layer portions 204P), the patterned (i.e., unremoved) portions of the first nanosheet material stack MS1, the patterned (i.e., unremoved) portions of the second sacrificial semiconductor material layer 205L (hereafter, second semiconductor material layer portions 205P), and the patterned (i.e., unremoved) portions of the second nanosheet material stack MS2. The patterned portions of the first and second nanosheet material laminates MS1 and MS2 each include a patterned (i.e., unremoved) portion of each sacrificial semiconductor material layer 206L (hereinafter, sacrificial semiconductor material layer portion 206P) and a patterned (i.e., unremoved) portion of each semiconductor channel material layer 208L (hereinafter, semiconductor channel material layer portion 208P).

[0075] In the exemplary structure shown in Figures 27A and 27B, the patterned first nanosheet material stack MS1 typically has an outermost wall vertically aligned with the outermost wall of each of the first and second sacrificial semiconductor material layer portions 204P and 205P, respectively, and the patterned second nanosheet material stack MS2 is also vertically aligned with the outermost wall of the patterned hard mask 210. In the exemplary structure shown in Figures 27A and 27B, each sacrificial semiconductor material layer portion 206P and each semiconductor channel material layer portion 208P may have a width of 6 nm to 100 nm and a height (i.e., vertical thickness) of 5 nm to 20 nm. The first and second sacrificial semiconductor material layer portions 204P and 205P have the same widths as described above for the widths of the sacrificial semiconductor material layer portion 206P and the semiconductor channel material layer portion 208P, respectively.

[0076] 28A and 28B, the exemplary structure shown in FIG. 27A and FIG. 27B, respectively, is illustrated after forming a dielectric liner 212 along the sidewalls of the patterned structure and forming a dielectric fill material 214 laterally adjacent to the dielectric liner 212. The dielectric liner 212 includes a dielectric material that is compositionally different from the dielectric fill material 214. In one example, the dielectric liner 212 is composed of silicon nitride and the dielectric fill material 214 is composed of silicon dioxide. The dielectric liner 212 and the dielectric fill material 214 are formed by first depositing a continuous layer of the dielectric liner material on the patterned structure shown in FIG. 27A and FIG. 27B. The deposition of the continuous layer of the dielectric liner material may include, but is not limited to, CVD, PECVD, ALD, or PVD. The continuous layer of the dielectric liner material is a conformal layer and may have a thickness of 5 nm to 20 nm, although other thicknesses are contemplated and may be used as the thickness of the continuous layer of the dielectric liner material. "Conformal layer" means that the material layer has a thickness along a horizontal surface that is the same as the thickness of the same material layer along a vertical surface. Dielectric fill material 214 is then formed by a deposition process (e.g., CVD or PECVD), after which a planarization process is used to remove the continuous layer of dielectric liner material and any dielectric fill material located above the top surface of patterned hard mask 210. The remaining continuous layer of dielectric liner material forms dielectric liner 212.

[0077] In addition to being located on the sidewalls of the patterned structures, the dielectric liner 212 is also located on the physically exposed surfaces of the dielectric material layer 202 that do not include the patterned structures. Along the sidewalls of the patterned structures, the dielectric liner 212 is present on the sidewalls of the patterned hard mask 210, the patterned second nanosheet material stack MS2 (including the sacrificial semiconductor material layer portions 206P and the semiconductor channel material layer portions 208P), the second sacrificial semiconductor layer portion 206, the patterned first nanosheet material stack MS1 (including the sacrificial semiconductor material layer portions 206P and the semiconductor channel material layer portions 208P), and the first sacrificial semiconductor layer portion 206. As shown in FIG. 28B, the dielectric liner 212 has a top surface that is coplanar with the top surfaces of both the dielectric fill material 214 and the patterned hard mask 210.

[0078] 29A and 29B, the exemplary structures shown in FIGS. 28A and 28B, respectively, are illustrated after the patterned structures have been patterned to provide a pair of patterned vertical stack structures. A gap exists between the pair of patterned vertical stack structures. Each patterned vertical stack structure includes a remaining (i.e., unetched) portion of the first sacrificial semiconductor material layer portion 204P (hereinafter, first sacrificial semiconductor material portion 204X), a remaining (i.e., unetched) portion of the first nanosheet material stack MS1 (hereinafter, pitch-tuned first nanosheet material stack MS1x), a remaining (i.e., unetched) portion of the second sacrificial semiconductor material layer portion 205P (hereinafter, second sacrificial semiconductor material portion 205X), and a remaining (i.e., unetched) portion of the second nanosheet material stack MS2 (hereinafter, pitch-tuned second nanosheet material stack MS2x). A portion of the patterned hard mask 210 also remains on top of each patterned vertical stack structure. An unetched portion of each sacrificial semiconductor material layer portion 206P (hereinafter, sacrificial semiconductor material portion 206x) and an unetched portion of each semiconductor channel material layer portion 208P (hereinafter, semiconductor channel material portion 208X) remain in each pitch-aligned first and second nanosheet material stacks MS1x and MS2x, respectively.

[0079] 30A and 30B, the exemplary structures shown in Fig. 29A and 29B, respectively, are illustrated after removing the remaining portions of the first and second sacrificial semiconductor material layers (i.e., the first sacrificial semiconductor material portion 204X and the second sacrificial semiconductor material portion 205X) from each patterned vertical stack structure. The removal of the first sacrificial semiconductor material portion 204X and the second sacrificial semiconductor material portion 205X ​​includes an etching process selected in removing the third semiconductor material constituting the first sacrificial semiconductor material portion 204X and the second sacrificial semiconductor material portion 205X ​​with respect to the first and second semiconductor materials constituting the sacrificial semiconductor material portion 206X and the semiconductor channel material portion 208X of each of the pitch-tuned first and second nanosheet material stacks MS1x and MS2x.

[0080] 31A and 31B, the exemplary structures shown in FIGS. 30A and 30B, respectively, are illustrated after forming a dielectric material in the volume previously including the remaining portions of the first and second sacrificial semiconductor material layers (i.e., the first sacrificial semiconductor material portion 204X and the second sacrificial semiconductor material portion 205X). As shown, a first dielectric insulating layer 216 is formed between the pitch-tuned first nanosheet material stack MS1x and the dielectric material layer 102, and a second dielectric insulating layer 217 is formed between the pitch-tuned first nanosheet material stack MS1x and the pitch-tuned second nanosheet material stack MS2x. The dielectric material constituting the first dielectric insulating layer 216 and the second dielectric insulating layer 217 may include any divot-filled dielectric material, such as, for example, SiN, SiOC, SiC, SiBCN, SiOCN, or SiO2. The dielectric materials constituting the first and second dielectric insulating layers 216 and 217 can be formed by a deposition process such as, for example, ALD, CVD or PECVD. An isotropic etch can be employed to remove and undercut the filler dielectric material present at the gate between the pair of vertical stacks.

[0081] 32A and 32B, the exemplary structures shown in FIGS. 31A and 31B, respectively, are illustrated after removing the dielectric fill material 214 and the dielectric liner 212. First, the dielectric liner 212 and the dielectric fill material 214 are deposited to fill the gap between the two nanosheet stacks, and then a planarization process is used to polish the dielectric fill material 214, which stops on the hard mask 210. The dielectric fill material is then selectively removed, stopping on the dielectric liner 212 and the patterned hard mask 210, followed by removing the patterned hard mask 210 and the dielectric liner 212. As shown in FIG. 32B, both sidewalls of the pair of patterned vertical stack structures are now exposed.

[0082] 33A and 33B, the exemplary structures shown in FIGS. 32A and 32B, respectively, are illustrated after forming a sacrificial dielectric liner 218. The sacrificial dielectric liner 218 is formed along the sidewalls and top surface of each patterned vertically stacked structure. The sacrificial dielectric liner 218 is composed of a dielectric material, such as, for example, silicon oxide, and the sacrificial dielectric liner 218 is a conformal layer. The sacrificial dielectric liner 218 can be formed by a deposition process, such as, for example, CVD, PECVD, ALD, or PVD.

[0083] 34A and 34B, the exemplary structure shown in FIG. 33A and FIG. 33B, respectively, is illustrated after forming a first sacrificial gate material 220. The first sacrificial gate material 220 may include any sacrificial gate material such as those described above for the sacrificial gate material present in the first sacrificial gate structure 108. In one embodiment, the first sacrificial gate material 220 is comprised of a-Si. The first sacrificial gate material 220 may be formed by a deposition process such as, for example, CVD, PECVD, or PVD. At this point in the application, the first sacrificial gate material 220 is formed laterally adjacent to the pair of patterned vertical stack structures and above the exposed top surface of each patterned vertical stack structure.

[0084] 35A and 35B, there is shown the example structure shown in Figures 34A and 34B, respectively, after recessing the first sacrificial gate material 220. Recessing includes a recess etch to form a recessed first sacrificial gate material 220 having a top surface somewhere between the top and bottom surfaces of the second dielectric insulating layer 217.

[0085] 36A and 36B, the exemplary structures shown in FIGS. 35A and 35B, respectively, are illustrated after forming a sacrificial material 222 on the recessed sacrificial gate material 220. The sacrificial material 222 comprises a material different from the first sacrificial gate material 220 and the subsequently formed second sacrificial gate material 224. Examples of materials that can be used as the sacrificial material 222 include, but are not limited to, silicon germanium alloy, aluminum oxide, titanium oxide, or titanium nitride. The sacrificial material 222 can be formed by directional deposition followed by etching to remove the sidewalls of the sacrificial material 222 of each patterned vertical stack structure. Alternatively, the sacrificial material 222 can be formed by deposition (e.g., CVD, PECVD, or PVD, etc.) to top-fill the gaps located between pairs of patterned vertical stacks, followed by recess etching. The formed sacrificial material 222 has a top surface that does not exceed the top surface of the second dielectric insulating layer 217. See, for example, FIG. 36B.

[0086] 37A and 37B, the exemplary structure shown in FIG. 36A and 36B, respectively, is illustrated after forming a second sacrificial gate material 224 and a hard mask layer 226. The second sacrificial gate material 224 formed on the sacrificial material 222 and laterally adjacent to and above the upper portion of each patterned vertical stack structure includes any sacrificial gate material, such as those described above for the sacrificial gate material present in the first sacrificial gate structure 108. In one embodiment, the second sacrificial gate material 224 is comprised of a-Si. The second sacrificial gate material 224 can be formed by a deposition process, such as, for example, CVD, PECVD, or PVD. The hard mask layer 226 formed on the second sacrificial gate material 224 includes any hard mask material, including those described above for the patterned hard mask layer 210. The hard mask layer 226 can be formed by a deposition process, including, but not limited to, CVD, PECVD, or PVD.

[0087] 38A and 38B, the example structures shown in FIGS. 37A and 37B, respectively, are illustrated after hard mask layer 226, second sacrificial gate material 224, sacrificial dielectric liner 218, sacrificial material 222, and first sacrificial gate material 220 have been patterned to form at least one sacrificial gate structure (three are shown in FIG. 38A as an example) that is overlaid with the remaining portion of hard mask layer 216. FIG. 38C illustrates the source / drain regions of the example structures shown in FIGS. 38A and 38B (i.e., cut line Y2-Y2 shown in FIG. 1). This patterning step includes lithography and etching. Each sacrificial gate structure is topped by remaining portions of hard mask layer 226, but includes remaining portions of second sacrificial material 224, remaining portions of sacrificial dielectric liner 218, remaining portions of sacrificial material layer 222, and remaining portions of first sacrificial gate material 220. Note that remaining portions of second sacrificial material 224, remaining portions of sacrificial dielectric liner 218, remaining portions of sacrificial material layer 222, and remaining portions of first sacrificial gate material 220 reside along the sidewalls of each patterned vertical stack structure.

[0088] 39A, 39B, and 39C, there is illustrated the example structure shown in FIG. 38A, 38B, and 38C, respectively, after removing remaining portions of the sacrificial material 222 laterally adjacent to the second dielectric insulating layer 217 and forming a gap 228 between the remaining portions of the first and second sacrificial gate materials 220 and 224, respectively. Removal of the remaining portions of the sacrificial material 222 includes an etching step selected in removing the sacrificial material 222.

[0089] 40A, 40B and 40C, the exemplary structures shown in FIGS. 39A, 39B and 39C, respectively, are illustrated after forming dielectric spacers 232 along the sidewalls of each sacrificial structure, during which the gaps 228 are filled with a dielectric spacer material to provide a layer of spacer dielectric material 230 between the remaining portions of the first and second sacrificial gate materials 220 and 224, respectively. The dielectric spacers 232 and the layer of spacer dielectric material 230 are composed of the same dielectric spacer material. The dielectric spacer material used in constructing the dielectric spacers 232 and the layer of spacer dielectric material 230 includes one of the dielectric spacer materials described above for the first dielectric spacer 110. The dielectric spacers 232, and thus the layer of spacer dielectric material 230, can be formed by deposition of a spacer dielectric material followed by a spacer etch, such as, for example, reactive ion etching (RIE). It is noted that in this embodiment of the present application, the layer of spacer dielectric material 230 serves as the SDSDM layer.

[0090] 41A, 41B and 41C, the exemplary structures shown in FIGS. 40A, 40B and 40C, respectively, are illustrated using a combination etch mask to pattern each patterned vertical stack structure including at least a first nanosheet stack and a second nanosheet stack, the sacrificial gate structure (214 / 224 / 226) and the dielectric spacer 232 covered with at least one hard mask as a combination etch mask, and the first and second nanosheet stacks are patterned to form a vertical nanosheet stack structure including at least a first nanosheet stack and a second nanosheet stack. The structure is shown after each of the nanosheet stacks includes alternating stacked sacrificial semiconductor material nanosheets 206 and semiconductor channel material nanosheets 208, recessing and providing gaps in each sacrificial semiconductor material nanosheet 206 of the first and second nanosheet stacks, and forming an internal spacer dielectric material 234 that fills each gap and resides along the sidewalls of the vertical nanosheet stack structure and along the sidewalls of the sacrificial gate structure (214 / 224 / 226) that is topped with at least one hard mask.

[0091] The etch removes all portions of the patterned vertical stack structures that are not protected by the respective etch masks of the combination. Note that the etch removes each patterned vertical stack structure from the source / drain regions as shown in FIG. 41C. The etch includes one or more etching (dry or chemical wet, or both) steps. Note that the etch physically exposes the lower surface of the dielectric material layer 202 as shown in FIG. 41A. A portion of each patterned vertical stack structure remains under the respective etch masks of the combination forming the nanosheet stacks mentioned above. Each nanosheet stack includes, from bottom to top, a remaining portion of the first dielectric insulating layer 216, a remaining portion of the pitch-tuned first nanosheet material stack MS1x (hereinafter, the first nanosheet stack), a remaining portion of the second dielectric insulating layer 216, and a remaining portion of the pitch-tuned second nanosheet material stack MS2x (hereinafter, the second nanosheet stack). Within each of the first and second nanosheet stacks, an unetched portion of each sacrificial semiconductor material portion 206X (hereinafter, sacrificial semiconductor material nanosheet 206) and an unetched portion of each semiconductor channel material portion 208X (hereinafter, semiconductor channel material nanosheet 208) remain, respectively.

[0092] Each sacrificial semiconductor material nanosheet 206 is then recessed using a lateral etching process such that the recessed sacrificial nanosheet 206 has a reduced width compared to the semiconductor channel material nanosheet. A gap (not specifically shown) is formed at each of the ends of the recessed sacrificial semiconductor material nanosheets 206.

[0093] The inner spacer dielectric material 234 is then formed using a deposition process such as, for example, ALD, CVD, PECVD, or PVD. The inner spacer dielectric material 234 includes one of the dielectric spacer materials described above for the first dielectric spacer 110. The dielectric spacer material constituting the inner spacer dielectric material 234 is compositionally different from the spacer dielectric material constituting the dielectric spacer 232. As shown in FIG. 41A, the inner dielectric spacer material 234 fills each gap and is present along the sidewalls of the vertical nanosheet stack structure and along the sidewalls of the sacrificial gate structure (214 / 224 / 226) that is topped with at least one hard mask. It should be noted that the inner dielectric spacer material 234 is also formed on the physically exposed underlying surface of the dielectric material layer 202 as shown in FIG. 41A and FIG. 41C.

[0094] 42A, 42B and 42C, the exemplary structures shown in Fig. 41A, 41B and 41C are shown after forming a dielectric material structure 236 on the lower portion of the internal spacer dielectric material 234 in the gaps between each vertical nanosheet stack structure and along the sidewalls of each vertical nanosheet. The dielectric material structure 236 is laterally adjacent to the first nanosheet stack of each vertical nanosheet stack structure and has a top surface that is substantially coplanar with the top surface of the remaining portion of the second dielectric insulating layer 217. The dielectric material structure 234 is composed of a flowable dielectric material, such as, for example, a flowable dielectric oxide, and the dielectric material structure 234 can be formed by deposition of the flowable dielectric material followed by recess etching. The dielectric material structure 234 is not laterally adjacent to the second nanosheet stack of the vertical nanosheet stack structure.

[0095] 43A, 43B and 43C, the exemplary structures shown in FIGS. 42A, 42B and 42C, respectively, are illustrated after removing an upper portion of the internal spacer dielectric material 234 along the sidewalls of the second nanosheet stack (the internal spacer dielectric material 234 remains in each gap located at the ends of the internal spacers 234S formed by the recessed sacrificial semiconductor material nanosheets), forming second source / drain regions 238 on the dielectric material structure 236 and adjacent to the second nanosheet stack, and forming a second ILD material layer 240 on the second source / drain regions 238.

[0096] The removal of the upper portion of the inner spacer dielectric material 234 along the sidewalls of the second nanosheet stack can be performed using an isotropic etch back process. The removal of the upper portion of the inner spacer dielectric material 234 exposes the sidewalls of each semiconductor channel material nanosheet 208 of the second nanosheet stack. The entire first nanosheet stack is protected by the remaining portion of the inner dielectric spacer material 234 and the dielectric material structure 236.

[0097] A second source / drain region 238 is then epitaxially grown outward from the physically exposed sidewall of each semiconducting channel material nanosheet 208 of the second nanosheet stack. The second source / drain region 238 corresponds to the second source / drain region 128 described above in the previously illustrated embodiment of this application. The second source / drain region 238 can be composed of a semiconducting material and a dopant of the same or opposite conductivity type compared to the dopant present in the first source / drain region that is subsequently formed.

[0098] A second ILD material layer 240 is then formed. The second ILD material layer 240 includes one of the dielectric materials described above for the first ILD material layer 118 described above in the previously illustrated embodiments of this application. The second ILD material layer 240 is formed utilizing one of the deposition steps described above in forming the first ILD material layer 118 described above in the previously illustrated embodiments of this application. A planarization step may be performed after the deposition step. It is noted that this planarization step removes the hard mask layer 226 present over the second sacrificial gate material 224.

[0099] 44A, 44B, and 44C, the exemplary structure shown in FIG. 43A, 43B, and 43C, respectively, is illustrated after an opening 242 has been formed generally through the remaining portion of the second sacrificial gate material 234 and the layer of spacer dielectric material 230, and into a portion of the remaining first sacrificial gate material 220. The opening 242 is formed by lithography and etching. The opening 242 defines where the gate kerf will subsequently be formed. The opening 242 has a critical dimension that is greater than the gate critical dimension.

[0100] 45A, 45B and 45C, the exemplary structures shown in Figs. 44A, 44B and 44C, respectively, are illustrated after the remaining portions of the first sacrificial gate material 220 and the second sacrificial gate material 224, the physically exposed portions of the sacrificial dielectric liner 218 and the recessed sacrificial semiconductor nanosheets 206 of the first and second nanosheet stacks have been removed to provide suspended semiconductor channel material nanosheets 208 within the first and second nanosheet stacks. The removal of the remaining portions of the first sacrificial gate material 220 and the second sacrificial gate material 224 can be accomplished using an etching process selected during the removal of the first sacrificial gate material 220 and the second sacrificial gate material 224, respectively. This etching exposes portions of the sacrificial dielectric liner 218. Note that the exposed portions of the sacrificial dielectric liner 218 are removed utilizing an etch selected in removing the sacrificial dielectric liner 218, while a portion of the sacrificial dielectric liner 218 remains along the sidewalls of the spacer dielectric material 230, for example, as shown in FIG. 45B. This remaining portion of the sacrificial dielectric liner may be referred to as sacrificial dielectric liner portion 218L. Each recessed sacrificial semiconductor nanosheet 206 of the first and second nanosheet stacks is removed utilizing an etch selected in removing the sacrificial semiconductor material relative to the semiconductor channel material.

[0101] As discussed above, the spacer dielectric material 230 functions as a stacked device isolation dielectric material layer having an opening 242 formed therein. In this embodiment, the spacer dielectric material 230, which functions as a stacked device isolation dielectric material layer, is laterally adjacent to the second dielectric insulating layer 217. The second dielectric insulating layer 217 is separated from the spacer dielectric material 230 by a portion of the sacrificial dielectric liner 218. Also, in this embodiment, the first dielectric insulating layer 216 is later positioned above the first FET device. These aspects of the present application will become more apparent in the processing steps described below.

[0102] 46A, 46B, and 46C, the exemplary structure shown in FIG. 45A, 45B, and 45C, respectively, is illustrated after forming the high-k gate dielectric material 244 and the a-Si layer 246. The high-k gate dielectric material 244 corresponds to the high-k gate dielectric material 134 described in the previous embodiment of the present application. The high-k gate dielectric material 244 may include one of the dielectric materials described above for the high-k gate dielectric material 134, have a thickness in the range described above for the high-k gate dielectric material 134, and be formed using one of the deposition processes described above for the high-k gate dielectric material 134. The high-k gate dielectric material 244 is formed on all physically exposed surfaces of the suspended semiconductor channel material nanosheets 208, the spacer dielectric material 230, the sacrificial dielectric liner portion 218L, and the second dielectric insulating layer 217. As described above in the previously illustrated embodiment, a deoxidization layer may be formed on the surface of the high-k gate dielectric material 244 prior to forming the a-Si layer 246. The a-Si layer 246 corresponds to the a-Si layer 136 in the previously illustrated embodiment of this application. As such, the a-Si layer 246 may be formed utilizing the same techniques as those described above for forming the a-Si layer 136 in the previously illustrated embodiment of this application.

[0103] 47A, 47B and 47C, the exemplary structure shown in FIG. 46A, 46B and 46C, respectively, is illustrated after forming a first gate cut dielectric structure 248 in a first portion of the modified gate kerf and partially into a second portion of the modified gate kerf. The modified gate kerf in this embodiment is the same as the modified gate kerf described in the previous embodiment of this application. Therefore, the above-mentioned processing steps in forming the modified gate kerf are also employed in this embodiment. However, the above-mentioned processing steps illustrated in FIG. 10A-FIG. 13C are employed in providing the modified gate kerf. As illustrated, the first gate cut dielectric structure 248 is formed into a portion of the dielectric material layer 202.

[0104] The first gate cut dielectric structure 248 corresponds to the first gate cut dielectric structure 142 described above for the previously illustrated embodiment of this application. Thus, the first gate cut dielectric structure 248 includes one of the dielectric materials described above for the first gate cut dielectric structure 142, and the first gate cut dielectric structure 248 can be formed utilizing the techniques described above for forming the first gate cut dielectric structure 142. It is noted that the first gate cut dielectric structure 248 penetrates an opening present in the spacer dielectric material 230 (i.e., the stacked device isolation dielectric layer). The first gate cut dielectric structure 248 has an extended portion (similar to the extended portion described for the first gate cut dielectric structure 142) that penetrates an opening present in the spacer dielectric material 230.

[0105] 48A, 48B, and 48C, there is shown the example structures shown in FIG. 47A, 47B, and 47C, respectively, after additional a-Si has been formed above the first gate cut dielectric structure 248 to fill the remaining volume of the second modified gate cut trench. The additional a-Si can be formed by deposition. In the present application, the additional a-Si re-establishes the integrity of the original a-Si layer 246. The additional a-Si is not shown separately in the drawings.

[0106] 49A, 49B, and 49C, the exemplary structures shown in FIGS. 48A, 48B, and 48C, respectively, are illustrated after forming a second gate cut dielectric structure 250 on the first gate cut dielectric structure 248. The second gate cut dielectric structure 250 corresponds to the second gate cut dielectric structure 144 described above in the previously illustrated embodiments of this application. Thus, the second gate cut dielectric structure 250 includes one of the dielectric materials described above for the second gate cut dielectric structure 144 in the previously illustrated embodiments of this application. The second gate cut dielectric structure 250 can be formed utilizing the same techniques described above in forming the second gate cut dielectric structure 144 (e.g., lithographically patterning the a-Si layer 236 to include openings and filling the openings with a dielectric material). In this embodiment, after the filling step, a planarization step is used to physically expose the top surface of the second ILD material layer 230, as shown in FIGS. 49A and 52C. However, the second gate cut dielectric structure 250 has a top surface that is coplanar with at least the second ILD material layer 240 .

[0107] 50A, 50B and 50C, the exemplary structure shown in FIG. 49A, 49B and 49C, respectively, is illustrated after removing the a-Si layer 246 located above the spacer dielectric material layer 230 to provide a gate cavity. Removal of the a-Si layer 246 located above the spacer dielectric material layer 230 includes a selective etch in removing the a-Si layer. At this point in the application, the deoxidization layer may also be removed by a selective etch that stops on the surface of the high-k gate dielectric material layer 244.

[0108] 51A, 51B and 51C, the exemplary structures shown in FIGS. 50A, 50B and 50C, respectively, are illustrated after forming a second gate electrode 251 on a physically exposed surface of the high-k gate dielectric material layer 244 located on a first set of suspended semiconductor channel material nanosheets 208 of the second nanosheet stack (left side of FIG. 51B) and forming another second gate electrode 252 on a physically exposed surface of the high-k gate dielectric material layer 244 located on a second set of suspended semiconductor channel material nanosheets 208 of another second nanosheet stack (right side of FIG. 51B), the device regions being separated by a second gate cut dielectric structure 250 and an enlarged portion of the first gate cut dielectric structure 248 passing through an opening in the spacer dielectric material 230.

[0109] The second gate electrode 251 corresponds to the second gate electrode 145 described above for the previously illustrated embodiment of the present application, and the further second gate electrode 252 corresponds to the further second gate electrode 146 described above for the previously illustrated embodiment of the present application. Thus, all WFMs and optional gate electrode materials described above for the second gate electrode 145 and the further second gate electrode 146 are applicable to the second gate electrode 251 and the further second gate electrode 252, respectively. Depending on the technique used to form the second gate electrode 251 and the further second gate electrode 252, the second gate electrode 251 and the further second gate electrode 252 may include compositionally the same WFM or compositionally different WFMs. In an embodiment, the second gate electrode 251 and the further second gate electrode 252 may include compositionally the same or compositionally different gate electrode materials. When the optional gate electrode material is present, the WFM is located between the gate electrode material and the high-k gate dielectric material layer. The second gate electrode 251 and the further second gate electrode 252 can be formed using one of the techniques described above for forming the second gate electrode 145 and the further second gate electrode 146 in the previously illustrated embodiments of this application.

[0110] 52A, 52B, and 52C, there is illustrated the exemplary structure shown in FIG. 51A, 51B, and 51C, respectively, after forming a second conductive-contact-containing ILD material layer 254, which includes a second source / drain contact structure 256 contacting the second source / drain region 238, a second gate contact structure 258 contacting the second gate electrode 251, a first gate contact structure 262, and a shared gate contact structure 260 embedded therein.

[0111] The second conductive-contact-containing ILD material layer 254 is the same as the second conductive-contact-containing ILD material layer 148 described above in the previously illustrated embodiments of this application. As such, the second conductive-contact-containing ILD material layer 254 is comprised of one of the dielectric materials described above for the second conductive-contact-containing ILD material layer 148, and the second conductive-contact-containing ILD material layer 254 may be formed utilizing one of the deposition techniques described above in forming the second conductive-contact-containing ILD material layer 148.

[0112] Each contact structure, i.e., second source / drain contact structure 256, second gate contact structure 258, first gate contact structure 262, and shared gate contact structure 260, can be formed by utilizing the techniques and materials described above for the various contact structures into the second conductive-contact-containing ILD material layer 148.

[0113] 53A, 53B, and 53C, the exemplary structures shown in FIGs. 52A, 52B, and 52C, respectively, are illustrated after forming back-end-of-the-line (BEOL) structures 264 and carrier wafer 266 on second conductive-contact-containing ILD material layer 254. BEOL structure 264 is the same as BEOL structure 162 described above in the previously illustrated embodiment of this application. Carrier wafer 266 is the same as carrier wafer 164 described in the previously illustrated embodiment of this application.

[0114] 54A, 54B, and 54C, the exemplary structure shown in FIG. 53A, 53B, and 53C, respectively, is illustrated after flipping the exemplary structure 180°, removing the semiconductor substrate 200, removing the dielectric material layer 202, and removing the physically exposed portion of the high-k dielectric material layer 244 located on the remaining portion of the a-Si layer 246. The flipping may be performed manually or by mechanical means such as, for example, a robotic arm. This flipping now physically exposes the surface of the semiconductor substrate 200 for further processing. The semiconductor substrate 200 may be removed utilizing one of the techniques described above for removing the semiconductor substrate 100 from the previously illustrated embodiments of this application. The removal of the semiconductor substrate 200 physically exposes the surface of the dielectric material layer 202 for further processing. The dielectric material layer 202 may be removed utilizing one of the techniques described above for removing the dielectric material layer 102 from the previously illustrated embodiments of this application. The removal of the semiconductor substrate dielectric material layer 202 physically exposes a portion of the high-k gate dielectric material layer 244 for further processing. However, etching may be performed after the removal of the dielectric material layer 202 to remove the adhesion layer from the high-k gate dielectric material layer 244. The removal of the dielectric material layer 202 also physically exposes portions of the inner spacer dielectric material 234 and the dielectric material structure 236 formed within the dielectric material layer 202. Also, a portion of the first gate cut dielectric structure 248 previously embedded in the dielectric material layer 202 is now physically exposed. The physically exposed portions of the high-k dielectric material layer 244 can be removed utilizing any etching process selected to remove the physically exposed portions of the high-k dielectric material layer 244.

[0115] 55A, 55B, and 55C, there is shown the exemplary structures shown in Figs. 54A, 54B, and 54C, respectively, after removal of the a-Si layer 246. The a-Si layer 246 can be removed utilizing an etch that is selective in removing the a-Si. At this point in the application, another etch can be used to selectively remove the deoxidized layer from the surface of the high-k gate dielectric material layer 244 such that the high-k gate dielectric material layer 244 is now exposed.

[0116] 56A, 56B and 56C, there is illustrated the exemplary structures shown in FIGS. 55A, 55B and 55C, respectively, after forming a first gate electrode 267 on a physically exposed surface of the high-k gate dielectric material layer 244 located on a first set of suspended semiconducting channel material nanosheets 208 of a first nanosheet stack and forming another first gate electrode 268 on a physically exposed surface of the high-k gate dielectric material layer 244 located on a second set of suspended semiconducting channel material nanosheets 208 of another first nanosheet stack, the device regions being separated by a first gate cut dielectric structure 248.

[0117] The first gate electrode 267 corresponds to the first gate electrode 165 described above for the previously illustrated embodiment of this application, and the further first gate electrode 268 corresponds to the further first gate electrode 166 described above for the previously illustrated embodiment of this application. Thus, all WFMs and optional gate electrode materials described above for the first gate electrode 165 and the further first gate electrode 166 are applicable to the first gate electrode 267 and the further first gate electrode 268, respectively. Depending on the technique used to form the first gate electrode 267 and the further first gate electrode 268, the first gate electrode 267 and the further first gate electrode 268 may include compositionally the same WFM or compositionally different WFMs. In an embodiment, the first gate electrode 267 and the further first gate electrode 268 may include compositionally the same or compositionally different gate electrode materials. When the optional gate electrode material is present, the WFM is located between the gate electrode material and the high-k gate dielectric material layer. The first gate electrode 267 and the further first gate electrode 268 can be formed utilizing one of the techniques described above for forming the first gate electrode 165 and the further first gate electrode 166 in the previously illustrated embodiments of this application. Note again that the first gate cut dielectric structure 248 has an enlarged portion that extends through an opening in the spacer dielectric material 230 (i.e., the stacked device isolation dielectric material layer), so that no WFM metal is shared between the various stacked device regions.

[0118] 57A, 57B, and 57C, there is shown the exemplary structure shown in Figures 56A, 56B, and 56C, respectively, after forming a backside gate dielectric cap layer 270. The backside gate dielectric cap layer 270 is formed by first recessing the high-k metal gates 268 and 244 from the backside of the wafer, followed by dielectric deposition and planarization.

[0119] 58A, 58B and 58C, the exemplary structures shown in Fig. 57A, 57B and 57C, respectively, are illustrated after recessing the dielectric material structure 236. The dielectric material structure 236 may be made recessed utilizing a recess etch process selected to remove the dielectric material structure 236. The recessed dielectric material structure 236 has a top surface that is below the bottom surface of the bottom semiconductor channel material nanosheet 208 of the first nanosheet stack.

[0120] 59A, 59B and 59C, the exemplary structures shown in FIG. 58A, 58B and 58C, respectively, are illustrated after forming the first source / drain regions 274. Prior to forming the first source / drain regions 274, the inner spacer dielectric material 234 is present along the sidewalls of the first nanosheet stack (the inner spacer dielectric material remains and forms the inner spacer 234S). Removal of the inner spacer dielectric material 234 present along the sidewalls of the first nanosheet stack can be performed using an isotropic etch-back process. Removal of the inner spacer dielectric material 234 exposes the sidewalls of each semiconductor channel material nanosheet 208 of the first nanosheet stack. The first source / drain regions 274 are then epitaxially grown outward from the physically exposed sidewalls of each semiconductor channel material nanosheet 208 of the first nanosheet stack. The first source / drain region 274 corresponds to the first source / drain region 116 described above in the previously illustrated embodiment of this application. The first source / drain region 247 can be composed of a semiconductor material and a dopant of opposite (or the same) conductivity type as the dopant present in the previously formed second source / drain region 238. In this embodiment, the first source / drain region 274 is separated from the second source / drain region 238 by the remaining portion of the inner spacer dielectric material 234 and the remaining portion of the dielectric material structure 236, see e.g., FIG. 59A.

[0121] 60A, 60B, and 60C, there is illustrated the example structure shown in Figures 59A, 59B, and 59C, respectively, after forming a first conductive-contact-containing ILD material layer 276, where the first conductive-contact-containing ILD material layer includes a first source / drain contact structure 278 contacting the first source / drain region 274. There is also a shared source / drain structure 280 contacting the second source / drain region 238 of the second FET device and the first source / drain region 274 of the first FET device. The first conductive-contact-containing ILD material layer 276 is the same as the first conductive-contact-containing ILD material layer 168 described above in the previously illustrated embodiments of this application. Thus, first conductive-contact-containing ILD material layer 276 is comprised of one of the dielectric materials described above for first conductive-contact-containing ILD material layer 168, and first conductive-contact-containing ILD material layer 276 may be formed utilizing one of the deposition techniques described above in forming first conductive-contact-containing ILD material layer 168. Each contact structure, i.e., first source / drain contact structure 278 and source / drain contact structure 280, may be formed into the other conductive-contact-containing ILD material layer utilizing the techniques and materials described above for the various contact structures.

[0122] 61A, 61B, and 61C, the exemplary structure shown in FIG. 60A, 60B, and 60C, respectively, is illustrated after forming a backside interconnect and BSPDN structure 282 on the first conductive-contact-containing ILD material layer 276. The backside interconnect and BSPDN structure 282 may be the same as the BSPDN structure 172 described above in the previously illustrated embodiment of this application, or may include an additional signal line near the metal line for the power supply.

[0123] While the present application has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

1. a first field effect transistor (FET) device stacked on a second FET device, the first FET device including a first functional gate structure including a first workfunction metal and the second FET device including a second functional gate structure including a second workfunction metal; a stacked device isolation dielectric material layer located between the first FET device and the second FET device; a first gate cut dielectric structure located laterally adjacent to the first FET device; a second gate cut dielectric structure located laterally adjacent to the second FET device; a portion of the first gate cut dielectric structure extends through an opening in the stacked device isolation dielectric material layer and is laterally adjacent to the second FET device.

2. 2. The semiconductor structure of claim 1 , wherein the portion of the first gate cut dielectric structure that penetrates the opening has an enlarged width compared to a width of a portion of the first gate cut dielectric structure that does not penetrate the opening and is laterally adjacent to the first FET device, the enlarged width preventing the first workfunction metal from being present in the second FET device and the second workfunction metal from being present in the first FET device.

3. 3. The semiconductor structure of claim 2 wherein said portion of said first gate cut dielectric structure that passes through said opening directly contacts a surface of said second gate cut dielectric structure.

4. 10. The semiconductor structure of claim 1 wherein said first FET device comprises at least one semiconducting nanosheet and said second FET device comprises at least one semiconducting fin.

5. 10. The semiconductor structure of claim 1 wherein said first FET device comprises at least one semiconductor nanosheet and said second FET device comprises at least one semiconductor nanosheet.

6. 3. The semiconductor structure of claim 2 further comprising another first FET device located laterally adjacent to said first FET device and separated by said first gate cut dielectric structure, said another first FET device including a third functional gate structure having a third workfunction metal.

7. 7. The semiconductor structure of claim 6, further comprising: another second FET device located laterally adjacent to said second FET device and separated by said second gate cut dielectric structure and said portion of said first gate cut dielectric structure that penetrates said opening, said another second FET device including a fourth functional gate structure having a fourth workfunction metal.

8. 3. The semiconductor structure of claim 2, wherein said first gate cut dielectric structure contacts a first surface of a first conductive-contact-containing interlayer dielectric (ILD) material layer, said first conductive-contact-containing ILD material layer including a first source / drain contact structure contacting a source / drain region of said first FET device.

9. 10. The semiconductor structure of claim 8 further comprising a backside power delivery network located on a second surface of said first conductive-contact-containing ILD material layer opposite said first surface of said first conductive-contact-containing ILD material layer.

10. the second gate disconnect dielectric structure contacting a first surface of the second conductive-contact-containing ILD material layer; the second conductive-contact-containing ILD material layer includes a second source / drain contact structure contacting a source / drain region of the second FET device, a second gate contact structure contacting the second functional gate structure, a shared gate contact structure contacting both the first functional gate structure and the second functional gate structure, and a second gate contact structure contacting the first functional gate structure but not the second functional gate structure; 3. The semiconductor structure of claim 2.

11. 11. The semiconductor structure of claim 10 further comprising a back-end-of-the-line structure located on a second surface of said second conductive-contact-containing ILD material layer opposite said first surface of said second conductive-contact-containing ILD material layer.

12. 10. The semiconductor structure of claim 1 wherein said first functional gate structure and said second functional gate structure further comprise a high-k gate dielectric material layer, said high-k gate dielectric material layer contacting a surface of said stacked device isolation dielectric material layer.

13. 3. The semiconductor structure of claim 2 wherein said stacked device isolation dielectric material layer is located laterally adjacent to a dielectric insulating layer located between said first FET device and said second FET device.

14. 14. The semiconductor structure of claim 13 wherein said dielectric insulating layer is separated from a spacer dielectric material by a sacrificial dielectric liner portion.

15. 15. The semiconductor structure of claim 14 wherein another dielectric insulating layer is positioned above said first FET device.

16. 16. The semiconductor structure of claim 15 further comprising a high-k gate dielectric material overlying said dielectric insulating layer and said another dielectric insulating layer.

17. 14. The semiconductor structure of claim 13 wherein said first FET device further comprises a first source / drain region separated from a second source / drain region of said second FET device by an inner spacer dielectric material and a dielectric material structure.

18. 13. The semiconductor structure of claim 12 wherein said first FET device is a first nanosheet FET device and said second FET device is a second nanosheet device.

19. 13. The semiconductor structure of claim 12 further comprising another first FET device located laterally adjacent to said first FET device and separated by said first gate cut dielectric structure, said another first FET device including a third functional gate structure having a third workfunction metal.

20. 20. The semiconductor structure of claim 19, further comprising: another second FET device located laterally adjacent to said second FET device and separated by said portion of said first gate cut dielectric structure that penetrates said second gate cut dielectric structure and said opening, said another second FET device including a fourth functional gate structure having a fourth workfunction metal.

21. 13. The semiconductor structure of claim 12, wherein said first gate cut dielectric structure contacts a first surface of a first conductive-contact-containing interlayer dielectric (ILD) material layer, said first conductive-contact-containing ILD material layer including a first source / drain contact structure contacting a source / drain region of said first FET device.

22. 22. The semiconductor structure of claim 21 further comprising a backside power delivery network located on a second surface of said first conductive-contact-containing ILD material layer opposite said first surface of said first conductive-contact-containing ILD material layer.

23. the second gate disconnect dielectric structure contacting a first surface of the second conductive-contact-containing ILD material layer; the second conductive-contact-containing ILD material layer includes a second source / drain contact structure contacting a source / drain region of the second FET device, a second gate contact structure contacting the second functional gate structure, a shared gate contact structure contacting both the first functional gate structure and the second functional gate structure, and a second gate contact structure contacting the first functional gate structure but not the second functional gate structure; 13. The semiconductor structure of claim 12.

24. 24. The semiconductor structure of claim 23 further comprising a back-end-of-the-line structure located on a second surface of said second conductive-contact-containing ILD material layer opposite said first surface of said second conductive-contact-containing ILD material layer.

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