Searching for the best read reference voltage for 3D NAND memory

Abstract

The memory system includes a memory controller configured to determine a first best read offset of a first best read reference voltage relative to a first default read reference voltage and configured to determine an anchor read reference voltage having the same offset as the first best read offset relative to a second default read reference voltage. The first and second default read reference voltages are set for reading a page from a set of MLCs in a semiconductor memory device. A first scan range may be determined based on the anchor read reference voltage. A second best read offset of the second best read reference voltage relative to the second read reference voltage may be determined by searching in the first scan range. A read process may be performed to read the page from the set of MLCs based on the first and second best read reference voltages.

Description

[Technical field]

[0001] This application relates to three-dimensional (3D) NAND flash memory operating technology. [Background technology]

[0002] Three-dimensional (3D) NAND flash memory employs state-of-the-art multi-level cell (MLC) technology to provide high storage density. A read-retry mechanism is used to improve the reliability of 3D NAND flash memory. For example, multiple retry steps with adjusted read reference voltage values ​​may be implemented to read a target page multiple times before the encoded page can be accurately decoded. A large number of read-retry operations may significantly increase the read latency and deteriorate the performance of the memory system. Summary of the Invention [Means for solving the problem]

[0003] An aspect of the present disclosure provides a method of a memory system. The method may include determining a first best read offset of a first best read reference voltage relative to a first default read reference voltage, and determining an anchor read reference voltage with the same offset as the first best read offset relative to a second default read reference voltage. The first default read reference voltage and the second default read reference voltage are set for reading a page from a set of multi-level cells (MLCs) in a semiconductor memory device of the memory system. A first scan range may be determined based on the anchor read reference voltage. An upper limit of the first scan range is the anchor read reference voltage plus an upper limit offset, and a lower limit of the first scan range is the anchor read reference voltage plus a lower limit offset. The upper limit offset and the lower limit offset may be positive or negative voltage values. A second best read offset of a second best read reference voltage relative to the second read reference voltage may be determined based on the first scan range.

[0004] In an embodiment, determining a first best read offset includes determining a second scan range, the second scan range having an upper limit that is the first default read reference voltage plus an upper limit offset and a lower limit that is the first default read reference voltage plus a lower limit offset; scanning the second scan range based on the coarse step voltage by performing a series of first single read operations within the second scan range, each first single read operation corresponding to a first read reference voltage, each first single read operation generating a bit count of either 1 or 0; The method includes determining, for each first single read operation, a first bit count difference between the bit count of the respective first single read operation and the bit count of a previous first single read operation, if available, and a second bit count difference between the bit count of the respective first single read operation and the bit count of a subsequent first single read operation, if available, and determining a first read reference voltage of a first single read operation in which a sum of the respective first bit count difference and the respective second bit count difference has a smallest value among the series of first single read operations to be the coarse best read reference voltage.

[0005] In an embodiment, the method may further include, when there are two or more first single read operations in which the sum of the respective first bit count differences and the respective second bit count differences have the same value, determining the first read reference voltage of the first single read operation in which the minimum value of the respective first bit count differences and the respective second bit count differences is the minimum value among the two or more first single read operations to be the coarse best read reference voltage.

[0006] In an embodiment, the method includes determining a third scan range, the third scan range having an upper limit that is a coarse best read reference voltage plus a coarse step voltage and a lower limit that is the coarse best read reference voltage minus the coarse step voltage; scanning the third scan range based on the fine step voltage by performing a series of second single read operations within the third scan range, each second single read operation corresponding to a second read reference voltage, each second single read operation generating a bit count of either 1 or 0; and for each second single read operation, determining a bit count of each second single read operation, if available, based on the fine step voltage. determining a first bit count difference between the bit count of the previous second single read operation and a bit count of a previous second single read operation, if available, and a second bit count difference between the bit count of each second single read operation and a bit count of a subsequent second single read operation; and determining a second read reference voltage of a second single read operation in which a sum of the respective first bit count difference and the respective second bit count difference has a minimum value among the series of second single read operations to be a first best read reference voltage, wherein an offset of the first best read reference voltage relative to the first default read reference voltage is the first best read offset.

[0007] In an embodiment, determining a second best read offset of the second best read reference voltage relative to the second default read reference voltage based on the first scan range includes scanning the first scan range by performing a series of third single read operations within the first scan range, each third single read operation corresponding to a third read reference voltage, each third single read operation generating a bit count of either 1 or 0; and for each third single read operation, comparing the bit count of the respective third single read operation with the bit count of a previous third single read operation, if available. determining a first bit count difference between the bit counts of each third single read operation and, if available, a second bit count difference between the bit counts of the respective third single read operation and the bit count of the subsequent third single read operation, and determining a third read reference voltage of the third single read operation in which a sum of the respective first bit count difference and the respective second bit count difference has a minimum value among the series of third single read operations to be a second best read reference voltage, where an offset of the second best read reference voltage relative to the second default read reference voltage is the second best read offset. In an example, the first single read operation, the second single read operation, and the third single read operation are fractional page read operations.

[0008] In an embodiment, the method may further include collecting a first set of first best read offsets, each of which is a voltage shift of a best read reference voltage from a first default read reference voltage, each of which corresponds to a memory cell condition that causes a set of memory cells to have a respective first best read offset, and each of which has a positive value or a negative value; setting a maximum value of the first set of first best read offsets to be an upper offset of a second scan range; and setting a minimum value of the first set of first best read offsets to be a lower offset of the second scan range.

[0009] In an embodiment, the method may further include collecting a second set of second best read offsets, each of which corresponds to the first set of first best read voltages and one of the respective memory cell conditions, each of which is a voltage shift of the best read reference voltage from the second default read reference voltage, and each of which has a positive or negative value; determining a difference between each pair of the first best read offset and each of the second best read offsets, the difference being equal to the respective second best read offset minus the respective first best read offset; setting a maximum value of the difference between each pair of the first best read offset and each of the second best read offsets to be an upper offset of the first scan range; and setting a minimum value of the difference between each pair of the first best read offset and each of the second best read offsets to be a lower offset of the first scan range.

[0010] In an embodiment, the method may further include determining that an error correction code (ECC) decoding process failed to read the page prior to the step of determining the first best read offset of the first best read reference voltage relative to the first default read reference voltage. In an embodiment, an ECC software decoding process is performed to read the page from the set of MLCs based on the first best read reference voltage and the second best read reference voltage. In an embodiment, the first or second default read reference voltage corresponds to a default read reference voltage of the MLC.

[0011] Aspects of the present disclosure provide a non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform a method.

[0012] An aspect of the present disclosure provides a memory system. The memory system may include a semiconductor memory device and a memory controller that operates the semiconductor memory device. The memory controller may include a circuit. The circuit is configured to determine a first best read offset of a first best read reference voltage relative to a first default read reference voltage, and to determine an anchor read reference voltage having the same offset as the first best read offset relative to a second default read reference voltage. The first default read reference voltage and the second default read reference voltage are set for reading a page from a set of multi-level cells (MLCs) in a semiconductor memory device in the memory system. A first scan range may be determined based on the anchor read reference voltage. An upper limit of the first scan range is the anchor read reference voltage plus an upper limit offset, and a lower limit of the first scan range is the anchor read reference voltage plus a lower limit offset. The upper limit offset and the lower limit offset may be positive or negative voltage values. A second best read offset of a second best read reference voltage relative to the second read reference voltage may be determined based on the first scan range.

[0013] The present disclosure can be understood from the following detailed description when read in conjunction with the accompanying drawings, in which: It should be noted that, in accordance with standard practice in the industry, various features have not been drawn to scale, and in fact, dimensions of various features may be increased or decreased for clarity of discussion. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1 is a block diagram of a system 100 having a memory device in accordance with some aspects of the present disclosure. [Figure 2A] FIG. 1 is a diagram of an example memory system in accordance with some aspects of the present disclosure. [Figure 2B] FIG. 1 is a diagram of an example memory system in accordance with some aspects of the present disclosure. [Diagram 3] 3 is a schematic circuit diagram of a memory device 300 including peripheral circuits, in accordance with some aspects of the present disclosure. [Figure 4] FIG. 2 is a diagram of an example of a peripheral circuit in accordance with some aspects of the present disclosure. [Diagram 5] 3 is a schematic diagram of a threshold voltage distribution of memory cells according to an embodiment of the present disclosure. [Figure 6] 11 is a diagram showing a state in which the memory cell threshold voltage distribution is shifted. [Figure 7] FIG. 7 is a diagram of a read process 700 according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram of a search process 800 for best read level based on Failed Bit Count (FBC), according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a diagram of a Bit Count Difference (BCD) table 900 for determining the best read level from a series of read levels (scan points) during the scanning process. [Figure 10A] FIG. 10 illustrates a BCD-based best read level search process 1000 according to an embodiment of the present disclosure. [Figure 10B]FIG. 10 illustrates a BCD-based best read level search process 1000 according to an embodiment of the present disclosure. [Figure 11A] 11A-11C are diagrams of two tables 1110 and 1120 to illustrate how to optimize the scan range used for the coarse search in the BCD-based search process 1000 according to an embodiment of the present disclosure. [Figure 11B] 11A-11C are diagrams of two tables 1130 and 1140 to illustrate how to optimize the scan range used for fine searching in the BCD-based search process 1000 according to an embodiment of the present disclosure. [Figure 12A] FIG. 2 is a diagram of a search process for best read level according to an embodiment of the present disclosure. [Figure 12B] FIG. 2 is a diagram of a search process for best read level according to an embodiment of the present disclosure. [Figure 12C] FIG. 2 is a diagram of a search process for best read level according to an embodiment of the present disclosure. [Figure 13] FIG. 13 illustrates a process 1300 for searching for the best read level according to an embodiment of the present disclosure. [Figure 14A] 1 is a diagram of a performance comparison between a first best read search process and a second best read search process according to an embodiment of the present disclosure. [Figure 14B] 1 is a diagram of a performance comparison between a first best read search process and a second best read search process according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. The present disclosure can also be used in a variety of other applications. The functional and structural features as described in the present disclosure can be combined, coordinated, and modified with one another in ways not explicitly depicted in the drawings, such that the combinations, coordination, and modifications are within the scope of the present disclosure.

[0016] Generally, terms can be understood, at least in part, from usage in context. For example, the term "one or more" as used herein can be used to describe a feature, structure, or characteristic in the singular sense, or can be used to describe a combination of features, structures, or characteristics in the plural sense, depending at least in part on the context. Similarly, terms such as "one" or "the" can be understood to convey a singular use or to convey a plural use, depending at least in part on the context. Also, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but instead may allow for the presence of additional factors not necessarily explicitly recited, depending at least in part on the context.

[0017] Although the present disclosure is not limited to three-dimensional (3D) NAND memory devices, 3D NAND devices may be used in some examples to illustrate the concepts of the present invention. For example, the techniques described herein may be applied to planar NAND memory devices.

[0018] Aspects of the present disclosure provide methods and techniques for searching for a best read reference voltage (best read level). The best read level can then be used for read retry or software decode processing. In an embodiment, a scan process can be performed across multiple scan points in a scan voltage range (scan range) corresponding to the read level. A series of single read operations can be performed at each scan point across a word line memory cell string that stores one or more pages of data. Each single read operation can output a bit count. A best read level can be determined based on a bit count difference between two consecutive single read operations. Thus, the search process does not rely on known data stored in the memory cells.

[0019] Also, a scan range optimization method is provided to accelerate the best level search process. For example, data of a first best read offset for a first default read reference voltage and a second best read offset for a second default read reference voltage corresponding to different memory cell conditions can be collected. A voltage difference range between the voltage value of the first best read offset and the voltage value of the respective second best read offset can be determined. The best read level resulting from the first search process at the first read level can be used as an anchor voltage for the second search process at the second read level. A search range for the second search process can be determined based on the voltage difference range around the anchor voltage.

[0020] FIG. 1 illustrates a block diagram of a system 100 having a memory device according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device. As illustrated in FIG. 1, the system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be an electronic device such as a central processing unit (CPU) or a processor of a system-on-chip (SoC) such as an application processor (AP). The host 108 may be configured to transmit data to or receive data from the memory device 104. The memory device 104 may be any memory device disclosed in the present disclosure.

[0021] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and can communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in high duty cycle environments, such as solid state drives (SSD) or embedded multimedia cards (eMMC) used as data storage devices for portable devices such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays.

[0022] The memory controller 106 may be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions with respect to data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some embodiments, the memory controller 106 is further configured to process error correction codes (ECC) with respect to data read from or written to the memory device 104. Any other suitable functions may also be performed by the memory controller 106, such as, for example, formatting the memory device 104. Consistent with some aspects of the present disclosure, in some embodiments, the memory controller 106 is configured to implement, in whole or in part, a best read reference voltage search method as described herein.

[0023] The memory controller 106 can communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the external device through at least one of a variety of interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0024] The memory controller 106 and the one or more memory devices 104 can be integrated into various types of storage devices and can be included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package, that is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0025] In one example, as shown in FIG. 2A, the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. The memory card 202 may be a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a SmartMedia (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may further include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG. 1). In another example, as shown in FIG. 2B, the memory controller 106 and the multiple memory devices 104 may be integrated into an SSD 206. The SSD 206 may further include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 in FIG. 1). In some embodiments, the storage capacity and / or operating speed of SSD 206 is greater than the storage capacity and / or operating speed of memory card 202 .

[0026] FIG. 3 shows a schematic circuit diagram of a memory device 300 including peripheral circuits according to some embodiments of the disclosure. The memory device 300 may be an example of the memory device 104 in FIG. 1. The memory device 300 may include a memory cell array 301 and peripheral circuits 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array in which memory cells 306 are provided in the form of an array of NAND memory strings 308 each extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the area of ​​the memory cell 306. Each memory cell 306 may be either a floating gate type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor.

[0027] In some embodiments, each memory cell 306 is a single level cell (SLC) that has two possible memory states and can store one bit of data. For example, a first memory state "0" can correspond to a first range of voltages, and a second memory state "1" can correspond to a second range of voltages. In some embodiments, each memory cell 306 is a multi-level cell (MLC) that can store more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell (also known as a double level cell (DLC)), three bits per cell (also known as a triple level cell (TLC)), or four bits per cell (also known as a quad level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. The fourth nominal memory value may be used for the erased state.

[0028] As shown in FIG. 3, each NAND memory string 308 may include a source select gate (SSG) 310 (also referred to as a source select transistor) at its source end and a drain select gate (DSG) 312 (also referred to as a drain select transistor) at its drain end. The SSG 310 and DSG 312 may be configured to activate a selected NAND memory string 308 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same block 304 are coupled through the same source line 314, e.g., a common source line (SL). In other words, all the NAND memory strings 308 in the same block 304 have an array common source (ACS) according to some embodiments. The DSG 312 of each NAND memory string 308 is coupled to a respective bit line 316 through which data may be read or written via an output bus (not shown) according to some embodiments. In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of a transistor comprising DSG 312) or a deselect voltage (e.g., 0V) to each DSG 312 via one or more DSG lines 313, and / or by applying a select voltage (e.g., above the threshold voltage of a transistor comprising SSG 310) or a deselect voltage (e.g., 0V) to each SSG 310 via one or more SSG lines 315.

[0029] As shown in FIG. 3, the NAND memory strings 308 may be organized into multiple blocks 304, each of which may have a common source line 314, such as coupled to an ACS. In some embodiments, each block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 in the same block 304 are erased simultaneously. To erase memory cells 306 in a selected block 304, the source line 314 coupled to the selected block 304 and the unselected blocks 304 in the same plane as the selected block 304 may be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20V or more). In some examples, the erase operation may be performed at a half-block level, a quarter-block level, or a level having any suitable number of blocks or any suitable fraction of a block.

[0030] Memory cells 306 of adjacent NAND memory strings 308 are coupled through word lines 318 that select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is the basic data unit for program operations. The size of one page 320 in bits can be related to the number of NAND memory strings 308 coupled by word lines 318 in one block 304. For ease of description, the memory cells 306 in one page 320 can be coupled to the same word line 318, and the terms "page" and "word line" can be used interchangeably in this disclosure. However, in some examples, the memory cells 306 in one page 320 can be coupled to more than one word line 318. Each word line 318 can include multiple control gates (gate electrodes) at each memory cell 306 in the respective page 320 and gate lines connecting the control gates together. In some embodiments, each word line 318 can be coupled to multiple pages (or a portion of a page) of memory cells based on the control of the SSGs and DSGs.

[0031] The peripheral circuitry 302 may be coupled to the memory cell array 301 through bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of the memory cell array 301 by applying voltage and / or current signals to and sensing voltage and / or current signals from each targeted memory cell 306 through the bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuitry 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology.

[0032] For example, Figure 4 shows several peripheral circuits including page buffer / sense amplifiers 404, column decoder / bit line drivers 406, row decoder / word line drivers 408, voltage generators 410, control logic 412, registers 414, interface 416, and data bus 418. It will be understood that in some examples, additional peripheral circuits not shown in Figure 4 may also be included.

[0033] The page buffer / sense amplifier 404 may be configured to read data from and program (write) data to the memory cell array 301 according to control signals from the control logic 412. In one example, the page buffer / sense amplifier 404 may store a page of program data (write data) for programming into a page 320 of the memory cell array 301. In another example, the page buffer / sense amplifier 404 may perform a program verify operation to ensure that data has been properly programmed into the memory cells 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 404 may sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 406 may be configured to be controlled by the control logic 412 and to select one or more NAND memory strings 308 by applying a bit line voltage generated from the voltage generator 410.

[0034] The row decoder / word line driver 408 can be configured to be controlled by the control logic 412 and can be configured to select / deselect the block 304 of the memory cell array 301 and to select / deselect the word line 318 of the block 304. The row decoder / word line driver 408 can be further configured to drive the word line 318 using a word line voltage generated from the voltage generator 410. In some embodiments, the row decoder / word line driver 408 can also select / deselect and drive the SSG line 315 and the DSG line 313. As described in more detail below, the row decoder / word line driver 408 is configured to apply a read voltage to the selected word line 318 in a read operation on the memory cell 306 coupled to the selected word line 318. The read voltage can be either a read voltage corrected with an empty block based read offset when the read voltage is applied to the word line 318 in an empty block, or a default read voltage without an empty block based read offset when the read voltage is applied to the word line 318 in a full block.

[0035] Voltage generator 410 may be controlled by control logic 412 and configured to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages supplied to memory cell array 301. As described in more detail below, depending on whether a read operation is performed on an empty block or a full block, control logic 412 may control voltage generator 410 to provide a default read voltage or a corrected read voltage having an offset from the default read voltage to row decoder / word line driver 408.

[0036] The control logic 412 may be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The registers 414 may be coupled to the control logic 412 and may include status registers, instruction registers, and address registers for storing status information, instruction operation codes (OP codes), and instruction addresses for controlling the operation of each of the peripheral circuits. As described in detail below, the status registers of the registers 414 may comprise one or more registers configured to store free block information, such as having an ADSV list, indicating free blocks of all the blocks 304 in the memory cell array 301. In some embodiments, the free block information also indicates the last programmed page of each free block.

[0037] 5 shows a schematic diagram of a threshold voltage distribution of memory cells according to an embodiment of the present disclosure. The horizontal axis represents the threshold voltage of the memory cells (denoted as Vth). The vertical axis represents the number of memory cells corresponding to different threshold voltages.

[0038] In FIG. 5, the memory cells may be memory cells in a 3D NAND memory device corresponding to a page, a codeword, a word line memory cell string, a block, a plane, a die, etc. The memory cells are TLC and may be programmed (or erased) to be one of eight states (memory states), denoted S0-S7. Memory cells that are programmed (or erased) to be in a particular state may have threshold voltages that are distributed within a voltage range. Thus, in FIG. 5, each state (S0-S7) is shown to have a threshold voltage distribution. In some examples, these distributions may each be modeled using a Poisson distribution.

[0039] A TLC memory cell can represent three bits depending on which state the memory cell is in. In other words, three bits can be encoded in one of eight states. The mapping between states and each of the three bits can vary in different embodiments. In FIG. 5, the eight states S0-S7 are mapped to 111, 110, 100, 000, 010, 011, 001, and 101, respectively. The least significant bit (LSB) of the eight states can belong to a lower page. The middle significant bit (CSB) of the eight states can belong to a middle page. The most significant bit (MSB) of the eight states can belong to an upper page.

[0040] In FIG. 5, seven default read reference voltages V1-V7 are positioned between respective memory cell threshold voltage distributions. Ideally, each memory cell threshold voltage distribution can be included within two neighboring default read reference voltages. In other words, it is desired that a programmed or erased memory cell can remain in its intended state and thereby maintain the three bits represented. However, the memory cell threshold distribution may shift or expand from one distribution to another distribution due to, for example, program / erase (P / E) cycles, retention period, write or read disturb, temperature change, etc. Such a change in the memory cell threshold distribution may cause a read error.

[0041] For a particular default read reference voltage, if the memory cell has a threshold voltage below the default read reference voltage, the memory cell is said to be in a lower state. If the memory cell has a threshold voltage above the default read reference voltage, the memory cell is said to be in an upper state. Also, in FIG. 5, states to the right of the default read reference voltage are referred to as upper states relative to the default read reference voltage. States to the left of the default read reference voltage are referred to as lower states relative to the default read reference voltage.

[0042] Corresponding to different MLC technologies, different sets of default read reference voltages may be used. For example, SLC may use one default read reference voltage to distinguish two states. DLC may use three default read reference voltages to distinguish four states. QLC may use 15 default read reference voltages to distinguish 16 states.

[0043] FIG. 6 illustrates a situation where the memory cell threshold voltage distributions are misaligned. Distributions D1 and D2 (dashed lines) represent ideal memory cell threshold voltage distributions corresponding to two neighboring states (such as S1 and S2 in FIG. 5). V default A default read reference voltage 601, denoted as D1, is positioned between distributions D1 and D2. Corresponding to an ideal threshold voltage distribution, the memory cell is in a state that accurately represents or maps to an encoded bit of data programmed into the memory cell. Typically, the state of the memory cell at the time the memory cell is being programmed may be the ideal distribution. Stated differently, the memory cell at the time the memory cell is being programmed may have an ideal distribution of threshold voltages (or states).

[0044] Corresponding to distributions D1 and D2, when a single read operation is performed using the default read reference voltage 601, the memory cells belonging to distribution D2, for example, are in a state of 0 (V default A memory cell belonging to distribution D1, for example, is detected as being in a 1 state (indicating that the memory cell has a threshold voltage greater than V default5. When a set of memory cells is programmed, the set of memory cells are detected to have a threshold voltage less than the threshold voltage distribution (indicating that the set of memory cells has a threshold voltage less than the threshold voltage distribution), resulting in a bit of 1. Those detected bits correspond to the ideal threshold voltage distribution, or state, of the memory cells at the time they are being programmed. Thus, those bits are referred to as original bits or ideal bits with respect to the corresponding default read reference voltage 601. It should be noted that when the data to be programmed into the set of memory cells is known, the ideal state of the set of memory cells (e.g., states S0-S7 in FIG. 5) may be determined based on the data without a read operation. Thus, original bits may be derived or calculated when the associated data is known. Thus, original bits may also be used to refer to derived or calculated bits in the context of determining erroneous bits based on known data.

[0045] A read operation at a single read reference voltage (eg, a default or non-default read reference voltage) is referred to as a single read operation, as compared to a page read operation, in which multiple read operations occur at multiple different read reference voltages.

[0046] Distributions D1' and D2' represent the actual memory cell threshold voltage distributions when the results of the ideal distributions D1 and D2 deviate. Under the actual distributions, when a single read operation is performed using the default read reference voltage 601, the memory cell threshold voltages belong to distribution D2', but V default The memory cells each having a smaller threshold value are in, for example, a state of 1 (V default These memory cells will be detected as having a lower threshold voltage (indicating that the memory cells have a lower threshold voltage), resulting in a bit of 1. Thus, the original bit 0 represented by these memory cells will be flipped to become a 1. These flipped bits are referred to as upper state flipped bits when the respective memory cells change state from a higher state to a lower state.

[0047] It belongs to distribution D1', but V defaultThe memory cells each having a larger threshold value are, for example, in a 0 state (V default The memory cells D1′ and D2′ will be detected to be in states 1 and 0, indicating that the memory cells have a higher threshold voltage than the lower state, resulting in a bit 0. Thus, the original bit 1 represented by these memory cells will be inverted to be a 0. These inverted bits are referred to as lower state inverted bits when the respective memory cells change state from a lower state to a higher state. Besides the memory cells associated with lower or upper state inverted bits, other memory cells belonging to distributions D1′ and D2′ can still be correctly detected to be in states 1 and 0, respectively.

[0048] During a page read operation (including multiple single read operations), flipped bit errors from multiple single read operations can result in bit errors in the codeword of the page. When the Raw Bit Error Rate (RBER) of a codeword reaches a level that exceeds the ECC correction capability, the associated data (e.g., corresponding to a page) cannot be retrieved, resulting in ECC decoding failure. To achieve successful ECC correction, it is desirable to reduce the number of flipped bits in a single read operation.

[0049] This disclosure provides techniques and methods for searching for the best read reference voltage to minimize or reduce the number of flipped bits. opt 6 shows an optimum read reference voltage 602, denoted as . The optimum read reference voltage 602 may be a read reference voltage where the magnitude of flipped bits (including flipping from 1 to 0 or from 0 to 1) is smallest compared to other read reference voltages in the search range 610. A best read reference voltage 603 may be an output of the search process and is close to the optimum read reference voltage 602. The discrepancy between the best read reference voltage 603 and the optimum read reference voltage 602 may be limited to be within an accuracy as set in each search process.

[0050] As shown, the search range 610 may have an upper offset 612 and a lower offset 611 defined relative to the default read reference voltage 601. Thus, the upper limit of the search range 610 may be the default read reference voltage 601 plus the upper offset 612. The lower limit of the search range 610 may be the default read reference voltage 601 plus the lower offset 611 (which has a negative value).

[0051] 7 illustrates a read process 700 according to an embodiment of the present disclosure. The process 700 may be performed by the memory controller 106 to read data (such as a page or an upper page) from the 3D NAND memory device 104. The process 700 begins at S711.

[0052] At S711, a read operation may be performed, for example, to read a page from memory device 104. The page may be one of a lower page, a middle page, or an upper page stored in a set of TLCs. Thus, multiple single read operations, each based on a default read reference voltage, may be performed on memory cells storing the page. For example, corresponding to the mapping between the three bits and the eight states (S0-S7) in FIG. 5, three single read operations at default read reference voltages V2, V4, and V6 may be performed to read the middle page. The bits resulting from each single read operation may be processed to generate raw bits of a codeword belonging to the page.

[0053] In S712, ECC decoding may be performed based on the raw bits of the codeword. Various types of ECC (Low Density Parity Code (LDPC)) may be used in various embodiments. In S713, it is determined whether the ECC decoding is successful. When the RBER of the codeword exceeds the ECC correction capability, the ECC decoding of the page will fail. When the ECC decoding fails, the process 700 proceeds to S714. Otherwise, the process 700 proceeds to S716, where it ends.

[0054] In S714, tuning of the read reference voltage is performed to determine a new read reference voltage. In S715, a read retry is performed based on the new read reference voltage. The operation in S715 may be similar to the operation in S711, but with an updated read reference voltage. Based on the generated codeword raw bits from S715, a second iteration of ECC decoding may be performed in S712. The read retry may be repeated until process 700 reaches S716 or until the available read reference voltage for the read retry is exhausted.

[0055] When a read error occurs (at S713), in various embodiments, there may be various methods for read error handling. In some examples, a read-retry table is used for read-retry processing. One or more lists of read reference voltages for read-retry may be provided in the read-retry table, for example, by the manufacturer of each 3D NAND memory device or memory system (such as SSD). Typically, the read-retry table is built based on consideration of a limited number of factors, such as retention period, read disturb, cross temperature, first read problems, etc. Thus, the read-retry table may not be comprehensive for all situations.

[0056] In some embodiments, the best read reference voltage search method disclosed herein may be employed in place of or in addition to using a read-retry table to determine the next read retry reference voltage.

[0057] In some embodiments, after an ECC decoding failure, a best read reference voltage search method is launched to find the best read reference voltage. The best read reference voltage can then be used as a base voltage for a software LDPC decoding process. In an example of a software LDPC decoding process, multiple read-retry read reference voltages can be set around the best read reference voltage. Thus, multiple read retry operations can be performed in a (step-wise) manner to obtain a log-likelihood ratio (LLR). The LLR can be fed into an ECC engine (which may be separate from the memory controller 106 or may be part of the memory controller 106) for software decoding of the codeword.

[0058] 8 illustrates a process 800 for searching for a best read level based on failed bit count (FBC) in accordance with an embodiment of the present disclosure. The term best read level herein refers to a best read reference voltage level. Process 800 may be performed in a laboratory environment where known data is programmed into, such as a block of memory cells in a memory device.

[0059] The process 800 may include multiple coarse or fine scan processes. Each scan process may cover a search range of read reference voltages with step voltages. At each scan point (corresponding to a particular read reference voltage level, or read level), the read bits resulting from a single read operation may be compared to the original bits to determine the FBC (magnitude of flipping bits from 0 to 1 or 1 to 0). The original bits may be derived based on known data. The read level with the smallest FBC may be determined to be the best read level for each scan process. The search range may be defined relative to each default read reference voltage (or referred to as the default voltage). The best read level may be expressed as a best read offset relative to the default voltage.

[0060] The process 800 may include one step of coarse scanning (S810) and two steps of fine scanning (S820 and S830). TLC is used as an example for explaining the process 800.

[0061] In S810, a coarse scan is performed on the word line cell strings with default voltages. The default voltages may be, for example, V1-V7, which are all default voltages configured for the TLC. The word line cell strings may include memory cells controlled by word lines. The word line cell strings may store three pages of known data. Thus, the initial state or original bits of the word line cell strings may be calculated based on the known data. The block under test may include multiple layers of word lines.

[0062] A scan range and step voltage may be provided for each coarse scan. For example, a lower offset of -300mV and an upper offset of 300mV may be provided for each default voltage. Thus, the scan range may be {-300mV, +300mV} with the respective default voltage at the midpoint. For example, a coarse step voltage of 100mV may be provided. Thus, seven scan points are provided: -300mV, -200mV, -100mV, 0, 100mV, 200mV, and 300mV.

[0063] For each coarse scan, the read level at the scan point with the smallest FBC may be determined to be the best read level. In some examples, for each scan point, the read bits from the word line memory cell string may include bits of multiple code words. The FBC for each code word may be determined. The maximum FBC for each code word may be determined for each scan point or read level. Thus, the read level at which the maximum FBC for each code word is the smallest is determined as the best read level (referred to as the coarse best read level) for each coarse scan. Thus, the best read offset (referred to as the coarse best read offset) may be determined for each coarse scan.

[0064] If multiple read levels of a coarse scan have the same maximum FBC per codeword, then the total FBC of all codewords at each read level is considered. The read level with the smallest total FBC is determined to be the best read level. If multiple read levels of a coarse scan have the same minimum total FBC, then the read level with the smaller offset is determined to be the best read level.

[0065] In S820, a first fine scan is performed at a coarse best read level for the word line memory cell strings in the block. For example, seven first fine scans can be performed at seven coarse best read levels for each of the word line memory cell strings. Each first fine scan can be provided with a scan range {-200ms, 200ms} with a respective coarse best read level in the middle. Assuming that the offset of the coarse best read level from S810 is -100ms, when the lower and upper offsets for the respective default voltages are used to define the scan range, the scan range becomes {-300ms, 100ms}. Each first fine scan can be provided with a fine step voltage of, for example, 20ms, which is smaller than the coarse step voltage of 100mV. In a similar manner as in S810, a fine best read level and a corresponding fine best read offset can be found for each first fine scan based on the FBC.

[0066] In S830, a second fine scan is performed at a fine best read level for the word line memory cell strings in the block. For example, seven second fine scans can be performed at seven fine best read levels for each word line memory cell string. Each second fine scan can be provided with a scan range {-10ms, 10ms} with a fine best read level in the middle. Assuming that the offset of the fine best read level from S820 is -120ms, when the lower and upper offsets for the respective default voltages are used to define the scan range, the scan range becomes {-130ms, -110ms}. Each second fine scan can be provided with a fine step voltage of 10ms (or less than 10ms), for example, which is less than the fine step voltage of 20mV. In a similar manner as in S810 or S820, a final fine best read level and a corresponding final fine best read offset can be found for each second fine scan based on the FBC. Finally, for the block of memory cells, the best read level is obtained for each of the seven default voltages for each word line memory cell string. In various examples, the results can be used as a basis for various evaluations or experiments. For example, the results can be used to evaluate the performance of an LDPC algorithm.

[0067] The FBC-based method described herein can typically be used for a test or experimental environment. The FBC-based method relies on known data being programmed into memory cells. For real memory systems, the data stored in the memory device may not be known. The FBC-based method can scan all word line memory cell strings. For real memory systems, the best level of searching is performed in one word line memory cell string in response to a failed page read operation for the word line memory cell string. In the FBC-based method, scanning the word line memory cell string may be too time consuming and therefore not suitable for real memory systems.

[0068] In some embodiments, a bit count difference (BCD) based best read level search method is used. In the BCD based method, the bit count difference between adjacent read levels (scanning points) is calculated and used to determine the best read level. Therefore, the BCD based method does not rely on known data programmed into the memory device, which may not be available in the real memory system.

[0069] Also, the BCD-based method is used to find the best read level for reading a page. Therefore, a scan operation is performed at a limited number of default voltages instead of all default voltages of the word line memory cell strings. For example, to read the middle page, a scan operation can be performed around three default voltages (e.g., V2, V4, and V6) to find three best read levels. Also, a scan operation is not performed at all word line memory cell strings in the entire block.

[0070] In some examples, in the BCD-based method, for each read level (scan point), a partial page read is used instead of a full page read during a single read operation. For example, a page stored in a word line memory cell string may be 16 kBytes long. A page may include four code words, each 4 kBytes long. Thus, the BCD-based method can read from memory cells corresponding to the code words instead of pages. The bits resulting from a single read operation can be reduced. Thus, the delay in data transmission from the memory device to the memory controller can be reduced.

[0071] In some examples, the scan range used in the BCD-based method is optimized based on some worst-case observed read level deviations. Thus, the scan time can be reduced. In some examples, the BCD-based method can use one coarse scan and one fine scan. The scan process is simplified compared to one coarse scan and two fine scans in the search process 800. In some examples, hardware support is available to calculate the bit count for BCD. Compared to the FBC calculation performed using software, the time to calculate the bit count can be reduced.

[0072] FIG. 9 shows a BCD table 900 for determining the best read level from a set of read levels (scan points) during a scan process. The scan process can be part of a BCD-based best read level search process. The first column of the BCD table 900 contains a set of scan points covered in the scan process. The scan points are represented by a scan point offset (or read level offset). A step voltage of 10 mV is used. At each scan point, a single read operation can be performed. Bits can be read from a set of memory cells belonging to a word line memory cell string. For example, memory cells with a threshold voltage lower than the scan point read level are read as 1. Memory cells with a threshold voltage higher than the scan point read level are read as 0.

[0073] Considering the current scan point, two BCDs can be calculated. The first BCD, denoted BCD-L, can be the BCD between the current scan point and the left scan point adjacent to the current scan point. The second BCD, denoted BCD-R, can be the BCD between the current scan point and the right scan point adjacent to the current scan point. The left or right location can be relative to a search range along the threshold voltage axis. Typically, a larger read level is to the right of a smaller read level. For read levels close to the left or right boundary of the search range, the left or right scan points are unavailable. The respective BCD-L or BCD-R are not calculated and are unavailable. Typically, read levels close to the boundary of the search range can be excluded from candidate scan points for selecting the best read level.

[0074] Given the above BCD-L and BCD-R corresponding to each scan point, the best reading level can be selected from a series of scan points. First, the reading level at the scan point with the smallest sum of BCD-L and BCD-R (denoted as Sum(BCD-L, BCD-R)) can be determined to be the best reading level. If multiple scan points have the same sum of BCD-L and BCD-R, the reading level at the scan point with the smallest minimum value of BCD-L or BCD-R (denoted as Min(BCD-L, BCD-R)) is determined to be the best reading level among these multiple scan points. If there are still multiple scan points with the same minimum value of BCD-L or BCD-R, the scan point closest to the midpoint of the scan range can be determined as the best scan point with the best reading level. Corresponding to the best reading level, the corresponding scan point offset can be determined to be the best reading offset for each default voltage.

[0075] 10A-10B show a BCD-based best read level search process 1000 according to an embodiment of the present disclosure. The BCD-based search process 1000 may be implemented to find the best read reference voltage for a page read operation. The process 1000 may include two parts: a coarse search part from S1002 to S1016 and a fine search part from S1024 to S1036.

[0076] In S1002, ECC decoding fails a page read operation. For example, raw codeword bits of a target page are obtained based on data read from a memory device by one or more single read operations. LDPC hardware decoding based on the raw codeword bits may fail due to high RBER. A BCD-based search process 1000 may then be initiated to find the best read level for retrying read or software LDPC decoding of the target page.

[0077] In S1004, a read level corresponding to a default voltage may be initialized. Depending on which MLC technology the target page uses, what type the target page is (e.g., lower page or upper page), and how the bits are encoded by the memory cell state, the number of read levels to be covered may be determined. For example, for SLC, a single read operation at a read level may be performed. For DLC, one read level is covered to read the lower page, and two read levels are covered to read the upper page. For TLC, two read levels, three read levels, and two read levels may be covered to read the lower page, the middle page, and the upper page, respectively. The coarse search and the fine search cover the read levels determined in S1004.

[0078] In S1006, it is determined whether the next reading level is available. If all reading levels determined in S1004 have been completed and a next reading level is not available, the process 1000 proceeds to S1024 and enters the fine search portion. Otherwise, the process 1000 proceeds to S1008 with the selection of a reading level from among the reading levels determined in S1004. The reading levels can be selected in any order.

[0079] In S1008, the scan point offsets may be initialized corresponding to the selected read level. For example, the number and position (voltage value) of each scan point may be determined based on the scan range (or scan voltage range) and the step voltage. The scan points may be indicated in the form of scan point offsets for each default voltage corresponding to the selected read level. For example, upper and lower offsets for the default voltage may be provided to indicate the scan range.

[0080] In S1010, it is determined whether the next scan point offset is available. If all scan point offsets determined in S1008 have been completed and the next scan point offset is not available, process 1000 proceeds to S1016. Otherwise, process 1000 proceeds to S1012. In S1012, a scan point offset is selected from the scan point offsets determined in S1008. The scan point offsets can be selected in any order.

[0081] In S1014, a single read operation may be performed at the scan point of the selected scan point offset to memory cells storing the target page. The bits resulting from the single read operation may be stored in memory. If the read bits of the neighboring scan points are available in memory, the BCD-L or BCD-R between the current scan point and the neighboring scan points may be calculated and stored in a BCD table, such as the table shown in FIG. 9. The process 1000 may return to S1010 to process the next scan point offset, if available.

[0082] In S1016, the BCD-L and BCD-R for each scan point offset in the current stage are entered into a BCD table corresponding to the current read level selected in S1006. Based on the BCD table, a coarse best read offset can be determined for the current read level. The coarse best read offset can be used as the center scan point offset for the fine search corresponding to the current read level. The process 1000 can proceed to S1006 to process the next read level, if available.

[0083] In S1024, the fine search portion of process 1000 begins based on the coarse best read offset for each read level. Specifically, in S1024, the read levels corresponding to the default voltages are initialized in a manner similar to S1004. The same set of read levels may be determined. In S1026, it may be determined whether the next read level is available. When all read levels have been covered, process 1000 may proceed to S1038, where it ends. If not, process 1000 proceeds to S1028 with the selected read level.

[0084] In S1028, the scan point offset for the fine search corresponding to the selected reading level can be initialized. For example, the number and position of the scan point offset for the fine search can be determined based on the fine scan range and the fine step voltage. For example, the fine scan range can use each coarse best reading level as a center point. An upper and lower limit can be set for the center location.

[0085] In S1030, it may be determined whether the next scan point offset is available. If all scan point offsets have been covered, the process 1000 proceeds to S1036. If not, the process 1000 proceeds to S1032. In S1032, the next scan point offset is selected. In S1034, a single read operation is performed at the selected scan point offset to read bits from memory cells that store the target page. The BCD-L or BCD-R of the current scan point offset or neighboring scan point offsets may be calculated to fill the BCD table. The process 1000 may return to S1030 to process the next available scan point offset.

[0086] In S1036, the BCD table corresponding to the current read level is filled. A fine best read offset can be determined for the current read level. The process 1000 can proceed to S1026 to process the next available read level. When the process 1000 ends in S1038, a best read level corresponding to the fine best read offset is available for each read level. In some examples, the obtained best read level can be subsequently used in the LDPC software decoding process.

[0087] FIG. 11A illustrates two tables 1110 and 1120 for illustrating how to optimize a scan range used for a coarse search in a BCD-based search process 1000 according to an embodiment of the present disclosure. In the example of FIG. 11A, an optimized scan range (referred to as an optimized coarse scan range) for a coarse search at a particular read level corresponding to a respective default voltage may be determined based on a set of data provided in table 1110. Table 1110 includes seven columns. Each column corresponds to one of seven read levels (or seven default voltages) for TLC. The seven read levels are denoted as RD1-RD7. Table 1110 includes a number of rows.

[0088] Each row includes a set of best read offsets, each corresponding to one of seven read levels, RD1 through RD7. Each best read offset has an offset value (in mV) relative to a respective default voltage (such as V1 through V7 in FIG. 5). For example, for read level RD1, the first best read offset is −130 mV and the last best read offset is −60 mV relative to the default voltage V1.

[0089] Each row of best read offsets can correspond to memory cell conditions that cause the set of memory cells to have or exhibit a respective best read offset. For example, the conditions can be a combination of factors. The factors can include workload type, environmental temperature, retention period, read disturb, crossover temperature, first read issues, fabrication process, etc. Different conditions can correspond to different values ​​of the factors. For example, the set of memory cells can be subjected to conditions in a laboratory environment. The best read offsets can be measured from these memory cells. In some embodiments, the conditions under consideration can be a set of extreme conditions that are associated with a worst case situation. Thus, some of the best read offsets can each represent a maximum change in the best read offset under extreme conditions.

[0090] Table 1120 shows an optimized coarse search range derived based on the best read offsets collected in table 1110. As shown, for each read level (RD1, RD2, and RD3), the minimum value of each column of best read offsets is used as the lower offset, while the maximum value of each column of best read offsets is used as the upper offset. The lower offset and the upper offset together can define an optimized coarse search range for each read level for each default voltage. For example, the lower boundary voltage of the optimized coarse search range is the default voltage plus the lower offset. The upper boundary voltage of the optimized coarse search range is the default voltage plus the upper offset.

[0091] In table 1120, the offsets in the first, second, and third columns may be used for the coarse search at each reading level RD1, RD2, and RD3, respectively. Other upper and lower offsets for other reading levels may be derived similarly, if desired.

[0092] FIG. 11B shows two tables 1130 and 1140 to illustrate how to optimize the scan range used for the fine search in the BCD-based search process 1000 according to an embodiment of the present disclosure. Table 1130 includes a number of rows of values ​​equal to the best read offset rows in table 1110. The first column of table 1130 includes a list of best read offset differences between columns RD2 and RD4. Each such best read offset difference may be the difference between two best offset values ​​in the same row in table 1110 but in different columns RD2 and RD4. For example, considering the last row of table 1110, the difference between the value of column RD2 and the value of column RD4 is −40mV−(−30)mV=−10mV (subtract the lower level value from the higher read level value). Similarly, the second column of table 1130 includes a list of best read offset differences between columns RD4 and RD6.

[0093] Table 1140 shows optimized fine search ranges for read levels RD4 and RD6. The optimized search ranges can be derived based on the best read offset differences in table 1130. Specifically, for the fine search range of RD4 in table 1140, a lower offset of -80 mV can be the minimum of the best read offset differences listed in the first column of table 1130, and an upper offset of 50 mV can be the maximum of the best read offset differences listed in the first column of table 1130. These lower and upper offsets can be offsets relative to the anchor voltage when used in the fine search process. For example, the anchor voltage for RD4 can have an anchor offset relative to the default voltage of RD4. The anchor offset can be equal to the fine best read offset of read level RD2. The fine best read offset of RD2 can be found, for example, in the optimized coarse search range of RD2 {-190 mV, 70 mV} indicated in table 1120. Two iterations of the search (a coarse search and a fine search) can be performed to find the best fine reading of the set of RD2, such as in the example of FIGS. 10A-10B.

[0094] Similarly, for the fine search range of RD6 in table 1140, a lower offset of -160 mV may be the minimum of the best read offset differences listed in the second column of table 1130, and an upper offset of 60 mV may be the maximum of the best read offset differences listed in the second column of table 1130. These lower and upper offsets may be offsets relative to an anchor voltage for RD6. The anchor voltage for RD6 may have an anchor offset relative to the respective default voltage of RD6. The anchor offset of RD6 may be equal to the fine best read offset of the read level RD4. The fine best read offset of RD4 may be found, for example, in the optimized fine search range of RD2 {-80 mV, 50 mV} indicated in table 1140. Table 1140 also lists a fine search range {-100 mV, 100 mV} for RD2. This fine search range may be set based on any other method.

[0095] In the previous description, a combination of coarse and fine search is first performed in the coarse search range of RD2 in table 1120 to find the fine best read offset of RD2. When the fine best read offset of RD2 is used as the anchor offset, a fine search is performed in the fine search range of RD4 in table 1140 to find the fine best read offset of RD4. The fine best read offset of RD4 is used as the anchor offset, and the fine search range of RD6 can be determined in the fine search range of RD6 in table 1140. In this manner, three best read offsets can be determined for read levels RD2, RD4, and RD6 and can be used to read the middle page in the example of FIG. 5.

[0096] In other examples, the above order (from RD2 to RD6) may be changed to any order. For example, the above searches may be in any order, such as RD6, RD2, and RD4. A combination of coarse and fine searches may start from RD6 and continue with two fine searches in RD2 and RD4. In this order, the coarse search range and fine search range of the corresponding level may be adjusted accordingly. For example, the fine best offset of RD6 may be used as the anchor offset of RD2. Thus, the fine search range of RD2 may be determined based on the best read offset difference between the best read offset of RD2 and the best read offset of RD6. Also, the fine best offset of RD6 may be used as the anchor offset of RD4. Alternatively, the fine best offset of RD2 is used as the anchor offset of RD4.

[0097] The above description uses the read levels RD2, RD4, and RD6 of the middle pages of a TLC as an example to explain the coarse search range or fine search range optimization methods. However, the search optimization methods can be used for any kind of MLC with one, two, three, four, or more pages stored.

[0098] Compared with setting the search range indiscriminately, the search range (or scan range) obtained using the search range optimization method disclosed herein can be shorter, thus accelerating the best read level search process. Also, when the search range optimization method disclosed herein is used, some rough search processes can be skipped, which can further accelerate the best read level search process. Furthermore, the search range optimization method disclosed herein does not rely on a specific search method. The search range optimization method can be used to provide an optimized countermeasure range to any best read search method.

[0099] 12A-12C show a search process of the best read level according to an embodiment of the present disclosure. The best read levels corresponding to default voltages V2 and V4 for reading the middle page from the TLC can be determined during the process. Optimized coarse and fine search ranges are used during the process.

[0100] FIG. 12A illustrates a coarse search range 1210. The coarse search range 1210 has an upper offset 1212 of 70 mV and a lower offset 1211 of −190 mV relative to a default voltage 1213 of V2. The coarse search range 1210 may be an optimized coarse search range determined using the coarse search range optimization method described in the examples of FIGS. 11A-11B. A coarse search with a step voltage of 100 mV may be performed across the coarse search range 1210 to find a coarse best read level 1214 with a coarse best read offset 1215 of −30 mV relative to the default voltage 1213 of V2.

[0101] 12B shows a fine search range 1220 defined with a coarse best read level 1214 as the central scan point 1214. The fine search range 1220 may have a lower offset 1221 of -100 mV and an upper offset 1222 of 100 mV relative to the central scan point 1214. Following the coarse search in FIG. 12A, a fine search with a 10 mV step voltage may be performed across the fine search range 1220 to find a fine best read level 1223. The fine best read level may have a fine best read offset 1224 of -50 mV relative to the V2 default voltage 1213.

[0102] FIG. 12C shows another fine search range 1230 for a reading level corresponding to a default voltage 1235 of V4. The fine search range 1230 may be determined based on another scanning point (anchor voltage) 1233. The anchor scanning point 1233 may have the same offset value as the fine best reading offset 1224 of -50 mV, but relative to the default voltage 1235 of V4. The fine search range 1230 may have a lower offset 1231 of -80 mV and an upper offset 1232 of 50 mV relative to the anchor scanning point 1233. Following the fine search in FIG. 12B, another fine search may be performed in the fine search range 1230 with a voltage step of 10 mV to find a best reading level 1236. The best reading level 1236 may have a best reading offset 1237 relative to the default voltage V4.

[0103] 13 illustrates a process 1300 for searching for the best read level according to an embodiment of the present disclosure. The process 1300 may begin at S1310.

[0104] In S1310, a first best read offset of a first best read reference voltage relative to a first default read reference voltage can be determined. For example, to determine the first best read offset, a second scan range can be determined. The second scan range can have an upper limit that is the first default read reference voltage plus an upper limit offset and a lower limit that is the first default read reference voltage plus a lower limit offset. The second scan range can be scanned based on a coarse step voltage by performing a series of first single read operations within the second scan range. Each first single read operation generates a bit count of either 1 or 0. Each first single read operation corresponds to a first read reference voltage.

[0105] For example, for each first single read operation, if available, a first bit count difference between the bit count of the respective first single read operation and the bit count of a previous first single read operation may be determined. If available, a second bit count difference between the bit count of the respective first single read operation and the bit count of a subsequent first single read operation may be determined. The first read reference voltage of the first single read operation whose sum of the respective first bit count difference and the respective second bit count difference has the smallest value among the series of first single read operations may be determined to be the coarse best read reference voltage.

[0106] In an example, when there are two or more first single read operations in which the sum of the respective first bit count differences and the respective second bit count differences has the same value, the minimum value of the respective first bit count differences and the respective second bit count differences may be determined such that the first read reference voltage of the first single read operation having the minimum value among the two or more first single read operations becomes the coarse best read reference voltage.

[0107] In some examples, a third scan range may then be determined. The third scan range may have an upper limit that is the coarse best read reference voltage plus the coarse step voltage and a lower limit that is the coarse best read reference voltage minus the coarse step voltage. The third scan range may be scanned based on the fine step voltage by performing a series of second single read operations within the third scan range. Each second single read operation corresponds to a second read reference voltage. Each second single read operation generates a bit count of either one or zero.

[0108] For each second single read operation, a first bit count difference between the bit count of the respective second single read operation and the bit count of the previous second single read operation, if available, may be determined. Also, a second bit count difference between the bit count of the respective second single read operation and the bit count of the subsequent second single read operation, if available, may be determined. Thus, a second read reference voltage of the second single read operation in which the sum of the respective first bit count difference and the respective second bit count difference has a minimum value among the series of second single read operations may be determined to be the first best read reference voltage. The offset of the first best read reference voltage relative to the first default read reference voltage is the first best read offset.

[0109] In S1320, an anchor read reference voltage may be determined that has the same offset as the first best read offset relative to the second default read reference voltage. The first default read reference voltage and the second default read reference voltage are set for reading a page from a set of MLCs in a semiconductor memory device.

[0110] In S1330, a first scan range may be determined based on the anchor read reference voltage. For example, an upper limit of the first scan range is the anchor read reference voltage plus an upper limit offset. A lower limit of the first scan range is the anchor read reference voltage plus a lower limit offset. The upper limit offset and the lower limit offset may be positive voltage values ​​or negative voltage values.

[0111] In S1340, a second best read offset of a second best read reference voltage relative to a second default read reference voltage may be determined by searching in a first scan range. For example, the first scan range may be scanned by performing a series of third single read operations within the first scan range. Each third single read operation corresponds to a third read reference voltage. Each third single read operation generates a bit count of either 1 or 0.

[0112] For each third single read operation, if available, a first bit count difference between the bit count of the respective third single read operation and the bit count of the previous third single read operation may be determined. If available, a second bit count difference between the bit count of the respective third single read operation and the bit count of the subsequent third single read operation may be determined. Thus, a third read reference voltage of a third single read operation in which the sum of the respective first bit count difference and the respective second bit count difference has a minimum value among the series of third single read operations may be determined to be the second best read reference voltage. An offset of the second best read reference voltage relative to the second default read reference voltage is the second best read offset. In some examples, the first single read operation, the second single read operation, and the third single read operation are partial page read operations.

[0113] In S1350, a read process may be performed to read a page from the set of MLCs based on the first best read reference voltage and the second best read reference voltage. Process 1300 may end.

[0114] 14A-14B show a performance comparison between a first best read search process and a second best read search process according to an embodiment of the present disclosure. The first best read search process can be a best read level search process based on FBC, such as in the example of FIG. 8. The second best read search process can be a best read level search process based on BCD, such as in the example of FIG. 9-13.

[0115] FIG. 14A shows the total time to complete the first best read level search process for a word line memory cell string. A word line memory cell string may contain MLC with (n+1) states. Thus, there are n read levels to be processed. The total time, denoted as T, is T=SUM(K, M, N)*(tR+tDMA+tOH)*nLevel (1) In formula (1), n ​​level represents the number of read levels to be processed. K, M, and N respectively indicate the number of scan steps performed during the coarse scan, the first fine scan, and the second fine scan when processing each read level. The time for each scan step includes the page read time tR, the data transfer time (e.g., between the memory device and the memory controller), tDMA, and the firmware (FW) processing overhead time tOH.

[0116] FIG. 14B shows the total time to complete the second best read level search process for a word line memory cell string. The word line memory cell string may also include an MLC with (n+1) states. However, the number of read levels processed is less than n. For example, to read a middle page of a TLC, the search process may be performed at three read levels (e.g., RD2, RD4, and RD4). Thus, the total time, denoted as T', is: T'=K'*(tR'+tDMA'+tOH')+ΣM[i]*(tR'+tDMA'+tOH') (2) In equation (2), K' represents the number of scan steps performed during a coarse scan at the first read level among the read levels processed. M'[i] represents the number of scan steps performed during a fine scan at each read level indexed by i. The time for each scan step includes a single read operation time tR', a data transfer time (e.g., between the memory device and the memory controller), tDMA', and a firmware (FW) processing overhead time tOH'.

[0117] Comparing the example of FIG. 14B with the example of FIG. 14A, the read time tR' can be smaller than tR because a single read operation can be used instead of a normal page read operation. The data transmission time tDMA' can be smaller than tDMA because a partial page read can be used instead of a full page read, reducing the amount of data transmitted. The FW processing overhead tOH' can be smaller than tOH because the bit counting (at each scan step) in the second search method can have hardware acceleration support, while the FBC (comparison between read bits and original bits) can be implemented using FW. The number of scan steps K' and M'[i] can also be reduced from K and M due to the adoption of search range optimization technique. The second fine search is excluded from the second search method, and therefore N does not appear in formula (2). Also, as shown in FIG. 14B, the coarse scan (including K' scan steps) is performed only in the first read level. The other read levels each include only fine scans. The coarse scan can also be reduced to one time.

[0118] In various embodiments, the best read level search methods disclosed herein may be implemented in a memory controller (such as memory controller 106) or in a memory device (such as memory device 104). These methods may be triggered in response to an ECC decoding failure or may run in the background. In some embodiments, the methods disclosed herein may be implemented in hardware, software, or a combination thereof. In an example, the best read level search methods disclosed herein may be implemented in instructions stored on a non-transitory computer-readable medium. A processor or processing circuit may execute the instructions to implement the respective methods.

[0119] Aspects of the present disclosure provide a memory controller that implements the techniques disclosed herein. For example, the memory controller may include circuitry configured to implement the methods. The method may include determining a first best read offset of a first best read reference voltage relative to a first default read reference voltage; determining an anchor read reference voltage having the same offset as the first best read offset relative to a second default read reference voltage, where the first default read reference voltage and the second default read reference voltage are set for reading a page from a set of multi-level cells (MLCs) in a semiconductor memory device in the memory system; determining a first scan range based on the anchor read reference voltage, where an upper limit of the first scan range is the anchor read reference voltage plus an upper limit offset and a lower limit of the first scan range is the anchor read reference voltage plus a lower limit offset, where the upper limit offset and the lower limit offset are positive voltage values ​​or negative voltage values; determining a second best read offset of a second best read reference voltage relative to the second read reference voltage by searching in the first scan range; and performing a read process to read a page from the set of MLCs based on the first best read reference voltage and the second best read reference voltage.

[0120] Aspects of the present disclosure provide a non-transitory computer-readable medium storing instructions implementing the techniques disclosed herein, for example, the instructions, when executed by a processor (or processing circuit), can cause the processor (or processing circuit) to implement a method. The method may include determining a first best read offset of a first best read reference voltage relative to a first default read reference voltage; determining an anchor read reference voltage having the same offset as the first best read offset relative to a second default read reference voltage, where the first default read reference voltage and the second default read reference voltage are set for reading a page from a set of multi-level cells (MLCs) in a semiconductor memory device in the memory system; determining a first scan range based on the anchor read reference voltage, where an upper limit of the first scan range is the anchor read reference voltage plus an upper limit offset and a lower limit of the first scan range is the anchor read reference voltage plus a lower limit offset, where the upper limit offset and the lower limit offset are positive voltage values ​​or negative voltage values; determining a second best read offset of a second best read reference voltage relative to the second read reference voltage by searching in the first scan range; and performing a read process to read a page from the set of MLCs based on the first best read reference voltage and the second best read reference voltage.

[0121] The above outlines the features of some embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be easily used as a basis for designing or modifying other processes and structures to carry out the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure. [Explanation of symbols]

[0122] 100 Systems 102 Memory System 104 Memory Devices 106 Memory Control Device 108 Host 202 Memory Card 204 Memory card connector 206 SSD 208 SSD Connector 300 Memory Devices 301 Memory Cell Array 302 Peripheral Circuit 304 Block 306 Memory Cells 308 NAND memory strings 310 Source Select Gate, SSG 312 Drain select gate, DSG 314 Source Line 316 bit lines 318 Word Line 320 pages 404 Page Buffer / Sense Amplifier 406 Column Decoder / Bit Line Driver 408 Row Decoder / Word Line Driver 410 Voltage Generator 412 Control Logic 414 Register 416 Interface 418 Data Bus 601 Default read reference voltage 602 Optimal Reading Reference Voltage 603 Best Read Reference Voltage 610 Search Range 611 Lower Limit Offset 612 Upper Limit Offset 700 Read Process 800 Best read level search process 900 BCD table Search process for best read level based on 1000 BCD 1110, 1120 Tables for coarse search 1130, 1140 Tables for fine search 1210 Coarse search range 1211 Lower Offset 1212 Upper Offset 1213 Default Voltage 1214 Coarse best read level, central scanning point 1215 Coarse Best Read Offset 1220 Fine Search Range 1221 Lower Offset 1222 Upper Offset 1223 Fine best read level 1224 Fine Best Read Offset 1230 Fine Search Range 1231 Lower Offset 1232 Upper Offset 1233 scanning points, anchor voltage 1235 Default Voltage 1236 Best Reading Level 1237 Best Read Offset D1, D2, D1', D2' distribution S0, S1, S2, S3, S4, S5, S6, S7 status V1, V2, V3, V4, V5, V6, V7 Default reading reference voltage Vth Threshold voltage

Claims

1. 1. A method for a memory system, comprising: determining a first best read offset of a first best read reference voltage relative to a first default read reference voltage; determining an anchor read reference voltage having an offset the same as the first best read offset relative to a second default read reference voltage, the first default read reference voltage and the second default read reference voltage being set for reading a page from a set of multi-level cells (MLCs) in a semiconductor memory device in the memory system; determining a first scan range based on the anchor read reference voltage, an upper limit of the first scan range being the anchor read reference voltage plus an upper limit offset, and a lower limit of the first scan range being the anchor read reference voltage plus a lower limit offset, the upper limit offset and the lower limit offset being positive voltage values ​​or negative voltage values; determining a second best read offset of a second best read reference voltage relative to the second read reference voltage based on the first scan range; The method includes:

2. The step of determining the first best read offset comprises: determining a second scan range, the second scan range having an upper limit that is the first default read reference voltage plus an upper limit offset and a lower limit that is the first default read reference voltage plus a lower limit offset; scanning the second scan range based on a coarse step voltage by performing a series of first single read operations within the second scan range, each first single read operation corresponding to a first read reference voltage, each first single read operation generating a bit count of either one or zero; For each first single read operation, a first bit count difference between the bit counts of the first single read operation and a previous first single read operation, if available; and a second bit count difference between the bit counts of the first single read operation and each of the subsequent first single read operations, if available; determining determining the first read reference voltage of the first single read operation in which a sum of each of the first bit count differences and each of the second bit count differences has a minimum value among the series of first single read operations to be a coarse best read reference voltage; The method of claim 1 , comprising:

3. 3. The method of claim 2, further comprising: when there are two or more first single read operations in which the sum of the respective first bit count differences and the respective second bit count differences has the same value, determining the first read reference voltage of the first single read operation in which the minimum value of the respective first bit count differences and the respective second bit count differences is the minimum value among the two or more first single read operations to be the coarse best read reference voltage.

4. determining a third scan range, the third scan range having an upper limit that is the coarse best read reference voltage plus the coarse step voltage and a lower limit that is the coarse best read reference voltage minus the coarse step voltage; scanning the third scan range based on fine step voltages by performing a series of second single read operations within the third scan range, each second single read operation corresponding to a second read reference voltage, each second single read operation generating a bit count of either one or zero; For each second single read operation, a first bit count difference between the bit count of each second single read operation and the bit count of a previous second single read operation, if available; and a second bit count difference between the bit count of each of the second single read operations and the bit count of a subsequent second single read operation, if available; determining determining the second read reference voltage of the second single read operation in which a sum of each of the first bit count differences and each of the second bit count differences has a minimum value among the series of second single read operations to be the first best read reference voltage, wherein an offset of the first best read reference voltage relative to the first default read reference voltage is the first best read offset; The method of claim 2 , further comprising:

5. determining a second best read offset of the second best read reference voltage relative to the second default read reference voltage based on the first scan range, scanning the first scan range by performing a series of third single-read operations within the first scan range, each third single-read operation corresponding to a third read reference voltage, each third single-read operation generating a bit count of either one or zero; For each third single read operation, a first bit count difference between the bit count of each said third single read operation and the bit count of a previous said third single read operation, if available; and a second bit count difference between the bit count of each of the third single read operations and the bit count of a subsequent third single read operation, if available; determining determining a third read reference voltage of the third single read operation in which a sum of each of the first bit count differences and each of the second bit count differences has a minimum value among the series of third single read operations to be the second best read reference voltage, wherein an offset of the second best read reference voltage relative to the second default read reference voltage is the second best read offset; The method of claim 4 , comprising:

6. The method of claim 5 , wherein the first single read operation, the second single read operation, and the third single read operation are partial page read operations.

7. collecting a first set of first best read offsets, each first best read offset being a voltage shift of a best read reference voltage from the first default read reference voltage, each first best read offset corresponding to a memory cell condition that causes a set of memory cells to have a respective first best read offset, each of the first set of first best read offsets having a positive value or a negative value; setting a maximum value of the first set of first best read offsets to be the upper offset of the second scan range; setting a minimum of the first set of first best read offsets to be the lower offset of the second scan range; The method of claim 2 , further comprising:

8. collecting a second set of second best read offsets, each second best read offset corresponding to the first set of first best read voltages and one of the respective memory cell conditions, each second best read offset being a voltage shift of a best read reference voltage from the second default read reference voltage, the second set of second best read offsets having positive or negative values, respectively; determining a difference between each pair of the first best read offset and a respective second best read offset, the difference being equal to the respective second best read offset minus the respective first best read offset; setting the maximum of the differences between each pair of the first best read offset and a respective second best read offset to be the upper offset limit of the first scan range; setting the minimum of the differences between each pair of the first best read offset and a respective second best read offset to be the lower offset of the first scan range; The method of claim 7 further comprising:

9. 2. The method of claim 1, further comprising, prior to the step of determining the first best read offset of the first best read reference voltage relative to the first default read reference voltage, determining that an error correction code (ECC) decoding process failed to read the page.

10. 2. The method of claim 1, further comprising: performing an ECC software decode process to read the page from the set of MLCs based on the first best read reference voltage and the second best read reference voltage.

11. The method of claim 1 , wherein the first or second default read reference voltage corresponds to a default read reference voltage of the MLC.

12. A semiconductor memory device; determining a first best read offset of a first best read reference voltage relative to a first default read reference voltage; determining an anchor read reference voltage having the same offset as the first best read offset relative to a second default read reference voltage, the first default read reference voltage and the second default read reference voltage being set for reading a page from a set of multi-level cells (MLCs) in the semiconductor memory device; determining a first scan range based on the anchor read reference voltage, an upper limit of the first scan range being the anchor read reference voltage plus an upper limit offset, and a lower limit of the first scan range being the anchor read reference voltage plus a lower limit offset, the upper limit offset and the lower limit offset being positive voltage values ​​or negative voltage values; determining a second best read offset of a second best read reference voltage relative to the second read reference voltage based on the first scan range; a memory controller comprising circuitry configured to: A memory system comprising:

13. The circuit comprises: determining a second scan range, the second scan range having an upper limit that is the first default read reference voltage plus an upper limit offset and a lower limit that is the first default read reference voltage plus a lower limit offset; scanning the second scan range based on a coarse step voltage by performing a series of first single read operations within the second scan range, each first single read operation corresponding to a first read reference voltage, each first single read operation generating a bit count of either one or zero; For each first single read operation, a first bit count difference between the bit count of each of the first single read operations and the bit count of a previous first single read operation, if available; and a second bit count difference between the bit count of each of the first single read operations and the bit count of a subsequent first single read operation, if available; and determining determining the first read reference voltage of the first single read operation in which a sum of each of the first bit count differences and each of the second bit count differences has a minimum value among the series of first single read operations to be a coarse best read reference voltage; The memory system of claim 12 , further configured to:

14. The circuit comprises: when there are two or more first single read operations in which the sum of each of the first bit count differences and each of the second bit count differences has the same value, a minimum value of each of the first bit count differences and each of the second bit count differences determines the first read reference voltage of the first single read operation having the minimum value among the two or more first single read operations to be the coarse best read reference voltage. The memory system of claim 13 further comprising:

15. The circuit comprises: determining a third scan range, the third scan range having an upper limit that is the coarse best read reference voltage plus the coarse step voltage and a lower limit that is the coarse best read reference voltage minus the coarse step voltage; scanning the third scan range based on fine step voltages by performing a series of second single read operations within the third scan range, each second single read operation corresponding to a second read reference voltage, each second single read operation generating a bit count of either one or zero; For each second single read operation, a first bit count difference between the bit count of each second single read operation and the bit count of a previous second single read operation, if available; and a second bit count difference between the bit count of each of the second single read operations and the bit count of a subsequent second single read operation, if available; and determining determining the second read reference voltage of the second single read operation in which a sum of each of the first bit count differences and each of the second bit count differences has a minimum value among the series of second single read operations to be the first best read reference voltage, wherein an offset of the first best read reference voltage relative to the first default read reference voltage is the first best read offset; The memory system of claim 13 , further configured to:

16. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform a method, the method comprising: determining a first best read offset of a first best read reference voltage relative to a first default read reference voltage; determining an anchor read reference voltage having the same offset as the first best read offset relative to a second default read reference voltage, the first default read reference voltage and the second default read reference voltage being set for reading a page from a set of multi-level cells (MLCs) in a semiconductor memory device; determining a first scan range based on the anchor read reference voltage, an upper limit of the first scan range being the anchor read reference voltage plus an upper limit offset, and a lower limit of the first scan range being the anchor read reference voltage plus a lower limit offset, the upper limit offset and the lower limit offset being positive voltage values ​​or negative voltage values; determining a second best read offset of a second best read reference voltage relative to the second read reference voltage based on the first scan range; 2. A non-transitory computer readable medium comprising:

17. The step of determining the first best read offset comprises: determining a second scan range, the second scan range having an upper limit that is the first default read reference voltage plus an upper limit offset and a lower limit that is the first default read reference voltage plus a lower limit offset; scanning the second scan range based on a coarse step voltage by performing a series of first single read operations within the second scan range, each first single read operation corresponding to a first read reference voltage, each first single read operation generating a bit count of either one or zero; For each first single read operation, a first bit count difference between the bit count of each of the first single read operations and the bit count of a previous first single read operation, if available; and a second bit count difference between the bit count of each of the first single read operations and the bit count of a subsequent first single read operation, if available; determining determining the first read reference voltage of the first single read operation in which a sum of each of the first bit count differences and each of the second bit count differences has a minimum value among the series of first single read operations to be a coarse best read reference voltage; 20. The non-transitory computer readable medium of claim 16, comprising:

18. The method comprises:

20. The non-transitory computer-readable medium of claim 17, further comprising: when there are two or more first single read operations in which the sum of the respective first bit count difference and the respective second bit count difference has the same value, determining the first read reference voltage of the first single read operation in which the minimum value of the respective first bit count difference and the respective second bit count difference has the minimum value among the two or more first single read operations to be the coarse best read reference voltage.

19. The method comprises: determining a third scan range, the third scan range having an upper limit that is the coarse best read reference voltage plus the coarse step voltage and a lower limit that is the coarse best read reference voltage minus the coarse step voltage; scanning the third scan range based on fine step voltages by performing a series of second single read operations within the third scan range, each second single read operation corresponding to a second read reference voltage, each second single read operation generating a bit count of either one or zero; For each second single read operation, a first bit count difference between the bit count of each second single read operation and the bit count of a previous second single read operation, if available; and a second bit count difference between the bit count of each of the second single read operations and the bit count of a subsequent second single read operation, if available; determining determining the second read reference voltage of the second single read operation in which a sum of each of the first bit count differences and each of the second bit count differences has a minimum value among the series of second single read operations to be the first best read reference voltage, wherein an offset of the first best read reference voltage relative to the first default read reference voltage is the first best read offset; 20. The non-transitory computer readable medium of claim 17, further comprising:

20. determining a second best read offset of the second best read reference voltage relative to the second default read reference voltage based on the first scan range, scanning the first scan range by performing a series of third single-read operations within the first scan range, each third single-read operation corresponding to a third read reference voltage, each third single-read operation generating a bit count of either one or zero; For each third single read operation, a first bit count difference between the bit count of each said third single read operation and the bit count of a previous said third single read operation, if available; and a second bit count difference between the bit count of each of the third single read operations and the bit count of a subsequent third single read operation, if available; determining determining a third read reference voltage of the third single read operation in which a sum of each of the first bit count differences and each of the second bit count differences has a minimum value among the series of third single read operations to be the second best read reference voltage, wherein an offset of the second best read reference voltage relative to the second default read reference voltage is the second best read offset; 20. The non-transitory computer readable medium of claim 19, comprising:

Images