Light emitting diode and method for its manufacture by selective growth of active layer from trench bounded region - Patents.com

Abstract

A method for forming a light emitting diode includes forming a first conductivity type compound semiconductor layer on a substrate; etching the first conductivity type compound semiconductor layer to form a first pillar structure and a second pillar structure without exposing the substrate between the first and second pillar structures; selectively growing a semiconductor active layer on the first and second pillar structures; and selectively growing a second conductivity type compound semiconductor layer on the semiconductor active layer.

Description

[Technical field]

[0001] This application claims the benefit of priority from U.S. Provisional Application No. 63 / 299,245, filed January 13, 2022, the entire contents of which are incorporated herein by reference. FIELD OF THE DISCLOSURE This disclosure relates to light emitting devices, and more particularly to light emitting diodes selectively grown from regions separated by trenches and methods for making the same. [Background technology]

[0002] Light-emitting elements are used in electronic displays, such as the backlighting of liquid crystal displays found in laptops and televisions. Light-emitting elements include light-emitting diodes (LEDs) and many other types of electronic devices configured to emit light.

[0003] In light emitting devices such as light emitting diodes (LEDs), the wavelength of emitted light is determined by the band gap and thickness confinement effects of the LED's active region. The active region often contains one or more bulk semiconductor layers and / or quantum wells (QWs). For III-nitride based LED devices such as GaN-based devices, the active region (e.g., bulk semiconductor layers or QW well layers) material is InN. x Ga 1-x N, where 0 <x<1である。

[0004] The band gap of such III-nitride materials depends on the amount of In incorporated into the active region. Higher indium content results in a smaller band gap and longer wavelength emitted light. As used herein, the term "wavelength" refers to the peak emission wavelength of the LED. It should be understood that the typical emission spectrum of a semiconductor LED is a narrow band of wavelengths centered around the peak wavelength. Summary of the Invention

[0005] A method of forming a light emitting diode of one embodiment includes forming a first conductivity type compound semiconductor layer on a substrate, etching the first conductivity type compound semiconductor layer to form a first pillar structure and a second pillar structure without exposing the substrate between the first and second pillar structures, selectively growing a semiconductor active layer on the first and second pillar structures, and selectively growing a second conductivity type compound semiconductor layer on the semiconductor active layer.

[0006] A light emitting diode structure of one embodiment includes: a first light emitting diode including a first portion of a first conductive type compound semiconductor layer, a first portion of a semiconductor active layer located on the first portion of the first conductive type compound semiconductor layer, and a first portion of a second conductive type compound semiconductor layer located on the first portion of the semiconductor active layer; a second light emitting diode including a second portion of the first conductive type compound semiconductor layer, the second portion of the semiconductor active layer located on the second portion of the first conductive type compound semiconductor layer, and the second portion of the second conductive type compound semiconductor layer located on the second portion of the semiconductor active layer; a trench separating the first light emitting diode and the second light emitting diode; and a third portion of the semiconductor active layer and a third portion of the second conductive type compound semiconductor layer located in the trench, wherein an upper surface of the third portion of the second conductive type compound semiconductor layer is located below the first and second portions of the semiconductor active layer. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a side cross-sectional view of an intermediate structure that may be used in forming an LED structure, according to various embodiments. [Diagram 2] FIG. 2 is a side cross-sectional view of a further intermediate structure that may be used in forming an LED structure, according to various embodiments. [Diagram 3] FIG. 3 is a side cross-sectional view of a further intermediate structure that may be used in forming an LED structure, according to various embodiments. [Figure 4]FIG. 4 is a side cross-sectional view of a further intermediate structure that may be used in forming an LED structure, according to various embodiments. [Diagram 5] FIG. 5 is a side cross-sectional view of a further intermediate structure that may be used in forming an LED structure, according to various embodiments. [Figure 6] FIG. 6 is a side cross-sectional view of a further intermediate structure that may be used in forming an LED structure, according to various embodiments. [Figure 7] FIG. 7 is a side cross-sectional view of a further intermediate structure that may be used in forming an LED structure, according to various embodiments. [Figure 8] FIG. 8 is a side cross-sectional view of a further intermediate structure that may be used in forming an LED structure, according to various embodiments. [Figure 9] FIG. 9 is a side cross-sectional view of a further intermediate structure that may be used in forming an LED structure, according to various embodiments. [Figure 10] FIG. 10 is a side cross-sectional view of a further intermediate structure that may be used in forming an LED structure, according to various embodiments. [Figure 11] FIG. 11 is a side cross-sectional view of an LED structure according to various embodiments. [Figure 12A] FIG. 12A is a side cross-sectional view of a further intermediate structure that may be used in forming an LED structure, according to various embodiments. [Figure 12B] FIG. 12B is a side cross-sectional view of a further intermediate structure that may be used in forming an LED structure, according to various embodiments. [Figure 12C] FIG. 12C is a side cross-sectional view of a further intermediate structure that may be used in forming an LED structure, according to various embodiments. [Figure 13A] FIG. 13A is a side cross-sectional view of a further intermediate structure that may be used in forming an LED structure, according to various embodiments. [Figure 13B] FIG. 13B is a side cross-sectional view of a further intermediate structure that may be used in forming an LED structure, according to various embodiments. [Figure 14]FIG. 14 is a side cross-sectional view of a source coupon including multiple light emitting diodes that may be transferred to a backplane according to various embodiments. [Figure 15A] FIG. 15A is a side cross-sectional view of an intermediate structure having a source coupon disposed on a backplane prior to attachment of light emitting diodes to the backplane, according to various embodiments. [Figure 15B] FIG. 15B is a vertical cross-sectional view of a further intermediate structure in which the backplane and the first source coupon are brought into contact with each other such that opposing pairs of diode-side bonding material portions and backplane-side bonding material portions contact each other, according to various embodiments. [Figure 15C] FIG. 15C is a vertical cross-sectional view of the intermediate structure of FIG. 15B in which sequential laser irradiation steps can be performed to selectively irradiate a peeling laser beam to each buffer layer covering a first light emitting diode that is then transferred to a backplane, according to various embodiments. [Figure 15D] FIG. 15D is a side cross-sectional view of the intermediate structure of FIG. 15B where the liquid gallium-rich droplets have solidified into solid gallium-rich material portions, according to various embodiments. [Figure 15E] FIG. 15E is a vertical cross-sectional view of the intermediate structure of FIG. 15B in which the backplane and the first source coupon are pressed together with a greater force, thereby inducing deformation of the bonding material portions, according to various embodiments. [Figure 15F] FIG. 15F is a vertical cross-sectional view of the intermediate structure of FIG. 15B in which sequential localized laser irradiation steps can be performed to induce reflow and subsequent bonding of each mating pair of diode-side bonding material portions and backplane-side bonding material portions according to various embodiments. [Figure 15G] FIG. 15G is a side cross-sectional view of a further intermediate structure in which the first source coupon and backplane are removed from clamp 400 and heated, according to various embodiments. [Figure 16A]FIG. 16A is a side cross-sectional view of a further intermediate structure in which a second source coupon including a second light emitting diode disposed on a second substrate may be provided, according to various embodiments. [Figure 16B] FIG. 16B is a vertical cross-sectional view of a further intermediate structure in which the backplane and second source coupon are brought into contact with each other such that opposing pairs of diode-side bonding material portions and backplane-side bonding material portions contact each other, according to various embodiments. [Figure 16C] FIG. 16C is a vertical cross-sectional view of a further intermediate structure in which the second source coupon is separated from the backplane after the first subset of second light emitting diodes are bonded to the backplane according to one embodiment. [Figure 17] FIG. 17 is a side cross-sectional view of a further intermediate structure in which a third subset of light emitting diodes is bonded to a backplane according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] A display device, such as a direct-view display, may be formed from a regular array of pixels. Each pixel may include a collection of subpixels that emit light at a respective peak wavelength. For example, a pixel may include red, green, and blue subpixels. Each subpixel may include one or more light-emitting diodes that emit light at a particular wavelength. A conventional arrangement is to have red, green, and blue (RGB) subpixels within each pixel. Each pixel is driven by a backplane circuit such that any combination of colors within the color gamut of each pixel may be displayed on the display. A display panel may be formed by a process in which LED subpixels are soldered or otherwise electrically attached to bond pads on a backplane. The bond pads are electrically driven by the backplane circuit and other driving electronics.

[0009] FIG. 1 is a vertical cross-sectional view of an intermediate structure 100 that may be used to form an LED structure, according to various embodiments. The intermediate structure 100 may include a support substrate 102 and a buffer layer 104. The buffer layer 104 may be a doped single crystal compound semiconductor layer, such as a doped single crystal III-V compound semiconductor layer (e.g., an n-type doped GaN single crystal layer). The buffer layer 104 may have a first conductivity type doping, which may be p-type or n-type. The support substrate 102 may be any single crystal substrate (such as a single crystal sapphire substrate) that may serve as an epitaxial growth template for the buffer layer 104. In an embodiment, the interface between the support substrate 102 and the buffer layer 104 may be planar or non-planar (e.g., the interface may be textured if the support substrate includes a patterned sapphire substrate (PSS)).

[0010] The support substrate 102 can be any single crystal layer of material that allows epitaxial growth of compound semiconductor material, such as III-V compound semiconductor material, from the top surface of the single crystal layer of material. The support substrate 102 can be an AI substrate using either the basal plane (i.e., c-plane) growth surface or the r-plane growth surface. 2 O 3 (sapphire), diamond, Si, Ge, GaN, AlN, both wurtzite (α) and zinc-blende (β) SiC, InN, GaP, GaAsP, GaAs, InP, ZnO, ZnS, and ZnSe, etc. For example, the support substrate 102 may include sapphire (i.e., single crystal aluminum oxide) with a suitable surface orientation.

[0011] The support substrate 102 may include PSS having a patterned (e.g., rough) growth surface. The top surface of the support substrate 102 may or may not include bumps, dimples, and / or angled cuts to facilitate epitaxial growth of the single crystal compound semiconductor material of the buffer layer 104, to facilitate separation of the buffer layer 104 from the support substrate 102 in a subsequent separation process, and / or to improve light extraction efficiency through the buffer layer 104. If the top surface of the support substrate 102 includes bumps and / or dimples, the lateral dimensions of each bump or dimple may range from 1.5 microns to 6 microns, although smaller and larger lateral dimensions may be employed. The center-to-center distance between adjacent pairs of bumps or dimples may range from 3 microns to 15 microns, although smaller and larger distances may be employed. The arrangement of the bumps or dimples may include various geometric configurations. The height of the bumps and / or depth of the dimples may be on the order of 1 to 3 microns, although smaller and larger heights and / or depths may also be employed.

[0012] The buffer layer 104 may include a single crystal compound semiconductor material, such as a III-V compound semiconductor material. The buffer layer 104 may have a thickness of 1 to 2 microns. The deposition process for forming the buffer layer 104 may employ various techniques, including metalorganic chemical vapor deposition (MOCVD), metalorganic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), metalorganic molecular beam epitaxy (MOMBE), or atomic layer deposition (ALD). The buffer layer 104 may have a constant or graded composition such that the composition of the buffer layer 104 at the interface with the supporting substrate 102 provides a substantial lattice match with the two-dimensional lattice structure of the top surface of the supporting substrate 102. The composition of the buffer layer 104 may be gradually changed during the deposition process. If a PSS support substrate 102 is used, the bottom surface of the buffer layer 104 may be a patterned (ie, rough) surface.

[0013] Materials that can be employed at the bottom of the buffer layer 104 include, for example, Ga 1-w In w As 1 N 1-y where w and y can be zero (i.e., buffer layer 104 can be composed of GaN) and are selected to match the lattice constant of the top surface of support substrate 102. Al or P can also be optionally included in the bottom material of the buffer layer, in which case the bottom of buffer layer 104 contains Ga that matches the lattice constant of the top surface of support substrate 102. 1-w-z In w Al z N 1-x-y As y P x Materials that may be employed on top of the buffer layer 104 may include, but are not limited to, direct transition III-V compound materials such as gallium nitride (GaN), aluminum nitride (AIN), gallium phosphide (GaP), gallium arsenide (GaAs), gallium antimonide (GaSb), indium nitride (InN), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), and the like.

[0014] The composition of the buffer layer 104 may be graded between the bottom and top portions of the buffer layer 104 such that dislocations caused by the gradual change in lattice constant along the growth direction (vertical direction) do not propagate to the top surface of the buffer layer 104. In one embodiment, the thin bottom portion of the buffer layer 104, less than 1 micron thick, may be undoped or lightly doped with silicon.

[0015] The intermediate structure 100 may further include a continuous first conductivity type semiconductor material layer 106L, which may be formed as a blanket material layer having a uniform thickness and extending continuously across the entire area of ​​the buffer layer 104. As used herein, a "continuous" element refers to a single element that extends continuously between each segment of the element without discontinuities. The continuous first conductivity type semiconductor material layer 106L may include a doped single crystalline compound semiconductor material having a first conductivity type doping, i.e., the conductivity type of the doping of the buffer layer 104.

[0016] The material of the continuous first conductivity type semiconductor material layer 106L may be the same as or different from the material of the buffer layer 104, and may be epitaxially aligned with the material of the buffer layer 104. In one embodiment, the material of the continuous first conductivity type semiconductor material layer 106L may be selected to match the average lattice constant of the subsequently applied material layers of the active layer 602 (see, for example, FIG. 6 and the associated discussion below) and to reduce mechanical stress in the active layer 602. For example, the material of the continuous first conductivity type semiconductor material layer 106L may include n-type gallium nitride. In one embodiment, the first conductivity type may be n-type. In another embodiment, the first conductivity type may be p-type. The epitaxial growth process for growing the continuous first conductivity type semiconductor material layer 106L may be selective or non-selective. The continuous first conductivity type semiconductor material layer 106L may be formed by a deposition process that may employ any of MOCVD, MOVPE, MBE, HVPE, LPE, MOMBE, or ALD. In an alternative embodiment, instead of a separate buffer layer 104 and first conductivity type semiconductor material layer 106L, a single first conductivity type semiconductor material layer 106L may be formed directly on the substrate 102, and the buffer layer 104 may be omitted.

[0017] The intermediate structure 100 may further include an optional continuous masking layer 108L formed on the continuous first conductivity type semiconductor material layer 106L. The continuous masking layer 108L may include a hard mask material such as silicon nitride, silicon carbide, silicon carbide nitride, or a dielectric metal oxide (aluminum oxide, titanium oxide, tantalum oxide, etc.). Other embodiments may include various other materials (e.g., photoresist) for the continuous masking layer 108L. The continuous masking layer 108L may be deposited by a conformal or non-conformal deposition process. In an embodiment, the continuous masking layer 108L may be deposited by chemical vapor deposition (CVD), ALD, or physical vapor deposition (PVD). The thickness of the continuous masking layer 108L may range from about 2 nm to about 20 nm, such as from about 3 nm to about 12 nm, although smaller and larger thicknesses may also be used.

[0018] FIG. 2 is a vertical cross-sectional view of a further intermediate structure 200 that may be used to form an LED structure, according to various embodiments. The intermediate structure 200 may be formed by patterning the continuous masking layer 108L to form a patterned mask 108. In this regard, a photoresist (not shown) may be formed on the top surface of the continuous masking layer 108L shown in FIG. 1. The photoresist may then be patterned using photolithography techniques to form a patterned photoresist. The patterned photoresist may then be used as a mask during patterning of the continuous masking layer 108L. The patterning of the continuous masking layer 108L may be performed using an anisotropic etching process. After etching, the remaining photoresist may be removed by ashing or dissolving with a solvent. Alternatively, if the continuous masking layer 108L includes a photoresist, it may be directly exposed and patterned using photolithography techniques to form the patterned mask 108.

[0019] The resulting patterned mask 108 may include a plurality of distinct structures (two are shown in this example, but there may be thousands or millions of distinct structures), which serve as an etch mask for patterning the continuous first conductivity type semiconductor material layer 106L in further processing steps, as described in further detail below. In one embodiment, the discrete portions of the patterned mask 108 may be arranged as a two-dimensional or one-dimensional periodic array. In one embodiment, the discrete portions of the patterned mask 108 may be arranged as a two-dimensional or one-dimensional periodic array. The lateral width of each discrete portion of the patterned mask 108 may be between 1 and 50 microns, such as between 5 and 20 microns.

[0020] FIG. 3 is a vertical cross-sectional view of a further intermediate structure 300 that may be used in forming an LED structure, according to various embodiments. The intermediate structure 300 may be formed by etching the continuous first conductive type semiconductor material layer 106L of FIG. 2 with the patterned mask 108. In this regard, the etching step may include and / or consist of at least one anisotropic etching step (such as at least one reactive ion etching step). The etching step may be performed without exposing the surface of the substrate 102. In one embodiment, the etching step may etch through a portion of the continuous first conductive type semiconductor material layer 106L until the top surface of the buffer layer 104 is physically exposed. In an alternative embodiment, the etching process may be a timed etching step that terminates after the portions of the continuous first conductive type semiconductor material layer 106L that are not masked by the patterned mask 108 have been etched by the etching step through only a portion of its thickness. In this case, horizontal portions of the continuous first conductivity type semiconductor material layer 106L are exposed between portions of the patterned mask 108. In this alternative embodiment, the buffer layer 104 may be present or may be omitted. In another alternative embodiment in which the buffer layer 104 is present, the etch may continue to etch partially through the thickness of the buffer layer 104 without reaching the surface of the substrate 102. Typically, at least 1 micron, e.g., 1-2 microns, of semiconductor material may remain on the surface of the substrate 102.

[0021] After etching, the unetched portions of the continuous first conductive type semiconductor material layer 106L form a plurality of pillar structures. In this exemplary embodiment, the plurality of pillar structures may include a first pillar structure 106a and a second pillar structure 106b. Each of the first pillar structure 106a and the second pillar structure 106b may include vertical walls and may have a lateral extension in the range of 1 micron to 50 microns, for example, in the range of 5 microns to 20 microns. Each of the first pillar structure 106a and the second pillar structure 106b may have a height that is comparable to or greater than the lateral dimension. For example, in one embodiment, the first pillar structure 106a and the second pillar structure 106b may have a height in the range of 10 microns to 50 microns. The vertical sidewalls of the pillar structures 106a and 106b may be damaged by the reactive ion etching and may include dangling bonds.

[0022] FIG. 4 is a vertical cross-sectional view of a further intermediate structure 400 that may be used to form an LED structure, according to various embodiments. The intermediate structure 400 may be formed by removing the patterned mask 108 from the intermediate structure 300 of FIG. 3. The patterned mask 108 may be removed by selective wet or dry etching (e.g., if it includes a hard mask) or ashing (e.g., if it includes a photoresist or carbon hard mask). The first pillar structure 106a and the second pillar structure 106b may each have a top surface 402 oriented parallel to a c-plane surface of the first conductivity type semiconductor material. For example, the top surface 402 may include a c-plane (e.g., (0001) plane family) gallium nitride surface. In this manner, the top surface 402 of each of the first pillar structure 106a and the second pillar structure 106b may form a template for selective epitaxial growth of a high-quality active material layer of an LED. The first pillar structure 106 a and the second pillar structure 106 b are laterally separated by a trench 404 .

[0023] 5 is a vertical cross-sectional view of a further intermediate structure 500 that may be used to form an LED structure, according to various embodiments. The intermediate structure 500 may be formed by selective epitaxial growth of a regrowth layer 502 on the top surface 402 of the pillar structures 106a and 106b. In this regard, the regrowth layer 502 may additionally include a layer of doped semiconductor material that may be formed by any selective epitaxial deposition process employing any of MOCVD, MOVPE, MBE, HVPE, LPE, MOMBE, or ALD. The regrowth layer 502 may or may not include the same doped semiconductor material as the first conductivity type semiconductor material layer that forms the first pillar structure 106a and the second pillar structure 106b. The regrowth layer 502 may be selected to be lattice-matched to the first conductivity type semiconductor material layer that forms the first pillar structure 106a and the second pillar structure 106b. The regrown layer 502 may include a high quality single crystal surface with low defect density suitable for forming additional layers of an LED device. In one embodiment, the regrown layer 502 may include an n-type GaN layer having a c-plane top surface.

[0024] Without wishing to be bound by any particular theory, the inventors believe that if the sapphire substrate 102 is exposed between the pillar structures 106a and 106b during the growth of the gallium-containing regrown layer 502 (e.g., an n-type GaN layer), undesirable semiconductor edge effects may occur. Specifically, without wishing to be bound by any particular theory, the inventors believe that the exposed sapphire (or another oxide) substrate 102 may cause gallium atoms to diffuse onto the sidewalls of the pillar structures as the regrown layer 502 is grown on each pillar structure, forming bumps on the ends of the regrown layer 502. The bumps may cause the regrown layer 502 on each pillar structure to have a non-uniform thickness, resulting in a non-planar top surface of the regrown layer 502. Thus, subsequent growth of an active layer on the non-planar top surface of the regrown layer 502 may result in reduced quality of the active layer (e.g., non-uniform quantum well thickness and differences in electrical conductivity and quantum efficiency between the ends and center of each active layer located on each pillar structure). However, by not exposing the substrate 102 between the pillar structures, the edge effects discussed above are avoided or reduced, and the regrown layer 502 has a more planar surface on each pillar structure. As a result, the active layer grown on the regrown layer 502 is of more uniform and higher quality.

[0025] 6 is a vertical cross-sectional view of a further intermediate structure 600 that may be used to form an LED structure, according to various embodiments. The intermediate structure 600 may include an active layer 602 and a second conductive type semiconductor material layer 604 formed on the first pillar structure 106a and the second pillar structure 106b. In this manner, a first vertical LED 601a and a second vertical LED 601b may be formed. The first vertical LED and the second vertical LED include laterally separated pillar-shaped LEDs.

[0026] The active layer 602 and the second conductivity type semiconductor material layer 604 may comprise single crystal semiconductor material selectively grown on the regrowth layer 502 using any suitable epitaxial growth method. The active layer 602 may comprise at least one semiconductor material that emits light upon application of a suitable electrical bias. For example, the active layer 602 may comprise a single or multiple quantum well (MQW) structure that emits light upon application of an electrical bias. For example, the quantum well may comprise an indium gallium nitride well located between gallium nitride or aluminum gallium nitride barrier layers. Alternatively, the active layer 602 may comprise other semiconductor layers or stacks of layers suitable for light emitting diode applications. The active layer 602 may be configured to emit light of any color, such as blue light, green light, red light, etc.

[0027] The second conductivity type semiconductor material layer 604 may include a compound semiconductor material having a doping of a second conductivity type opposite to the first conductivity type. The compound semiconductor material of the second conductivity type semiconductor material layer 604 may be any suitable semiconductor material, such as p-type gallium nitride or aluminum gallium nitride. For example, the continuous first conductivity type semiconductor material layer 106L may include n-type doped GaN and the second conductivity type semiconductor material layer 604 may include p-type doped GaN.

[0028] The total thickness of the active layer 602 and the second conductive type semiconductor material layer 604 is less than the thickness of each pillar structure (e.g., 106a or 106b). In this way, the active layer 602 and the second conductive type semiconductor material layer 604 deposited between the pillar structures 106a, 106b do not reach the height of the portion of the active layer 602 located on each pillar structure 106a, 106b in each vertical LED 601a, 601b. Therefore, the active layer 602 and the second conductive type semiconductor material layer 604 do not short the active layer 602 in each vertical LED 601a, 601b.

[0029] The active layer 602 and the second conductivity type semiconductor material layer 604 are selectively grown from the regrown layer 502 and are therefore not subjected to reactive ion etching. Thus, RIE-induced sidewall damage and sidewall dangling bonds are not generated in the active layer 602 and the second conductivity type semiconductor material layer 604. This results in improved semiconductor material quality and improved device performance in the active layer 602. Furthermore, since the substrate 102 is not exposed between the pillar structures during the growth of the regrown layer 502, the regrown layer 502 has a more planar surface above each pillar structure. This may result in the active layer 602 grown on the regrown layer 502 being of more uniform and higher quality.

[0030] FIG. 7 is a vertical cross-sectional view of a further intermediate structure 700 that may be used to form an LED structure, according to various embodiments. A dielectric matrix layer 702 may be formed between the vertical LEDs 601a and 601b. The dielectric matrix layer 702 may comprise a planarizable passivation material, such as an organic polymer or silicon oxide, or may comprise a self-planarizing passivation material, such as flowable oxide (FOX). In embodiments in which the dielectric matrix layer 702 comprises a non-planarizable dielectric material, a chemical mechanical polishing (CMP) process may be performed to provide a planar upper surface. The upper surface of the dielectric matrix layer 702 may be above or flush with the upper surface of the second conductive type semiconductor material layer 604. If the upper surface of the dielectric matrix layer 702 is flush with the upper surface of the second conductive type semiconductor material layer 604, the upper surface of the second conductive type semiconductor material layer 604 in each vertical LED 601a and 601b is exposed to the upper surface of the dielectric matrix layer 702.

[0031] 8 is a vertical cross-sectional view of a further intermediate structure 800 that may be used to form an LED structure, according to various embodiments. When the top surface of the dielectric matrix layer 702 is located above the top surface of the second conductive type semiconductor material layer 604, a photolithographic patterning process is performed to form openings over the vertical LEDs 601a and 601b, respectively. The second conductive type semiconductor material layer 604 is exposed in each opening.

[0032] Next, an electrode 802 is formed on the vertical LEDs 601a and 601b. If openings are present in the dielectric matrix layer 702, the electrode 802 may be formed by a damascene process. In a damascene process, a conductive material for the electrode is formed on the top surface of the dielectric matrix layer 702 and in the openings in the dielectric matrix layer 702. The conductive material is then planarized (e.g., by CMP) to leave the conductive material electrode 802 only in the openings that contact the second conductive type semiconductor material layer 604 of each vertical LED. If the top surface of the dielectric matrix layer 702 is coplanar with the top surface of the second conductive type semiconductor material layer 604, a continuous conductive material layer is formed on the top surface of the dielectric matrix layer 702. This continuous conductive layer is photolithographically patterned (e.g., by photolithography and etching) to form an electrode 802 that contacts the second conductive type semiconductor material layer 604 of each vertical LED exposed at the top surface of the dielectric matrix layer 702.

[0033] The electrode 802 may include an optional transparent conductive oxide layer 806 and an optional reflector layer 808. The transparent conductive oxide layer 806 may include a transparent conductive oxide material such as indium tin oxide or aluminum doped zinc oxide. Alternatively, the transparent conductive oxide layer 806 may be replaced with a silver or aluminum layer to provide a contact to the p-type semiconductor material (e.g., layer 604 of each vertical LED). In this case, the silver or aluminum layer may function as a reflector material layer, and subsequent deposition of a reflector material layer may be omitted.

[0034] The reflector layer 808 may be a metal. In one embodiment, the reflector layer 808 may include at least one material selected from silver, aluminum, copper, or gold. In one embodiment, the reflector material may be a thin-film distributed Bragg reflector (DBR) with a small change in refractive index to provide better reflectivity. Thus, the DBR reflector material may include at least one electrically conductive material and / or at least one electrically insulating material. The combination of the transparent conductive oxide layer 806 and the reflector layer 808 forms a p-side electrode 802 for each vertical LED 601a, 601b.

[0035] 9 is a vertical cross-sectional view of a further intermediate structure 900 that may be used to form an LED structure, according to various embodiments. A via cavity may be formed through the dielectric matrix layer 702. For example, a photoresist layer (not shown) may be formed on the dielectric matrix layer 702 and lithographically patterned to form a through opening. An anisotropic etching process may be performed to etch the dielectric matrix layer 702 until the surface of the buffer layer 104 is physically exposed to form a via cavity. In other embodiments, multiple via cavities may be formed such that each subsequently formed light emitting diode has a respective contact via structure. The photoresist layer may then be removed, for example by ashing.

[0036] At least one conductive material may be deposited in each via cavity. The at least one conductive material may include, for example, a metal liner material, such as TiN, TaN, WN, and a metal fill material, such as W, Cu, Mo, Al, Ag, Co, Au, Ni, Sn, other elemental metals, and / or alloys or combinations thereof. A CMP process and / or a selective recess etch may be performed to remove a portion of the at least one conductive material from the top surface of the dielectric matrix layer 702. A contact via structure 902 is formed in each via cavity. Each contact via structure 902 may include a metal liner 904, which may include a remaining portion of the metal liner material, and a metal fill material portion 906, which may include a remaining portion of the metal fill material. Each contact via structure 902 may extend vertically through the dielectric matrix layer 702 and may contact the buffer layer 104.

[0037] 10 is a vertical cross-sectional view of a further intermediate structure 1000 that may be used in forming an LED structure, according to various embodiments. Conductive bonding structures 1004, 1006 may be formed on the electrodes 802 and the contact via structures 802. The conductive bonding structures 1004, 1006 may include a first conductive bonding structure 1004 formed in electrical contact with a respective one of the p-side electrodes 802 and a second conductive bonding structure 1006 formed in electrical contact with a respective one of the contact via structures (e.g., n-side contact via structures) 902. The conductive bonding structures 1004, 1006 may include a solder material, which may include tin and, optionally, an alloy of tin with silver, gold, copper, bismuth, indium, zinc, and / or antimony. It should be understood that the shapes of the conductive bonding structures 1004, 1006 as shown are only schematic and may not represent the true shapes of the conductive bonding structures 1004, 1006.

[0038] The conductive bonding structures 1004, 1006 may be attached (i.e., bonded) to a supporting substrate, such as a backplane 1002. The conductive bonding structures 1004, 1006 may be bonded to bond pads or bonding structures (e.g., solder balls) disposed on the backplane 1002. Bonding may include bonding that reflows the conductive bonding structures, such as thermal (e.g., furnace anneal) bonding, laser bonding, or flash lamp bonding.

[0039] The backplane 1002 may be an active or passive matrix backplane substrate for driving the vertical LEDs 601a, 601b. As used herein, "backplane substrate" refers to any substrate configured to mount multiple devices thereon. The backplane 1002 may include a backplane substrate. The backplane substrate may be a substrate onto which various devices (e.g., LEDs) may be subsequently transferred.

[0040] In one embodiment, the backplane 1002 may include a substrate including silicon, glass, plastic, and / or at least one other material that may provide structural support to devices subsequently transferred thereon. In one embodiment, the backplane substrate may be a passive backplane substrate having a metal interconnect structure (not shown) including metallization lines, e.g., in a cross-shaped grid, and no active device circuitry. In another embodiment, the backplane substrate may be an active backplane substrate, which may include a metal interconnect structure as a cross-shaped grid of conductive lines, and may further include device circuitry at one or more intersections of the cross-shaped grid of conductive lines. The device circuitry may include one or more transistors, such as thin film transistors (TFTs).

[0041] FIG. 11 is a vertical cross-sectional view of an LED structure 1100 according to various embodiments. The substrate 102 and optionally the buffer layer 104 may be removed from the LEDs 601a and 601b. The removal may be performed by laser lift-off, mechanical removal, and / or selective etching. The removal step may be performed before or after the bonding step shown in FIG. 10. A second electrode 1102 is deposited on the exposed bottom side of the vertical LED. The second electrode 1102 may include a transparent conductive layer such as ITO, AZO, etc. The second electrode 1102 may be a common n-side electrode for all the vertical LEDs 601a, 601b in the device. The second electrode 1102 is in electrical contact (e.g., directly or indirectly) with a contact via structure 902 that is electrically connected to the backplane 1002. The vertical LEDs 601a, 601b include bottom-emitting LEDs that emit radiation (e.g., visible light) through the second electrode 1102.

[0042] Each of the vertical light emitting diodes 601a, 601b may emit the same color light (e.g., have the same peak emission wavelength) or may emit different colors of light (e.g., have different peak emission wavelengths). For example, the light emitting diodes may emit one of red, green, or blue light to form an RGB display. Alternatively, a color conversion medium such as quantum dots, phosphors, dyes, etc. may be provided between each light emitting diode and a viewer. The color conversion medium may be provided on the second electrode 1102 opposite the LEDs 601a, 601b. In this case, each light emitting diode may emit the same color light (e.g., blue light or ultraviolet light), and the color conversion medium may include red, green, and optionally blue (in the case of ultraviolet light emitting LEDs) color conversion medium to form an RGB display.

[0043] 11, a light emitting diode structure 1100 according to an embodiment includes a first light emitting diode 601a and a second light emitting diode 601b. The first LED 601a includes a first portion 106a of a first conductive type compound semiconductor layer 106L, a first portion 602a of a semiconductor active layer 602 located on the first portion 106a of the first conductive type compound semiconductor layer, and a first portion 604a of a second conductive type compound semiconductor layer 604 located on the first portion 602a of the semiconductor active layer.

[0044] The second LED 601b includes a second portion 106b of the first conductive type compound semiconductor layer 106L, a second portion 602b of the semiconductor active layer 602 located on the second portion 106b of the first conductive type compound semiconductor layer, and a second portion 604b of the second conductive type compound semiconductor layer 604 located on the second portion 602b of the semiconductor active layer. The trench 404 separates the first light emitting diode 601a and the second light emitting diode 601b.

[0045] The third portion 602c of the semiconductor active layer 602 and the third portion 604c of the second conductive type compound semiconductor layer 604 are located in the trench 404. The upper surface of the third portion 604c of the second conductive type compound semiconductor layer 604 is located below the first portion 602a and the second portion 602b of the semiconductor active layer 602 in each of the LEDs 601a and 601b.

[0046] In one embodiment, the first portion 502a of the semiconductor regrowth layer 502 is located between the first portion 106a of the first conductive type compound semiconductor layer 106L and the first portion 602a of the semiconductor active layer 602 in the first light emitting diode 601a. ​​The second portion 502b of the semiconductor regrowth layer 502 is located between the second portion 106b of the first conductive type compound semiconductor layer 106L and the second portion 602b of the semiconductor active layer 602 in the second light emitting diode 601b. The third portion 502c of the semiconductor regrowth layer 502 is located below the third portion 602c of the semiconductor active layer 602 in the trench 404.

[0047] In one embodiment, the semiconductor regrowth layer 502 comprises an n-type GaN single crystal layer having a c-plane top surface, the first conductivity type compound semiconductor layer 106L comprises an n-type GaN single crystal, the second conductivity type compound semiconductor layer 604 comprises a p-type GaN single crystal, and the semiconductor active layer 602 comprises at least one InGaN quantum well.

[0048] In one embodiment, the first electrodes 802a, 802b are disposed on the first and second portions 604a, 604b of the second conductivity type compound semiconductor layer 604 in the first and second light emitting diodes, respectively. A first conductive bonding structure 1004 is electrically connected to the first electrodes 802a, 802b. The dielectric matrix layer 702 laterally surrounds the first and second light emitting diodes 601a, 601b. The backplane 1002 is electrically connected to the first conductive bonding structure 1004.

[0049] In one embodiment, a common second electrode 1102 is located on the first and second portions 106a, 106b of the first conductive type compound semiconductor layer 106L, a contact via structure 902 extends vertically through the dielectric matrix layer 702 and electrically contacts the common second electrode 1102, and a second conductive bonding structure 1006 electrically connects the contact via structure 902 to the backplane 1002.

[0050] In one embodiment described above, the first portion 602a of the semiconductor active layer 602 is free of sidewall dangling bonds or reactive ion etch induced sidewall damage.

[0051] FIG. 12A is a vertical cross-sectional view of a further intermediate structure 1200a that may be used to form an LED structure, according to various embodiments. As shown in FIG. 12A, a via cavity 1202 may be formed through the dielectric matrix layer 702. For example, a photoresist layer (not shown) may be formed on the dielectric matrix layer 702 and lithographically patterned to form a through opening. An anisotropic etching process may be performed to etch through the dielectric matrix layer 702 until the top surface 1204 of the buffer layer 104 is physically exposed to form a via cavity. In other embodiments, multiple via cavities may be formed such that each subsequently formed light emitting diode has a respective contact via structure. The photoresist layer may then be removed, for example, by ashing.

[0052] FIG. 12B is a vertical cross-sectional view of a further intermediate structure 1200b that may be used to form an LED structure, according to various embodiments. In contrast to the embodiment of FIG. 9, an electrical insulation layer 1206 may be formed in the via cavity 1202 prior to the formation of the via contact structure 902. The intermediate structure 1200b may be formed from the intermediate structure 1200a by depositing an electrical insulation layer 1206 on the surface of the via cavity 1202 of FIG. 12A. The electrical insulation layer 1206 may include silicon oxide, silicon nitride, or silicon oxynitride. The electrical insulation layer 1206 may be conformally deposited as a thin film. The electrical insulation layer 1206 is then etched using an anisotropic etching process (e.g., reactive ion etching) in a sidewall spacer etching process to remove horizontal portions of the electrical insulation layer 1206 from the exposed top surface 1204 of the buffer layer 104 and the top surface of the dielectric matrix layer 702. This leaves sidewall spacer portions of the electrically insulating layer 1206 on the sidewalls of the via cavity 1202. The top surface 1204 of the buffer layer 104 is exposed in the via cavity 1202, as shown in Figure 12B.

[0053] 12C is a vertical cross-sectional view of a further intermediate structure 1200c that may be used to form an LED structure, according to various embodiments. With reference to FIG. 9, the intermediate structure 1200c may be formed by forming contact via structures 902 using the processes described above. Each contact via structure 902 may extend vertically through the dielectric matrix layer 702 and may contact the buffer layer 104 and remaining sidewall spacer portions of the electrical insulation layer 1206. The presence of the electrical insulation layer 1206 is advantageous in that it may prevent or reduce electrical shorts and leakage currents from the contact via structures 902 to surrounding portions of the intermediate structure 1200c.

[0054] 13A and 13B are vertical cross-sectional views of further intermediate structures 1300a and 1300b, respectively, that may be used to form an LED structure, according to various embodiments. The intermediate structure 1300a may be formed by forming a patterned mask layer 1302 on the intermediate structure 600 of FIG. 6. The electrode 802 may be formed on the intermediate structure 600 of FIG. 6 before forming the patterned mask layer 1302 on the electrode 802. Alternatively, the electrode 802 may be formed in a later step. For example, the patterned mask layer 1302 may be formed by depositing a photoresist material on the intermediate structure 600 of FIG. 6 or on the electrode 802 located on the intermediate structure 600. The deposited photoresist material may then be patterned using photolithography techniques to form the patterned mask layer 1302 on the first vertical LED 601a and the second vertical LED 601b of FIG. 6. 13B, an anisotropic etching process (e.g., reactive ion etching) may then be performed to remove the active layer 602, the second conductivity type semiconductor material layer 604, the regrown layer 502, and optionally a portion of the buffer layer 104 in the trench 404 and other areas between and adjacent the first vertical LED 601a and the second vertical LED 601b. After the etching process is completed, the patterned mask layer 1302 may be removed by ashing or dissolving in a solvent.

[0055] FIG. 14 illustrates a vertical cross-sectional view of a source coupon 1 including a plurality of the above-mentioned light emitting diodes 601a, 601b, 601c separated by trenches 404 according to various embodiments. With reference to FIGS. 1-6, 13A, and 13B, the light emitting diodes 601a, 601b, 601c may be formed using the methods described above. The light emitting diodes 601a, 601b, 601c may each be configured to emit radiation having a narrow band of wavelengths having a peak at a particular wavelength. In this manner, the light emitting diodes 601a, 601b, 601c may each emit light corresponding to a first color. For example, the light emitting diodes 601a, 601b, 601c may be configured to emit blue light and labeled 601BL. In other embodiments (see, for example, FIGS. 16A-17), the light emitting diodes 601a, 601b, 601c may be configured to emit green light and labeled 601G. In a further embodiment (see, e.g., FIG. 17), light emitting diodes 601a, 601b, 601c may be configured to emit red light, and are labeled 601R. As described below with reference to FIGS. 15A-17, the light emitting diodes (601BL, 601G, 601R) may be arranged on a backplane 32 to form multiple sub-pixels of a pixel of a display device, each pixel configured to emit multiple colors.

[0056] The first source coupon 1 may include a first substrate, which may include the support substrate 102 described above. The first substrate 102 may also be referred to as a first growth substrate or a first source substrate. As described above, the first light emitting diode 601BL is disposed on the first substrate 102. The first substrate 102 may be any suitable substrate on which an LED layer may be grown, such as a single crystal substrate. For example, the first substrate 102 may be a sapphire substrate. With reference to FIG. 5, as described above, each first light emitting diode 601BL may include a buffer layer 104, a first conductive type semiconductor layer 106, and a regrown layer 502. With reference to FIG. 6, as described above, the active layer 602 may be disposed on the regrown layer 502 and the first conductive type semiconductor layer 106, and the second conductive type semiconductor layer 604 may be disposed on the active layer 602.

[0057] As described above with reference to FIGS. 1-4, the light emitting diodes 601BL may be formed such that trenches 404 separate adjacent light emitting diodes 601BL. The trenches 404 define an area associated with each of the first LEDs 601BL. Specifically, a set of continuous material layers over the first substrate 102 and laterally bounded by a set of trenches 404 constitutes the first light emitting diodes 601BL. In one embodiment, the trenches 404 may be formed in a grid pattern to provide an array of first light emitting diodes, which may be a periodic array of first light emitting diodes 601BL. The first light emitting diodes 601BL may emit light at a first peak wavelength, e.g., blue light having a first peak wavelength in the blue spectral range.

[0058] 15A is a vertical cross-sectional view of an intermediate structure 1500a having the source coupon 1 of FIG. 14 disposed on the backplane 32 prior to attachment of the light emitting diodes 601BL to the backplane 34, according to various embodiments. A diode-side bonding material portion 17 may be attached to an electrode 802 located on the second conductivity type semiconductor layer 604 of each first light emitting diode 601BL. In one embodiment, the diode-side bonding material portion 17 may be a solder material portion, such as pure tin or an alloy of tin and indium.

[0059] The backplane 32 may include a substrate and a metal interconnect layer 325 formed on a front side of the substrate. In one embodiment, the substrate may include a plastic (e.g., polymer) substrate. Alternatively, the substrate may be a semiconductor substrate (e.g., a silicon wafer) that includes a plurality of active matrix selector elements, such as CMOS-configured field effect transistors, below the metal interconnect layer 325. In one embodiment, the metal interconnect layer 325 may include a plurality of metal interconnect structures located on and / or above the surface of the substrate and embedded in at least one insulating material. The metal interconnect layer 325 provides electrical connections between light emitting diodes bonded onto the backplane 32 and input / output pins of the backplane 32.

[0060] The bonding pads 34 may be provided on a surface of the backplane 32 overlying the metal interconnect layer 325. In one embodiment, the bonding pads 34 may be arranged as a two-dimensional periodic array or a one-dimensional periodic array. The bonding pads 34 may include a bonding pad material such as gold, copper, nickel, titanium, titanium nitride, tungsten, tungsten nitride, another metal having a higher melting point than the subsequently used solder material, their alloys, and / or their layer stacks. A backplane-side bonding material portion 37 may be attached to the bonding pads 34. In one embodiment, the backplane-side bonding material portion 37 may be a solder material portion such as pure tin or an alloy of tin and indium. The first source coupon 1 and the backplane 32 may be aligned such that pairs of the diode-side bonding material portion 17 and the backplane-side bonding material portion 37 face each other at each grid point of the periodic array of the bonding pads 34.

[0061] 15B is a vertical cross-sectional view of a further intermediate structure 1500b in which the backplane 32 and the first source coupon 1 are brought into contact with each other such that opposing pairs of the diode-side bonding material portions 17 and the backplane-side bonding material portions 37 are in contact with each other, according to various embodiments. Each of the diode-side bonding material portions 17 may have an area overlap with the respective underlying backplane-side bonding material portion 37. In one embodiment, the area of ​​the overlap may be at least 70% of the area of ​​the diode-side bonding material portion 17, and may be, for example, greater than 80% and / or greater than 90%. In one embodiment, the geometric center of each diode-side bonding material portion 17 may overlap the geometric center of the underlying backplane-side bonding material portion 37.

[0062] In general, at least one bonding material portion (17, 37) may be disposed between each vertically adjacent pair of a respective one of the bonding pads 34 and a respective one of the first light emitting diodes 601BL. In one embodiment, a pair of diode-side bonding material portion 17 and backplane-side bonding material portion 37 may be provided between each vertically adjacent pair of a respective one of the bonding pads 34 and a respective one of the first light emitting diodes 601BL. In one embodiment, the diode-side bonding material portion 17 may be omitted. In another embodiment, the backplane-side bonding material portion 37 may be omitted.

[0063] In one embodiment, a soldering agent 35 may be provided between the backplane 32 and the first light emitting diode 601BL such that the soldering agent 35 laterally surrounds each of the bonding material portions (17, 37). The soldering agent 35 may be any suitable liquid flux that reacts with tin oxide to produce metallic tin bonding material portions (17, 37). In one embodiment, a fixture such as a clamp 400 may be used to hold the assembly of the backplane 32 and the first source coupon 1 in place without lateral slippage. In an exemplary embodiment, the clamp 400 may include an upper plate 400U that presses against one backside of the backplane 32 or the first source coupon 1, a lower plate 400L that presses against the other backside of the backplane 32 or the first source coupon 1, a frame 400F that includes mechanical support elements that hold the upper plate 400U and the lower plate 400L in place, and an adjustment unit 400A that adjusts the force applied to the upper plate 400U and / or the lower plate 400L or adjusts the distance between the upper plate 400U and the lower plate 400L. The plate that contacts the first source coupon 1, such as the upper plate 400U, may include a material that is transparent to UV, visible, or IR laser radiation and / or may include a central opening such that the upper plate 400U clamps only the ends of the first source coupon 1 while the laser beam can pass through it.

[0064] In an exemplary embodiment, the backplane 32 and the first source coupon 1 may be held in place while applying a compressive force along a direction perpendicular to the assembly of the backplane 32, the bonding material portions (17, 37), and the first source coupon 1. The magnitude of the compressive force may be selected so that the bonding material portions (17, 37) do not significantly deform, i.e., so that the bonding material portions (17, 37) maintain their pre-clamped shape and do not bond the respective bonding material portions 17, 37 to each other. In an exemplary embodiment, when 100,000 pairs of diode-side bonding material portions 17 and backplane-side bonding material portions 37 are present between the backplane 32 and the first source coupon 1, the magnitude of the compressive force applied by the clamp 400 may be in the range of 250N to 400N.

[0065] FIG. 15C is a vertical cross-sectional view of an intermediate structure 1500b on which a sequential laser irradiation process may be performed to selectively laser irradiate with a peeling laser beam LD each buffer layer 104 covering the first light emitting diodes 601BL that are subsequently transferred to the backplane 32, according to various embodiments. The collection of all the first light emitting diodes 601BL that are subsequently transferred to the backplane 32 is referred to herein as a first subset of the first light emitting diodes 601BL. The peeling laser beam LD performs a partial laser lift-off process used for partial lift-off of the first subset of the first light emitting diodes 601BL, referred to herein as a peeling laser irradiation process. Each buffer layer 104 of the first subset of the first light emitting diodes 601BL is sequentially irradiated one by one with the peeling laser beam LD. The lateral dimensions (e.g., diameter) of the peeling laser beam LD may be comparable to the lateral dimensions of the first light emitting diodes 601BL. In this manner, each buffer layer 104 may be individually irradiated without causing significant compositional changes in adjacent buffer layers 104.

[0066] The delamination laser beam LD may have an ultraviolet or visible wavelength and may be absorbed by the gallium and nitrogen-containing III-V compound semiconductor material of the irradiated buffer layer 104. Without wishing to be bound by a particular theory, it is believed that the irradiation of the buffer layer 104 with the delamination laser beam LD evaporates nitrogen atoms without evaporating gallium atoms or with minimal evaporation of gallium atoms. Thus, the irradiation tends to reduce the proportion of nitrogen atoms in the remaining material. The first source coupon 1 and the backplane 32 may be mechanically secured by clamps 400 during and after this process.

[0067] In one embodiment, without being bound by any particular theory, it is believed that the irradiated subset of the buffer layer 104 in the first subset of the first light emitting diodes 601BL may be converted into gallium rich droplets 111. The gallium rich droplets 111 may be comprised of pure liquid gallium rich droplets or may include an alloy of gallium and nitrogen containing gallium at an atomic concentration of greater than 55%, for example, between 60% and 99% atomic concentration.

[0068] FIG. 15D is a vertical cross-sectional view of the intermediate structure 1500b of FIG. 15B according to various embodiments, in which the liquid gallium-rich droplets 111 solidify into solid gallium-rich material portions (e.g., pure gallium or gallium-rich alloy particles or regions) 211 after irradiation when the temperature of the first source coupon 1 is maintained below the melting point of gallium (e.g., 29.76° C.) or its alloys. In one embodiment, each remaining portion of the laser-irradiated buffer layer 104 (which is a subset of the buffer layer 104 in the first subset of first light-emitting diodes 601BL) may include gallium-rich material portions 211 (i.e., solid pure gallium or gallium-rich alloy particles or regions). In one embodiment, the gallium-rich material portions 211 may include gallium atoms at an atomic concentration of more than 55%, for example, between 60% and 100%. Gallium-rich material portion 211 may have an average thickness in the range of 5 nm to 100 nm, such as in the range of 10 nm to 50 nm, although lesser and greater thicknesses may also be employed.

[0069] Each gallium-rich material portion 211 may include a continuous layer of material or may include a cluster of ball-shaped material portions. The subset of the buffer layer 104 located within the second subset of first light emitting diodes 601BL that is not subsequently transferred to the backplane 32 is not irradiated with the laser beam LD and therefore remains as a buffer layer 104, such as a gallium nitride buffer layer, having approximately 50 atomic percent gallium and therefore a higher melting point than the gallium-rich material portions 211.

[0070] Because the backplane-side bonding material portions 37 and diode-side bonding material portions 17 in each adjacent pair only contact each other during laser irradiation and are not bonded to each other, mechanical shock from the laser irradiation is not transferred to the backplane 32, which may include a relatively fragile polymer. Thus, the partial laser lift-off described above with respect to Figures 15C and 15D to form the gallium-rich material portions 211 may cause little or no damage to the backplane 32 and the conductive elements (34, 325) thereon. Furthermore, the partial laser lift-off process prevents damage to the resolidified bonding material portions in subsequent processing steps, such as the processing step of Figure 15F, due to the bonding reflow that occurs after the partial laser lift-off.

[0071] 15E is a vertical cross-sectional view of the intermediate structure 1500b of FIG. 15B, where the backplane 32 and the first source coupon 1 are pressed together with a larger force, thereby inducing deformation of the bonding material portions (17, 37) (i.e., coining the bonding material portions to smooth the rough bonding surface). Thus, each mating pair of the respective diode-side bonding material portion 17 and the respective backplane-side bonding material portion 37 may be pressed together with a second pressure, which is greater than the first pressure, after the transformation of a subset of the buffer layer 104 into the gallium-rich material portion 211. The second pressure is sufficient to form deformations of the diode-side bonding material portion 17 and the backplane-side bonding material portion 37. In an illustrative example, when 100,000 pairs of diode side bonding material portions 17 and backplane side bonding material portions 37 are present between the backplane 32 and the first source coupon 1, the magnitude of the compressive force applied by the clamp 400 may be in the range of 500N to 1000N.

[0072] FIG. 15F is a vertical cross-sectional view of the intermediate structure 1500b of FIG. 15B, in which a sequential localized laser irradiation step may be performed to induce reflow and subsequent bonding of each mating pair of diode-side bonding material portions 17 and backplane-side bonding material portions 37 underlying the first subset of first light-emitting diodes 601BL transferred to the backplane 32. The laser irradiation induces bonding of the first subset of first light-emitting diodes 601BL to the backplane 32, and is referred to herein as a bonding laser irradiation step. The laser beam LB used in the bonding laser irradiation step may have a photon energy smaller than the band gap of the III-V compound semiconductor material (e.g., gallium and nitrogen-containing material) included in the first light-emitting diodes 601BL, and thus passes through the first light-emitting diodes 601BL. For example, the laser beam LB used in the bonding laser irradiation step may be an infrared laser beam, such as a carbon dioxide laser beam having a wavelength of 9.4 microns or 10.6 microns.

[0073] The laser beam LB may be applied sequentially to each mating pair of the diode-side bonding material portion 17 and the backplane-side bonding material portion 37. The irradiated pairs of the diode-side bonding material portion 17 and the backplane-side bonding material portion 37 are each heated to a reflow temperature at which the bonding material (which may be a solder material) of the pair of the diode-side bonding material portion 17 and the backplane-side bonding material portion 37 reflows. When the irradiation of the laser beam to the mating pair of the diode-side bonding material portion 17 and the backplane-side bonding material portion 37 is completed, the reflowed material resolidifies to obtain the resolidified bonding material portion 47. The resolidified bonding material portion 47 is bonded to the bonding pad 34 and the electrode 82 of the first light-emitting diode 601BL, respectively.

[0074] In general, the first subset of first light emitting diodes 601BL may be bonded to one of the respective underlying bonding pads 34 by localized laser irradiation of a set of at least one respective underlying bonding material portion (17, 37) to reflow and resolidify to form a resolidified bonding material portion 47. In one embodiment, each mating pair of the diode-side bonding material portion 17 and the backplane-side bonding material portion 37 may be pressed together with a second pressure during the localized laser irradiation. Each first light emitting diode 601BL in the first subset of first light emitting diodes 601BL may be bonded to the backplane 32, and each first light emitting diode 601BL in the second subset of first light emitting diodes 601BL may remain unbonded to the backplane 32. The gallium-rich material portion 211 may provide a weak adhesion between the first substrate 102 and the first conductivity type semiconductor layer 106. Because the first light emitting diode 601BL is held in place by the gallium rich material portion 211, a lower power laser beam LB may be used than in conventional bonding processes, further reducing damage to the backplane 32. The soldering agent 35 may be evaporated during irradiation by the laser beam LB or may be poured out after this step.

[0075] FIG. 15G is a vertical cross-sectional view of a further intermediate structure 1500g, in which the first source coupon 1 and backplane 32 are removed from the clamps 400 and heated to a temperature higher than the melting temperature of the gallium-rich material portion 211 and lower than the melting temperature of the amorphous buffer layer 104 (e.g., below the melting temperature of gallium nitride). For example, if the gallium-rich material portion 211 (see, e.g., FIG. 15F) comprises pure gallium, the temperature may be raised to at least 30° C., e.g., 35-50° C., thereby melting the gallium-rich material portion 211 into gallium-rich droplets 111 (see, e.g., FIG. 15C). This allows the first collection of the backplane 32 and the first subset of the first light-emitting diodes 601BL to be separated from the second collection of the first substrate 102 and the second subset of the first light-emitting diodes 601BL with or without the application of mechanical force. For example, the second assembly can be pulled away from the first assembly with a force of less than 100N.

[0076] Optionally, gallium-rich material portion 311 (such as remnants of resolidified gallium-rich droplets 111 or portion 211) may be present on the surface of buffer layer 104 (see, for example, FIG. 15G). Gallium-rich material portion 311 may include an atomic concentration of gallium of more than 55%, and may be more than 95%. In an embodiment, gallium-rich material portion 311 may consist essentially of gallium and may have a thickness in the range of 5 nm to 100 nm, for example, in the range of 10 nm to 50 nm. If a single color LED device is desired, the fabrication process may end with the step shown in FIG. 15G. Alternatively, the steps shown in FIG. 15A to FIG. 15G may be repeated to bond LEDs of different colors to backplane 32 to form a multicolor display.

[0077] FIG. 16A is a vertical cross-sectional view of a further intermediate structure 1600a according to various embodiments, in which a second source coupon 2 including second light emitting diodes 601G disposed on a second substrate 102 may be provided. Each of the second light emitting diodes 601G may include a respective additional buffer layer 104 at an interface with the second substrate 102. The second light emitting diodes 601G may include voids and be arranged in a pattern including a mirror image pattern of a first subset of the first light emitting diodes 601BL in the first collection. In an embodiment, the second light emitting diodes 601G may emit light at a second peak wavelength different from the first peak wavelength. The second source coupon and the first collection may be aligned with each other such that each of the first light emitting diodes 601BL on the backplane 32 is located under a void of one of the second source coupons.

[0078] 16B is a vertical cross-sectional view of a further intermediate structure 1600b according to various embodiments, where the backplane 32 and the second source coupon 2 are in contact with each other. In this regard, the second light emitting diodes 601G may be disposed on the first collection such that at least one additional bonding material portion (17, 37) is disposed between each vertically adjacent pair of a respective one of the bonding pads 34 and a respective one of the second light emitting diodes 601G. The second source coupon 2 may be aligned and clamped to the first assembly using the clamp 400 using the process steps described above with respect to FIG. 15B. A soldering agent 35 (not shown for clarity) may also be used during these steps. A subset of the additional buffer layers 104 may then be converted into additional gallium-rich material portions 211 (see, for example, FIG. 15D ) by performing the processing steps of FIG. 15C and FIG. 15D on each additional buffer layer 104 in the first subset of second light-emitting diodes 601G that are then transferred to the backplane 32.

[0079] 15C-15F may then be performed to bond the first subset of second light emitting diodes 601G to one of the respective underlying bonding pads 34 by localized laser irradiation of the pair of at least one respective additional underlying bonding material portion (17, 37). The irradiated pair of diode-side bonding material portion 17 and backplane-side bonding material portion 37 may each be heated to a reflow temperature at which the bonding material (which may be a solder material) of the pair of diode-side bonding material portion 17 and backplane-side bonding material portion 37 reflows. Once irradiation of the laser beam has been completed on the mating pair of diode-side bonding material portion 17 and backplane-side bonding material portion 37, the reflowed material may resolidify to obtain a resolidified bonding material portion 47 (see, for example, FIG. 15F). Resolidified bonding material portion 47 is bonded to bonding pad 34 and contact level material layer 15 of second light emitting diode 601G, for example as shown in FIG. 16C.

[0080] 16C is a vertical cross-sectional view of a further intermediate structure 1600c according to one embodiment, in which the second source coupon 2 is separated from the backplane 32 after the first subset of the second light emitting diodes 601G are bonded to the backplane. In this regard, the third collection of the backplane 32, the first subset of the first light emitting diodes 601BL, and the first subset of the second light emitting diodes 601G may be separated (i.e., detached) from the fourth assembly of the second substrate 102 and the second subset of the second light emitting diodes 601G that are not bonded to the backplane 32 by separating them at the additional gallium-rich material portion 211. The gallium-rich material portion 311 (such as a resolidified gallium-rich layer) may be located on a surface of the first conductivity type semiconductor layer 106 of the second light emitting diodes 601G.

[0081] 17 is a vertical cross-sectional view of a further intermediate structure 1700, according to an embodiment, in which a subset of the third light emitting diodes 601R are bonded to the backplane 32. In this regard, a third source coupon (not shown) may be provided, including the third light emitting diodes 601R disposed on a third substrate. Each of the third light emitting diodes 601R may include a respective additional buffer layer 104 at an interface with the third substrate. The third light emitting diodes 601R may include voids and be arranged in a pattern including a mirror image pattern of the first subset of the first light emitting diodes 601BL and the first subset of the second light emitting diodes 601G in the third collection. In an embodiment, the third light emitting diodes 601R may emit light at a third peak wavelength different from the first peak wavelength and the second peak wavelength.

[0082] 15B-15G may be performed to transfer the first subset of the third light emitting diodes 601R to the backplane 32. The backplane 32 may include an array of pixels to provide a direct-view display device. Each pixel may include one or more of the LEDs (601BL, 601G, 601R). In one embodiment, the backplane 32 may be a display frame for a direct-view display device, and each pixel of the direct-view display device may include at least one red light emitting diode (e.g., the third light emitting diode 601R) configured to emit light at a peak wavelength in the range of 620 nm to 750 nm, at least one green light emitting diode (e.g., the second light emitting diode 601G) configured to emit light at a peak wavelength in the range of 495 nm to 570 nm, and at least one blue light emitting diode (e.g., the first light emitting diode 601BL) configured to emit light at a peak wavelength in the range of 450 nm to 495 nm.

[0083] Next, the above-mentioned dielectric matrix layer 702 is formed between the light emitting diodes (601BL, 601G, 601R). A common electrode 1102 is formed on the dielectric matrix layer 702 and electrically contacts the buffer layer 104 side of the light emitting diodes (601BL, 601G, 601R).

[0084] The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.

Claims

1. 1. A method of forming a light emitting diode, comprising the steps of: forming a first conductive type compound semiconductor layer on a substrate; Etching the first conductivity type compound semiconductor layer to form a first pillar structure and a second pillar structure without exposing the substrate between the first and second pillar structures; Selectively growing a semiconductor active layer on the first and second pillar structures; Selectively growing a second conductivity type compound semiconductor layer on the semiconductor active layer; A method comprising:

2. selectively growing a semiconductor regrowth layer on the first pillar structure and the second pillar structure; the semiconductor active layer is selectively grown on the semiconductor regrowth layer; The method of claim 1.

3. the semiconductor regrowth layer, the semiconductor active layer, and the third portion of the second conductive type compound semiconductor layer are also formed in a trench located between the first pillar structure and the second pillar structure; an upper surface of the third portion of the second conductive type compound semiconductor layer is located below a first portion and a second portion of the semiconductor active layer located on the first pillar structure and the second pillar structure, respectively; The method of claim 2.

4. the first conductive type compound semiconductor layer and the second conductive type compound semiconductor layer each contain a Group III nitride material; The method of claim 2.

5. the first conductive type compound semiconductor layer includes an n-type GaN single crystal; the second conductive type compound semiconductor layer includes a p-type GaN single crystal; the semiconductor active layer includes at least one InGaN quantum well; each of the first pillar structure and the second pillar structure has a top surface that is a c-plane surface of the n-type GaN; the semiconductor regrowth layer includes an n-type GaN layer lattice-matched to the crystal structures of the first pillar structure and the second pillar structure and having an upper c-plane surface; The method according to claim 4.

6. The method further includes forming a compound semiconductor buffer layer on the substrate before forming the first conductive type compound semiconductor layer. The method according to claim 3.

7. the substrate comprises sapphire; etching the first conductive type compound semiconductor layer includes etching the first conductive type compound semiconductor layer so as to expose the compound semiconductor buffer layer in the trench between the first pillar structure and the second pillar structure without exposing the sapphire substrate in the trench between the first pillar structure and the second pillar structure; The method according to claim 6.

8. the first pillar structure, a first portion of the semiconductor regrowth layer located on the first pillar structure, a first portion of the semiconductor active layer located on the first portion of the semiconductor regrowth layer, and a first portion of the second conductivity type compound semiconductor layer located on the first portion of the semiconductor active layer comprise a first light emitting diode; the second pillar structure, a second portion of the semiconductor regrowth layer located on the second pillar structure, a second portion of the semiconductor active layer located on the second portion of the semiconductor regrowth layer, and a second portion of the second conductive type compound semiconductor layer located on the second portion of the semiconductor active layer comprise a second light emitting diode; The method of claim 1.

9. The method further includes forming a first electrode on the first portion and the second portion of the second conductive type compound semiconductor layer in the first light emitting diode and the second light emitting diode. The method according to claim 8.

10. bonding the first electrode to a backplane; removing the substrate; forming a common second electrode on the first and second pillar structures opposite the first electrodes of the first and second light emitting diodes; The method of claim 9 further comprising:

11. bonding a first electrode of a first light emitting diode to the backplane without bonding the first electrode of the second light emitting diode to the backplane; peeling the first light emitting diode from the substrate using laser lift-off while the second light emitting diode remains on the substrate; The method of claim 9 further comprising:

12. attaching a third light emitting diode and a fourth light emitting diode to the backplane; filling spaces between the first, third and fourth light emitting diodes with a dielectric matrix layer; The method of claim 11 , further comprising forming a common second electrode over the first, second and third light emitting diodes.

13. a first light emitting diode including a first portion of a first conductive type compound semiconductor layer, a first portion of a semiconductor active layer located on the first portion of the first conductive type compound semiconductor layer, and a first portion of a second conductive type compound semiconductor layer located on the first portion of the semiconductor active layer; a second light-emitting diode including: a second portion of the first conductive type compound semiconductor layer; a second portion of the semiconductor active layer located on the second portion of the first conductive type compound semiconductor layer; and a second portion of the second conductive type compound semiconductor layer located on the second portion of the semiconductor active layer; a trench separating the first light emitting diode and the second light emitting diode; and, a third portion of the semiconductor active layer and a third portion of the second conductive type compound semiconductor layer located in the trench, wherein an upper surface of the third portion of the second conductive type compound semiconductor layer is located below the first portion and the second portion of the semiconductor active layer; Including, Light emitting diode structure.

14. a first portion of a semiconductor regrowth layer located between the first portion of the first conductive type compound semiconductor layer and the first portion of the semiconductor active layer in the first light emitting diode; a second portion of the semiconductor regrowth layer located between the second portion of the first conductive type compound semiconductor layer and the second portion of the semiconductor active layer in the second light emitting diode; and, a third portion of the semiconductor regrowth layer located in the trench below the third portion of the semiconductor active layer; 14. The light emitting diode structure of claim 13 further comprising:

15. the first conductivity type compound semiconductor layer and the second conductivity type compound semiconductor layer each include a Group III nitride material; 15. The light emitting diode structure of claim 14.

16. the semiconductor regrowth layer includes an n-type GaN single crystal layer having a c-plane upper surface; the first conductive type compound semiconductor layer includes an n-type GaN single crystal; the second conductive type compound semiconductor layer includes a p-type GaN single crystal; The semiconductor active layer includes at least one InGaN quantum well.

16. The light emitting diode structure of claim 15.

17. In the first light emitting diode and the second light emitting diode, a first electrode is further located on the first portion and the second portion of the second conductive type compound semiconductor layer.

14. The light emitting diode structure of claim 13.

18. a first conductive bonding structure electrically connected to the first electrode; a dielectric matrix layer laterally surrounding the first and second light emitting diodes; a backplane electrically connected to the first conductive bonding structure; Further comprising:

20. The light emitting diode structure of claim 17.

19. a common second electrode located on the first portion and the second portion of the first conductive type compound semiconductor layer; a contact via structure extending vertically through the dielectric matrix layer and electrically contacting the common second electrode; a second conductive bonding structure electrically connecting the contact via structure to the backplane; Further comprising:

20. The light emitting diode structure of claim 18.

20. the first portion of the semiconductor active layer is free of sidewall dangling bonds or reactive ion etch induced sidewall damage; 14. The light emitting diode structure of claim 13.

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