Highly area-efficient semiconductor protection devices

Abstract

A highly area-efficient semiconductor device is described. Such a semiconductor device (200) may be disposed within an isolation structure (245) and includes a diode coupled to the isolation structure (245). In this manner, the semiconductor device may achieve a smaller footprint by utilizing area that would otherwise be left as inactive space (or dead space). Also, the semiconductor device may include multiple fingers of doped regions (270, 275) arranged horizontally, vertically, or a combination of both. The fingers of the doped regions form diodes connected in parallel with parallelized metal lines to facilitate carrying large amounts of current. The parallelized metal lines with shortened lengths improve problems associated with parasitic resistance of the metal lines during ESD or surge events.

Description

[Technical field]

[0001] The present description relates generally to the field of semiconductor devices, and more particularly to a highly area-efficient semiconductor protection device. [Background technology]

[0002] A semiconductor chip or integrated circuit (IC) contains multiple functional blocks connected together, such as input / output (I / O) blocks that send and receive electrical signals, signal processing blocks that handle the electrical signals, and a controller that manages the overall functionality of the IC. The functional blocks of an IC operate in their own power domains with different operating characteristics. Thus, interfaces between functional blocks are required to have certain attributes, such as isolating noise between one functional block and another and providing a conductive current path between functional blocks during electrostatic discharge (ESD) or surge events, among others.

[0003] For that purpose, one or more semiconductor protection devices may be placed at the interfaces between the functional blocks. Since a typical IC includes several such protection devices, it is desirable for the protection devices to be area efficient to avoid occupying a significant area of ​​the IC while handling the desired level of ESD or surge current. During normal operation of the IC, the protection devices are inactive so as not to interfere with normal operation. Although the protection devices are inactive (e.g., diodes under reverse bias conditions), their presence tends to increase the parasitic capacitance of the IC. It is therefore also desirable for the protection devices to have a small footprint to provide a low capacitance to the IC. Summary of the Invention

[0004] This description describes a semiconductor protection device that is highly area efficient. The protection device may include two or more diodes connected in parallel and in opposite directions. This summary is not an extensive overview of the description and is not intended to identify key or critical elements of the description or to delineate the scope thereof. Rather, the primary purpose of this summary is to present some concepts of the description in a simplified form as a prelude to the more detailed description that is presented later.

[0005] In some embodiments, a semiconductor device includes a first diode including a first pn junction across a p-doped region and a first n-well including the p-doped region, and a second diode including a second pn junction across the p-well and a second n-well adjacent the p-well. The first n-well is coupled to a first terminal and the p-doped region is coupled to a second terminal. The p-well is coupled to the first terminal and the second n-well is coupled to the second terminal, and the second n-well overlaps a third n-well of an isolation structure surrounding the semiconductor device.

[0006] In some embodiments, a semiconductor device includes a first diode including a first pn junction across an n-doped region and a p-well including the n-doped region, and a second diode including a second pn junction across a p-doped region and an n-well including the p-doped region. The n-doped region is coupled to a first terminal and the p-well is coupled to a second terminal. The p-doped region is coupled to the first terminal and the n-well is coupled to the second terminal, and the n-well overlaps a deep n-well of an isolation structure surrounding the semiconductor device.

[0007] In some embodiments, a semiconductor device includes a p-well including an n-doped region and an n-well surrounding the p-well. A first diode is formed across the n-doped region and the p-well. The n-well includes a p-doped region surrounding the p-well. A second diode is formed across the p-doped region and the n-well, where the n-well overlaps a deep n-well of an isolation structure surrounding the semiconductor device. [Brief description of the drawings]

[0008] For a more complete understanding of the following description, reference should be made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0009] [Figure 1] 1 illustrates a schematic diagram of a semiconductor die having multiple functional blocks and a protection device in accordance with an embodiment of the present disclosure.

[0010] [Figure 2A] 1 illustrates a schematic diagram and an equivalent circuit of a semiconductor device according to an embodiment of the present disclosure. [Figure 2B] 1 illustrates a schematic diagram and an equivalent circuit of a semiconductor device according to an embodiment of the present disclosure. [Figure 2C] 1 illustrates a schematic diagram and an equivalent circuit of a semiconductor device according to an embodiment of the present disclosure.

[0011] [Figure 3A] 1 illustrates a schematic diagram and an equivalent circuit of a semiconductor device according to an embodiment of the present disclosure. [Figure 3B] 1 illustrates a schematic diagram and an equivalent circuit of a semiconductor device according to an embodiment of the present disclosure. [Figure 3C] 1 illustrates a schematic diagram and an equivalent circuit of a semiconductor device according to an embodiment of the present disclosure.

[0012] [Figure 4] 1 illustrates a schematic diagram of a semiconductor device in accordance with an embodiment of the present disclosure;

[0013] [Diagram 5] 1 illustrates a schematic diagram of a semiconductor device in accordance with an embodiment of the present disclosure; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The present description will be described with reference to the accompanying drawings. The components in the drawings are not drawn to scale. Instead, emphasis is placed on clearly illustrating the overall features and principles of the present description. In order to provide an understanding of the present description, a number of specific details and relationships are described with reference to the examples of the drawings. Corresponding numerals and symbols in different drawings generally refer to corresponding parts unless otherwise indicated. The drawings and examples are not meant to limit the scope of the present description to such examples, and other embodiments are possible by replacing or modifying at least some of the elements described or shown. In addition, where the elements of the present description can be partially or completely implemented using known components, parts of such components that facilitate understanding of the present description will be described, and detailed descriptions of other parts of such components will be omitted so as not to obscure the present description.

[0015] The various structures described herein can be formed using semiconductor processing techniques. Layers including various materials can be formed on a substrate using, for example, deposition techniques (e.g., chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, plating), thermal processing techniques (e.g., oxidation, nitridation, epitaxy), and / or other suitable techniques. Similarly, portions of layers can be selectively removed using, for example, etching techniques (e.g., plasma (or dry) etching, wet etching), chemical mechanical planarization, and / or other suitable techniques, some of which may be combined with photolithography processes.

[0016] The semiconductor devices, integrated circuits, or IC components described herein may be formed on a semiconductor substrate (or die) including various semiconductor materials such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, silicon carbide, etc. In some cases, the substrate refers to a semiconductor wafer. The electrical conductivity (or resistivity) of the substrate (or a region of the substrate) can be controlled by doping techniques with various chemical species (which may also be referred to as acceptor or donor dopant atoms), including but not limited to boron, indium, arsenic, or phosphorous. Doping may be performed by ion implantation or other suitable doping techniques during the initial formation or growth of the substrate (or epitaxial layer grown on the substrate). A region or layer of the substrate doped with p-type dopant atoms (e.g., boron, indium, or other suitable acceptor dopant atoms) may be referred to as a p-type (first conductivity type or p-doped) region, layer, well, etc. Similarly, a region or layer of a substrate doped with n-type dopant atoms (e.g., phosphorus, arsenic, or other suitable donor dopant atoms) may be referred to as an n-type (second conductivity type or n-doped) region, layer, well, etc.

[0017] As used in this description, terms such as "first" and "second" are used to arbitrarily distinguish between elements that such terms describe. Thus, these terms in this specification and claims are not meant to indicate any temporal or other prioritization of such elements. Additionally, terms such as "front", "back", "top", "bottom", "above", "below", "vertical", "horizontal", "lateral", "below", "upper", "upper side", "lower side", and the like are used to refer to the relative orientation or position of features in a semiconductor device, given the orientation shown in the figures. For example, "upper" or "top" can refer to a feature that is located closer to the top of the page than another feature. Terms so used are interchangeable under appropriate circumstances, such that embodiments of the technology described herein can operate in other orientations than those illustrated or otherwise described herein, for example. As used herein, the term "approximately" can refer to a variation of ±5% to ±10% of the stated value in some cases. In other cases, the term "approximately" can refer to a variation of ±10% to ±20% of the stated value.

[0018] The present description describes a semiconductor device or circuit with high area efficiency. The semiconductor device in the present description includes a diode coupled to an isolation structure that surrounds the semiconductor device. In this way, the semiconductor device utilizes area that may otherwise be left as inactive space (or dead space) to improve area efficiency. The semiconductor device may be placed between different power or ground domains of an IC to isolate noise propagation from one power (or ground) domain to another. Also, during an ESD or surge event, the semiconductor device may provide a continuous path for current flow between all pairs of pins of an IC, which may be connected to different functional blocks (and thus different power or ground domains). The semiconductor device described herein has experimentally demonstrated area efficiency of about 50% or more while maintaining the same or better performance, e.g., ESD protection capability.

[0019] As described in more detail in this description, a semiconductor device may include multiple fingers of doped regions (e.g., strips of semiconductor substrate doped with n-type or p-type dopant species) arranged horizontally, vertically, or a combination of both. The fingers of doped regions are arranged to form parallel-connected diodes with the metal lines connected thereto, but with their anode and cathode terminals reversed; that is, their polarities are reversed. In other words, the anode of the first diode is connected to the cathode of the second diode, and the cathode of the first diode is connected to the anode of the second diode. Such diodes may be referred to as anti-parallel (AP) diodes. The fingers of doped regions are also arranged to facilitate reducing the length of the metal lines along the current flow direction during an ESD or surge event. The metal lines are also highly parallelized to facilitate the carrying of large amounts of current. The parallelized metal lines with reduced length improve problems associated with the parasitic resistance of the metal lines.

[0020] 1 is a schematic diagram of a semiconductor die (or IC) 100 in accordance with an embodiment of the present disclosure. The semiconductor die 100 may be a mixed-signal semiconductor chip or a power management IC (PMIC) that includes multiple functional blocks with their own power domains, such as analog power domain 105 (also individually identified as 105a-105c), digital power domain 110 (also individually identified as 110a-110c), clock signal power domain 115 (also individually identified as 115a-115d), and power domain 120 (also individually identified as 120a and 120b). The power domain 120 may be application specific, such as a power signal area for a PMIC. Each individual power domain of the semiconductor die 100 may have different operating characteristics, such as operating voltage levels, allowable noise margins, ground potentials, etc.

[0021] The semiconductor die 100 includes AP diodes 125 (some of which are individually identified as AP diodes 125a-125i), each of which includes an embodiment of a semiconductor device described with reference to FIGS. 2A-5. The AP diodes 125 are located between two power domains. For example, the AP diode 125e is located between the analog power domain 105a with an analog ground (which may be considered a relatively silent ground) and the power domain 120a with a power ground (which may be considered a relatively noisy ground). The AP diodes 125 mitigate noise propagation between different power domains within a certain value, such as, for example, 300 mV. In some embodiments, the AP diodes 125 are stacked (e.g., connected in series) so that noise propagation can be mitigated within a larger value, such as, for example, 600 mV. The AP diodes 125 also provide a connection between different power domains to safely dissipate current caused by an ESD or surge event. In this regard, every pin of semiconductor die 100 is coupled to another pin through one or more AP diodes 125. For example, a pin connected to analog power domain 105a is coupled to a pin connected to digital power domain 110a through, for example, AP diodes 125e, 125d, and 125i.

[0022] 2A-2C illustrate a schematic diagram and an equivalent circuit of a semiconductor device 200 in an embodiment of the present description. Fig. 2A shows a plan view (which may be considered as a composite layout) of the semiconductor device 200 surrounded by an isolation structure 245, Fig. 2B shows a cross-sectional view of the semiconductor device 200 and the isolation structure 245 as shown in Fig. 2A, and Fig. 2C is an equivalent circuit of the semiconductor device 200. These figures will be described simultaneously in the following description.

[0023] 2B, semiconductor device 200 may be fabricated using a p-type substrate 230 having an n-type layer 235 formed thereon. Semiconductor device 200 also has a p-type layer 240 formed on n-type layer 235. Thus, n-type layer 235 is "buried" under p-type layer 240 and may be referred to as an n-type buried layer (NBL). In some embodiments, NBL 235 has a net doping density of about 1×10 18 cm -3 In some embodiments, the NBL 235 may be omitted. The p-type layer 240 may be an epitaxial layer including p-type dopant atoms and may be referred to as a p-type epitaxial layer 240 (epi layer 240 or p-epi layer 240). In some embodiments, the net doping density of the p-epi layer 240 may be on the order of 1×10 16 cm -3 In some embodiments, the thickness of p-epi layer 240 may be about 6 micrometers (μm) after completing process steps to form semiconductor device 200.

[0024] As shown in FIG. 2A , the semiconductor device 200 is surrounded by an isolation structure 245. The isolation structure 245 includes a deep n-doped well 246 (deep n-well 246) and a deep trench isolation (DTI) structure 247. The deep n-well 246 extends from the surface 201 of the p-epi layer 240 of the semiconductor device 200 toward the substrate 230 and connects to the NBL 235. Thus, the depth of the deep n-well 246 is greater than the thickness of the epi layer 240 (e.g., about 6 μm). In some embodiments, the depth of the deep n-well 246 can be about 9 μm from the surface 201. In some embodiments, the net doping density of the deep n-well 246 is about 1×10 18 cm -3 The area surrounded by the isolation structure 245 (e.g., deep n-well 246) may be referred to as an isolation tank 250. Thus, isolation tank 250 may refer to the p-epi layer 240 confined by an n-type region. In other words, isolation tank 250 may be laterally surrounded by deep n-well region 246 and vertically separated from substrate 230 by NBL 235.

[0025] In some embodiments, the DTI structure 247 can be omitted from the isolation structure 245, as described with reference to Figure 5. In such embodiments, the thickness of the p-epi layer can be about 3 μm after completing process steps to form a semiconductor device (e.g., semiconductor device 500). Also, the depth of the deep n-well is greater than the epi layer thickness (e.g., about 3 μm), which can be about 5.7 μm deep from the surface 201.

[0026] The semiconductor device 200 includes a first n-type doped well 260 (first n-type well 260). The semiconductor device 200 also includes a p-doped well 265 (p-well 265) surrounding the first n-well 260. The semiconductor device 200 also includes a second n-doped well 261 (second n-well 261) surrounding the p-well 265. The second n-well 261 at least partially overlaps the deep n-well 246. The second n-well 261 may also contact the DTI structure 247 if the isolation structure 245 includes the DTI structure 247. In some embodiments, the first and second n-wells 260 and 261 are formed simultaneously, for example, by forming a photoresist pattern that opens regions corresponding to the first and second n-wells 260 and 261, and then performing an ion implantation process to introduce n-type dopant atoms. The net dopant concentration in the n-doped and p-doped wells is about 1×10 18 cm -3 In some embodiments, the depth of n-wells 260 and 261 and p-well 265 may be on the order of about 1.4 μm from surface 201. Thus, n-wells 260 and 261 and p-well 265 may be referred to as shallow n-wells and shallow p-wells in view of their relatively shallow dopant profile compared to deep n-well 246, which has a relatively deep dopant profile as illustrated in FIG.

[0027] The first n-well 260 includes at least one p-doped region 270 (FIGS. 2A and 2B illustrate two p-doped regions 270a and 270b) and at least one n-doped region 275 (FIGS. 2A and 2B illustrate three n-doped regions 275a-c). As shown in FIG. 2A and 2B, the p-doped regions 270 and the n-doped regions 275 in the first n-well 260 alternate with each other. The p-doped region 270 located in the first n-well 260 forms a first pn junction corresponding to the first diode D1 as shown in FIG. 2B and 2C. The first n-well 260 is coupled to a first terminal N1 / H (which may be referred to as node 1 or a high node) through an n-doped region 275 (e.g., n-doped regions 275a-275c) in the first n-well 260. The p-doped region 270 in the first n-well 260 is coupled to a second terminal N2 / L (which may be referred to as node 2 or a low node). The first and second terminals (e.g., high node and low node) are arbitrarily designated and therefore interchangeable without affecting the operation of the semiconductor device 200. The net dopant concentration of the n-doped region (which may be referred to as an n+ region) and the p-doped region (which may be referred to as a p+ region) is about 1×10 18 cm -3 2B, the semiconductor device 200 includes shallow trench isolation (STI) structures 255 that separate (isolate) the individual p-doped regions 270 and n-doped regions 275. In some embodiments, isolation structures other than the STI structures 255, such as local oxidation of silicon (LOCOS) structures, silicide block structures, polysilicon structures, etc., may be formed to separate the individual p-doped regions 270 and n-doped regions 275 from one another.

[0028] As described above, the p-well 265 surrounds the first n-well 260, and the second n-well 261 surrounds the p-well 265. Thus, the p-well 265 is located between the first n-well 260 and the second n-well 261 such that an inner boundary of the p-well 265 abuts the first n-well 260 and an outer boundary of the p-well 265 abuts the second n-well 261. That is, the second n-well 261 is adjacent to the outer boundary of the p-well 265. The outer boundary of the p-well 265 abutting the second n-well 261 forms a second p-n junction corresponding to the second diode D2, as shown in FIGS. 2B and 2C. In other words, the second diode D2 (i.e., the second p-n junction) is formed at the interface between the p-well 265 and the second n-well 261 along the outer boundary (or perimeter) of the p-well 265. The p-well 265 is coupled to the first terminal N1 / H through p-doped regions (e.g., p-doped regions 270c and 270d) in the p-well 265. The second n-well 261 is coupled to the second terminal N2 / L through n-doped regions (e.g., n-doped regions 275d and 275e) in the second n-well 261. Because the second n-well 261 overlaps the deep n-well 246, the n-doped regions (e.g., n-doped regions 275d and 275e) connecting the second n-well 261 to the second terminal N2 / L can be considered to be located within the deep n-well 246.

[0029] In this way, the first diode D1 and the second diode D2 form an anti-parallel diode, as shown in FIG. 2C. In other words, the anode of the first diode D1 (e.g., the p-doped region 270a) is connected to the cathode of the second diode D2 (e.g., the second n-well 261) at the second terminal N2 / L, and the cathode of the first diode D1 (e.g., the first n-well 260) is connected to the anode of the second diode D2 (e.g., the p-well 265) at the first terminal N1 / H. The AP diode 125 described with reference to FIG. 1 may be or may include an example of an aspect of the semiconductor device 200.

[0030] The semiconductor device 200 includes a first conductive structure 280 corresponding to a first terminal N1 / H and a second conductive structure 285 corresponding to a second terminal N2 / L, as shown in FIG. 2(a). In some embodiments, the first and second conductive structures 280 and 285 include metal lines (e.g., aluminum, copper, tungsten). The semiconductor device 200 also includes contacts 290 connecting the first and second conductive structures 280 and 285 to the respective p-doped regions 270 and n-doped regions 275. The p-doped regions 270 and n-doped regions 275 extend in a first direction parallel to each other (e.g., a horizontal direction, such as the orientation of the semiconductor device 200 shown in FIG. 2A) along a surface 201 of the p-epi layer 240. The first and second conductive structures 280 and 285 include portions (strips or fingers) covering the contacts 290 that extend in a second direction perpendicular to the first direction (e.g., a vertical direction such as the orientation of the semiconductor device 200 shown in FIG. 2A).

[0031] The layout configuration of the conductive structures 280 and 285 relative to the p-doped region 270 and the n-doped region 275, in conjunction with the location of the contacts 290 connecting the p-doped region 270 and the n-doped region 275 to the respective conductive structures 280 and 285, facilitates reducing the distance that current flows through the conductive structures 280 and 285, for example, during an ESD or surge event. The reduced distance reduces the length of the conductive strips of the first and second conductive structures 280 and 285, thereby reducing their sheet resistance, which can reduce the amount of voltage drop across the conductive strips. The conductive structures 280 and 285, which comprise multiple strips parallel to one another, further help improve the current handling capabilities of the semiconductor device 200.

[0032] Also, the footprint of the semiconductor device 200 overlaps a portion of the isolation structure 245. For example, the second n-well 261 of the semiconductor device 200 overlaps the deep n-well 246 of the isolation structure 245. In other words, the semiconductor device 200 extends (e.g., expands) beyond the boundaries of the isolation tank 250. In this manner, the semiconductor device 200 has improved area efficiency compared to other AP diode layouts that are confined inside the isolation tank 250 at a distance from the boundaries of the isolation tank 250 (e.g., the deep n-well 246).

[0033] 2A-2C illustrate the first n-well 260 including two p-doped regions 270 and three n-doped regions 275, the present description is not so limited. For example, the first n-well 260 may include one p-doped region 270 located between two n-doped regions 275. The first n-well 260 may also include three or more p-doped regions 270 and four or more n-doped regions 275, alternating with one another.

[0034] 3A-3C illustrate a schematic diagram and an equivalent circuit of a semiconductor device 300 in an embodiment of the present description. Fig. 3A shows a plan view of the semiconductor device 300 surrounded by an isolation structure 245 (which may be considered as a composite layout), Fig. 3B shows a cross-sectional view of the semiconductor device 300 and isolation structure 245 marked in Fig. 3A, and Fig. 3C is an equivalent circuit of the semiconductor device 300. These figures will be described simultaneously in the following description.

[0035] The semiconductor device 300 includes an embodiment of the semiconductor device 200 described with reference to Figures 2A-2C. For example, as shown in Figure 3B, the semiconductor device 300 includes a p-type substrate 230, an n-type buried layer (NBL) 235, and a p-epi layer 240. The semiconductor device 300 is also surrounded by an isolation structure 245 including a deep n-doped well 246 (deep n-well 246) and a deep trench isolation (DTI) structure 247. The deep n-well 246 extends from a surface 301 of the semiconductor device 300 toward the substrate 230 and connects to the NBL 235. The area surrounded by the isolation structure 245 (e.g., the deep n-well 246) may be referred to as an isolation tank 250.

[0036] The semiconductor device 300 includes a p-doped well 365 (p-well 365). The semiconductor device 300 also includes an n-doped well 360 (n-well 360) surrounding the p-well 365. The n-well 360 at least partially overlaps the deep n-well 246. Also, if the isolation structure 245 includes a DTI structure 247, the n-well 360 may abut the DTI structure 247. The n-well 360 and the p-well 365 include aspects of the first and second n-wells 260 and 261, and the p-well 265, respectively, such as dopant profiles and net dopant concentrations. Thus, the n-well 360 and the p-well 365 may be referred to as a shallow n-well and a shallow p-well.

[0037] The p-well 365 includes at least one n-doped region 375 (FIGS. 3A and 3B illustrate two n-doped regions 375a and 375b, which include an embodiment of the n-doped region 275) and at least one p-doped region 370 (FIGS. 3A and 3B illustrate three p-doped regions 370a-370c, which include an embodiment of the p-doped region 270). As shown in FIG. 3A and 3B, the p-doped regions 370 and the n-doped regions 375 are interleaved with each other in the p-well 365. The n-doped region 375 located in the p-well 365 forms a first pn junction, which corresponds to the first diode D1 shown in FIG. 3B and 3C. The n-doped region 375 in the p-well 365 is coupled to a first terminal N1 / H (which may be referred to as node 1 or high node). The p-well 365 is coupled to a second terminal N2 / L (which may be referred to as node 2 or the low node) through a p-doped region 370 (eg, p-doped regions 370a-370c) within the p-well 365.

[0038] As described above, the n-well 360 surrounds (e.g., encircles) the p-well 365. The n-well 360 also includes at least one p-doped region 370 (FIGS. 3A and 3B illustrate two p-doped regions 370d and 370e) and at least one n-doped region 375 (FIGS. 3A and 3B illustrate four n-doped regions 375c-375f). The p-doped regions 370 (e.g., p-doped regions 370d and 370e) located within the n-well 360 form a second pn junction corresponding to the second diode D2 as shown in FIGS. 3B and 3C. The p-doped regions 370 (e.g., p-doped regions 370d and 370e) within the n-well 360 are coupled to the first terminal N1 / H. The n-well 360 is coupled to the second terminal N2 / L via n-doped regions 375 (e.g., n-doped regions 375c-375f) within the n-well 360. As described above, the n-well 360 overlaps the deep n-well 246. Thus, some of the n-doped regions 375 within the n-well 360 (e.g., n-doped regions 375c and 375e) may also be considered to be located within the deep n-well 246.

[0039] In this way, the first diode D1 and the second diode D2 constitute an anti-parallel diode, as shown in FIG. 3C. In other words, the anode (e.g., p-well 365) of the first diode D1 is connected to the cathode (e.g., n-well 360) of the second diode D2 at the second terminal N2 / L, and the cathode (e.g., n-doped region 375a) of the first diode D1 is connected to the anode (e.g., p-doped region 370e) of the second diode D2 at the first terminal N1 / H. The AP diode 125 described with reference to FIG. 1 may be or may include an example of an aspect of the semiconductor device 300.

[0040] The semiconductor device 300 includes a first conductive structure 380 corresponding to the first terminal N1 / H and a second conductive structure 385 corresponding to the second terminal N2 / L, which are shown in FIG. 3A. The first and second conductive structures 380 and 385 include aspects of the first and second conductive structures 280 and 285 described with reference to FIG. 2A. The semiconductor device 300 also includes contacts 290 connecting the first and second conductive structures 380 and 385 to the respective p-doped regions 370 and n-doped regions 375. The p-doped regions 370 and n-doped regions 375 extend in a first direction parallel to each other along a surface 301 of the semiconductor device 300 (e.g., a horizontal direction such as the orientation of the semiconductor device 300 shown in FIG. 3A). The first and second conductive structures 380 and 385 include portions (strips or fingers) that cover the contacts 290 and extend in a second direction perpendicular to the first direction (e.g., a vertical direction as in the orientation of the semiconductor device 300 shown in FIG. 3A).

[0041] Similar to semiconductor device 200, the layout configuration of conductive structures 380 and 385 relative to p-doped region 370 and n-doped region 375, in conjunction with the location of contacts 290 connecting p-doped region 370 and n-doped region 375 to the respective conductive structures 380 and 385, facilitates reducing the distance that current travels through conductive structures 380 and 385 during, for example, an ESD or surge event. The reduced distance reduces the length of the conductive strips of first and second conductive structures 380 and 385, thereby reducing their sheet resistance, such that the amount of voltage drop across the conductive strips can be reduced. Conductive structures 380 and 385 comprising multiple strips parallel to one another further aids in improving the current handling capabilities of semiconductor device 300.

[0042] Also, the footprint of the semiconductor device 300 overlaps a portion of the isolation structure 245. For example, the n-well 360 of the semiconductor device 300 at least partially overlaps the deep n-well 246 of the isolation structure 245. In other words, the semiconductor device 300 extends (e.g., expands) beyond the boundaries of the isolation tank 250. In this manner, the semiconductor device 300 has improved area efficiency compared to other AP diode layouts that are confined inside the isolation tank 250 at a distance from the boundaries of the isolation tank 250 (e.g., the deep n-well 246).

[0043] 3A-3C illustrate that the p-well 365 includes two n-doped regions 375 and three p-doped regions 370, but the present description is not limited thereto. For example, the p-well 365 may include one n-doped region 375 and two p-doped regions 370, each of which is located next to a respective side of the n-doped region 375. The p-well 365 may also include three or more n-doped regions 375 and four or more p-doped regions 370, alternating with each other. Similarly, the amount of n-doped regions 375 and p-doped regions 370 in the n-well 360 may be varied (reduced or increased compared to that of FIGS. 3A and 3B) within the scope of the present description. For example, instead of having two n-doped regions 375c and 375d (or n-doped regions 375e and 375f) on either side of p-doped region 370d (or p-doped region 370e), n-doped region 375d (or n-doped region 375f) may be omitted.

[0044] FIG. 4 illustrates a schematic diagram of a semiconductor device 400 in an embodiment of the present description. The semiconductor device 400 includes aspects of the semiconductor devices 200 and 300 described with reference to FIGS. 2A-3C. For example, as shown in FIG. 3B, the semiconductor device 400 includes a p-type substrate 230, an n-type buried layer (NBL) 235, and a p-epi layer 240. FIG. 4 shows a top view of the semiconductor device 400 (which may be considered a composite layout) surrounded by a structural isolation layer 245. The semiconductor device 400 may be considered a variation of the semiconductor device 300 in that the n-type and p-type regions 370, 375 are rotated 90° relative to the semiconductor device 400. Thus, the cross-sectional view shown in FIG. 3B corresponds to the cross-sectional view of the semiconductor device 400 as marked in FIG. 4.

[0045] The semiconductor device 400 includes first and second conductive structures 480, 485 corresponding to the first terminal N1 / H and the second terminal N2 / L, respectively. In this regard, the first and second conductive structures 480 and 485 can be considered to be modified in layout to form an AP diode based on the arrangement of the n-type region 375 and the p-type region 370 of the semiconductor device 400. Also, the contacts 290 are distributed so that the p-doped region 370 and the n-doped region 375 can be appropriately coupled to the first and second conductive structures 480 and 485, respectively. This applies the equivalent circuit shown in FIG. 3C to the semiconductor device 400.

[0046] Similar to semiconductor device 300, an n-doped region 375 located in p-well 365 forms a first pn junction corresponding to first diode D1 shown in Figures 3B and 3C. The n-doped region 375 in p-well 365 is coupled to a conductive structure 480 corresponding to a first terminal N1 / H. The p-well 365 is coupled through a p-doped region 370 in p-well 365 to a conductive structure 485 corresponding to a second terminal N2 / L.

[0047] The n-well 360 surrounds (e.g., encircles) the p-well 365. A p-doped region 370 located within the n-well 360 forms a second pn junction corresponding to the second diode D2, as shown in Figures 3B and 3C. The p-doped region 370 within the n-well 360 is coupled to a conductive structure 480 corresponding to the first terminal N1 / H. The n-well 360 is coupled via an n-doped region 375 within the n-well 360 (or within the deep n-well 246) to a conductive structure 485 corresponding to the second terminal N2 / L.

[0048] In this way, the first diode D1 and the second diode D2 constitute an anti-parallel diode, as shown in FIG. 3C. In other words, the anode of the first diode D1 (e.g., p-well 365) is connected to the cathode of the second diode D2 (e.g., n-well 360) at the second terminal N2 / L, and the cathode of the first diode D1 (e.g., n-doped region 375 in p-well 365) is connected to the anode of the second diode D2 (e.g., p-doped region 370 in n-well 360) at the first terminal N1 / H. The AP diode 125 described with reference to FIG. 1 may be or may include an example of an embodiment of the semiconductor device 400.

[0049] 4, p-doped region 370 and n-doped region 375 extend in a second direction (e.g., vertical, such as the orientation of semiconductor device 400 shown in FIG. 4) parallel to one another along the surface of semiconductor device 400. First and second conductive structures 480 and 485 include portions (strips or fingers) that cover contact 290 and extend in the same direction (e.g., second direction, vertical) as p-doped region 370 and n-doped region 375.

[0050] Similar to the semiconductor devices 200 and 300, the layout configuration of the conductive structures 480 and 485 relative to the p-doped region 370 and the n-doped region 375, in conjunction with the location of the contacts 290 connecting the p-doped region 370 and the n-doped region 375 to the respective conductive structures 480 and 485, facilitates reducing the distance that current flows through the conductive structures 480 and 485 during, for example, an ESD or surge event. The reduced distance reduces the length of the conductive strips of the first and second conductive structures 480 and 485, thereby reducing their sheet resistance, which can reduce the amount of voltage drop across the conductive strips. The conductive structures 480 and 485, which comprise multiple strips parallel to one another, further help improve the current handling capabilities of the semiconductor device 400. Additionally, the footprint of the semiconductor device 400 overlaps a portion of the isolation structure 245. For example, the n-well 360 of the semiconductor device 400 overlaps the deep n-well 246 of the isolation structure 245 such that the semiconductor device 400 has improved area efficiency.

[0051] FIG. 5 illustrates a schematic diagram of a semiconductor device 500 in an embodiment of the present description. FIG. 5 shows a plan view (which may be considered a composite layout) of the semiconductor device 500 surrounded by an isolation structure including a deep n-well 246. In comparison with the isolation structure 245, the isolation structure surrounding the semiconductor device 500 lacks a DTI structure, e.g., the DTI structure 247 is omitted from the isolation structure 245. The semiconductor device 500 includes aspects of the semiconductor devices 200, 300, and 400 described with reference to FIGS. 2A-4. For example, the semiconductor device 500 includes a p-type substrate 230, an n-type buried layer (NBL) 235, and a p-epi layer 240 described with reference to FIGS. 2B and 3B. The deep n-well 246 extends from the surface of the semiconductor device 500 toward the substrate 230 and connects to the NBL 235. The area surrounded by the isolation structure (e.g., the deep n-well 246) may be referred to as an isolation tank. Semiconductor device 500 may be considered a variation of semiconductor device 400 in that the n-type and p-type regions 370 and 375 outside of p-well 365 have been modified to improve the area efficiency of semiconductor device 500.

[0052] The semiconductor device 500 includes a p-doped well 365 (p-well 365). The semiconductor device 500 also includes an n-doped well 360 (n-well 360) that surrounds (e.g., encircles) the p-well 365. The n-well 360 at least partially overlaps the deep n-well 246. The n-well 360 and the p-well 365 include aspects of the first and second n-wells 260 and 261 and the p-well 265, respectively, such as, for example, dopant profile, net dopant concentration, etc. Thus, the n-well 360 and the p-well 365 may be referred to as a shallow n-well and a shallow p-well.

[0053] The p-well 365 includes at least one n-doped region 375 (FIG. 5 illustrates multiple n-doped regions 375) and at least one p-doped region 370 (FIG. 5 illustrates multiple p-doped regions 370). As shown in FIG. 5, the p-doped regions 370 and the n-doped regions 375 in the p-well 365 are interleaved with each other. The n-doped region 375 located in the p-well 365 forms a first pn junction corresponding to a first diode D1 (e.g., the D1 diode shown in FIGS. 3B and 3C). The n-doped region 375 in the p-well 365 is coupled to a first conductive structure 580 corresponding to a first terminal N1 / H (which may be referred to as node 1 or high node). The p-well 365 is coupled to a second conductive structure 585 corresponding to a second terminal N2 / L (which may be referred to as node 2 or the low node) via a p-doped region 370 within the p-well 365.

[0054] As described above, the n-well 360 surrounds (e.g., encircles) the p-well 365. The n-well 360 also includes at least one p-doped region 370 (FIG. 5 illustrates two p-doped regions 370) and at least one n-doped region 375 (FIG. 5 illustrates two n-doped regions 375a and 375b). FIG. 5 also shows one n-doped region 375c spanning the deep n-well 246 and the n-well 360. The p-doped region 370 located within the n-well 360 forms a second pn junction corresponding to the second diode D2 (e.g., the D2 diode shown in FIGS. 3B and 3C). The n-doped region 375 and the p-doped region 370 outside the p-well 365 surround (e.g., surround) the p-well 365. In this manner, most of the area of ​​the isolation tank is utilized as either the n-doped region 375 or the p-doped region 370 such that the area efficiency of the semiconductor device 500 can be further increased.

[0055] The p-doped region 370 in the n-well 360 is coupled to the first terminal N1 / H (first conductive structure 580). The n-well 360 is coupled to the second terminal N2 / L (second conductive structure 585) through the n-doped region 375 in the n-well 360. The n-doped region 375c spanning the deep n-well 246 and the n-well 360 is also coupled to the second terminal N2 / L. Thus, the first diode D1 and the second diode D2 of the semiconductor device 500 constitute an anti-parallel diode as shown in FIG. 3C. The AP diode 125 described with reference to FIG. 1 may be an example of an embodiment of the semiconductor device 500 or may include the embodiment.

[0056] Although various embodiments of the present description have been described, they are presented as examples and not as limitations. Several modifications to the described embodiments may be made in the present description without departing from the spirit or scope of the present description. For example, the examples described above with reference to Figures 2A-5 include various doped portions (e.g., n-wells, p-wells, deep n-wells, n-doped regions and p-doped regions) based on a p-type epilayer formed on a p-type substrate, but in some embodiments, anti-parallel diodes may be fabricated based on an n-type epilayer formed on an n-type substrate with various doped portions of opposite polarity, e.g., by swapping acceptor and donor dopant atoms. Also, in some embodiments, the various doped portions may be formed in a substrate (n-type or p-type wafer) without an epilayer formed on the substrate. Also, in the illustrated embodiments, various features or components are shown as having a particular arrangement or configuration, but other arrangements and configurations are possible. Also, aspects of the present technology described in the context of some examples may be combined or eliminated in other embodiments. Thus, the breadth and scope of the present description should not be limited by any of the above described embodiments.

Claims

1. A semiconductor device comprising: a first diode including a first pn junction across a p-doped region and a first n-well including the p-doped region, the first n-well being coupled to a first terminal and the p-doped region being coupled to a second terminal; a second diode including a second pn junction across a p-well and a second n-well adjacent to the p-well, the p-well being coupled to the first terminal and the second n-well being coupled to the second terminal; Including, The semiconductor device, wherein the second n-well overlaps a third n-well of an isolation structure surrounding the semiconductor device.

2. 10. The semiconductor device of claim 1, The semiconductor device, wherein the p-well abuts the first n-well.

3. 10. The semiconductor device of claim 1, The semiconductor device, wherein the first n-well is coupled to the first terminal through an n-doped region in the first n-well.

4. 10. The semiconductor device of claim 1, the p-well is coupled to the first terminal through the p-doped region in the p-well.

5. 10. The semiconductor device of claim 1, the second n-well is coupled to the second terminal through an n-doped region in the second n-well.

6. 10. The semiconductor device of claim 1, The semiconductor device, wherein the isolation structure includes a deep trench isolation (DTI) structure that contacts the second n-well.

7. 10. The semiconductor device of claim 1, the third n-well is coupled to an n-type buried layer over which the first and second diodes are located.

8. 10. The semiconductor device of claim 1, the p-well is coupled to a p-type epitaxial layer on which the first and second diodes are located.

9. 10. The semiconductor device of claim 1, The semiconductor device, wherein the p-well surrounds the first n-well and the second n-well surrounds the p-well.

10. 10. The semiconductor device of claim 1, the second terminal includes a conductive structure; the p-doped region extends in a first direction along a surface of the semiconductor device; A semiconductor device, wherein the conductive structure includes a portion extending in a second direction perpendicular to the first direction, the portion covering a contact to the p-doped region.

11. 10. The semiconductor device of claim 1, The semiconductor device, wherein the first and second diodes form an anti-parallel diode.

12. The semiconductor device of claim 1, a third n-well of the isolation structure spaced apart from the p-well and the first n-well.

13. The semiconductor device of claim 1, the third n-well extends under the second n-well without extending under the first n-well and the p-well.

14. The semiconductor device of claim 1, A semiconductor device wherein the p-well does not include any n-doped regions.

15. The semiconductor device of claim 1, The semiconductor device, wherein the isolation structure extends deeper than the first n-well, the second n-well, and the p-well.

16. A semiconductor device comprising: a first diode including a first pn junction across an n-doped region and a p-well including the n-doped region, the n-doped region coupled to a first terminal and the p-well coupled to a second terminal; a second diode including a second pn junction across a p-doped region and an n-well including the p-doped region, the p-doped region coupled to the first terminal and the n-well coupled to the second terminal; Including, The semiconductor device, wherein the n-well overlaps a deep n-well of an isolation structure surrounding the semiconductor device.

17. 17. The semiconductor device of claim 16, The semiconductor device, wherein the p-well abuts the n-well.

18. 17. The semiconductor device of claim 16, the n-well is coupled to the first terminal through an n-doped region in the deep n-well.

19. 17. The semiconductor device of claim 16, The semiconductor device, wherein the n-well is coupled to the first terminal through an n-doped region within the n-well.

20. 17. The semiconductor device of claim 16, The semiconductor device, wherein the p-well is coupled to the second terminal through a p-doped region within the p-well.

21. 17. The semiconductor device of claim 16, The semiconductor device, wherein the isolation structure includes a deep trench isolation (DTI) structure that contacts the n-well.

22. 17. The semiconductor device of claim 16, the deep n-well is coupled to an n-type buried layer over which the first and second diodes are located.

23. 17. The semiconductor device of claim 16, the p-well is coupled to a p-type epitaxial layer on which the first and second diodes are located.

24. 17. The semiconductor device of claim 16, The semiconductor device wherein the n-well surrounds the p-well.

25. 17. The semiconductor device of claim 16, the first terminal includes a conductive structure; the n-doped region extends in a first direction along a surface of the semiconductor device; A semiconductor device, wherein the conductive structure includes a portion extending in a second direction perpendicular to the first direction, the portion covering a contact to the n-doped region.

26. 17. The semiconductor device of claim 16, the first terminal includes a conductive structure; the n-doped region extends in a first direction along a surface of the semiconductor device; A semiconductor device, wherein the conductive structure includes a portion extending in the first direction, the portion covering a contact to the n-doped region.

27. 17. The semiconductor device of claim 16, The semiconductor device, wherein the first and second diodes form an anti-parallel diode.

28. A semiconductor device comprising: a p-well including an n-doped region, a first diode formed across the n-doped region and the p-well; an n-well surrounding the p-well, the n-well including a p-doped region surrounding the p-well, a second diode formed across the p-doped region and the n-well; Including, The semiconductor device, wherein the n-well overlaps a deep n-well of an isolation structure surrounding the semiconductor device.

29. 29. The semiconductor device of claim 28, The semiconductor device wherein the p-well is adjacent to the n-well.

30. 29. The semiconductor device of claim 28, a semiconductor device, wherein the n-doped region of the p-well is coupled to a first terminal, the p-well is coupled to a second terminal, the p-doped region of the n-well is coupled to the first terminal, and the n-well is coupled to the second terminal.

31. 2631. The semiconductor device of claim 2630, the p-well is coupled to the second terminal through a p-doped region in the p-well; The semiconductor device, wherein the n-well is coupled to the second terminal through an n-doped region in the n-well, the n-doped region surrounding the p-well.

32. 27. The semiconductor device of claim 26, the first terminal includes a conductive structure; the n-doped region extends in a first direction along a surface of the semiconductor device; A semiconductor device, wherein the conductive structure includes a portion extending in the first direction, the portion covering a contact to the n-doped region.

33. 29. The semiconductor device of claim 28, The semiconductor device, wherein the first and second diodes form an anti-parallel diode.

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