Composite silicon carbide substrate and method for preparing same

Abstract

The present application provides a composite silicon carbide substrate and a method for preparing the same. [Means] The substrate includes a single crystal silicon carbide layer and a silicon carbide support layer, a first doped silicon carbide layer is provided between the single crystal silicon carbide layer and the silicon carbide support layer, and a bonding interface layer is provided between the first doped silicon carbide layer and the single crystal silicon carbide layer. The preparation method includes step (1) depositing a first doped silicon carbide layer on the silicon carbide support layer to obtain a first composite layer, step (2) bonding the first composite layer obtained in step (1) to a single crystal silicon carbide layer that has been subjected to ion implantation or laser irradiation, applying stress, and obtaining an assembly of the composite silicon carbide substrates, and step (3) heat treating the assembly of the composite silicon carbide substrates obtained in step (2) to obtain the composite silicon carbide substrates. The composite silicon carbide substrate according to the present application can reduce or eliminate the resistance of the bonding interface, and has a simple and efficient preparation method and excellent controllability.

Description

[Technical field]

[0001] The present application relates to the technical field of semiconductor materials, for example silicon carbide substrates, in particular composite silicon carbide substrates and methods for preparing same. [Background technology]

[0002] Devices made from silicon carbide single crystals have advantages such as resistance to high temperatures, high pressures, high frequencies, high power, radiation resistance and high efficiency, and are of great value in applications in the fields of RF and new energy.

[0003] A typical manufacturing method for silicon carbide single crystal substrate includes growing silicon carbide single crystal by physical vapor transport to obtain a silicon carbide single crystal ingot, machining the outer periphery of the ingot to obtain the required diameter and surface quality, then cutting the ingot into slices, grinding and polishing the slices to the required thickness and flatness to obtain the final silicon carbide single crystal substrate. Due to the low efficiency of growing silicon carbide single crystal by physical vapor transport, the cost of a single silicon carbide single crystal substrate is high.

[0004] In order to reduce the cost of silicon carbide substrates, those skilled in the art have proposed a composite substrate structure in which a single single crystal silicon carbide thin layer is bonded to a low-cost support substrate, which forms a bonding layer between the single crystal silicon carbide thin layer and the support substrate, and the presence of the bonding layer may adversely affect the vertical conductivity of the substrate.

[0005] In order to reduce or eliminate the resistance of the bonding interface, related scholars propose that before bonding, ion implantation is performed on the two bonding surfaces to increase the doping concentration near the bonding surfaces, and then bonding is performed. This embodiment can effectively reduce the resistance of the bonding interface, but it requires multiple ion implantation steps, making the preparation process complicated.

[0006] In summary, providing a composite substrate that can reduce or eliminate the resistance at the bonding interface and has a simple and efficient preparation process has already become one of the problems that need to be urgently solved in the field. Summary of the Invention [Problem to be solved by the invention]

[0007] The following is a general summary of the subject matter described in detail in this document. This summary is not intended to limit the scope of the claims.

[0008] The present application provides a composite silicon carbide substrate and a preparation method thereof, the composite silicon carbide substrate being capable of reducing or eliminating the resistance at the bonding interface, and the preparation method thereof being simple, efficient, and excellent in controllability. [Means for solving the problem]

[0009] In aspect 1, the present application provides a method for producing a method for manufacturing a semiconductor device comprising: a single crystal silicon carbide layer and a silicon carbide support layer; a first doped silicon carbide layer is provided between the single crystal silicon carbide layer and a silicon carbide support layer; a bonding interface layer is provided between the first doped silicon carbide layer and the single crystal silicon carbide layer; The doping concentration of the first doped silicon carbide layer is 1×10 19 / cm 3 For example, 1×10 19 / cm 3 , 5×10 19 / cm 3 , 1×10 20 / cm 3 , 4×10 20 / cm 3 , 8×10 20 / cm 3 or 1×10 21 / cm 3 may be, but are not limited to, the recited numerical values; other unrecited numerical values ​​within the numerical range apply as well. A composite silicon carbide substrate is provided.

[0010] The composite silicon carbide substrate of the present application further reduces or eliminates the resistance of the bonding interface layer by increasing the doped silicon carbide layer, thereby reducing interface conduction loss and heat generation in semiconductor devices fabricated with the substrate.

[0011] The doping concentration of the first doped silicon carbide layer according to the present invention is 1×10 19 / cm 3 That is, if the doping concentration is too low, the first doped layer cannot effectively reduce or eliminate the resistance of the bonding interface layer.

[0012] The single crystal silicon carbide layer according to the present application is a high quality silicon carbide layer, and the silicon carbide support layer is a low quality silicon carbide layer, and the difference between the high quality and low quality is the defect density such as micropipes, dislocations, carbon coatings, etc. in the silicon carbide crystal, and the defect density in the high quality silicon carbide layer is smaller than that in the low quality silicon carbide layer. The silicon carbide support layer may be polycrystalline. By adopting a low quality silicon carbide layer, the total cost of the composite substrate can be reduced without significantly reducing the quality.

[0013] In a preferred technical solution of the present application, a second doped silicon carbide layer is provided on the silicon carbide support layer on a side remote from the single crystal silicon carbide layer.

[0014] A doped silicon carbide layer can be deposited on both of the two opposing surfaces of the silicon carbide support layer according to the present invention. By simultaneously depositing doped silicon carbide layers on the two opposing surfaces (front and back), the distortion of the substrate during the deposition process can be reduced, and the final composite substrate has a doped silicon carbide layer on the back surface of the silicon carbide support layer, which can further reduce the ohmic contact resistance of the back electrode fabricated thereon.

[0015] In one embodiment, a roughened interfacial layer is provided between the silicon carbide support layer and the first doped silicon carbide layer and / or the second doped silicon carbide layer.

[0016] The roughened interface layer of the present invention can absorb stress during the epitaxial growth of the composite substrate, reduce the distortion of the composite substrate during epitaxial growth, and improve the quality of the epitaxial layer.

[0017] In one embodiment, the roughened interfacial layer has a topography that includes undulations and / or waves.

[0018] In one embodiment, the roughened interface layer has a relief height of 3 to 500 nm, and may be, for example, 3 nm, 5 nm, 10 nm, 100 nm, 200 nm, 300 nm, 400 nm, or 500 nm, but is not limited to the recited values, and other unrecited values ​​within the numerical range apply as well.

[0019] In one embodiment, the thickness of the single crystal silicon carbide layer is 0.1 to 10 μm, and may be, for example, 0.1 μm, 1 μm, 2 μm, 4 μm, 6 μm, 8 μm, or 10 μm, but is not limited to the recited values, and other unrecited values ​​within the numerical range apply as well.

[0020] In one embodiment, the thickness of the bonding interface layer is 0.5 to 5 nm, and may be, for example, 0.5 nm, 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm, but is not limited to the recited values, and other unrecited values ​​within the numerical range apply as well.

[0021] In one embodiment, the thickness of the silicon carbide support layer is 200 to 1000 μm, and may be, for example, 200 μm, 400 μm, 600 μm, 800 μm, or 1000 μm, but is not limited to the recited values, and other unrecited values ​​within the numerical range apply as well.

[0022] In one embodiment, the thickness of the first doped silicon carbide layer is 5 to 50,000 nm, and may be, for example, 5 nm, 100 nm, 1000 nm, 10,000 nm, 20,000 nm, 30,000 nm, 40,000 nm or 50,000 nm, but is not limited to the recited values, and other unrecited values ​​within the numerical range apply as well.

[0023] In one embodiment, the thickness of the second doped silicon carbide layer is 5 to 50,000 nm, and may be, for example, 5 nm, 100 nm, 1000 nm, 10,000 nm, 20,000 nm, 30,000 nm, 40,000 nm or 50,000 nm, but is not limited to the recited values, and other unrecited values ​​within the numerical range apply as well.

[0024] The present application has limitations on the thickness of each layer in the composite substrate.

[0025] If the thickness of the single crystal silicon carbide layer is lower than 0.1 μm, the thickness is too small, which increases the difficulty of controlling the thickness uniformity and the cost; if the thickness of the single crystal silicon carbide layer is greater than 10 μm, the thickness is too large, which increases the usage of high-quality single crystal materials and increases the cost.

[0026] If the thickness of the bonding interface layer is less than 0.5 nm, the thickness is too small, which increases the difficulty and cost of manufacturing; if the thickness of the bonding interface layer is more than 5 nm, the thickness is too large, which increases the resistance of the bonding interface layer, which affects the performance of the semiconductor device manufactured with the substrate.

[0027] If the thickness of the silicon carbide support layer is less than 200 μm, the thickness is too small and the support layer is easily deformed and cannot perform a good supporting function. If the thickness of the silicon carbide support layer is more than 1000 μm, the thickness is too large and the amount of silicon carbide material used increases, resulting in increased costs.

[0028] When the thickness of the first / second doped silicon carbide layer is less than 5 nm, if the thickness is too small, the first doped layer cannot effectively reduce or eliminate the resistance of the bonding interface layer, and the second doped layer cannot effectively reduce the ohmic contact resistance of the back electrode; when the thickness of the first / second doped silicon carbide layer is greater than 50,000 nm, if the thickness is too large, the time required for manufacturing will increase and the cost will increase.

[0029] In one embodiment, the doping concentration of the second doped silicon carbide layer is 1×10 19 / cm 3 For example, 1×10 19 / cm 3 , 5×10 19 / cm 3 , 1×10 20 / cm 3 , 4×10 20 / cm 3 , 8×10 20 / cm 3 or 1×10 21 / cm 3 The range may be, but is not limited to, the recited numerical values, and other unrecited numerical values ​​within the numerical range apply as well.

[0030] In one embodiment, the doping elements in the first doped silicon carbide layer and the second doped silicon carbide layer include any one or a combination of at least two of B, N, P, or Al, and typical combinations include, but are not limited to, a combination of B and N, a combination of B and P, a combination of B and Al, a combination of B, N, and P, a combination of P, N, and Al, or a combination of B, N, P, and Al.

[0031] In one embodiment, the crystal type of the single crystal silicon carbide layer is any one of 4H, 6H and 3C, and is preferably 4H.

[0032] In one embodiment, the crystal type of the silicon carbide support layer is any one or a combination of at least two of 4H, 6H, or 3C, and typical combinations include, but are not limited to, a combination of 4H and 6H, a combination of 4H and 3C, a combination of 6H and 3C, or a combination of 4H, 6H, and 3C.

[0033] In one embodiment, the doping concentration of the silicon carbide support layer is 1×10 17 / cm 3 For example, 1×10 17 / cm 3 , 3×10 17 / cm 3 , 7×10 17 / cm 3 , 1×10 18 / cm 3 , 5×10 18 / cm 3 , or 9×10 18 / cm 3 The range may be, but is not limited to, the recited numerical values, and other unrecited numerical values ​​within the numerical range apply as well.

[0034] In one embodiment, the diameter of the composite silicon carbide substrate is 2 to 8 inches, and may be, for example, 2 inches, 4 inches, 6 inches, or 8 inches, but is not limited to the recited values, and other unrecited values ​​within the numerical range apply as well.

[0035] In aspect 2, the present application provides a method for producing a method for manufacturing a semiconductor device comprising the steps of: (1) depositing a first doped silicon carbide layer on the silicon carbide support layer to obtain a first composite layer; (2) bonding the first composite layer obtained in step (1) with a monocrystalline silicon carbide layer that has been subjected to ion implantation or laser irradiation, and obtaining an assembly of a composite silicon carbide substrate after applying stress; and (3) heat-treating the composite silicon carbide substrate assembly obtained in step (2) to obtain a composite silicon carbide substrate. A method for preparing the composite silicon carbide substrate according to embodiment 1 is provided.

[0036] In one embodiment, the depositing described in step (1) comprises chemical vapor deposition or liquid phase epitaxial deposition.

[0037] The chemical vapor deposition according to the present invention uses a reactive gas to react in a high-temperature reaction chamber to grow a highly doped silicon carbide layer on the surface of a low-quality silicon carbide substrate. The reactive gas includes at least a silicon source gas, a carbon source gas, and a doping gas, where the silicon source gas can be any one or a combination of at least two of silane, trichlorosilane, tetrachlorosilane, or dichlorosilane, the carbon source gas can be any one or a combination of at least two of ethylene, propane, or acetylene, and the doping gas is generally nitrogen gas.

[0038] The liquid phase epitaxial method is as follows: a silicon-containing co-solvent is placed in a graphite crucible, the co-solvent is heated and melted, and the carbon in the graphite crucible is dissolved in the co-solvent. Then, the surface of a low-quality silicon carbide substrate is brought into contact with or immersed in the co-solvent solution, and the carbon is precipitated at the solid-liquid interface of the silicon carbide substrate due to the supercooling of the surface of the silicon carbide substrate, and is combined with the silicon in the co-solvent to form a highly doped silicon carbide layer. Doping may be achieved by passing nitrogen gas through the reaction chamber, or by adding a metal element such as Al to the co-solvent.

[0039] In one embodiment, the depositing according to step (1) further comprises depositing a second doped silicon carbide layer on a side of the silicon carbide support layer remote from the first doped silicon carbide layer.

[0040] In one embodiment, the method further comprises a surface roughening treatment prior to the deposition in step (1).

[0041] In one embodiment, the roughening treatment comprises chemical etching and / or plasma etching.

[0042] The chemical etching in the present application is a wet etch.

[0043] In one embodiment, the height of the surface undulations after the roughening treatment is 3 to 500 nm, and may be, for example, 3 nm, 5 nm, 10 nm, 100 nm, 200 nm, 300 nm, 400 nm, or 500 nm, but is not limited to the recited numerical values, and other unrecited numerical values ​​within the numerical range also apply.

[0044] In one embodiment, the ions used in the ion implantation described in step (2) include hydrogen ions and / or helium ions.

[0045] In one embodiment, the depth of the ion implantation is 5 μm or less, and may be, for example, 5 μm, 4 μm, 3 μm, 2 μm, or 1 μm, but is not limited to the recited values, and other unrecited values ​​within the numerical range apply as well.

[0046] In one embodiment, the laser used for the laser irradiation described in step (2) comprises a pulsed laser.

[0047] In one embodiment, the pulsed laser comprises a solid-state laser or a fiber laser.

[0048] In one embodiment, the pulse width of the laser irradiation described in step (2) is 100 to 300 fs, and may be, for example, 100 fs, 140 fs, 180 fs, 220 fs, 260 fs, or 300 fs, but is not limited to the recited values, and other unrecited values ​​within the numerical range apply as well.

[0049] In one embodiment, the depth of the laser irradiation described in step (2) is 150 μm or less, and may be, for example, 150 μm, 140 μm, 130 μm, 120 μm, 110 μm, or 100 μm, but is not limited to the recited values, and other unrecited values ​​within the numerical range apply as well.

[0050] The purpose of the ion implantation or laser irradiation is to form a weakened layer at a certain depth within the single crystal silicon carbide layer from the ion implanted or laser irradiated surface.

[0051] In one embodiment, after bonding as described in step (2), a bonded interface layer is obtained.

[0052] In one embodiment, the method further comprises a pre-treatment step for the surfaces to be bonded prior to bonding as described in step (2).

[0053] In one embodiment, the pre-treatment process includes sequential grinding and polishing.

[0054] In one embodiment, the roughness of the polished surface to be bonded is 0.05 to 0.5 nm, for example, 0.05 nm, 0.1 nm, 0.2 nm, 0.3 nm, 0.4 nm, or 0.5 nm, but is not limited to the recited values, and other unrecited values ​​within the numerical range also apply.

[0055] In one embodiment, the stress application regime described in step (2) includes heat treatment or mechanical separation.

[0056] In one embodiment, when the method of applying stress described in step (2) is a heat treatment, the temperature of the heat treatment is 700 to 1300°C, for example, 700°C, 800°C, 900°C, 1000°C, 1100°C, 1200°C, or 1300°C, but is not limited to the recited values, and other unrecited values ​​within the numerical range also apply.

[0057] The purpose of applying stress is to split the single crystal silicon carbide layer along the weakened layer and separate the single crystal silicon carbide layer into two parts: a layer waiting to be recovered and the single crystal silicon carbide layer on the composite silicon carbide substrate.

[0058] In one embodiment, the temperature of the heat treatment described in step (3) is 1500 to 1900°C, and may be, for example, 1500°C, 1600°C, 1700°C, 1800°C, or 1900°C, but is not limited to the recited values, and other unrecited values ​​within the numerical range apply as well.

[0059] In one embodiment, the time for the heat treatment described in step (3) is 10 to 10,000 s, and may be, for example, 10 s, 100 s, 1000 s, 5000 s, or 10,000 s, but is not limited to the recited values, and other unrecited values ​​within the numerical range apply as well.

[0060] The purpose of the heat treatment described in step (3) is to repair damage to the bonding interface layer and reduce or eliminate resistance introduced into the bonding interface layer.

[0061] Prior to the heat treatment described in step (3) of the present application, a layer of carbon film or diamond-like film having a thickness of between 30 and 600 nm can be deposited on the surface of the composite substrate using known techniques in order to prevent sublimation and evaporation of the silicon on the surface.

[0062] The numerical ranges referred to in this application include not only the recited point values ​​but also any point values ​​between the recited numerical ranges that are not recited, and for the sake of space and clarity, this application does not exhaustively recite specific point values ​​included in the ranges. Effect of the Invention

[0063] Compared with the related art, the present application has the following beneficial effects:

[0064] (1) The composite silicon carbide substrate according to the present application can effectively reduce or eliminate the resistance of the bonding interface layer.

[0065] (2) In the composite silicon carbide substrate of the present application, by simultaneously depositing doped silicon carbide layers on two opposing surfaces of the silicon carbide support layer, distortion of the substrate during the deposition process can be reduced, and the second doped silicon carbide layer present on the back surface of the silicon carbide support layer in the final composite substrate can further reduce the ohmic contact resistance of a back surface electrode fabricated thereon.

[0066] (3) The roughened interface layer in the composite silicon carbide substrate according to the present invention can absorb stress during the epitaxial growth process of the composite substrate, reduce distortion of the composite substrate during epitaxial growth, and improve the quality of the epitaxial layer.

[0067] Other aspects may be understood upon reading and understanding the drawings and detailed description. [Brief description of the drawings]

[0068] The drawings are intended to provide a further understanding of the technical solution of the present application, constitute a part of the specification, and are used to interpret the technical solution of the present application together with the embodiments of the present application, and are not intended to limit the technical solution of the present application.

[0069] [Figure 1] 1 is a structural schematic diagram of a composite silicon carbide substrate according to Example 1 of the present application. [Diagram 2] FIG. 4 is a structural schematic diagram of a composite silicon carbide substrate according to Example 2 of the present application. [Diagram 3] 3 is a flow chart for preparing the composite silicon carbide substrate according to Example 1 of the present application. [Figure 4] 5 is a flow chart for preparing the composite silicon carbide substrate according to Example 2 of the present application. [Explanation of symbols]

[0070] 1...silicon carbide support layer; 2...first doped silicon carbide layer; 3...single crystal silicon carbide layer; 4...second doped silicon carbide layer; 300...weakened layer; 31...layer awaiting recovery. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0071] The technical solution of the present application will be further described below through specific embodiments. Those skilled in the art should understand that the above examples are only intended to assist in the understanding of the present application, and should not be regarded as specific limitations of the present application. EXAMPLES

[0072] The present example provides a composite silicon carbide substrate as shown in FIG. 1, which includes a single crystal silicon carbide layer 3 and a silicon carbide support layer 1 .

[0073] A first doped silicon carbide layer 2 was provided between the single crystal silicon carbide layer 3 and the silicon carbide support layer 1 .

[0074] A bonding interface layer was provided between the first doped silicon carbide layer 2 and the single crystal silicon carbide layer 3 .

[0075] The doping concentration of the first doped silicon carbide layer 2 is 1.2×10 20 / cm 3 It was.

[0076] The single crystal silicon carbide layer had a thickness of 1.5 μm, the bonding interface layer had a thickness of 2 nm, the silicon carbide support layer had a thickness of 345 μm, and the first doped silicon carbide layer had a thickness of 5 μm.

[0077] The doping element in the first doped silicon carbide layer was N, the single crystal silicon carbide layer 3 had a crystal type of 4H, and the silicon carbide support layer 1 was polycrystalline and had a crystal type of 3C.

[0078] The composite silicon carbide substrate had a diameter of 6 inches.

[0079] In the preparation method of the composite silicon carbide substrate, a flow chart of the preparation of the composite silicon carbide substrate is shown in FIG.

[0080] Step (1) A first doped silicon carbide layer 2 is deposited on the silicon carbide support layer 1 to obtain a first composite layer. Step (2) The first composite layer obtained in step (1) and the single crystal silicon carbide layer 3 that has been subjected to ion implantation are bonded to each other, and after applying stress, an assembly of the composite silicon carbide substrate is obtained. Step (3): The composite silicon carbide substrate assembly obtained in step (2) was subjected to a heat treatment at 1600° C. for 10 to 10000 s to obtain the composite silicon carbide substrate.

[0081] Here, in the ion implantation process described in step (2), a weakened layer 300 was formed in the single crystal silicon carbide layer 3. After applying stress, the single crystal silicon carbide layer was cleaved along the weakened layer 300, and the single crystal silicon carbide layer 3 was divided into two parts, a layer waiting to be collected 31 and a single crystal silicon carbide layer on a composite silicon carbide substrate, and the ion implantation depth was 1.5 μm.

[0082] The layer 31 to be recovered can be recycled and the above-mentioned composite substrate preparation method can be repeated. EXAMPLES

[0083] This embodiment provides a composite silicon carbide substrate as shown in FIG. 2. The composite silicon carbide substrate is different from Example 1 in that: In this embodiment, a second doped silicon carbide layer 4 is deposited on the back surface of the silicon carbide support layer 1, The only difference was that the second doped silicon carbide layer 4 had a thickness of 5 μm.

[0084] The method for preparing the composite silicon carbide substrate according to this embodiment is different from that of Example 1. As shown in FIG. 4, in this embodiment, the step (1) of depositing a first doped silicon carbide layer 2 on the silicon carbide support layer 1 is changed to the step (1) of simultaneously depositing a first doped silicon carbide layer 2 and a second doped silicon carbide layer 4 on the silicon carbide support layer 1; The only difference is that the second doped silicon carbide layer is provided on the side of the silicon carbide support layer 1 farther from the first doped silicon carbide layer 2 . EXAMPLES

[0085] This embodiment provides a composite silicon carbide substrate, and the composite silicon carbide substrate is distinguished from Example 1 in that: In this example, a wavy roughened interface layer was provided between the silicon carbide support layer 1 and the first doped silicon carbide layer 2, and the undulation height of the roughened interface layer was only 200 nm.

[0086] The difference between the preparation method of the composite silicon carbide substrate and Example 1 is that In this example, the only difference is that the surface of the silicon carbide support layer 1 waiting for deposition was subjected to a roughening treatment prior to the deposition described in step (1). EXAMPLES

[0087] This embodiment provides a composite silicon carbide substrate, and the composite silicon carbide substrate is distinguished from Example 2 in that: In this embodiment, a wavy roughened interface layer was provided independently between the silicon carbide support layer 1 and the first doped silicon carbide layer 2 and between the silicon carbide support layer 1 and the second doped silicon carbide layer 4, and the undulation height of the roughened interface layer was 200 nm.

[0088] The difference between the method for preparing the composite silicon carbide substrate and Example 2 is that In this example, the only difference was that the surface of the silicon carbide support layer 1 waiting for deposition was subjected to a roughening treatment prior to the deposition described in step (1).

[0089] This comparative example provides a composite silicon carbide substrate, and the composite silicon carbide substrate is distinguished from Example 1 in that: In this comparative example, the first doped silicon carbide layer 2 was omitted, and the only difference was that the silicon carbide support layer had a thickness of 350 μm.

[0090] The thickness of the single crystal silicon carbide layer and the thickness of the bonding interface layer were the same as in Example 1.

[0091] The difference between the preparation method of the composite silicon carbide substrate and Example 1 is that In this comparative example, the deposition process described in step (1) was omitted.

[0092] Performance Test: (1) The interface resistances of the composite silicon carbide substrates according to Examples 1 to 4 and Comparative Example 1 were compared. The method for measuring the interface resistance is as follows. A back electrode was formed on the surface of the polycrystalline substrate of the composite silicon carbide substrate, and a circular front electrode with a diameter of 0.3 mm was formed on the surface of the single crystal layer. A voltage V was applied between the front electrode and the back electrode, and the corresponding current I was recorded, a VI curve was obtained, and the resistance value was calculated. (2) The quality of the mold surface was detected, that is, the BOW and WARP values ​​were detected, the BOW being the degree of bending of the mold surface, and the WARP value being the amount of warping of the mold surface. The amounts of distortion during the epitaxial process of the composite substrates according to Examples 1 to 4 and Comparative Example 1 were compared, and the epitaxial thickness was 15 μm. After the epitaxial growth was completed, the mold surface of the epitaxial substrate was measured to obtain the BOW and WARP values, which were then compared with the values ​​before the epitaxial growth to obtain the absolute value of the change.

[0093] The results of the performance detection according to the present application are shown in Table 1.

[0094] [Table 1]

[0095] As can be seen from analyzing Table 1 and comparing the resistance values ​​of Examples 1-2 and Comparative Example 1, the doped silicon carbide layer in the composite silicon carbide substrate of the present application can effectively reduce the interface resistance of the bonding interface in the composite substrate and can also reduce the ohmic contact resistance of the back electrode of the composite substrate.

[0096] As can be seen from the comparison of the absolute values ​​of the BOW and WARP changes between Example 1 and Example 3, and Example 2 and Example 4, the roughened interface layer can effectively reduce the distortion of the composite substrate during the epitaxial process.

[0097] In summary, the composite silicon carbide substrate of the present application can reduce or eliminate the interface resistance at the bonding interface in the composite substrate, reduce the ohmic contact resistance of the back electrode of the composite substrate, and reduce distortion of the composite substrate during the epitaxial process, and the preparation method is simple and efficient, with excellent controllability.

[0098] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. The applicant declares that all modifications or replacements that a person skilled in the art can easily conceive within the technical scope set forth in the present application, as understood by those skilled in the art, are included in the scope of protection and disclosure of the present application.

Claims

1. a single crystal silicon carbide layer and a silicon carbide support layer; a first doped silicon carbide layer is provided between the single crystal silicon carbide layer and a silicon carbide support layer; a bonding interface layer is provided between the first doped silicon carbide layer and the single crystal silicon carbide layer; The doping concentration of the first doped silicon carbide layer is 1×10 １９ / cm ２ That's all. Composite silicon carbide substrate.

2. a second doped silicon carbide layer is provided on the silicon carbide support layer on a side remote from the single crystal silicon carbide layer; a roughened interface layer is provided between the silicon carbide support layer and the first doped silicon carbide layer and / or the second doped silicon carbide layer; the roughened interface layer has an undulating and / or corrugated topography; The roughened interface layer has a undulation height of 3 to 500 nm; The composite silicon carbide substrate of claim 1 .

3. The single crystal silicon carbide layer has a thickness of 0.1 to 10 μm, the thickness of the bonding interface layer is 0.5 to 5 nm; The silicon carbide support layer has a thickness of 200 to 1000 μm; the first doped silicon carbide layer has a thickness of 5 to 50,000 nm; The second doped silicon carbide layer has a thickness of 5 to 50,000 nm; The composite silicon carbide substrate according to claim 2 .

4. The doping elements of the first doped silicon carbide layer and the second doped silicon carbide layer include any one or a combination of at least two of B, N, P, or Al; the single crystal silicon carbide layer has a crystal type of any one of 4H, 6H, and 3C; The silicon carbide support layer has a crystal type of any one or a combination of at least two of 4H, 6H, or 3C, The doping concentration of the silicon carbide support layer is 1×10 １７ / cm ２ That's all. The composite silicon carbide substrate has a diameter of 2 to 8 inches. The composite silicon carbide substrate according to claim 3 .

5. (1) depositing a first doped silicon carbide layer on the silicon carbide support layer to obtain a first composite layer; Step (2) of bonding the first composite layer obtained in step (1) with a monocrystalline silicon carbide layer that has been subjected to ion implantation or laser irradiation to obtain a composite silicon carbide substrate assembly after applying stress; and (3) heat treating the composite silicon carbide substrate assembly obtained in step (2) to obtain the composite silicon carbide substrate. A method for preparing the composite silicon carbide substrate according to any one of claims 1 to 4.

6. The depositing according to step (1) comprises chemical vapor deposition or liquid phase epitaxy; The depositing according to step (1) further comprises depositing a second doped silicon carbide layer on a side of the silicon carbide support layer remote from the first doped silicon carbide layer. The preparation method according to claim 5.

7. Further comprising a surface roughening treatment prior to the deposition in step (1), The surface roughening treatment includes chemical etching and / or plasma etching; The height of the surface undulations after the roughening treatment is 3 to 500 nm. The preparation method according to claim 5.

8. The ions used in the ion implantation described in step (2) include hydrogen ions and / or helium ions; The depth of the ion implantation is 5 μm or less; The laser used in the laser irradiation described in step (2) includes a pulsed laser, The pulsed laser includes a solid-state laser or a fiber laser; The pulse width of the laser irradiation described in step (2) is 100 to 300 fs; The depth of the laser irradiation described in step (2) is 150 μm or less; The preparation method according to claim 5.

9. Obtaining a bonding interface layer after bonding according to step (2), Prior to the bonding in step (2), a pretreatment process for the surface to be bonded is further included; The pretreatment process includes grinding and polishing performed in sequence, The roughness of the polished surface to be bonded is 0.05 to 0.5 nm; The preparation method according to claim 5.

10. The stress application method described in step (2) includes heat treatment or mechanical separation; When the stress application method described in step (2) is a heat treatment, the temperature of the heat treatment is 700 to 1300° C.; The temperature of the heat treatment described in step (3) is 1500 to 1900° C.; The time of the heat treatment described in step (3) is 10 to 10,000 s; The preparation method according to claim 5.

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