High-precision heterogeneous integration

Abstract

A method for performing high-precision heterogeneous integration, comprising: etching a first and a second bonding surface to create nanostructures on the first and / or second bonding surface; the first and second bonding surfaces are bonded together, and an exclusion zone resulting from particles resting on the bonding interface is at least two times smaller than the bonding of the two bonding surfaces without nanostructures.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 299,631, entitled "High Precision Heterogenous Integration," filed January 14, 2022, which is incorporated by reference in its entirety.

[0002] This application further claims priority to U.S. Provisional Patent Application No. 63 / 357,810, entitled "High Precision Heterogenous Integration," filed July 1, 2022, which is incorporated by reference herein in its entirety.

[0003] The present invention relates generally to heterogeneous integration, and more particularly to high precision heterogeneous integration. [Background technology]

[0004] The semiconductor industry is facing a new era where device scaling and cost reduction are no longer following the path they have followed over the past few decades. Packing more transistors onto a monolithic integrated circuit (IC) is becoming more difficult and expensive at each node. Semiconductor companies are now looking for technological outlets to bridge this gap and improve price performance while at the same time adding more functionality through integration. Integrating all functionality onto a single chip (known as a system-on-chip (SoC)) presents many challenges, including higher costs and design complexity. An attractive alternative is heterogeneous integration, which integrates devices that can be designed and manufactured separately in an optimized manner with the most suitable process technology using advanced packaging techniques.

[0005] Heterogeneous integration refers to the combination of separately manufactured components into a higher level assembly (system-in-package (SiP)) that as a whole results in increased functionality and improved operating characteristics.

[0006] The components being combined can be of different system levels (e.g. pre-assembled packages or subsystems), different functions (e.g. special purpose processors, DRAM, flash memory, surface mounted devices (SMD), resistors / capacitors / inductors, filters, connectors, MEMS devices, sensors) and different technologies (e.g. one is optimized for die size while the other is optimized for low power). The whole idea behind heterogeneous integration is to integrate multiple dies into the same package. This allows the package to perform certain advanced functions in a small form factor.

[0007] By using heterogeneous integration to combine chips with different process nodes and technologies, such techniques enable the continued increase in functional density and decrease in cost per function necessary to maintain advances in electronics cost and performance. Heterogeneous integration is essential to maintain the rate of progress in improved performance, decreased latency, smaller size, lighter weight, reduced power requirements per function, and reduced cost.

[0008] Unfortunately, the integration of separately manufactured components into a higher level assembly (system-in-package (SiP)) is not possible with sufficient precision. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] U.S. Patent No. 6,916,584 [Patent Document 2] U.S. Patent No. 6,919,152 [Patent Document 3] U.S. Patent No. 6,921,615 [Patent Document 4] U.S. Patent No. 8,394,282 [Patent Document 5] U.S. Patent Application No. 15 / 457283 [Patent Document 6] U.S. Pat. No. 9,415,418 [Patent Document 7] U.S. Patent No. 9,718,096 [Patent Document 8] U.S. Patent Application No. 17 / 413523 [Patent Document 9] International Application No. PCT / US2021 / 024250 [Patent Document 10] European Patent Application No. 17767252.4 [Patent Document 11] U.S. Patent Application No. 16 / 322882 [Patent Document 12] International Application No. PCT / US2021 / 019732 [Patent Document 13] European Patent Application No. 14767171.3 [Patent Document 14] U.S. Patent Application No. 63 / 336901 [Patent Document 15] U.S. Patent Application No. 63 / 314725 [Non-patent literature]

[0010] [Non-Patent Document 1] Ajay et al., “Methods for Nano-Precise Overlay in Advanced in Pick-and-Place Assembly,” Dissertation, August 2019 Summary of the Invention [Means for solving the problem]

[0011] In one embodiment of the present disclosure, a method for increasing a yield of a bonding process includes performing an etch on one or more of a first bonding surface and a second bonding surface to create nanostructures in one or more of the first bonding surface and the second bonding surface, the method further includes bonding the first bonding surface with the second bonding surface, where an exclusion zone resulting from particles resting on the bonding interface is at least two times smaller than bonding of the two bonding surfaces without the nanostructures.

[0012] In another embodiment of the present disclosure, a method for reducing the impact of particles on a yield of a bonding process includes performing an etch on one or more of a first bonding surface and a second bonding surface to create an island structure, the method further includes bonding the first bonding surface with a second bonding surface, where an exclusion zone resulting from particles resting at the bonding interface is at least two times smaller than bonding of the two bonding surfaces without the nanostructures.

[0013] In a further embodiment of the present disclosure, a method for fabricating a semiconductor device comprising two or more known good dies includes bonding two or more adjacent known good dies to a product substrate with their metal pads facing away from the product substrate, the two or more known good dies having substantially the same average thickness, and after the bonding step, performing gap filling, planarization, and / or metallization between the dies to fabricate the semiconductor device.

[0014] In another embodiment of the present disclosure, a method for making a substrate having two or more known good die mounted thereon includes bonding the two or more known good die to a substrate using direct bonding, fusion bonding, or hybrid bonding, wherein an average thickness of the two or more known good die is substantially the same, and the substrate comprises nanostructures etched at the bonding interface.

[0015] In a further embodiment of the present disclosure, a method for producing a substrate populated with two or more known good die includes bonding the two or more known good die to a substrate using an adhesive, a UV-curable adhesive, a photoswitchable adhesive, or a nanoimprint resist, wherein an average thickness of the two or more known good die is substantially the same.

[0016] The above has outlined rather broadly the features and technical advantages of one or more embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described below which may form the subject of the claims of the invention.

[0017] A further understanding of the invention can be obtained from the following detailed description when considered in conjunction with the accompanying drawings. [Brief description of the drawings]

[0018] [Figure 1] FIG. 1 illustrates an exemplary system for pick-and-place assembly, according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 illustrates an exemplary die stack on a carrier substrate according to an embodiment of the present disclosure. [Diagram 3] FIG. 2 illustrates an exemplary die stack on a tape frame according to an embodiment of the present disclosure. [Figure 4] FIG. 2 illustrates an exemplary die stack on a transfer substrate according to an embodiment of the present disclosure. [Diagram 5] FIG. 2 illustrates preparation of a transfer wafer according to an embodiment of the present disclosure. [Figure 6] FIG. 2 illustrates an exemplary die peel chuck, according to an embodiment of the present disclosure. [Figure 7] FIG. 1 illustrates an exemplary die thickness measurement method, according to an embodiment of the present disclosure. [Figure 8] FIG. 1 illustrates an alternative exemplary die thickness measurement method, according to an embodiment of the present disclosure. [Figure 9A]FIG. 2 illustrates a die encapsulation layer with etched pin structures according to an embodiment of the present disclosure. [Figure 9B] FIG. 2 illustrates optional inkjetted gel-cured polymer-based pins on the encapsulation layer of a die according to an embodiment of the present disclosure. [Figure 9C] FIG. 2 illustrates optional compliant pins on an encapsulation layer of a die according to an embodiment of the present disclosure. [Figure 10A] FIG. 9B is a top view of the structure of FIG. 9A according to an embodiment of the present disclosure. [Figure 10B] FIG. 9C is a top view of the structure of FIG. 9B according to an embodiment of the present disclosure. [Figure 11] FIG. 1 illustrates an exemplary gantry-based adaptive multi-chip transfer system (AMS), in accordance with an embodiment of the present disclosure. [Figure 12A] FIG. 2 illustrates a cross section of a gantry xy stage according to an embodiment of the present disclosure. [Figure 12B] FIG. 2 illustrates an alternative cross section of a gantry xy stage according to an embodiment of the present disclosure. [Figure 13A] FIG. 2 illustrates a die before dicing, according to an embodiment of the present disclosure. [Figure 13B] FIG. 2 illustrates a die after dicing, according to an embodiment of the present disclosure. [Figure 14A] FIG. 14 illustrates the x / y distance between the lower primary alignment marks shown in FIGS. 13A and 13B according to an embodiment of the present disclosure. [Figure 14B] FIG. 13 illustrates an embodiment of the present disclosure in which the positions of the upper and lower perimeter marks with respect to the circuit elements and primary alignment marks are known by design. [Figure 15A] FIG. 1 illustrates an exemplary massively parallel diactuation method, in accordance with an embodiment of the present disclosure. [Figure 15B] FIG. 1 illustrates an alternative exemplary massively parallel diactuation method, in accordance with an embodiment of the present disclosure. [Figure 16A]FIG. 1 illustrates a direct die-to-wafer (D2W) bonding approach according to an embodiment of the present disclosure. [Figure 16B] FIG. 1 illustrates a direct die-to-wafer (D2W) bonding approach according to an embodiment of the present disclosure. [Figure 16C] FIG. 1 illustrates a direct die-to-wafer (D2W) bonding approach according to an embodiment of the present disclosure. [Figure 17A] FIG. 1 illustrates an apparatus for die thinning according to an embodiment of the present disclosure. [Figure 17B] 17B illustrates a die thinning technique using the apparatus of FIG. 17A according to an embodiment of the present disclosure. [Figure 17C] FIG. 17B illustrates an alternative die thinning approach using the apparatus of FIG. 17A according to an embodiment of the present disclosure. [Figure 18A] FIG. 1 illustrates an apparatus for particle removal according to an embodiment of the present disclosure. [Figure 18B] 18B illustrates an exemplary particle removal technique using the apparatus of FIG. 18A, according to an embodiment of the present disclosure. [Figure 19] 1 is a flowchart of a method for performing direct bonding according to an embodiment of the present disclosure. [Figure 20A] 20 is a cross-sectional view for performing direct bonding using the steps described in FIG. 19 according to an embodiment of the present disclosure. [Figure 20B] 20 is a cross-sectional view for performing direct bonding using the steps described in FIG. 19 according to an embodiment of the present disclosure. [Figure 20C] 20 is a cross-sectional view for performing direct bonding using the steps described in FIG. 19 according to an embodiment of the present disclosure. [Figure 20D] 20 is a cross-sectional view for performing direct bonding using the steps described in FIG. 19 according to an embodiment of the present disclosure. [Figure 20E]20 is a cross-sectional view for performing direct bonding using the steps described in FIG. 19 according to an embodiment of the present disclosure. [Figure 20F] 20 is a cross-sectional view for performing direct bonding using the steps described in FIG. 19 according to an embodiment of the present disclosure. [Figure 21] 13 is a flowchart of an alternative method for performing direct bonding, according to an embodiment of the present disclosure. [Figure 22A] 22 is a cross-sectional view for performing direct bonding using the steps described in FIG. 21 according to an embodiment of the present disclosure. [Figure 22B] 22 is a cross-sectional view for performing direct bonding using the steps described in FIG. 21 according to an embodiment of the present disclosure. [Figure 22C] 22 is a cross-sectional view for performing direct bonding using the steps described in FIG. 21 according to an embodiment of the present disclosure. [Figure 22D] 22 is a cross-sectional view for performing direct bonding using the steps described in FIG. 21 according to an embodiment of the present disclosure. [Figure 22E] 22 is a cross-sectional view for performing direct bonding using the steps described in FIG. 21 according to an embodiment of the present disclosure. [Figure 22F] 22 is a cross-sectional view for performing direct bonding using the steps described in FIG. 21 according to an embodiment of the present disclosure. [Figure 23] 13 is a flowchart of a further method for performing direct bonding, according to an embodiment of the present disclosure. [Figure 24A] 24 is a cross-sectional view for performing direct bonding using the steps described in FIG. 23 according to an embodiment of the present disclosure. [Figure 24B] 24 is a cross-sectional view for performing direct bonding using the steps described in FIG. 23 according to an embodiment of the present disclosure. [Figure 24C] 24 is a cross-sectional view for performing direct bonding using the steps described in FIG. 23 according to an embodiment of the present disclosure. [Figure 24D] 24 is a cross-sectional view for performing direct bonding using the steps described in FIG. 23 according to an embodiment of the present disclosure. [Figure 24E] 24 is a cross-sectional view for performing direct bonding using the steps described in FIG. 23 according to an embodiment of the present disclosure. [Figure 24F] 24 is a cross-sectional view for performing direct bonding using the steps described in FIG. 23 according to an embodiment of the present disclosure. [Figure 24G] 24 is a cross-sectional view for performing direct bonding using the steps described in FIG. 23 according to an embodiment of the present disclosure. [Diagram 25] FIG. 2 illustrates a die coolant according to an embodiment of the present disclosure. [Figure 26] FIG. 26 is a cross-sectional view of the die and heat spreader layer of FIG. 25 in accordance with an embodiment of the present disclosure. [Figure 27] FIG. 13 illustrates an alternative die coolant according to an embodiment of the present disclosure. [Figure 28] 1 is a flowchart of a method for integrating a thinned die with a heat spreader according to an embodiment of the present disclosure. [Figure 29A] FIG. 29 is a cross-sectional view for integrating a thinned die with a heat spreader using the steps described in FIG. 28 according to an embodiment of the present disclosure. [Figure 29B] FIG. 29 is a cross-sectional view for integrating a thinned die with a heat spreader using the steps described in FIG. 28 according to an embodiment of the present disclosure. [Figure 29C] FIG. 29 is a cross-sectional view for integrating a thinned die with a heat spreader using the steps described in FIG. 28 according to an embodiment of the present disclosure. [Diagram 30] FIG. 2 illustrates an exemplary assembly of a SiP using a hierarchical feedstock chip, according to an embodiment of the present disclosure. [Diagram 31]1 is a flowchart of a method for fabricating a SiP according to an embodiment of the present disclosure. [Figure 32A] 32 is a cross-sectional view for fabricating a SiP using the steps described in FIG. 31 according to an embodiment of the present disclosure. [Figure 32B] 32 is a cross-sectional view for fabricating a SiP using the steps described in FIG. 31 according to an embodiment of the present disclosure. [Figure 32C] 32 is a cross-sectional view for fabricating a SiP using the steps described in FIG. 31 according to an embodiment of the present disclosure. [Fig. 32D] 32 is a cross-sectional view for fabricating a SiP using the steps described in FIG. 31 according to an embodiment of the present disclosure. [Figure 32E] 32 is a cross-sectional view for fabricating a SiP using the steps described in FIG. 31 according to an embodiment of the present disclosure. [Fig. 32F] 32 is a cross-sectional view for fabricating a SiP using the steps described in FIG. 31 according to an embodiment of the present disclosure. [Diagram 33] 1 is an alternative method for fabricating a SiP according to an embodiment of the present disclosure. [Figure 34A] 34 is a cross-sectional view for fabricating a SiP using the steps described in FIG. 33 according to an embodiment of the present disclosure. [Figure 34B] 34 is a cross-sectional view for fabricating a SiP using the steps described in FIG. 33 according to an embodiment of the present disclosure. [Figure 34C] 34 is a cross-sectional view for fabricating a SiP using the steps described in FIG. 33 according to an embodiment of the present disclosure. [Fig. 34D] 34 is a cross-sectional view for fabricating a SiP using the steps described in FIG. 33 according to an embodiment of the present disclosure. [Diagram 35] 1 is a flowchart of a method for performing heterogeneous integration according to an embodiment of the present disclosure. [Figure 36A]FIG. 36 is a cross-sectional view for performing heterogeneous integration using the steps described in FIG. 35 according to an embodiment of the present disclosure. [Figure 36B] FIG. 36 is a cross-sectional view for performing heterogeneous integration using the steps described in FIG. 35 according to an embodiment of the present disclosure. [Figure 36C] FIG. 36 is a cross-sectional view for performing heterogeneous integration using the steps described in FIG. 35 according to an embodiment of the present disclosure. [Figure 36D] FIG. 36 is a cross-sectional view for performing heterogeneous integration using the steps described in FIG. 35 according to an embodiment of the present disclosure. [Figure 37] FIG. 2 illustrates details regarding a heterogeneous integration process, according to certain embodiments of the present disclosure. [Figure 38A] 1A-1D illustrate a wafer-to-wafer bonding method according to an embodiment of the present disclosure. [Figure 38B] 1A-1D illustrate a wafer-to-wafer bonding method according to an embodiment of the present disclosure. [Figure 39A] FIG. 1 illustrates an alternative wafer-to-wafer bonding method according to an embodiment of the present disclosure. [Figure 39B] FIG. 1 illustrates an alternative wafer-to-wafer bonding method according to an embodiment of the present disclosure. [Figure 40A] FIG. 2 illustrates a nano / micro patterned support wafer according to an embodiment of the present disclosure. [Figure 40B] FIG. 2 illustrates a nano / micro patterned support wafer according to an embodiment of the present disclosure. [Figure 40C] FIG. 2 illustrates a nano / micro patterned support wafer according to an embodiment of the present disclosure. [Diagram 41]1 is a flowchart of a method for preparing a reconstructed wafer for face-to-back (F2B) bonding, according to an embodiment of the present disclosure. [Figure 42A] FIG. 42 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 41 according to an embodiment of the present disclosure. [Figure 42B] FIG. 42 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 41 according to an embodiment of the present disclosure. [Figure 42C] FIG. 42 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 41 according to an embodiment of the present disclosure. [Fig.42D] FIG. 42 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 41 according to an embodiment of the present disclosure. [Figure 42E] FIG. 42 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 41 according to an embodiment of the present disclosure. [Fig.42F] FIG. 42 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 41 according to an embodiment of the present disclosure. [Fig.42G] FIG. 42 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 41 according to an embodiment of the present disclosure. [Fig. 42H]FIG. 42 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 41 according to an embodiment of the present disclosure. [Fig.42I] FIG. 42 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 41 according to an embodiment of the present disclosure. [Fig.42J] FIG. 42 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 41 according to an embodiment of the present disclosure. [Figure 42K] FIG. 42 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 41 according to an embodiment of the present disclosure. [Figure 42L] FIG. 42 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 41 according to an embodiment of the present disclosure. [Figure 42M] FIG. 42 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 41 according to an embodiment of the present disclosure. [Figure 42N] FIG. 42 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 41 according to an embodiment of the present disclosure. [Diagram 43] 1 is a flowchart of an alternative method for preparing a reconstructed wafer for face-to-back (F2B) bonding, according to an embodiment of the present disclosure. [Figure 44A]FIG. 44 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 43 according to an embodiment of the present disclosure. [Figure 44B] FIG. 44 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 43 according to an embodiment of the present disclosure. [Figure 44C] FIG. 44 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 43 according to an embodiment of the present disclosure. [Fig.44D] FIG. 44 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 43 according to an embodiment of the present disclosure. [Figure 44E] FIG. 44 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 43 according to an embodiment of the present disclosure. [Fig.44F] FIG. 44 is a cross-sectional view for preparing a reconstructed wafer for face-to-back (F2B) bonding using the steps described in FIG. 43 according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] As mentioned in the background section, the semiconductor industry is facing a new era where device scaling and cost reduction are no longer following the path they have followed over the past few decades. Packing more transistors into a monolithic integrated circuit (IC) is becoming more difficult and expensive at each node. Semiconductor companies are now looking for technological outlets to bridge this gap and improve cost performance while at the same time adding more functionality through integration. Integrating all functionality onto a single chip (known as a system-on-chip (SoC)) presents many challenges, including higher costs and design complexity. An attractive alternative is heterogeneous integration, which integrates devices that can be designed and manufactured separately in an optimized manner with the most suitable process technology using advanced packaging techniques.

[0020] Heterogeneous integration refers to the combination of separately manufactured components into a higher level assembly (system-in-package (SiP)) that as a whole results in increased functionality and improved operating characteristics.

[0021] The components being combined can be of different system levels (e.g. pre-assembled packages or subsystems), different functions (e.g. special purpose processors, DRAM, flash memory, surface mounted devices (SMD), resistors / capacitors / inductors, filters, connectors, MEMS devices, sensors) and different technologies (e.g. one is optimized for die size while the other is optimized for low power). The whole idea behind heterogeneous integration is to integrate multiple dies into the same package. This allows the package to perform certain advanced functions in a small form factor.

[0022] By using heterogeneous integration to combine chips with different process nodes and technologies, such techniques enable the continued increase in functional density and decrease in cost per function necessary to maintain advances in electronics cost and performance. Heterogeneous integration is essential to maintain the rate of progress in improved performance, decreased latency, smaller size, lighter weight, reduced power requirements per function, and reduced cost.

[0023] Unfortunately, the integration of separately manufactured components into a higher level assembly (system-in-package (SiP)) is not possible with sufficient precision.

[0024] The principles of the present invention, as discussed further below, provide a means for improving the precision in integrating separately manufactured components into a higher level assembly (system-in-package (SiP)).

[0025] Before discussing the figures, the following provides definitions of various terms used herein.

[0026] As used herein, SiP refers to system in package. A SiP is formed of separately manufactured dies that are physically and / or mechanically integrated to create a system that is larger than the individual dies. It is used interchangeably with the terms multi-chip module (MCM), 2.5D IC, and 3D IC.

[0027] As used herein, a field refers to an individual die or a subset of dies that are collocated in a SiP.

[0028] As used herein, SPP refers to x and SPP y This refers to the SiP pitch (SPP) on the product substrate, including the

[0029] As used herein, an adaptive multi-chip transfer system (AMS) refers to a system used to transfer the fields and / or dies from one substrate to another while maintaining thermo-mechanical stability.

[0030] As used herein, a variable pitch mechanism (VPM) is used to change the pitch of a die before it is placed on a transfer / product / intermediate substrate.

[0031] As used herein, a chucking module (CM) is used to securely hold (within predetermined maximum and minimum lateral dimensions) a die having non-arbitrary and / or arbitrary lateral dimensions in a thermo-mechanically stable manner. A CM and its auxiliary systems (such as a CM receptacle) as well as one or more dies held by the CM are referred to interchangeably as a CM system and a CM assembly.

[0032] As used herein, the term alignment is used interchangeably with superposition and placement.

[0033] As used herein, metrology microscope assembly refers to a subsystem for measuring the alignment of a die relative to a fiducial. It can consist of metrology optics, imaging elements, and electronics.

[0034] As used herein, actuation units include X-axis, Y-axis, Z-axis, θ X axis, θ Y axis, and θ Z They are used to move one or more dies along one or more of the axes. They may also be used to produce deformations in one or more dies. Herein, actuation units are also referred to as short-stroke actuators and short-stroke stages.

[0035] As used herein, the term wafer is used interchangeably with the term substrate.

[0036] As used herein, a photoswitchable adhesive (LSA) is a type of adhesive material that can reversibly switch its phase and / or adhesive strength when exposed to light of a particular wavelength.

[0037] The terms dice and dies are used interchangeably herein.

[0038] The abbreviation "PL" stands for photolithography.

[0039] The abbreviation "NIL" stands for nanoimprint lithography, which also includes Jet and Flash Imprint Lithography (J-FIL).

[0040] As used herein, an adhesive is a material that can be used to bond (temporarily or permanently) two surfaces together. The adhesive can be comprised of one or more of the following materials: die gap-fill material, curable dielectric material (e.g., UV-curable dielectric material), silicon low-k dielectric (SiLK), hydrogen silsesquioxane (HSQ), spin-on-glass material, spin-on dielectric, flowable oxide, and photoswitchable adhesive (LSA).

[0041] As used herein, bonding is a process for temporary or permanent attachment of one die / substrate to another. Bonding can be bump bonding, micro-bump bonding, eutectic bonding, thermo-compression bonding, hybrid bonding, anodic bonding, fusion bonding, solder bump bonding, wire bonding, etc. In one embodiment, during bonding, in-situ metrology is performed using one or more of the following methods: moire metrology, or optionally an imaging-based system (monitoring the absolute position of the die, optionally with an interferometric stage, and a sensor to monitor any global movement of the two bonding objects relative to each other). Also, during bonding, the dies being bonded may be bent in a concave or convex shape (to facilitate optional adhesive curing and evacuating volatiles).

[0042] In one embodiment, the general purpose direct bonding process (hybrid / fusion bonding) utilizes water during the bonding process. In one embodiment, water is applied to the bonding surfaces using spin coating, ink jetting, slot die coating, etc. In one embodiment, only enough water is applied to create a thin film (50 nm, 100 nm, 200 nm, etc.). Excess water may be directed to micro / nano recesses near the bonding surfaces. In one embodiment, in-liquid alignment is performed as the two bonding surfaces are pressed together in a manner similar to NIL. In one embodiment, the in-liquid alignment occurs within a few hundred milliseconds. If an adhesive is used at the bonding interface, the adhesive is applied only to the metal-free areas (optionally recessed areas). In one embodiment, the rheology of the adhesive is optimized to increase or decrease the amount of time available for in-liquid alignment (see, for example, U.S. Patent Nos. 5,993, 6,133, 5,141, 5,199, 6,182, 6,199, 7,133, 7,199, 8,199, 9,103, 9,104, 9,105, 9,106, 9,107, 9,108, 9,109, 9,111, 9,112, 9,113, 9,114, 9,115, 9,116, 9,117, 9,118, 9,119 ... For UV curable adhesives, an optical wave guide may be used at the interface between the two surfaces being joined (optionally through a recess) to cure the adhesive.

[0043] Reference is now made to FIG. 1, which illustrates an exemplary system 100 for pick-and-place assembly, according to one embodiment of the present disclosure.

[0044] As shown in FIG. 1, such a system 100 includes a transfer substrate chuck 101 and a source substrate chuck 102 on an XY motion stage 103. As further shown in FIG. 1, the transfer substrate chuck 101 holds a transfer substrate 104, and the source substrate chuck 102 holds a source substrate 105. As further shown in FIG. 1, various dies 106, such as die 106A ("die A"), die 106B ("die B"), and die 106C ("die C"), are lifted from a source substrate, such as the source substrate 105, and placed on the transfer substrate 104. The dies 106A-106C may be referred to collectively or individually as dies 106 or die 106, respectively. It should be noted that any number of dies 106 may be lifted from the source substrate 105 and placed on the transfer substrate 104, and the numbers shown in FIG. 1 are used for illustrative purposes.

[0045] As further shown in FIG. 1, the system includes a transfer substrate chuck 101 and an optional inkjet 107 for applying an adhesive 108 .

[0046] Additionally, as shown in FIG. 1, the system 100 includes an optional alignment microscope 109 and an adaptive multi-chip transfer system (AMS) 110 for lifting one or more dies 106 from the source substrate 105 and placing them on the transfer substrate 104.

[0047] Additionally, as shown in FIG. 1, an AMS frame 111 and a stable metrology frame 112 are mounted on the xy motion stage 103 .

[0048] Additionally, as shown in FIG. 1, die release adhesive 113 is used to release die 106 from source substrate 105, such as die 106A.

[0049] FIG. 1 further illustrates bad die 114 that did not meet the electrical requirements of the test program.

[0050] Further explanation of FIG. 1 is provided below.

[0051] In one embodiment, an transfer chuck (AMS) 110 is used to lift one or more dies 106 from a source substrate 105 and place them on a product substrate. In one embodiment, the AMS 110 is used to permanently bond the lifted dies 106 to the product substrate. The bonding can be one or more of the following types: bump bonding, micro-bump bonding, eutectic bonding, thermo-compression bonding, hybrid bonding, anodic bonding, fusion bonding, solder bump bonding, and wire bonding. In one embodiment, the system 100 for pick and place assembly includes one or more heaters, a high pressure fabrication subsystem, a solder application subsystem, a solder reflow subsystem, a plasma cleaning subsystem, or a plasma activation subsystem.

[0052] In one embodiment, a high throughput pick-and-place system (e.g., a chip shooter) is utilized to pick and place the die 106 from the source substrate 105 onto the transfer substrate 104. In one embodiment, the throughput of the chip shooter is optimized to match the throughput of other consecutive components in the pick-and-place assembly line (e.g., adhesive application stations, precision alignment modules, etc.).

[0053] Reference is now made to FIG. 2, which illustrates an exemplary die stack on a carrier substrate according to certain embodiments of the present disclosure.

[0054] As shown in FIG. 2, the die stacks 201A-201B are disposed on a carrier substrate 202. As further shown in FIG. 2, the die stacks 201A-201B include a die thickening layer n-1 203A (e.g., silicon oxide), a die thickening layer n-2 203B, ..., and a die thickening layer 1 203N. The die stacks 201A-201B may be referred to collectively or individually as die stacks 201 or a die stack 201, respectively. Furthermore, the die thickening layers 203A-203N may be referred to collectively or individually as die thickening layers 203 or a die thickening layer 203, respectively. Although FIG. 2 shows two die stacks 201, any number of die stacks 201 may be disposed on the carrier substrate 202. Additionally, each die stack 201 may include any number of die thickening layers 203 .

[0055] In addition, a gel curing adhesive 204 is applied near the ends of the die thickening layer 203, as shown in Figure 2. Further, a full curing adhesive 205 is applied away from the ends of the die thickening layer 203, such as the die thickening layer 203N, as shown in Figure 2.

[0056] Additionally, FIG. 2 shows the die 106 with the active side facing down and an adhesive 206 (eg, a photoswitchable adhesive) between the carrier substrate 202 and the die 106 .

[0057] Referring now to FIG. 3 in conjunction with FIG. 2, FIG. 3 illustrates an exemplary die stack on a tape frame according to one embodiment of the present disclosure.

[0058] As shown in Fig. 3, the die stack 201 is placed on a tape frame 301, where a gel curing adhesive 204 is applied away from the die thickening layer 2 203B towards the tape film on the tape frame 301. Further, as shown in Fig. 3, an adhesive 206 (e.g., a photoswitchable adhesive) is placed between the die thickening layer 1 (203N) and the die thickening layer 2 (203B).

[0059] Referring now to FIG. 4 in conjunction with FIGS. 2-3, FIG. 4 illustrates an exemplary die stack on a transfer substrate according to certain embodiments of the present disclosure.

[0060] As shown in FIG. 4, the die stack 201 is placed on a transfer substrate 104 (e.g., glass, sapphire, and / or fused silica) using an optional spin-coated adhesion layer 401 between the transfer substrate 104 and the die thickening layer 203 of the transparent die stack 201 (labeled as element 402).

[0061] Reference is now made to FIG. 5, which illustrates preparation of a transferred wafer according to one embodiment of the present disclosure.

[0062] 5, height adjustment zones (or recesses) 501 are created in the transfer wafer 104. In one embodiment, such zones 501 are created using patterning techniques such as photolithography, nanoimprint lithography, direct laser lithography, or electron beam lithography, followed by wet etching.

[0063] In one embodiment, optionally, adhesive coating 502 may be inkjetted to compensate for die thickness variations due to total thickness variation (TTV).

[0064] Additionally, as shown in FIG. 5, in one embodiment, a “chipshooter” glue 503 may be spin-coated onto the surface of the transfer substrate 104 to implement chipshooters (a placement technique for low-precision simple package components such as resistors and capacitors in electronic packaging).

[0065] Reference is now made to FIG. 6, which illustrates an exemplary die peel chuck, according to an embodiment of the present disclosure.

[0066] As shown in Figure 6, the die stack 201 is placed on a locally deformed carrier substrate 601 (locally deformed carrier substrate 202) where peeling (marking the limit or boundary) is initiated at interface 602. Further as shown in Figure 6, the locally deformed carrier substrate 601 is placed on a portion of a substrate chuck (carrier substrate chuck) 603 in the manner shown in Figure 6 using a addressable local vacuum 604 and addressable local pressure 605.

[0067] Reference is now made to FIG. 7, which illustrates an exemplary die thickness measurement method, according to certain embodiments of the present disclosure.

[0068] As shown in FIG. 7, the die 106 faces down so that a lower portion of the circuit elements 701 is adhered via an adhesive 702 (eg, the light switchable adhesive 206) to the carrier substrate 202 during backgrinding or the like.

[0069] Additionally, as shown in FIG. 7, there is an optional variable pitch mechanism (VPM) 703 along with an exemplary optical and imaging assembly 704 that emits dual beams 705 to detect the thickness of the die 106 from the die backside 711 (the backside of the die 106) to the lower portion of the circuit element 701 (the thickness of the circuit element is precisely known).

[0070] Additionally, an optional mirror assembly 706 is utilized to sense multiple marks using a single imaging assembly, as shown in Figure 7. Additionally, Figure 7 shows an exemplary visible light path 707, where the visible beam reflects off the bottom of the die 106 (the die 106 is facing downwards).

[0071] Further, Figure 7 shows a thickness sensing substrate 708 with chirped moire marks 709 at the SiP (system in package) pitch. Additionally, Figure 7 shows an exemplary infrared (IR) light path 710, where the IR beam reflects off the lower portion of the circuit element 701 (which acts as a reflective medium for the IR light).

[0072] Reference is now made to FIG. 8, which illustrates an alternative exemplary die thickness measurement method, according to certain embodiments of the present disclosure.

[0073] As shown in Figure 8, in comparison with the exemplary die thickness measurement method of Figure 7, an IR beam 801 reflects off the lower portion of the circuit element 701 (which acts as a reflective medium for the IR light) and the die backside 711. The interference of the two reflected beams can be used to infer die thickness information.

[0074] Reference is now made to FIG. 9A, which illustrates a die encapsulation layer with etched pin structures according to an embodiment of the present disclosure.

[0075] As shown in Figure 9A, the encapsulation layer 901 of the die 106 is etched to form pin structures 902. According to an embodiment of the present disclosure, a top view of the structure of Figure 9A is shown in Figure 10A.

[0076] Additionally, FIG. 10A shows a vacuum moat (an area of ​​vacuum surrounding the die encapsulation layer 901).

[0077] 9B, which illustrates optional inkjetted gel-cured polymer-based pins 903 on the encapsulation layer 901 of the die 106, according to an embodiment of the present disclosure. A top view of the structure of FIG. 9B is shown in FIG. 10B, according to an embodiment of the present disclosure.

[0078] Additionally, FIG. 10B shows closely spaced inkjet drops forming a vacuum moat 1002 (an area of ​​vacuum surrounding the die encapsulation layer 901).

[0079] Reference is now made to FIG. 9C, which illustrates optional compliant pins 904 on the encapsulation layer 901 of the die 106, according to an embodiment of the present disclosure.

[0080] A more detailed description of Figures 2-8, 9A-9C, and 10A-10B is provided below.

[0081] In one embodiment, the die 106 on the carrier substrate 202 includes one or more die thickening layers 203 (e.g., the die faces down on the back-grind carrier substrate 202, or alternatively, the die faces up on the transfer substrate 104). In one embodiment, the one or more die thickening layers 203 are transparent. In one embodiment, the one or more die thickening layers 203 are made of silicon oxide, sapphire, silicon nitride, aluminum oxide, fused silica, glass, silicon carbide, polymer, and / or metal coating. In one embodiment, one or more adhesive layers are present between the die thickening layers 203 and between the die thickening layers 203 and the die 106. In one embodiment, the one or more adhesive layers, such as the adhesive layer 206, are made of a photoswitchable adhesive, an imprint resist, and / or an epoxy. In one embodiment, the one or more die thickening layers 203, the die 106, and the carrier substrate 202 are bonded together using one or more of the following bonding techniques: bump bonding, micro-bump bonding, mass reflow, eutectic bonding, thermo-compression bonding, hybrid bonding, anodic bonding, and fusion bonding. In one embodiment, the one or more die thickening layers 203 are grown and / or deposited on the die 106 using one or more material deposition techniques, such as chemical vapor deposition, physical vapor deposition, electroplating, sputtering, thermal evaporation, and the like. In one embodiment, the one or more die thickening layers 203 are transferred to the previous die thickening layer 203 or to the die 106 as a large substrate that will later be diced together with the die 106 using a suitable dicing technique. In one embodiment, the one or more adhesive layers, such as the adhesive layer 206, are applied using one or more of the following methods, such as inkjetting, spin coating, knife edge coating, and the like. In one embodiment, the one or more adhesive layers, such as the adhesive layer 204, consist of gel-cured adhesive drops. In one embodiment, the gel curing adhesive drop 204 is made of a monomeric material. In one embodiment, the solid-liquid ratio of the adhesive gel is adjusted by varying the level of oxygen in the curing environment (which can be air or nitrogen-added air). Note that a higher oxygen concentration results in a higher percentage of liquid in the gel and vice versa.In one embodiment, the curing is carried out using UV light.

[0082] In one embodiment, the die 106, active side down against the backgrind carrier substrate 202, is adhered to the backgrind substrate using a photoswitchable adhesive.

[0083] In one embodiment, an adhesion promoter may be utilized at one or more of the interfaces between one or more adhesion layers, such as adhesion layer 206, and one or more of the die thickening layer 203, the die 106, and the carrier substrate 202. Exemplary adhesion promoters include BARC, ValMat, and TranSpin.

[0084] The following elements depict general methods for enabling or preventing delamination of a multi-layer stack of adhesives and substrates at specific interfaces. These methods may be applied, for example, during pick-up of a die from a back-grind carrier substrate 202 (for direct die-to-wafer assembly), during pick-up of a die from a tape film on a tape frame 301 (for assembly onto a transfer substrate 104), during precision alignment correction of a die 106 on a transfer substrate 104, etc.

[0085] For example, one such factor is gel cure time and oxygen concentration. In one embodiment, the gel cure time and oxygen concentration in the environment are used to weaken certain adhesive interfaces and strengthen certain adhesive interfaces. Both shorter cure times and higher oxygen concentrations result in a higher percentage of liquid in the adhesive (oxygen poisoning affects the cure quality of commonly used UV crosslinkable materials such as acrylics).

[0086] Another factor is the spatial density of the adhesive gel drops: a higher density of adhesive gel drops results in stronger adhesion.

[0087] A further factor is the thickness of the adhesive: the thicker the adhesive in the liquid state (e.g. the liquid light switchable adhesive), the weaker the adhesive strength: if its thickness exceeds 100 nm or even 1000 nm, even if there is a wetted interface, the effective adhesive in the liquid state is much weaker because of the reduced capillary effect.

[0088] Another factor is the spatial placement of the adhesive drops. Debonding will begin more easily if the adhesive drops are applied away from the edge compared to when the adhesive drops are applied all the way to the edge. For example, a circular spatial placement of the adhesive drops in a rectangular die will lead to debonding initiation near the apex of the die where there are no adhesive drops. The greater the distance of the adhesive drops from the edge, the greater the tendency for debonding to occur.

[0089] A further factor is the inherent light absorption of the layer. In one embodiment, certain adhesive layers are treated with light of specific wavelengths to enable or disable peeling. For example, a photoswitchable adhesive exposed to visible light will strengthen the bond. Alternatively, an adhesive with IR absorbing nanoparticles dispersed therein will strengthen the bond when the polymeric material reaches its glass transition temperature (T g ) adhesive strength weakens when exposed to certain wavelengths of IR radiation.

[0090] Another element includes a special wafer chuck for initiating the cleavage, as shown in FIG.

[0091] In one embodiment, one or more dies 106 intended to be present on the SiP are thickened (before integration) to a predefined thickness. Dies 106 from one type of source substrate may have an inherent additional thickness. In one embodiment, die thickening is performed using one or more of the following methods: layer transfer (of die thickener) using direct bonding or adhesive layers, and / or coating using inkjetting, material deposition (CVD, PVD, sputtering, etc.), spin coating, and / or knife edge coating.

[0092] In one embodiment, the die thickening is performed using a layer made of one or more magnetic materials (e.g., a film of a magnetic material such as a non-magnetic material with suspended magnetic particles, iron oxide, chromium, barium, and magnetic compounds thereof). In one embodiment, the die thickening is performed using an adhesive to reduce and / or eliminate die thickness variations across the substrate. In one embodiment, the adhesive is applied to the backside of the die 106 to be thickened using inkjetting.

[0093] In one embodiment, the transfer substrate 104 has etched recesses 501 of different heights to accommodate dies of different heights so that the top surfaces of all dies are at substantially the same height. The dies 106 can be attached to the transfer substrate 104 using one or more of adhesives, imprint resists, photoswitchable adhesives, and epoxies. The etched recesses 501 of different heights can be fabricated using one or more of the following techniques: nanoimprint lithography or nanomolding using a multi-tier template. In one embodiment, the transfer substrate chuck 101 includes a UV and visible light source for switching an optional photoswitchable adhesive embedded in the die thickening layer 203 of the dies 106. In one embodiment, the UV and / or visible light source is in a addressable array. In one embodiment, the UV and / or visible light source is an array of interspersed UV and visible light LEDs.

[0094] In one embodiment, the die thickness measurement is performed on a die 106 that is placed active side down on a carrier substrate 202. In one embodiment, the die thickness measurement is performed before or after back grinding. In one embodiment, the die thickness measurement is performed on every die 106 on the substrate or a selected sample of dies 106. In one embodiment, the die thickness measurement is performed at two or more locations on the die 106 where the die thickness measurement is performed. In one embodiment, the die thickness measurement is performed using capacitive, optical, electrical, and / or mechanical methods. In one embodiment, the die thickness is measured by measuring the distance from a special mark on a thickness sensing substrate 708 as shown in FIG. 7 to the backside of the die 106 and the lower portion of the die circuitry 701 ... lower portion of the die 106. 2 -d 1) + (thickness of the circuit element, which is known precisely). In one embodiment, the mark is a chirped moire mark. Note that in FIG. 7, for example, the distance measurements from the die backside 711 and the lower portion of the circuit element 701 using visible light and IR light, respectively, can either be performed simultaneously or staggered in time. In another embodiment, the die thickness measurement is performed using thin film metrology from the die backside 711 as shown in FIG. 8. In one embodiment, IR light of an appropriate wavelength is utilized to create thin film interference between the die backside 711 and the lower portion of the die circuit element 701. The wavelength of the IR light utilized may be larger than the gap between the die backside 711 and the lower portion of the circuit element 701 (e.g., if the gap is about 20 μm, a mid-IR light source may be utilized). Alternatively, a phase unwrapping technique is utilized to determine the thickness of the die. In the two embodiments for die thickness measurement described immediately above, instead of using the underside portion of the circuit element 701, metal structures in the die kerf area are utilized for thickness measurement before dicing. In one embodiment, the metal structures are either structures already present in the die kerf for another purpose or structures created specifically for thickness measurement. In one embodiment, the metal structures are repeating structures (e.g., lines and spaces) or are uniform, continuous layers of metal.

[0095] In one embodiment, one or more of the dies 106 include an encapsulation layer on one or more of its front or back sides, with the encapsulation layer 901 having vacuum moats 1001, 1002. In one embodiment, the encapsulation layer 901 also has pins 902, 903, 904. In one embodiment, the pins 902, 903, 904 and / or the vacuum moats 1001, 1002 are fabricated using one or more of the following methods: coating the encapsulation layer and patterning the pins / moats using patterning techniques (e.g., photolithography and / or nanoimprint lithography). Alternatively, the following methods are utilized to create the pins 902, 903, 904 and / or vacuum moats 1001, 1002: ashing the encapsulation layer 901 in selected areas using an atmospheric pressure plasma jet to create the pins 902, 903, 904 / moats 1001, 1002, inkjetting a UV curable fluid in selected areas on the die 106, and UV curing the applied fluid to create the pins 902, 903, 904 / moats 1001, 1002. Masks for patterning the encapsulation layer using nanoimprint lithography are fabricated using one or more of the following techniques: diamond cutting, laser ablation, and computer numerical control (CNC) machining. In one embodiment, a multi-layer mask is utilized to perform multi-layer patterning on the die 106 using nanoimprint lithography. Resist patterning followed by etching is utilized to simultaneously fabricate the vacuum moats 1001, 1002 on the die 106 as well as the die die 106 (assuming the die 106 was not diced prior to the patterning step). In one embodiment, the vacuum moats 1001, 1002 and / or pins 902, 903, 904 are fabricated directly on the die substrate (backside or frontside). In one embodiment, the pins 902, 903, 904 and / or vacuum moats 1001, 1002 fabricated on the die 106 are compliant in the z-direction. In one embodiment, the encapsulation layer 901 used to fabricate the vacuum moats 1001, 1002 is (e.g., O 2The encapsulation layer 901 can be removed (using plasma ashing). In one embodiment, the encapsulation layer 901 is made of one or more of the following materials: carbon, imprint resist, epoxy, polymer, metal layer, chrome, aluminum oxide, and photoswitchable adhesive. In one embodiment, dedicated equipment is utilized to fabricate the pins 902, 903, 904, and / or vacuum moats 1001, 1002. In one embodiment, a dedicated module integrated into an existing tool is utilized to fabricate the pins 902, 903, 904, and / or vacuum moats 1001, 1002. In one embodiment, the module utilizes a process for high speed plasma etching.

[0096] In one embodiment, a flat surface with a vacuum hole in the center is utilized to pick and place the die 106 using the vacuum moats 1001, 1002.

[0097] In one embodiment, a chucking module (CM) has a fixed lateral dimension that is smaller than the dimension of the smallest die 106 in a group of dies 106 being picked and placed using the CM. In one embodiment, the CM is utilized to pick and place a thickened die 106, where the thickening of the die is performed using one or more of the methods described above.

[0098] Reference is now made to FIG. 11, which illustrates an exemplary gantry-based AMS, in accordance with an embodiment of the present disclosure.

[0099] As shown in FIG. 11, source wafers 105A-105F (e.g., source wafers 1-6) are placed on a granite platen 1101. Source wafers 105A-105F may each be referred to collectively or individually as source wafers 105 or a source wafer 105. Further, FIG. 11 shows a gantry xy stage 1102 that is used to mark, label, measure, or inspect source wafers 105, such as source wafers 105A, 105D. Additionally, FIG. 11 shows a wafer 1103, such as a transfer wafer 104 or a product wafer.

[0100] In addition, FIG. 11 shows an exemplary Nx1 AMS 1104 and an exemplary NxM AMS 1105.

[0101] Additionally, as shown in FIG. 11, each source wafer 105 is supported by a long stroke nano-precision xyθ stage, such as stage 1106.

[0102] Referring now to FIG. 12, FIG. 12A shows a cross section of a gantry xy stage 1102 according to one embodiment of the present disclosure.

[0103] As shown in FIG. 12A, FIG. 12A shows a chucking module (CM) 1201 on a gantry-based AMS.

[0104] Additionally, FIG. 12A shows circuit elements 1202 of die 106 as well as die top alignment marks 1203 .

[0105] In addition, as shown in FIG 12A, the die 106 is placed on a portion of the transfer substrate 104 (acting as a golden reference wafer) via a fluid 1204 (e.g., a liquid adhesive), and the portion of the transfer substrate 104 is supported by a portion of the transfer substrate chuck 101, as shown in FIG 12A.

[0106] 12A further illustrates an optional variable pitch mechanism (VPM) 703 along with an exemplary optical and imaging assembly 704 that emits a light beam 1205 to sense the thickness of the die 106. In one embodiment, the light beam 1205 corresponds to infrared (IR) light used in alignment metrology.

[0107] In addition, as shown in Figure 12A, an optional mirror assembly 706 is utilized to detect multiple marks using a single imaging assembly. In connection with such detection, an optional auxiliary mark 1206 on the transfer substrate 104 for Moire metrology is utilized.

[0108] Reference is now made to FIG. 12B, which illustrates an alternative cross-section of the gantry xy stage 1102, according to an embodiment of the present disclosure.

[0109] In comparison to FIG. 12A, the gantry xy stage 1102 of FIG. 12B utilizes underside die alignment marks 1207 as opposed to the topside die alignment marks 1203 shown in FIG. 12A.

[0110] Reference is now made to FIG. 13A, which illustrates a die 106 prior to dicing, according to an embodiment of the present disclosure.

[0111] As shown in FIG. 13A, die 106 includes upper peripheral alignment mark 1301, lower peripheral alignment mark 1302, and lower primary alignment mark 1303.

[0112] Reference is now made to FIG. 13B, which illustrates the die 106 after dicing, according to an embodiment of the present disclosure.

[0113] As shown in FIG. 13B, the relative position 1304 is known.

[0114] Reference is now made to FIG. 14A, which illustrates the x / y distance between the lower primary alignment marks 1303 shown in FIGS. 13A and 13B, according to one embodiment of the present disclosure.

[0115] As shown in FIG. 14A, in one embodiment, the x / y distance between the lower primary alignment marks 1303 is smaller than the smallest x and y lateral dimensions for all dies 106 on a substrate (e.g., transfer substrate 104, intermediate substrate, product substrate).

[0116] 14B, which shows that the positions of the upper perimeter mark 1301 and the lower perimeter mark 1302 with respect to the circuit element 1202 and the primary alignment mark 1303 are known by design according to an embodiment of the present disclosure. As a result, alignment between the circuit element 1202 and the lower primary alignment mark 1303 is obtained by measuring the alignment between the perimeter marks 1301, 1302 prior to dicing.

[0117] Reference is now made to FIG. 15A, which illustrates an exemplary massively parallel diactuation method, in accordance with one embodiment of the present disclosure.

[0118] Specifically, FIG. 15A shows a group 1501 of dies 106 on an exemplary substrate 1502 , where the dies 106 are surrounded by a light switchable adhesive 1503 .

[0119] Additionally, as shown in FIG. 15A, a carrier 1504 for the lattice of actuators utilizes a group of piezoelectric manipulators 1505 to move and control the die 106 .

[0120] Reference is now made to FIG. 15B, which illustrates an alternative exemplary massively parallel diactuation method, in accordance with an embodiment of the present disclosure.

[0121] In comparison to FIG. 15A, FIG. 15B illustrates the use of an electromagnetic actuator 1506 (rather than a piezoelectric manipulator 1505 ) to move and control the die 106 , which has a surrounding magnetic layer 1507 .

[0122] 16A-16C, which illustrate a direct die-to-wafer (D2W) bonding approach according to one embodiment of the present disclosure.

[0123] 16A, the carrier substrate 202 is held by a substrate chuck 1601. For example, if the carrier substrate 202 corresponds to the source substrate 105, the source substrate 105 is held by the source substrate chuck 102.

[0124] In one embodiment, the carrier substrate 202 includes diced and backside thinned dies 106 on a glass carrier. In one embodiment, the carrier substrate 202 is secured on a selective release chuck 1601.

[0125] Further, as shown in Figure 16A, the active side of the die 106 faces down. In addition, Figure 16A shows the use of a light switchable adhesive 1503 as previously discussed.

[0126] In one embodiment, the die 106 is lifted using an AMS 110, as shown in FIG. 16B.

[0127] In one embodiment, plasma treatment is performed in an optional atmospheric pressure plasma chamber to perform direct bonding as shown in FIG. 16C.

[0128] As shown in Figure 16C, IR measurements 1602 are performed through the backside of the die 106. Additionally, air cushions 1603 are created around each die 106 using the CM assembly 1201, as shown in Figure 16C.

[0129] Further, as shown in FIG. 16C, the die 106 on the carrier substrate 202 is picked and placed onto a target substrate, such as a product substrate 1604.

[0130] In one embodiment, thickness variations between the die of a single wafer, as well as topography variations on a product wafer 1604, are compensated for using tip / tilt / z compliance for each CM 1201.

[0131] In one embodiment, variations in die thickness across different source wafers (eg, source substrate 105) are compensated for using a sequencing method in which the thinnest die 106 is assembled first.

[0132] 11, 12A-12B, 13A-13B, 14A-14B, 15A-15B, and 16A-16C, in one embodiment, an alignment system for measuring the alignment of the die 106 on a substrate (e.g., transfer substrate 104, source substrate 105, product substrate 1604, intermediate substrate) is under the chuck of each of said substrates. In one embodiment, one or more of the following alignment methods are utilized for measuring the die alignment, i.e., relative alignment measurement (e.g., using a moire-based alignment method) and absolute alignment measurement (e.g., using an imaging-based alignment method). In one embodiment, the microscope used in the alignment measurement is a low numerical aperture (NA) microscope. In one embodiment, the microscope used in the alignment measurement is a very low numerical aperture (NA) microscope. In one embodiment, the microscope used in the alignment measurement has an NA of less than 0.05. In one embodiment, the microscope used in the alignment metrology has a NA of less than 0.01. In one embodiment, the die alignment is performed using a SPP X and SPP YThe alignment marks are measured relative to corresponding marks on a substrate (e.g., transfer substrate 104) that is aligned to a grid where . In one embodiment, the marks are moire alignment marks. In one embodiment, the substrate with the alignment mark grid is also called a golden reference wafer and is made of one or more of thermo-mechanically stable materials (e.g., sapphire, fused silica, glass, and silicon). In one embodiment, die pick-and-place is implemented using one or more AMS mounted on a gantry stage 1102. In one embodiment, the gantry stage 1102 further includes one or more source substrates 105, each of which may have a unique size and form factor. One or more of the wafers (e.g., source wafer 105, product wafer 1604, transfer wafer 104, intermediate wafer) and corresponding chucks are mounted on an independent XYθ wafer stage.

[0133] In one embodiment, the positions of multiple dies on a substrate are changed in parallel, where a light switchable adhesive (e.g., adhesive 1503) is present between the dies (e.g., a group of dies 106) and the substrate (e.g., substrate 1502), and a group of actuators (e.g., piezoelectric manipulators 1505) are utilized to change the position of one or more of the dies. The group of actuators can be one or more of piezoelectric type (contact-based force application), electrostatic type (non-contact force application), and electromagnetic type (non-contact force application). In one embodiment, a set of actuators is utilized to change the position of all the dies 106 on the substrate (e.g., substrate 1502) in a rigid body manner.

[0134] In one embodiment, as discussed above with respect to FIGS. 16A-16C, the die 106 on the carrier substrate 202 (e.g., a back-ground carrier substrate) is picked and placed on the target substrate (e.g., a product substrate 1604) and directly bonded to the substrate. In one embodiment, such bonding is bump bonding, micro-bump bonding, mass reflow, eutectic bonding, thermo-compression bonding, hybrid bonding, anodic bonding, and / or fusion bonding. In one embodiment, the die 106 is cleaned and surface activated using plasma prior to hybrid bonding. In one embodiment, the adhesive (e.g., adhesive 1503) between the carrier substrate 202 and the die 106 is a photoswitchable adhesive. In one embodiment, stray adhesive drops remaining on the die 106 after pick-up are cleaned during a plasma cleaning step. In one embodiment, the AMS 110 is used to create a fluid cushion (e.g., an air cushion) around one or more of the die 106 bonded to the product substrate 1604. When direct wafer-to-wafer bonding is being performed, one of the wafers to be bonded may include through-holes (e.g., such through-holes are created using deep etching techniques such as MACE and DRIE) through which air can be supplied to create a fluid cushion between the two wafers being bonded.

[0135] In one embodiment, an array of die testing units is utilized to test important functional characteristics for a group of one or more dies 106 on one or more substrates (e.g., source substrate 105, transfer substrate 104, intermediate substrate, product substrate 1604). Important functional characteristics may include electrical performance, power consumption, and good / bad die testing. In one embodiment, an array of die testing units is disposed on a VPM (e.g., VPM 703), which may be used to vary the pitch of the die testing units.

[0136] In one embodiment, an array of die metrology units is utilized to measure key characteristics for a group of one or more dies 106 on one or more substrates (e.g., source substrate 105, transfer substrate 104, intermediate substrate, product substrate 1604). Key characteristics may include die thickness, particle count, die stress, die bending, and quality of one or more deposited layers. In one embodiment, an array of die metrology units is disposed on a VPM (e.g., VPM 703), which may be used to vary the pitch of the die metrology units.

[0137] Reference is now made to FIG. 17A, which illustrates an apparatus for die thinning according to an embodiment of the present disclosure.

[0138] As shown in Fig. 17A, the apparatus includes a carrier substrate 202 held by a substrate chuck 1601. Further, as shown in Fig. 17A, a die attach material 1503 is placed between the carrier substrate 202 and the die 106. In one embodiment, optionally, the die attach material 1503 may also act as an encapsulant. Further, in one embodiment, the die 106 is active side down.

[0139] Additionally, FIG. 17A shows a diced die 1701 with die attach 1503 covering the sides of the die.

[0140] Additionally, FIG. 17A shows a die thinning module 1702 for thinning the die along with an optional short stroke stage 1703.

[0141] FIG. 17B illustrates a die thinning technique using the apparatus of FIG. 17A according to an embodiment of the present disclosure.

[0142] As shown in Figure 17B, Figure 17B shows the die backside 711 being thinned using the die thinning module 1702. As further shown in Figure 17B, a MACE catalyst 1704 is utilized to perform a wet chemical etch of the die backside 711 using a metal catalyst. Additionally, as shown in Figure 17B, an optional encapsulation layer 1705 is utilized to prevent damage to the die thinning module 1702 from the MACE catalyst 1704 and the etchant.

[0143] FIG. 17C illustrates an alternative die thinning approach using the apparatus of FIG. 17A according to an embodiment of the present disclosure.

[0144] Referring to FIG. 17C, the die thinning module 1702 includes a local temperature controller 1706 along with locally applied MACE etchant 1707, black silicon 1708, and gold (Au) 1709, and the die backside 711 is covered with gold 1709.

[0145] In one embodiment, die thinning is performed using metal assisted chemical etching (MACE), anodization, silicon anodization, electrochemical etching, electropolishing, inkjet enabled etching and planarization, and / or plasma etching.

[0146] In one embodiment, die thinning is performed using a part (which may be a substrate or part of a substrate) that includes one or more machined pillars covered with a MACE catalyst (e.g., MACE catalyst 1704). In one embodiment, the part is made of chrome, steel, gold, metal, silicon, polymer, and / or PTFE (polytetrafluoroethylene). In one embodiment, the part is made of micromachined silicon covered with an encapsulation layer (e.g., chrome) and a MACE catalyst (e.g., gold).

[0147] In one embodiment, the die thickness variation is measured using capacitive, optical, electrical, and / or mechanical methods. In one embodiment, the die thickness variation is measured using the exemplary techniques described in Figures 7-8.

[0148] In one embodiment, an array of die thinning modules 1702 is used to thin one or more dies 106 simultaneously. In one embodiment, the die thinning modules 1702 are located in a VPM (e.g., VPM 703). In one embodiment, a die thickness measurement module is located in a VPM (e.g., VPM 703). In one embodiment, a control knob is utilized in the die thinning module 1702 to adjust the local die thinning rate based on feedback from the die thickness measurement module. In one embodiment, such control knob controls temperature, electric field, radiation of appropriate spectrum, and / or etchant concentration. In one embodiment, temperature control is performed using a set of thermoelectric heaters / coolers, incident light of appropriate spectrum, and optionally adjusted using a digital micromirror device (DMD), a fluidic temperature control module, and / or a microfluidic temperature control module. In one embodiment, the die thinning module 1702 is scanned across one or more dies 106. In one embodiment, the die thinning module 1702 spans one or more dies 106.

[0149] In one embodiment, the die thinning etchant (if required) is applied locally around the area being thinned by the die thinning module 1702. In one embodiment, the die thinning etchant (if required) is applied in bulk such that one or more die backsides 711 are partially or completely submerged in the etchant.

[0150] In one embodiment, die thinning is performed by creating black silicon 1708 on the backside of the die 106 (e.g., die backside 711) and then oxidizing the black silicon 1708 and removing it using an oxide etch (e.g., using a wet or dry HF etch). In one embodiment, the black silicon 1708 is created using electrochemical etching of silicon, anodization of silicon, photogeneration-based anodization of silicon, and / or MACE. In one embodiment, etch depth control is performed using one or more of the methods described above. In one embodiment, a gold film is deposited on the die backside 711 and used to create the black silicon 1708 through a MACE process.

[0151] In one embodiment, a die 106 with a buried oxide layer (e.g., a die fabricated using an SOI wafer) and other buried sacrificial layers (e.g., SiGe) is thinned by removing the bulk substrate from the die 106 using a sacrificial layer etchant (e.g., wet or gas phase HF for an oxide sacrificial layer). In one embodiment, while the sacrificial layer etch is performed, the die 106 is face down and attached to the carrier substrate 202 using an adhesive (e.g., adhesive 1503) (which may optionally also act as a sealant against the sacrificial layer etchant).

[0152] In one embodiment, diamond thinning and / or polishing is performed using a plasma-based and / or chemical etching process. In one embodiment, diamond thinning and / or polishing is performed using an oxygen plasma-based process. In one embodiment, diamond thinning and / or polishing is performed using a nickel-based process. Thinning and / or polishing is performed using one or more thinning modules 1702 with thickness feedback obtained from a thickness measurement module (as previously described).

[0153] In one embodiment, dicing is performed before or after die thinning using laser-based, plasma-based, and / or chemical (e.g., MACE-based) methods. In embodiments where dicing is performed before die thinning, an encapsulation layer is utilized to protect the die front-side during die back-side thinning. In one embodiment, the adhesive (e.g., adhesive 1503) utilized to adhere the die 106 to the carrier substrate 202 is also used to protect the die front-side during die back-side thinning.

[0154] Reference is now made to FIG. 18A, which illustrates an apparatus for particle removal according to an embodiment of the present disclosure.

[0155] As shown in Fig. 18A, the apparatus includes a carrier substrate 202 held by a substrate chuck 1601. Further, as shown in Fig. 18A, a die attach material 1503 is placed between the carrier substrate 202 and the die 106. In one embodiment, optionally, the die attach material 1503 may also act as an encapsulant. Further, in one embodiment, the die 106 is active side down.

[0156] Additionally, FIG. 18A shows a diced die 1701 with die attach 1503 covering the sides of the die.

[0157] 18A further illustrates a particle removal module 1801 for removing particles. In addition, the apparatus of FIG.

[0158] FIG. 18B illustrates an exemplary particle removal technique using the apparatus of FIG. 18A, according to one embodiment of the present disclosure.

[0159] As shown in Figure 18B, a MACE based probe 1802 is utilized for removal of particles 1803 on the die backside 711. Further, as shown in Figure 18B, a MACE catalyst 1804 is utilized for removal of particles 1803 on the die backside 711. Additionally, as shown in Figure 18B, a locally applied MACE etchant 1805 is utilized to etch away particles 1803.

[0160] In one embodiment, plasma cleaning, oxygen plasma cleaning, atmospheric plasma cleaning, MACE, compressed air, and / or electrostatic probes are used to remove particles (e.g., particles 1803) from the backside (e.g., die backside 711) or frontside of the die 106. In one embodiment, particles (e.g., particles 1803) on the backside or frontside of the die 106 are detected using imaging-based, interferometry-based, acoustic, probe-based, and / or electrostatic methods. In one embodiment, a set of probes (e.g., probes 1802) is utilized to remove particles (e.g., particles 1803) from the die backside or frontside (e.g., die backside 711). In one embodiment, the set of probes (e.g., probes 1802) utilize a locally applied MACE etchant 1805 to etch away particles (e.g., particles 1803), including silicon-based particles. In one embodiment, a set of probes (e.g., probe 1802) utilizes adhesive-based particle pickup (the probe tip may include an adhesive that adheres the particle to the probe tip), localized sonication, and / or localized vacuum suction to remove a particle (e.g., particle 1803) from the die 106 and attach it to the probe (e.g., probe 1802).

[0161] Reference is now made to Fig. 19, which is a flowchart of a method 1900 for performing direct bonding, according to an embodiment of the present disclosure. Figs. 20A-20F show cross-sectional views for performing direct bonding using the steps described in Fig. 19, according to an embodiment of the present disclosure.

[0162] Referring to FIG. 19 in conjunction with FIGS. 20A-20F, in step 1901, the oxide surrounding the upper portions of the substrates 2002A, 2002B is etched to expose the pillars 2005, as shown in FIGS. 20A-20B.

[0163] As shown in FIG. 20A, the die 2001 includes two substrates 2002A, 2002B, and includes a back end metal layer 2003 and a front end 2004.

[0164] An oxide etch is performed on the structure of FIG. 20A resulting in exposed pillars 2005, as shown in FIG. 20B.

[0165] In step 1902, as shown in Figure 20C, a conformal oxide 2006 is deposited on the structure of Figure 20B.

[0166] In step 1903, an anisotropic oxide etch is performed resulting in the structure shown in Figure 20D. Additionally, as a result of the anisotropic oxide etch being performed, oxide spacers 2007 are formed around the metal pillars 2005, as shown in Figure 20D.

[0167] In step 1904, direct bonding of an unetched die to the structure of Figure 20D is performed, as shown in Figures 20E and 20F. Figure 20E shows an unetched die 208 directly bonded to the structure shown in Figure 20D, resulting in the structure shown in Figure 20F, which contains particles 2009 in the gaps between pillars 2005 of the structure of Figure 20D.

[0168] Reference is now made to Figure 21, which is a flowchart of an alternative method 2100 for performing direct bonding, according to an embodiment of the present disclosure. Figures 22A-22F show cross-sectional views for performing direct bonding using the steps described in Figure 21, according to an embodiment of the present disclosure.

[0169] Referring to FIG. 21 in conjunction with FIGS. 22A-22F, in step 2101, the oxide surrounding the upper portions of the substrates 2002A, 2002B is etched to expose the pillars 2005, as shown in FIGS. 22A-22B.

[0170] As shown in FIG. 22A, the die 2001 includes two substrates 2002A, 2002B, and includes a back end metal layer 2003 and a front end 2004.

[0171] As shown in FIG. 22B, an oxide etch is performed on the structure of FIG. 22A, resulting in exposed pillars 2005.

[0172] In step 2102, polysilicon is deposited, followed by planarization and porosification, as shown in Figure 22C.

[0173] In step 2103, as shown in FIG. 22D, the polysilicon 2201 and a portion of the pillars 2005 are etched, followed by the deposition of a thin oxide coating 2202, followed by planarization.

[0174] In step 2104, direct bonding of the unetched die to the structure of Fig. 22D is performed, as shown in Fig. 22E and Fig. 22F. Fig. 22E shows an unetched die 2008 directly bonded to the structure shown in Fig. 22D, resulting in the structure shown in Fig. 22F, which includes particles 2009 that have broken through the thin oxide layer 2202 and are embedded in the porous layer (see 2201 and 2202 in Fig. 22F).

[0175] Reference is now made to Fig. 23, which is a flowchart of a further method 2300 for performing direct bonding, according to an embodiment of the present disclosure. Figs. 24A-24G show cross-sectional views for performing direct bonding using the steps described in Fig. 23, according to an embodiment of the present disclosure.

[0176] Referring to FIG. 23 in conjunction with FIGS. 24A-24G, in step 2301, the oxide surrounding the upper portions of the substrates 2002A, 2002B is etched to expose the pillars 2005, as shown in FIGS. 24A-24B.

[0177] As shown in FIG. 24A, the die 2001 includes two substrates 2002A, 2002B, and includes a back end metal layer 2003 and a front end 2004.

[0178] An oxide etch is performed on the structure of FIG. 24A resulting in exposed pillars 2005, as shown in FIG. 24B.

[0179] In step 2302, polysilicon 2401 is deposited followed by planarization, as shown in Figure 24C.

[0180] In step 2303, the polysilicon 2401 and portions of the pillars 2005 are etched, followed by the deposition of a thin oxide coating 2402, which is patterned and etched as shown in Figure 24D.

[0181] In step 2304, an anisotropic silicon etch is performed to create mushroom structures 2403, as shown in Figure 24E.

[0182] In step 2305, direct bonding of an unetched die to the structure of Fig. 24E is performed, as shown in Fig. 24F and Fig. 24G. Fig. 24F shows an unetched die 2008 directly bonded to the structure shown in Fig. 24E, resulting in the structure shown in Fig. 24G, which includes particles 2009 between mushroom structures 2403.

[0183] With reference to Figures 19, 20A-20F, 21, 22A-22F, 23, and 24A-24G, two substrates 2001, 2008 need to be bonded. Such substrates can be wafers, diced dies, etc. In one embodiment, an etch-back process is utilized to reduce the contact area (during direct bonding) between the two substrates. Such reduction of the contact area can make the direct bonding process more tolerant to particles. The probability of particles landing at the bonding interface is lower (compared to non-etched back substrates). In one embodiment, direct bonding is performed such that there is first a low temperature oxide-to-oxide bonding step, followed by an annealing step to bond the metal connections. In one embodiment, only one of the two substrates 2001, 2008 that will be directly bonded, e.g., substrate 2001, is subjected to the etch-back process. In one embodiment, one of the substrates 2001, 2008 is an interposer and the other substrate is a die that is bonded to the interposer. In one embodiment, the etch-back process is performed only on the interposer. In one embodiment, the area of ​​the etched-back regions is larger compared to the regions that are not etched back. The etch-back process etches away regions of oxide such that only metal pillars (e.g., pillars 2005) (which are exposed as the oxide layer is etched back) and sparse regions of oxide remain after the etch-back. The remaining oxide may be continuous with the metal pillars (e.g., pillars 2005). In one embodiment, after the etch-back, metal pillars (e.g., pillars 2005) with regions of oxide that are co-centered and / or continuous remain. In one embodiment, one or more of the following patterning techniques are utilized to perform this etch-back process: photolithography, nanoimprint lithography, direct laser lithography, and / or electron beam lithography, followed by dry and / or wet etching. In one embodiment, an initial oxide etching process is used to etch back all the oxide (exposing the metal pillars 2005).Subsequently, a conformal oxide coating (eg, coating 2006) and then an anisotropic oxide etch are performed to form oxide spacers (eg, spacers 2007) around the metal pillars (eg, pillars 2005).

[0184] In one embodiment, one or both of the two substrates 2001, 2008 to be directly bonded contain nanofeatures and / or microfeatures that undergo one or more processes whereby, when a particle (e.g., particle 2009) is present at a certain location between the two substrates, the nanofeatures and / or microfeatures either pierce the particle and / or break off locally in a predictable manner.

[0185] In one embodiment, a porous layer (see 2201, 2202 in FIG. 22F) is created in silicon around a metal pillar (e.g., pillar 2005). In one embodiment, this porous layer is created in silicon (using a silicon porosification technique such as MACE, anodization of silicon, electrochemical etching, etc.). In one embodiment, a porous layer (e.g., mesoporous aluminum oxide) is deposited in the etched back areas (in the process described above) and optionally planarized. In one embodiment, optionally, a thin homogeneous layer of silicon oxide is deposited on one or more of the porous layers described above.

[0186] In one embodiment, mushroom structures 2403 are created in the area around the metal pillars (e.g., pillar 2005). These mushroom structures 2403 may have a base made of silicon and a top made of a different material (e.g., silicon oxide) suspended in the silicon base. The tops of the mushrooms may collapse in a predictable manner when asymmetrically loaded by particles such as particle 2009.

[0187] In one embodiment, die thinning is utilized to bring temperature hot spots closer to the heat sink. In 2.5D integration, the cooling fluid may interfere with the die backside (e.g., die backside 711). In 3D ICs, the cooling fluid may interfere with both the die backside (e.g., die backside 711) and the die frontside (for dies in a 3D stack).

[0188] Reference is now made to FIG. 25, which illustrates a die coolant according to an embodiment of the present disclosure.

[0189] As shown in FIG. 25, the die 106 is bonded to the package substrate 2501 via an adhesive 2502. Furthermore, as shown in FIG. 25, there are hot spots 2503 in the die 106, which are areas that have cooled slower than the surrounding material. In addition, as shown in FIG. 25, a heat spreader layer (also referred to herein simply as a "heat spreader") 2504 is placed between the die 106 and the fluid cooling liquid 2505 via a thermal interface layer 1 (TIM1) 2506A and a thermal interface layer 2 (TIM2) 2506B. The thermal interface layers 2506A-2506B may be referred to collectively or individually as thermal interface layers 2506 or thermal interface layers 2506, respectively. In one embodiment, the heat spreader layer 2504 corresponds to a thermal packing component configured to transfer heat from a concentrated or high heat flux source to another area with a low heat flux source.

[0190] Reference is now made to FIG. 26, which is a cross section of the die 106 of FIG. 25 and a heat spreader layer 2504 (eg, a diamond heat spreader) according to an embodiment of the present disclosure.

[0191] 26, the heat spreader layer 2504 includes pillars 2601. For example, the pillars 2601 may be about 1 μm in height and about 100 nm in diameter. In one embodiment, the pillars 2601 correspond to 400 nm pitch pillars.

[0192] Further, as shown in FIG. 26, the heat spreader layer 2504 (e.g., diamond) may be attached to the die 106 using a thin adhesive layer, a thin TIM layer (e.g., TIM layer 2506), or a eutectic bond (all represented by element 2602).

[0193] In one embodiment, the TIM layer 2506 is located in the gaps between the pillars 2601 .

[0194] Further, as shown in FIG. 26, the upper portion of the die 106 corresponds to a thinned die where the leading end 2603 is heated unevenly, with darker shaded areas indicating hotter areas and lighter shaded areas indicating cooler areas.

[0195] In addition, FIG. 26 shows a trailing metal layer 2604 without significant Joule heating.

[0196] Referring to FIG. 27, FIG. 27 illustrates an alternative die coolant according to an embodiment of the present disclosure.

[0197] The structure of FIG. 27 is the same as that of FIG. 25, except that the fluid coolant 2505 is now integrated into the heat spreader 2504.

[0198]

[00136] Referring now to Figure 28, Figure 28 is a flowchart of a method 2800 for integrating a thinned die with a heat spreader, according to an embodiment of the present disclosure. Figures 29A-29C show cross-sectional views for integrating a thinned die with a heat spreader using the steps described in Figure 28, according to an embodiment of the present disclosure.

[0199] Referring to FIG. 28 along with FIG. 29A-29C, in step 2801, a heat spreader 2504 (e.g., a diced and micromachined diamond) is picked and placed onto the thinned die 106 on the carrier substrate 202, as shown in FIG. 29A-29B.

[0200] FIG. 29A shows that the thinned die 106 is attached to a carrier substrate 202, such as via an adhesive 2901.

[0201] FIG. 29B illustrates pick-and-place assembly of a heat spreader 2504 (eg, a diced micromachined diamond) to the thinned die 106 on the carrier substrate 202.

[0202] In step 2802, as shown in FIG. 29C, the die with integrated heat spreader (heat spreader 2504 with thinned die 106) is placed on an interposer 2902 (a chip that can be used as a bridge or conduit to allow electrical signals to flow through it to another element).

[0203] Further discussion regarding Figures 25-28 and 29A-29C is provided below.

[0204] In one embodiment, thermal hot spots 2503 on the die are reduced using a heat spreader 2504, which may be made of diamond, silicon carbide, boron nitride, and other materials with high thermal conductivity. In one embodiment, the heat spreader 2504 is made of a stack of multiple materials, such as diamond epitaxially grown on silicon, and other stacks of multiple materials, such as diamond with a metal coating, silicon carbide with a metal coating, and the like. In one embodiment, the heat spreaders 2504 are stacked on top of each other. In one embodiment, the heat spreader 2504 is attached to the die 106 for cooling using a thermal interface material (TIM) 2506. In one embodiment, the TIM 2506 is an adhesive, a thermally conductive adhesive, a thermally conductive polymer, a polymer interspersed with thermally conductive nanoparticles, a metal, an alloy (e.g., solder, dymalloy, etc.), and / or a thermally conductive dielectric. In one embodiment, the heat spreader 2504 is made of Dimalloy (or other alloy with tunable thermal expansion and high thermal conductivity), in one embodiment, the composition of said alloy is such that the thermal expansion of the alloy matches the thermal expansion of the die 106. In one embodiment, the TIM 2506 is made of a multi-layer stack of alloy layers whose thermal expansion changes gradually with height, such that the bottom of the layer matches the thermal expansion of the die 106 and the top matches the thermal expansion of the heat spreader 2504 (or vice versa depending on the configuration of the die 106 and heat spreader).

[0205] In one embodiment, the die backside (e.g., die backside 711) comprises machined features. In one embodiment, the die backside (e.g., die backside 711) comprises a nanopillar array. In one embodiment, the die backside (i.e., die backside 711) comprises a nanofeature array. In one embodiment, the die backside (e.g., die backside 711) comprises a microfeature array. The array is fabricated using MACE, anodization, anodization of silicon, electrochemical etching, and plasma etching, with optional patterning performed using photolithography, nanoimprint lithography, direct laser lithography, e-beam lithography, and the like. In one embodiment, the die backside (e.g., die backside 711) comprises black silicon. In one embodiment, die 106 is made of silicon, such as silicon with an epitaxially grown layer, such as GaN or other non-silicon substrate.

[0206] In one embodiment, the front and / or rear end of the heat spreader includes machined features. In one embodiment, the front and / or rear end of the heat spreader includes a nanopillar array. In one embodiment, the front and / or rear end of the heat spreader includes a nanofeature array. In one embodiment, the front and / or rear end of the heat spreader includes a microfeature array. In one embodiment, the heat spreader 2504 includes microchannels. In one embodiment, the heat spreader 2504 includes microchannels to integrate a fluid coolant 2505 into the heat spreader 2504 itself. In one embodiment, the arrays are fabricated using MACE, anodization, anodization of silicon, electrochemical etching, and / or plasma etching. In one embodiment, nickel-based etching is used to fabricate micro- and / or nanostructures in the diamond heat spreader. In one embodiment, oxygen plasma-based etching is used to fabricate micro- and / or nanostructures in the diamond heat spreader. In one embodiment, a hard mask (e.g., silicon, polysilicon, silicon nitride, etc.) that is resistant to oxygen plasma is utilized to etch diamond in specific areas. Optional patterning for the above etching step is performed using photolithography, nanoimprint lithography, direct laser lithography, electron beam lithography, etc.

[0207] In one embodiment, the heat spreader 2504 is attached to the die 106 using one or more of the following methods: adhesive, thermally conductive adhesive, thermally conductive polymer, polymer with thermally conductive nanoparticles dispersed therein, metal, alloy (e.g., solder, dimalloy, etc.), thermally conductive dielectric, eutectic bonding, hybrid bonding, fusion bonding, direct bonding, bonding with a solder layer, flip chip bonding, etc. An optional interfacial fluid layer between the die 106 and the heat spreader 2504 is ink jetted, spin coated, drop cast, knife edge coated, etc.

[0208] In one embodiment, the heat spreader substrate (e.g., diamond) is diced onto a unique carrier substrate and picked and placed on the die backside (e.g., die backside 711). In one embodiment, the dicing is performed using mechanical dicing, laser dicing, plasma dicing, or chemical dicing.

[0209] In one embodiment, the nanostructures in the heat spreader 2504 and / or the die backside (e.g., die backside 711) are tall and / or thin enough to accommodate (without substantial obstruction) differential thermal expansion between the die 106 and the heat spreader 2504 during chip operation. In one embodiment, the nanostructures in either or both of the heat spreader 2504 and the die backside (e.g., die backside 711) are tall and / or thin enough to accommodate (without substantial obstruction) particles between the die 106 and the heat spreader 2504 during assembly of the heat spreader 2504 to the die 106.

[0210] In one embodiment, the heat spreader substrate is assembled to the die 106 prior to dicing, and dicing of the assembled heat spreader+die stack is performed using laser-based, mechanical, plasma-based, and / or chemical dicing methods.

[0211] In one embodiment, a heat spreader 2504 is used that matches the thermal expansion of the die 106 and has a high thermal conductivity compared to the die 106 .

[0212] In one embodiment, if multiple dies of different thicknesses require a heat spreader 2504, all can be connected to the fluid cooling fluid 2505 using a multi-layer adapter plate, which is made using copper, aluminum, and other metals. In one embodiment, the adapter plate is computer numerically controlled (CNC) machined.

[0213] In one embodiment, the heat spreader 2504 is integrated into an existing chip that has been appropriately decapped.

[0214] Referring now to FIG. 30, FIG. 30 illustrates an exemplary assembly of a SiP (System in Package, which is a method of packing two or more integrated circuits inside a single package) using hierarchical feedstock chips according to one embodiment of the present disclosure.

[0215] As shown in Figure 30, various level 1 feedstocks (also called feedstock chips, which are used to create other feedstock chips or SiPs) 3001 are picked and placed to create level 2 feedstocks 3002. Additionally, as shown in Figure 30, the level 2 feedstocks 3002 are picked and placed to create SiPs 3003.

[0216] Further explanation regarding FIG. 30 is provided below.

[0217] In one embodiment, a tool for pick-and-place assembly is utilized to assemble the die 106 to create the SiP3003, which may be one or more of the following sizes: 100 mm, 200 mm, 300 mm wafer, or 1st, 2nd, 3rd, ... 10th generation glass substrate. In one embodiment, the tool for pick-and-place assembly includes an inkjet for adhesive application. In one embodiment, the inkjet is mounted on a VPM (e.g., VPM703). In one embodiment, the tool includes a plasma head for substrate cleaning and / or plasma activation. In one embodiment, the plasma head is mounted on a VPM (e.g., VPM703).

[0218] In one embodiment, one or more of the feedstock chips (e.g., feedstock chip 3001) selected from a defined set of feedstock types are used to assemble SiPs 3003 similar in one or more selected measures (chip power consumption, performance, area, etc.) into a monolithically fabricated SoC (system on chip). For example, a SiP with a size of 10 mm×10 mm can be assembled using three types of feedstock chips (types A, B, and C) each with a size of 100 μm. In one embodiment, the same feedstock chips (e.g., types A, B, and C) can be used to assemble SiPs with different functions and designs. In one embodiment, a first level feedstock chip 3001 is used to assemble a second level feedstock chip 3002. For example, three types of first level feedstock chips 3001A, B, C (each of which has a size of 100 μm) are used to make six second level feedstock chips 3002. In one embodiment, second level feedstock chips 3002 are used to create third level feedstock chips, and so on. In one embodiment, the first level feedstock chips 3001 are all the same size. In one embodiment, assembly of the SiP 3003 with the feedstock chips (e.g., second level feedstock chips 3002) is performed using a pick-and-place method such as that described above.

[0219]

[0046] Reference is now made to Figure 31, which is a flowchart of a method 3100 for fabricating a SiP, according to an embodiment of the present disclosure. Figures 32A-32F show cross-sectional views for fabricating a SiP using the steps described in Figure 31, according to an embodiment of the present disclosure.

[0220] 31 in conjunction with FIGS. 32A-32F, in step 3101, transfer wafer 2 104″ is attached to die 106 (facing up) of transfer wafer 1 104′ via adhesive 3201, as shown in FIGS. 32A-32B.

[0221] FIG. 32A shows that die 106 (facing up) is attached to transfer wafer 1 104 ′ via a light switchable adhesive (LSA) 206 .

[0222] A second transfer wafer (Transfer Wafer 2 104") is then attached to the dies 106 of Transfer Wafer 1 104' using adhesive 3201, as shown in FIG. 32B.

[0223] In step 3102, the photoswitchable adhesive 206 is removed, such as by using ultraviolet (UV) light, as shown in FIG. 32C.

[0224] In step 3103, as shown in FIG. 32D, a second transfer wafer (transfer wafer 2 104") with die 106 is bonded to product wafer 1604, such as via direct bonding as discussed herein.

[0225] In step 3104, transfer wafer 2 104'' is removed, leaving die 106 on product wafer 1604, as shown in Figure 32E.

[0226] In step 3105, metal wiring 3202 is constructed on die 106 using standard semiconductor processing to form SiP 3003, as shown in FIG. 32F.

[0227]

[00136] Reference is now made to Fig. 33, which is an alternative method for fabricating a SiP, according to an embodiment of the present disclosure. Figs. 34A-34D show cross-sectional views for fabricating a SiP using the steps described in Fig. 33, according to an embodiment of the present disclosure.

[0228] Referring to Figure 33 along with Figures 34A-34D, in step 3301, as shown in Figures 34A-34B, transfer wafer 1 104' is flipped upside down (including die 106 attached to transfer wafer 1 104' via LSA 206) and bonded to product wafer 1604, such as via direct bonding as discussed herein.

[0229] FIG. 34A shows that die 106 (facing down) is attached to transfer wafer 1 104 ′ via a light switchable adhesive (LSA) 206 .

[0230] Figure 34B illustrates flipping transfer wafer 1 104' upside down, which is bonded to product wafer 1604, such as via direct bonding as discussed herein, with die 106 now facing up, as further shown in Figure 34B.

[0231] In step 3302, transfer wafer 1 104' is removed along with LSA 206, as shown in Figure 34C.

[0232] In step 3303, metal wiring 3202 is constructed on die 106 using standard semiconductor processing to form SiP 3003, as shown in FIG. 34D.

[0233] A more detailed discussion of Figures 31, 32A-32F, 33, and 34A-34D is provided below.

[0234] In one embodiment, the die 106 is picked and placed on the transfer wafer 104' ("transfer wafer 1"). In one embodiment, the die 106 includes alignment marks on the front or back side, for example, made using sub-micrometer plasma dicing or sub-micrometer MACE, or includes etched marks on the back side of the die aligned to the front side. In one embodiment, the marks are moire type, box-in-box type, etc. In one embodiment, the transfer wafer 1 104' is transparent. In one embodiment, the transfer wafer 1 104' includes a set of alignment marks that are complementary to the die alignment marks. In one embodiment, there is a photoswitchable adhesive (e.g., adhesive 206) between the die 106 and the transfer wafer 104'. In one embodiment, the LSA 206 (photoswitchable adhesive) is used to precisely align the die 106 to the transfer wafer 1 104' along with complementary die and wafer marks. In one embodiment, if the die 106 is facing down on transfer wafer 1 104′, a bonding step is performed in a wafer-to-wafer manner from transfer wafer 1 104′ to product 1604 to product substrate 1604. If the die 106 on transfer wafer 1 104′ is facing up, the die 106 can be transferred to another transfer wafer 104″ (“Transfer Wafer 2”). A bonding step is then performed from transfer wafer 2 104″ to product 1604 in a wafer-to-wafer manner to product substrate 1604. In one embodiment, the bonding is one or more of the following types: eutectic bonding, thermo-compression bonding, direct bonding, hybrid bonding, anodic bonding, fusion bonding, and bonding using a thin layer of applied adhesive. In one embodiment, product wafer 1604 has a nanopillar array. In one embodiment, the nanopillar array is sparse (e.g., 1% to 4% of the substrate surface area) so that bonding occurs at sparse locations, reducing the probability of particle hot spots. In one embodiment, metal wiring between assembled dies 106 on product wafer 1604 is made using conventional semiconductor fabrication processes (metal deposition, dielectric deposition, planarization, etching, lithography, etc.).

[0235] In one embodiment, precision die thinning is performed on a die 106 facing down (metal structures facing down and bulk silicon facing up) on a carrier wafer 202 (e.g., a transparent carrier wafer or a glass carrier wafer), an intermediate wafer (e.g., a transfer wafer 104), a tape frame 301, a source wafer 105, a product wafer 1604, etc.

[0236] In one embodiment, precision die thinning (PDT) is performed using methods utilizing adaptively ink-jetted resist drops, such as those described in U.S. Patent No. 6,233,636; ...

[0237] In one embodiment, PDT enables die bonding and heterogeneous integration applications where a die is to be assembled on top of two or more pre-existing dies (on a production wafer, a reconstructed wafer, etc.) and spans the two or more dies (each of which may have a unique thickness). PDT reduces the thickness variation of the pre-existing dies to the extent that the top spanning die can make high quality contact with the pre-existing dies.

[0238] In one embodiment, PDT enables die-on-die stacking where low variation in thickness of bonded die is required for circuit performance reasons (e.g., for improved timing.) For example, lower thickness variation can allow for less variation in through silicon via (TSV) height, improving signal propagation time variation between products (e.g., system-in-package).

[0239]

[00136] Referring now to Figure 35, Figure 35 is a flowchart of a method 3500 for performing heterogeneous integration, according to an embodiment of the present disclosure. Figures 36A-36D show cross-sectional views for performing heterogeneous integration using the steps described in Figure 35, according to an embodiment of the present disclosure.

[0240] 35 in conjunction with FIGS. 36A-36D, in step 3501, fine alignment of the die 106 on a wafer 3601 (eg, transfer wafer 104, intermediate wafer) is performed as shown in FIGS. 36A-36B.

[0241] Figure 36A shows the die 106 (facing down) roughly aligned on a wafer 3601 (e.g., transfer wafer 104, intermediate wafer). As further shown in Figure 36A, the die 106 is attached to the wafer 3601 via an LSA 206 or another type of adhesive.

[0242] In one embodiment, the structure shown in FIG. 36A is obtained from a die 106 from a source wafer 105 on a tape frame 301. The die 106 is face up, optionally plasma activated, and optionally spin coated with a thin film of water. In one embodiment, die flipping and coarse placement is performed by a chip shooter with high throughput (e.g., 30000 dies per hour). Alternatively, the tape frame 301 is mounted upside down and the die 106 is picked up using a pick and place tool with the VPM 703, transferred to the short stroke stage array 1703, and finally placed on the transfer wafer 104.

[0243] In one embodiment, fine alignment of the dies 106 on the wafer 3601 is performed using LSA alignment to achieve sub-10 nm, sub-25 nm, sub-50 nm, sub-100 nm, or sub-200 nm assembly accuracy.

[0244] As shown in FIG. 36B, the die 106 is now precisely aligned as compared to the positioning of the die 106 as shown in FIG. 36A.

[0245] In step 3502, the gaps between the dies are filled and the precisely aligned dies 106 are bonded to the product wafer 1604, as shown in Figure 36C.

[0246] In one embodiment, such bonding is performed using direct bonding as discussed herein, hi one embodiment, direct bonding is performed using a standard wafer-to-wafer fusion bonder.

[0247] Note that PDT makes step 3502 possible because, without PDT, thickness variations in adjacent dies 106 could be as much as 5 μm, which would likely prevent wafer-to-wafer fusion bonding near the die boundaries.

[0248] In step 3503, as shown in FIG. 36D, the wafer 3601 (eg, transfer wafer 104, intermediate wafer) and the LSA 206 are removed.

[0249] In step 3504, metal wiring 3601 is constructed on the die 106 using standard semiconductor processing to form a system-in-package 3003, as shown in FIG. 36D.

[0250] Details regarding the heterogeneous integration process according to one embodiment of the present disclosure are shown in FIG.

[0251] 38A-B, which illustrate a wafer-to-wafer bonding method according to one embodiment of the present disclosure.

[0252] As shown in Figure 38A, Figure 38A shows the die 106 on the tape frame 301, where the tape frame 301 is mounted upside down. Additionally, as shown in Figure 38A, a portion of the die 106 is elevated, such as shown by element 3801.

[0253] In one embodiment, such lifted dies are placed on a die chuck (wafer-scale die chuck) 3802. In one embodiment, all or a portion (e.g., half, quarter, eighth, etc.) of the dies 106 from the tape frame 301 are picked and placed on the die chuck 3802 at a time. In one embodiment, the lifted dies are distributed on the die chuck 3802 in a checkerboard manner. In one embodiment, the die chuck 3802 has individually actuable chucking areas to pick out only known good dies.

[0254] In one embodiment, the die chuck 3802 is mounted on a stage that, after lifting a known good die from the tape frame 301, moves under the short-stroke stage array 1703 and transfers all the lifted dies to the short-stroke stage 1703, as shown in FIG.

[0255] 38B shows a nano-precision short-stroke stage 1703 (integral with the chuck) permanently or semi-permanently mounted to a thermo-mechanically stable frame (short-stroke stage frame) 3803. In embodiments where the short-stroke stage 1703 is semi-permanently mounted to the frame 3803, a variable pitch mechanism is utilized to rearrange the position of the short-stroke stage 1703.

[0256] Additionally, in one embodiment, as shown in FIG. 38B, product wafer 1604 includes already-existing layers of circuitry on die 3804 (eg, DRAM logic, SRAM, flash memory, imaging circuitry, etc.).

[0257] In one embodiment, the lifted die 106 is bonded to a product wafer 1604. In one embodiment, the bonding is performed in a submerged manner to achieve sub-10 nm, sub-25 nm, sub-50 nm, sub-00 nm, sub-200 nm, and sub-500 nm overlay accuracy. Such methods are discussed herein.

[0258] In one embodiment, in a multi-stack memory application (eg, high bandwidth memory (HBM)), the sizes of the dies 106, 3804 bonded together are substantially the same.

[0259] 39A-B, which illustrate an alternative wafer-to-wafer bonding method according to one embodiment of the present disclosure.

[0260] As shown in FIG. 39A, FIG. 39A shows the die 106 on the tape frame 301, which is normally mounted with the die 106 facing up.

[0261] In one embodiment, the short stroke stage array 1703 lifts the die 106 directly from the tape frame 301, as shown in FIG. 39B.

[0262] 39B shows a nano-precision short-stroke stage 1703 (integral with the chuck) permanently or semi-permanently mounted to a thermo-mechanically stable frame (short-stroke stage frame) 3803. In embodiments where the short-stroke stage 1703 is semi-permanently mounted to the frame 3803, a variable pitch mechanism is utilized to rearrange the position of the short-stroke stage 1703.

[0263] Additionally, in one embodiment, as shown in FIG. 39B, product wafer 1604 includes already-existing layers of circuitry on die 3804 (eg, DRAM logic, SRAM, flash memory, imaging circuitry, etc.).

[0264] In one embodiment, the lifted die 106 is bonded to a product wafer 1604. In one embodiment, the bonding is performed in a submerged manner to achieve sub-10 nm, sub-25 nm, sub-50 nm, sub-00 nm, sub-200 nm, and sub-500 nm overlay accuracy. Such methods are discussed herein.

[0265] In one embodiment, in a multi-stack memory application (eg, high bandwidth memory (HBM)), the sizes of the dies 106, 3804 bonded together are substantially the same.

[0266] 38A-B and 39A-B, in one embodiment, the types of bonding performed include fusion bonding, hybrid bonding, bump bonding, anodic bonding, etc. In one embodiment, the bonding utilizes a fluid such as water, LSA, or other adhesive to improve the overlay accuracy of the bond as described above. The short stroke stage 1703 is based on one or more of the actuation principles such as piezoelectric actuation, electromagnetic actuation (such as voice coil), thermal actuation, etc.

[0267] Reference is now made to Figures 40A-40C, which show a nano / micro patterned support wafer according to one embodiment of the present disclosure.

[0268] Figure 40A shows a top view of nano / micro patterned support wafer 4001. A close-up of the top view of nano / micro patterned support wafer 4001 is shown in Figure 40B.

[0269] As shown in Figure 40B, micro / nano fabricated pins 4002 are positioned on a supporting substrate 4003. Furthermore, as shown in Figure 40B, the illustrated arrangement of pins 4002 (see element 4004) provides mechanical stiffness in both the x and y directions.

[0270] A cross section at AA (see FIG. 40B) is shown in FIG. 40C. Specifically, FIG. 40C shows interface 4004 between die 106 and support substrate 4003. In one embodiment, interface 4004 is a fusion bonded interface (between two oxide surfaces) or an adhesive bonded interface.

[0271] 40C shows a particle 4005 on the pin 4002 that has been distorted by the concentrated load. In addition, FIG. 40C shows an exemplary particle 4006 between the support wafer pins 4002.

[0272] In one embodiment, the pins 4002 are optimized to satisfy the following constraints: (1) ability to support the die in the x, y, and z directions while also being able to handle thermo-mechanical loads during die processing such as polishing, chemical-mechanical polishing, grinding, dicing, etching, lithography, material deposition, coating, etc.; (2) individual pins can distort / bend due to concentrated loads, for example, when particles are present between the pins and the die; and (3) a sufficiently sparse distribution of pins such that most particles at the die-wafer interface rest in the gaps between the pins, such that the contact area between the pins and the die may be 0.1%, 0.5%, 1%, 2%, or 5% of the die area.

[0273] A table showing exemplary measurements of pin 4002 (W corresponds to width, L corresponds to length, H corresponds to height, P1 corresponds to the distance shown in FIG. 40B, and P2 corresponds to the distance shown in FIG. 40B) is provided below.

[0274] [Table 1]

[0275] In one embodiment, a nano- and / or micro-patterned support wafer 4001 is used as a substitute for the temporary wafer and / or carrier wafer 202 and / or transfer wafer 104 and / or product wafer 1604 discussed herein. In one embodiment, the pins 4002 are designed to warp and / or bend when particles (e.g., particle 4005) are present at the interface 4004 between the pins 4002 and the top die 106. Design optimization techniques, such as constrained optimization based on genetic algorithms (or other heuristic algorithms), may be used to arrive at an optimal shape for the pins. Further details regarding the design of such pins may be found in "Constrained Optimization of Pins," a paper by John Wiley & Sons, Inc., incorporated herein by reference in its entirety. In one embodiment, the wafer 4001 is made of one or more of silicon, silicon dioxide, aluminum oxide, sapphire, metal, metal oxide, polymer, PTFE, fluoropolymer, carbon, boron, and the like.

[0276] In one embodiment, the wafer 4001 is fabricated using patterning techniques such as particle lithography (PL), nanoimprint lithography (NIL), and deep etching techniques such as metal-assisted chemical etching, deep reactive ion etching (DRIE), reactive ion etching (RIE), and crystalline etching.

[0277] In one embodiment, the wafer 4001 is attached to the die (e.g., die 106) using one or more of the following methods: fusion bonding (oxide-oxide), hybrid bonding (oxide-oxide, metal-metal), direct bonding, anodic bonding, and covalent bonding. In embodiments where direct / fusion / hybrid bonding is utilized, a thin layer of water may be utilized at the interface between the die 106 and the support wafer pins 4002. In one embodiment, an adhesive is applied to the surface of the die 106 attached to the support wafer 4001 (using inkjetting, spin coating, dip coating, slot-die coating, etc.) or to the support wafer 4001 itself. In one embodiment, an adhesive is applied onto the support wafer pins 4002 using dip coating, vapor phase condensation, etc. In one embodiment, an adhesive is applied to the surface of the die 106 attached to the support wafer 4001 or to the support wafer 4001 itself. In one embodiment, an adhesive is applied onto the support wafer pins 4002 using dip coating, vapor phase condensation, etc. In one embodiment, an adhesive is applied to the surface of the die 106 attached to the support wafer 4001 or to the support wafer 4001 itself. In one embodiment, an adhesive is applied onto the support wafer pins 4002 using dip coating, inkjetting, etc.

[0278] In one embodiment, the support wafer 4001 is separated from the die it supported using (a) HF, gas phase HF (if direct / melt / hybrid bonding was the method of attachment), (b) thermal sliding (if a suitable adhesive with low glass transition temperature is utilized), and / or (c) UV removal (if a UV removal material such as a photoswitchable adhesive is utilized). If a gas phase based separation method is utilized (e.g., using gas phase HF), the sparse distribution of the pins allows for faster separation compared to the absence of pins (plain support wafer). In addition, the width (W) and / or length (L) as shown in the table above may be small (e.g., 50 nm, 100 nm, 200 nm) to allow for faster separation (with a nominal etch rate of about 60 nm / min) of the pins 4002 from the die 106 to which they are bonded.

[0279] Referring now to FIG. 41, FIG. 41 is a flow chart of a method 4100 for preparing a reconstituted wafer for face to back (F2B) bonding according to an embodiment of the present disclosure. As used herein, a reconstituted wafer refers to a new wafer on which a die is placed using a pick and place system. FIG. 42A-FIG. 42N show cross-sectional views for preparing a reconstituted wafer for face to back (F2B) bonding using the steps described in FIG. 41 according to an embodiment of the present disclosure. The source wafer 105 is described using FIG. 42A, FIG. 42C, FIG. 42E, FIG. 42G, FIG. 42H, FIG. 42I, FIG. 42K, FIG. 42M, and FIG. 42N. The buffer wafer 4201 is described using FIG. 42B, FIG. 42D, FIG. 42F, FIG. 42H, FIG. 42J, and FIG. 42L.

[0280] Referring to FIG. 41 together with FIG. 42A-42N, in step 4101, as shown in FIG. 42A, an adhesive 4202 (e.g., LSA, resist, NIL resist, etc.) is applied (e.g., spin coated, ink jetted, etc.) to a wafer 4203 (e.g., a transfer wafer 104, a carrier wafer 202).

[0281] Additionally, as shown in FIG. 42A, metal layer 4204 faces toward wafer 4202.

[0282] In addition, as shown in Figure 42C, source wafer 105 includes plasma diced bad die 4205. The remaining die are good die 4206. The die including bad die 4205 and good die 4206 may be collectively referred to herein as die 4208. Region 4207 is an undiced kerf region.

[0283] In step 4102, plasma dicing of the dies 4208 in the buffer wafer 4201 is performed, as shown in Figures 42B and 42D.

[0284] 42B, buffer wafer 4201 includes dies 4208 on wafer 4209 (e.g., transfer wafer 104, carrier wafer 202), which includes bad dies 4205 as well as good dies 4206. Additionally, FIG. 42B shows that the average thickness of dies 4208 is slightly larger (e.g., 500 nm, 1 μm, 2 μm, etc.) compared to dies 4208 on wafer 4203.

[0285] Further, FIG. 42D shows plasma dicing of die 4208 in buffer wafer 4201.

[0286] In addition, FIGS. 42B and 42D show a die 4210 for replacing a defective die 4205 on wafer 4203.

[0287] In step 4103, precision die thinning is performed on dies 4208 of buffer wafer 4201 to match the known thickness of bad dies 4205 on wafer 4203, as shown in Figures 42E-F. In one embodiment, such precision die thinning is performed with sub-50 nm root mean square error.

[0288] For example, as shown in Figures 42E-42F, die 4208 on buffer wafer 4201, such as die 4210, is thinned to match the known thickness of bad die 4205 on wafer 4203.

[0289] In step 4104, as shown in Figure 42G, the bad die 4205 on the wafer 4203 is removed using a pick and place tool that utilizes liquefied adhesive 4211 (e.g., UV irradiation from the chuck side). At this moment, there is no change on the buffer 4201, as shown in Figure 42H.

[0290] In step 4105, as shown in Figures 42J and 42L, a precisely thinned known good die, such as die 4210, on buffer wafer 4201 is picked up using a pick and place tool that utilizes liquefied adhesive 4211.

[0291] In step 4106, a UV-curable adhesive is applied to the location where the bad die 4205 was elevated on the wafer 4203, as shown in FIG. 42I.

[0292] In step 4107, a precisely thinned known good die, such as die 4210, is adhesively bonded to wafer 4203 where bad die 4205 was previously located, as shown in FIG. 42K to form a reconstructed wafer.

[0293] In step 4108, precision alignment (e.g., using a liquid-compatible alignment architecture) is performed on the reconstructed wafer 4213, as shown in Figure 42M. As shown in Figure 42M, a good die 4210 that replaced a bad die 4205 on wafer 4203 is aligned with respect to its neighbors.

[0294] In one embodiment, alignment marks on the corners of adjacent dies are used to measure the alignment of the new good die with respect to the wafer lattice. In such an embodiment, alignment marks on the wafer 4203 (e.g., carrier wafer 202) are not required.

[0295] Then, in step 4109, material 4212 is used to fill the gaps between dies 4202 on wafer 4203, as shown in Figure 42N. Planarization (e.g., chemical mechanical polishing) after filling the gaps between dies 4208 may also be performed.

[0296] Reference is now made to Fig. 43, which is a flow chart of an alternative method 4300 for preparing a reconstituted wafer for face to back (F2B) bonding, according to an embodiment of the present disclosure. Figs. 44A-44F show cross-sectional views for preparing a reconstituted wafer for face to back (F2B) bonding using the steps described in Fig. 43, according to an embodiment of the present disclosure.

[0297] Referring to Figure 43 along with Figures 44A-44F, in step 4301, as shown in Figures 44A and 44B, the defective die 4205 is removed using a precision pick-and-place tool (enabled by nanowire temporary fusion bonding / debonding) and replaced with a thickness-matched die 4210 from buffer wafer 4201.

[0298] 44A shows a top view of the source wafer 105 from which the bad die 4205 has been plasma diced. The remaining dies on the source wafer 105 are good dies 4206.

[0299] Referring now to Figure 44C, Figure 44C shows a cross-sectional view of AA in Figure 44A. As shown in Figure 44C, wafer 4203 (e.g., a silicon carrier wafer) includes nanowires 4401 that are temporarily fusion bonded to wafer 4203. In one embodiment, the regions near the edge of each die 4208 (good die 4206, bad die 4205) are free of nanowires. In such an embodiment, bad die, such as bad die 4205, are easier to remove.

[0300] Referring now to Figure 44D, Figure 44D shows a cross-sectional view of AA in Figure 44B. As shown in Figure 44D, water 4402 is inkjetted in separate areas under the replaced die (under the thickness-matched die 4210 that replaced the defective die 4205) for liquid alignment and fast evaporation. In one embodiment, water 4402 is confined within the island using capillary confinement or using a dense wall of nanowires near the periphery of the island (discussed further below).

[0301] In step 4302, as shown in Figure 44E, precision alignment is performed on the reconstructed wafer 4213. For example, the precision alignment is performed using a liquid-compatible alignment architecture.

[0302] In step 4303, die gap filling and planarization is performed on the reconstituted wafer 4213, as shown in FIG. 44F. For example, material 4212 is filled between the gaps between the dies 4208. In one embodiment, planarization, such as polishing mechanical features, is utilized to finish the reconstituted wafer 4213.

[0303] Further discussion regarding Figures 41, 42A-42N, 43, and 44A-44F is provided below.

[0304] A starting point is assumed of one or more types of die 4208 present on one or more source substrates 105, which may be a tape film or glass carrier wafer, to which the die 4208 is attached using either adhesive or direct bonding (e.g., fusion bonding, hybrid bonding, covalent bonding, etc.), or some other type of die transfer mechanism such as gel pack, waffle pack, etc. In one embodiment, the die 4208 are arranged on the source substrate 105 at a SiP pitch (where SiP pitch is the pitch along one or more of the x-axis and y-axis or a combination thereof of the system in package or SiP on the product substrate (e.g., product substrate 1604) prior to dicing of the product substrate into individual SiPs). If the die 4208 are arranged at a pitch different from the SiP pitch (SPPx, SPPy) along either the x-axis or y-axis, a pick and place tool may be used to lift the die 4208 from the source substrate 105 and attach the die 4208 to an intermediate source substrate at the SiP pitch. In one embodiment, the pick and place tool is a high throughput system (1000 chips per hour (cph) or greater, 2000 cph or greater, 5000 cph or greater, 10000 cph or greater, 20000 cph or greater, 50000 cph or greater, or 100000 cph or greater). In one embodiment, the pick and place tool is a low precision system (e.g., average +3 sigma overlay / alignment accuracy of 100 nm or greater, 250 nm or greater, 500 nm or greater, 1 μm or greater, 3 μm or greater). In one embodiment, the source substrate (e.g., source substrate 105) and intermediate source substrate are silicon wafers, glass wafers, silicon-on-insulator (SOI) wafers, sapphire wafers, silicon-on-sapphire (SOS) wafers, glass-on-silicon wafers, substrates with embedded sacrificial layers, polymer films, polymer plates, glass plates, tapes, tapes with frames, tape films, backgrind tapes, backgrind films, transfer wafers, carrier wafers, product wafers, circular substrates, square substrates, rectangular substrates with diameters of 50 mm, 100 mm, 150 mm, 200 mm, 300 mm, or 450 mm, and the like.The orientation of the die 4208 on the source substrate (e.g., source substrate 105) can be circuit side facing away from the source substrate or circuit side facing towards the source substrate (die back side facing away from the source substrate). The transfer of the die from the source substrate (e.g., source substrate 105) to the intermediate source substrate can be performed without flipping the die orientation. In another embodiment, the die orientation is flipped before placing the die on the intermediate source substrate by the pick and place tool.

[0305] The following description is based on Figure 41 and Figures 42A-42N. In one embodiment, the die 4208 is picked and placed onto the wafer 4203 (e.g., transfer / carrier substrate). The die 4208 can be placed in a die-to-die fashion using a pick-and-place tool, or alternatively, in a multi-die fashion, or alternatively, as part of an entire undiced source substrate (e.g., using a wafer-to-wafer bonder). In one embodiment, the die 4208 is placed either circuit side facing towards the wafer 4203 (e.g., transfer / carrier substrate) or circuit side facing away from the wafer 4203 (e.g., transfer / carrier substrate). In one embodiment, the die 4208 is attached to the wafer 4203 (e.g., transfer / carrier substrate) using a fluid, liquid, adhesive, liquid adhesive, photoswitchable adhesive (LSA), high temperature LSA (e.g., melting point of 150° C., 200° C., 300° C., or 400° C. or higher, optionally with non-organic compounds to achieve said high melting point), photoresist, nanoimprint resist, UV curable adhesive, gel adhesive, solid adhesive, spin coated liquid, ink jetted liquid, drop cast liquid, vapor phase condensed liquid, sub 10 um thick liquid, sub 5 um thick liquid, sub 2 um thick liquid, sub 1 um thick liquid, sub 500 nm thick liquid, sub 200 nm thick liquid, sub 100 nm thick liquid, sub 50 nm thick liquid, sub 20 nm thick liquid, sub 10 nm thick liquid, direct bonding, fusion bonding, hybrid bonding, mass reflow, eutectic bonding, anodic bonding, covalent bonding, thermo-compression bonding, or the like. In one embodiment, water is applied to wafer 4203 (eg, transfer / carrier substrate) prior to die attachment using spin coating, ink jetting, drop casting, vapor phase condensation, or the like.In one embodiment, the wafer 4203 (e.g., transfer / carrier substrate) comprises one or more of a silicon wafer, a glass wafer, a silicon-on-insulator (SOI) wafer, a sapphire wafer, a silicon-on-sapphire (SOS) wafer, a glass-on-silicon wafer, a substrate with an embedded sacrificial layer, a polymer film, a polymer plate, a glass plate, a tape, a tape frame, a tape film, a backgrind tape, a backgrind film, a transfer wafer, a carrier wafer, a product wafer, a circular substrate, a square substrate, and a rectangular substrate with a diameter of 50 mm, 100 mm, 150 mm, 200 mm, 300 mm, or 450 mm. In one embodiment, the wafer 4203 (e.g., transfer / carrier substrate) comprises nanostructures. In one embodiment, once attached to wafer 4203 (e.g., transfer / carrier substrate), any undiced known bad die (e.g., die 4205) may be diced using dicing methods such as plasma dicing, chemical dicing, and MACE-based dicing, where laser ablation, photolithography, mechanical dicing, nanoimprint lithography, DUV lithography, 193 nm immersion lithography, EUV lithography, and / or 365 nm lithography are used to pattern resist layers for plasma / chemical / MACE-based dicing methods. The known bad die (e.g., die 4205) may then be removed using a pick-and-place tool and replaced with a known good die (e.g., die 4210) from buffer wafer 4201. Pick-and-place may be performed in a die-to-die fashion or in a multiple die-to-die fashion.In one embodiment, removal of the faulty die is enabled by liquefying the photoswitchable adhesive 4211 (e.g., using UV light incident from the underside of a transparent transfer / carrier substrate using an optionally positionable light source such as an LED array, a fiber light source, a scannable light source, etc.), or alternatively, if the faulty die is melt-bonded to the wafer 4203 (e.g., a transfer / carrier substrate), by applying a lifting force stronger than the adhesive force of the melt bond (wherein in one embodiment no annealing is performed after said melt bonding of the die to the wafer 4203 (e.g., a transfer / carrier substrate), or in another embodiment an annealing step is performed to a suitable low temperature such as sub-100°C, sub-200°C, or sub-300°C). In one embodiment, a good die (e.g., die 4210) from buffer wafer 4201 that replaces a bad die (e.g., die 4205) is precisely thinned on the buffer wafer 4201 itself to match the thickness of the adjacent die, or alternatively is first picked and placed on wafer 4203 (e.g., transfer / carrier substrate) and then thinned to the matching thickness. In one embodiment, the thickness matching is performed in one or more of the following ways: such that the average thickness of the replaced die is matched to the average thickness of the adjacent dies; such that the average thickness of the replaced die is matched to the average thickness at the edge shared with the adjacent dies; such that the thickness at the shared edge is matched such that the step change in thickness when traversing from the adjacent die to the good die being replaced is less than one of 1 μm, 500 nm, 200 nm, 100 nm, 50 nm, 20 nm, or 10 nm. In one embodiment, the good die (e.g., die 4210) that replaces the bad die (e.g., die 4205) may then be aligned with respect to one or more of the neighboring dies or wafer 4203 (e.g., transfer / carrier substrate). In one embodiment, the above dies (known good / bad dies) include alignment marks on the front or back side, for example, created using sub-micrometer plasma dicing, or sub-micrometer MACE, or include etched marks on the back side of the die that are aligned to the front side.In one embodiment, the marks are of moire type, box-in-box type, etc. In one embodiment, the wafer 4203 (e.g., transfer / carrier substrate) is transparent. In one embodiment, the wafer 4203 includes a set of alignment marks that are complementary to the diamond alignment marks. Subsequently, gap filling, planarization, and bonding (e.g., from the transfer / carrier substrate to the product substrate 1604 in a wafer-to-wafer manner) steps are performed. In one embodiment, the bonding is one or more of the following types: eutectic bonding, thermocompression bonding, direct bonding, hybrid bonding, anodic bonding, fusion bonding, covalent bonding, bonding using a thin layer of applied adhesive, etc.

[0306] In one embodiment, one or more of the source substrate 105, intermediate substrate, transfer substrate 104, carrier substrate 202, product substrate 1604, die, and field are comprised of nanostructures. In one embodiment, the nanostructures are one or more of nanowires, nanopillars, microwires, and micropillars. In one embodiment, whenever an island is found, there are no nanostructures, and the island is defined to comprise one or more of a through silicon via (TSV), a metal pad, and an oxide spacer (created around the metal pad). In one embodiment, the nanostructure comprises an island (e.g., an exemplary nanostructure includes an oxide spacer around a metal pad created by an oxide etch step, optionally the oxide etch step being a high aspect ratio etch). In one embodiment, the nanostructure is fabricated from one or more of materials such as silicon, polysilicon, amorphous silicon, silicon oxide, silicon nitride, SiCN, carbon, polymers, ceramics, aluminum oxide, and metals. In one embodiment, the exclusion zone resulting from the particles resting on the bonding interface is at least two times smaller than in a bonding process using bonding surfaces without nanostructures. The presence of nanostructures on one or more of the two surfaces being bonded can be used to reduce the exclusion zone created by particles at the interface compared to the default case in which no nanostructures are present, or more generally to increase the yield during the bonding process. The exclusion zone can be reduced by 50%, 80%, 90%, or 99%, or even eliminated completely. In one embodiment, the mode of exclusion zone reduction is one or more of bending of the nanostructure, distortion of the nanostructure (when the load on the nanostructure exceeds a certain threshold), collapse of the nanostructure, fracture of the nanostructure, permanent deformation of the nanostructure, etc. The presence of the nanostructure can reduce the contact area between the bond to less than 99%, 95%, 90%, 70%, 50%, 25%, 10%, 5%, 2%, or 1% of the area of ​​the first or second bonded structure.In one embodiment, the nanostructures are designed to keep the contact area small enough to reduce particle events (i.e., a particle resting on one of the nanostructures and bending / warping / disintegrating / failure of the nanostructure), while optionally keeping the area large enough to allow / maximize axial conduction of heat through the bond interface, and also, optionally, allowing enough lateral space to allow lateral transport of cooling fluid (air, water, coolant, etc.). In one embodiment, the nanostructures are fabricated using reactive ion etching (RIE), MACE, Ru MACE (with a patterning process that may be photolithography, nanoimprint lithography (NIL), etc.). In one embodiment, the nanostructures are fabricated on the backside of the die. Alternatively, in one embodiment, the nanostructures are present on the frontside of the die (e.g., on polysilicon). Alternatively, the nanostructures are present only on the bulk substrate to which the die is attached. In one embodiment, the nanostructures, such as nanowires, are non-straight (or offset or twisted) to ameliorate the tendency of non-sparse nanostructures to bend / distort / collapse, hi one embodiment, such nanostructures are fabricated using a MACE-based process.

[0307] In one embodiment, during bonding of two surfaces, at least one of which has the above-mentioned nanostructures, a liquid (e.g., water, isopropyl alcohol, other aqueous solutions, gas-phase condensation, etc.) is applied to separate areas of one or both of the two surfaces. This may facilitate evaporation of said liquid during / after bonding through the gap between the separate areas. In one embodiment, the amount, size, or other application parameters of the water application may be such that at the beginning of bonding (to allow for a liquid alignment), it fills a height slightly greater than the nanostructures, and as bonding progresses, it falls below the height of the nanostructures.

[0308] In one embodiment, the nanostructures are released from the substrate to which they are bonded using one or more of the following methods: etching away the interfacial silicon oxide (using HF, gas phase HF, localized gas phase HF, etc.), or alternatively, simple peeling using vacuum suction (ideally performed prior to annealing or prior to high temperature annealing, e.g., using annealing temperatures above 200°C).

[0309] Consider the processes that may be used to create a substrate populated with two or more known good die (e.g., 2D layers), where the two or more die are bonded to the substrate using direct bonding, fusion bonding, and / or hybrid bonding techniques, and the average thickness of the two or more die is substantially the same (or matched in the manner previously described). A 2.5D device is defined as a device created using the above process with metallization on top of the optional 2D layer of the known good die, or alternatively, an interposer bonded on top of the 2D layer of the known good die. A 3D device is defined as a device created using the above process, where one or more layers of transistors are fabricated or integrated / bonded on top of the optional 2D layer of the known good die.

[0310] Further, in one embodiment, the replacement and alignment of the bad die with a good die is performed either in the same step (wherein the bonding head that picks and places the die is also precisely aligned with the die) or in two sets of steps (wherein a first set of one or more bonding heads picks and places the die inaccurately and a second set of one or more bonding heads precisely aligns the die).

[0311] In one embodiment, a dicing technique is used, such as plasma dicing, that allows for retention of the alignment marks in the die.

[0312] In one embodiment, alignment metrology of good dies from the buffer wafer 4201 to adjacent dies on a source wafer (e.g., source wafer 105) is performed using IR Moire metrology (similar to a technique used in nanoimprint lithography).

[0313] In one embodiment, diactuation with adhesive in liquid state is performed using a short stroke stage and / or stage actuation (using closed loop feedback from a metrology component such as a Moiré microscope).

[0314] In one embodiment, an alternative method for metrology is to pick up the entire reconstructed source wafers and bring them to a separately located metrology station, where the diamond alignment correction is performed in an open-loop fashion.

[0315] An alternative embodiment to performing precision die thinning (PDT) on buffer wafer 4201 is to lift the unthinned dies from buffer wafer 4201 and precisely thin them after they are placed on wafer 4203 (e.g., a transfer / carrier wafer).

[0316] In one embodiment, a reconstructed substrate for F2F W2W bonding is prepared by performing a wafer-scale transfer of a face-down reconstructed wafer (previously prepared) onto a second transfer / carrier substrate.

[0317] It should be noted that the adhesive (e.g., LSA) may not remain thermomechanically stable at the annealing temperature for fusion / hybrid bonding. After W2W bonding of the reconstructed wafer (e.g., reconstructed wafer 4213), the wafer 4203 (e.g., transfer / carrier wafer) and adhesive are immediately removed. Alternatively, the fusion / hybrid bonded wafer is partially annealed with the wafer 4203 (e.g., transfer / carrier wafer) attached in the presence of adhesive to a temperature at which the adhesive remains thermomechanically stable (e.g., about 100° C.), followed by removal of the LSA and wafer 4203 (e.g., transfer / carrier wafer) before the full anneal.

[0318] In an embodiment, one or more of the above processes are used to fabricate one or more of a semiconductor device, a system in package (SiP), a 2.5D integrated device, a 3D integrated device, a high bandwidth memory (HBM), logic on an SRAM device, a SRAM on a logic device, a DRAM on a logic device, logic on a DRAM device, logic on a memory device, a memory on a logic device, logic on an imaging array, an imaging array on a logic circuit, a face to face (F2F) integrated device (at least one bonded layer includes a first circuit layer and a second circuit layer, where the circuit sides of the two layers face each other), a face to back (F2B) integrated device (at least one bonded layer includes a first circuit layer and a second circuit layer, where the circuit side of one of the two layers faces the back or TSV side of the other of the two layers).

[0319] In one embodiment, the bonding in one or more of the above processes corresponds to one or more of fusion bonding (e.g., oxide-oxide), hybrid bonding (e.g., oxide-oxide, metal-metal), direct bonding, anodic bonding, covalent bonding, eutectic bonding, and adhesive bonding.

[0320] As a result of the above, the principles of the present invention provide a means for improving the precision of integrating separately manufactured components into a higher level assembly (System in Package (SiP)), i.e., the principles of the present invention provide a means for improving the precision of heterogeneous integration.

[0321] The description of various embodiments of the present invention is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements over the technology found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. [Explanation of symbols]

[0322] 100 Systems 101 Transfer substrate chuck 102 Supplier Board Chuck 103 XY Motion Stage 104 Transferring substrates, transferring wafers 105 Supplier substrate, supplier wafer 106 Die 107 Inkjet 108 Adhesive 109 Alignment Microscope 110 Adaptive multi-chip transfer system, transfer chuck, AMS 111 AMS Frame 112 Measurement Frame 113 Die Release Adhesive 114 Bad Die 201 Die stack 202 Carrier substrate, carrier wafer 203 Die thickening layer 204 Gel-curing adhesive, adhesive layer, gel-curing adhesive drop 205 Fully cured adhesive 206 Adhesive, photoswitchable adhesive, LSA 301 Tape Frame 401 Spin-Coated Layers 402 Elements 501 Height adjustment zone, recess 502 Adhesive Coating 503 Chip Shooter Glue 601 Carrier Board 602 Interface 603 Substrate chuck 604 Local Vacuum 605 Local Pressure 701 Circuit elements 702 Adhesive 703 Variable Pitch Mechanism, VPM 704 Optical and Imaging Assembly 705 Double Beam 706 Mirror Assembly 707 Visible Light Path 708 Thickness detection board 709 Moire Mark 710 Infrared light path 711 Die back side 801 IR Beam 901 Sealing layer, die sealing layer 902 Pin structure, pin 903 Pin 904 Compliant Pin 1001 Vacuum Mode 1002 Vacuum Mode 1101 Granite surface plate 1102 Gantry xy stage 1103 Wafer 1104 AMS 1105 AMS 1106 Stage 1201 Chucking module, CM assembly, CM 1202 Circuit elements 1203 Die top alignment mark 1204 Fluid 1205 Ray of light 1206 Supplementary Mark 1207 Die underside alignment mark 1301 Upper peripheral alignment marks 1302 Lower Periphery Alignment Marks 1303 Lower Primary Alignment Mark 1501 Die Group 1502 Board 1503 Photoswitchable adhesives, die adhesives 1504 Career 1505 Piezoelectric Manipulator 1506 Electromagnetic Actuator 1507 Magnetic Layer 1601 Substrate chuck, selective release chuck 1602 IR Measurement 1603 Air Cushion 1604 Product substrates, product wafers 1701 Die 1702 Die Thinning Module 1703 Short stroke stage, short stroke stage array 1704 MACE Catalyst 1705 Sealing layer 1706 Local Temperature Controller 1707 MACE Etchant 1708 Black Silicon 1709 Fri 1801 Particle Removal Module 1802 Probe 1803 Particles 1804 MACE Catalyst 1805 MACE Etchant 2001 Die, Board 2002 Substrate 2003 Back end metal layer 2004 front end 2005 Pillar, Metal Pillar 2006 Conformal oxide, coating 2008 Die, Board 2009 Particles 2201 Polysilicon 2401 Polysilicon 2402 Coating 2403 Mushroom structure 2501 Package Substrate 2502 Adhesive 2503 Hotspot 2504 Heat spreader layer 2505 Fluid Coolant 2506 Thermal interface layer, TIM layer, thermal interface material 2601 Pillar 2602 Elements 2603 Front end 2604 Back end metal layer 2901 Adhesive layer 2902 Interposer 3001 Feedstock Chip, SiP 3002 Feedstock, feedstock chips 3003 SiP, System in Package 3201 Adhesives 3202 Metal wiring 3601 Wafer, metal wiring 3801 elements 3802 Die Chuck 3803 Frame 3804 Die 4001 Support Wafer 4002 pin, support wafer pin 4003 Support substrate 4004 Elements, interfaces 4005 Particles 4006 Particles 4201 Buffer Wafer 4202 Adhesives, wafers, dies 4203 Wafer 4204 Metal layer 4205 Bad Die 4206 Good die 4207 area 4208 Die 4209 Wafer 4210 Die, good die 4212 Material 4213 Reconstructed Wafer 4401 Nanowires 4402 Water

Claims

1. 1. A method for increasing yield in a bonding process, comprising: Etching one or more of the first and second mating surfaces to create nanostructures in one or more of the first and second mating surfaces; and bonding the first bonding surface to the second bonding surface; The method, wherein the exclusion zone resulting from the particles resting at the bonded interface is at least two times smaller than the bond of two bonded surfaces without the nanostructures.

2. 2. The method of claim 1, wherein the presence of the nanostructures reduces a contact area in the bonding step to less than one of 50%, 25%, 10%, 5%, 2%, and 1% of an area of ​​the first bonding surface or the second bonding surface.

3. The method of claim 1 , wherein the bonding step comprises one of fusion bonding, hybrid bonding, direct bonding, anodic bonding, covalent bonding, and adhesive bonding.

4. The method of claim 1 , wherein the bonding step is used in face-to-face bonding or face-to-back bonding.

5. 10. The method of claim 1, wherein the bonding step is used for fabricating one or more of 2.5D devices, 3D devices, high bandwidth memories (HBM), logic on SRAM, SRAM on logic, DRAM on logic, logic on DRAM, logic on memory, memory on logic, logic on imaging arrays, and imaging arrays on logic.

6. The method of claim 1 , wherein the nanostructures are not present where there are one or more island structures.

7. 10. The method of claim 1, further comprising the step of peeling the bond between the first and second bonding surfaces, wherein hydrofluoric acid or vapor phase hydrofluoric acid is used to peel the bond between the first and second bonding surfaces.

8. The method of claim 1 , wherein the first and second bonding surfaces are peeled apart using a mechanical suction technique.

9. The method of claim 1 , further comprising the step of performing a liquid alignment during the bonding step.

10. The method of claim 1 , wherein the nanostructures are twisted to enhance their ability to reduce particle induced exclusion zones at the bond interface.

11. 1. A method for reducing the impact of particles on a yield of a bonding process, comprising: Etching one or more of the first and second bonding surfaces to create island structures; and bonding the first bonding surface to the second bonding surface; The method, wherein the exclusion zone resulting from the particles resting at the bonded interface is at least two times smaller than the bond of two bonded surfaces without the nanostructures.

12. The method of claim 11 further comprising the step of covering the recess created by the etching with a layer.

13. The method of claim 12 further comprising the step of rendering the layer porous using a porosifying method.

14. The method of claim 13 , wherein the layer comprises one or more of polysilicon and amorphous silicon.

15. 1. A method for fabricating a semiconductor device comprising two or more known good dice, comprising: bonding the two or more known good die adjacent to one another with metal pads facing away from the production substrate, the two or more known good die having substantially the same average thickness; and performing gap filling, planarization, and / or metallization between the dies after the bonding step to fabricate a semiconductor device.

16. 16. The method of claim 15, wherein the difference in average thickness of the two or more known good die is less than one of the following values: 1 μm, 500 nm, 200 nm, 100 nm, 50 nm, 20 nm, and 10 nm.

17. The method of claim 15 , wherein the bonding step comprises one of fusion bonding, hybrid bonding, direct bonding, anodic bonding, covalent bonding, eutectic bonding, and adhesive bonding.

18. The method of claim 15 , wherein the bonding step is used in face-to-face bonding or face-to-back bonding.

19. 20. The method of claim 15, further comprising performing one or more additional bonding processes for fabrication of one or more of a 2.5D device, a 3D device, a high bandwidth memory (HBM), logic on SRAM, SRAM on logic, DRAM on logic, logic on DRAM, logic on memory, memory on logic, logic on imaging array, and imaging array on logic.

20. 1. A method for producing a substrate populated with two or more known good dice, comprising: bonding the two or more known good die to the substrate using direct bonding, fusion bonding, or hybrid bonding; wherein the two or more known good die have substantially the same average thickness, and the substrate comprises nanostructures etched at a bonding interface.

21. 21. The method of claim 20, wherein the difference in average thickness of the two or more known good die is less than one of the following values: 1 μm, 500 nm, 200 nm, 100 nm, 50 nm, 20 nm, and 10 nm.

22. 1. A method for producing a substrate populated with two or more known good dice, comprising: bonding the two or more known good dies to the substrate using an adhesive, a UV curable adhesive, a photoswitchable adhesive, or a nanoimprint resist; wherein the two or more known good die have substantially the same average thickness.

23. 23. The method of claim 22, wherein the difference in average thickness of the two or more known good die is less than one of the following values: 1 μm, 500 nm, 200 nm, 100 nm, 50 nm, 20 nm, and 10 nm.

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