Method and apparatus for implementing address alterations between integrated circuits - Patents.com

Abstract

An example system includes a device (105) coupled to a data line (120), the device (105) configured to send a first command on the data line (120) including a first address, after sending the first command, read a first value on the data line (120) including data from a first target device (110) and a second target device (115), in response to reading the first value, send a second command on the data line (120) including the first address and data representing the first value, send a third command on the data line (120) including the first address, after sending the third command, read a second value on the data line (120) including data from the first target device (110) and the second target device (115), and in response to reading the second value, send a fourth command on the data line (120) including the first address.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE This description relates generally to inter-integrated circuit addressing, and more particularly to methods and apparatus for implementing inter-integrated circuit address configurations. [Background technology]

[0002] The Inter-Integrated Circuit (I2C) protocol is a serial communication protocol used to communicate between a target device and a primary device. A primary device can be coupled to multiple target devices through a single I2C bus. The primary device communicates to each target device by individually sending commands (e.g., read commands, write commands) that include the target device address. To implement I2C with multiple target devices on the same I2C bus, each target device has a different device address. Changing the device address requires a connection between each target device and the primary device in addition to being coupled to the I2C bus, which increases the number of pins required on the target device. Summary of the Invention

[0003] Regarding a method of I2C address resolution, an example system includes data lines and a device coupled to the data lines, the device configured to: send a first command on the data lines including a first address; after sending the first command, read a first value on the data lines including data from the first target device and the second target device; in response to reading the first value, send a second command on the data lines including the first address and data representing the first value; send a third command on the data lines including the first address; after sending the third command, read a second value on the data lines including data from the first target device and the second target device; in response to reading the second value, send a fourth command on the data lines including the first address; send a fifth command on the data lines including the second address; and after sending the fifth command, read a third value on the data lines including only data from the first target device. [Brief description of the drawings]

[0004] [Figure 1] FIG. 1 is a block diagram of an example system configured to implement I2C communication between an example primary device, an example first target device, and a second target device to modify device addresses of the target devices.

[0005] [Figure 2A] FIG. 2 illustrates an example read command configured to read a value from a register of a target device.

[0006] [Figure 2B] FIG. 2 illustrates an example I2C write command configured to set a value of a register of a target device.

[0007] [Diagram 3]2 is a communication diagram of an example command exchange for modifying an example first device address of a first target device of FIG. 1 and / or a second device address of a second target device of FIG. 1.

[0008] [Figure 4] 4 is a flowchart illustrating an example process that may be executed using machine-readable instructions and / or configured by hardware to implement the primary device of FIG. 1 to perform the command exchange of FIG. 3.

[0009] [Diagram 5] 4 is a flowchart illustrating an example process that may be executed using machine-readable instructions and / or configured by hardware to implement the first target device and / or the second target device of FIG. 1 to perform the command exchange of FIG. 3.

[0010] [Figure 6] FIG. 6 is a block diagram of an example processing platform including processor circuitry configured to execute example machine-readable instructions and / or the example operations of FIGS. 4 and 5 to implement the device address alteration of FIGS. 1 and 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The drawings are not necessarily to scale. Generally, like reference numbers in the drawings and this description refer to the same or similar parts. Although the drawings show layers and regions with perfect lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, the boundaries and / or lines may be unobservable, blended, and / or irregular.

[0012] The Inter-Integrated Circuit (I2C) protocol is a synchronous serial communication protocol used to communicate between a target device and a primary device. A typical I2C bus includes a data line (SDA) and a clock signal (SCL) that couple a target device to a primary device. A primary device may be a processing circuit, an integrated circuit, a microcontroller, etc. A target device may be an integrated circuit, a sensor, a peripheral device, etc. A primary device may be coupled to multiple target devices via a single I2C bus. In some applications, the same I2C bus is used to communicate between a primary device and multiple target devices.

[0013] The primary device may communicate with the target device by sending commands (e.g., read command, write command) that include the device address of the target device. The primary device may use I2C commands to set and / or read values ​​of registers in the target device. In one example, the I2C command is a synchronous serial data stream on a serial data terminal and includes a start bit, a device address, a read / write bit, a first acknowledge bit, a register address, a second acknowledge bit, and / or a stop bit. The primary device may communicate with individual target devices by sending I2C commands that include a device address unique to that target device. To implement I2C with multiple target devices on the same I2C bus, the target devices need to have different device addresses.

[0014] The device address is set during the manufacture of the target device. In some applications, a device manufacturer may use the same device address for all devices manufactured. In an I2C application that implements multiple identical target devices on the same I2C bus, an I2C command with a certain target device address may cause multiple devices to attempt to write to the serial data lines, resulting in corrupted data. To change the target device address, configuration pins are provided on the target device in addition to the serial data line terminals and clock terminals that comprise the I2C bus. The addition of configuration pins increases the number of pins used by the I2C bus on the target device.

[0015] Examples described herein include an exemplary method for I2C address modification using an I2C bus that modifies the device addresses of multiple target devices with the same device address such that the target devices determine and set distinct device addresses without using configuration pins.

[0016] The primary device may be configured to send a number of I2C commands to read from and write to the target device over the I2C bus. The target device may be configured to determine and set a device address based on commands received over the I2C bus from the primary device.

[0017] 1 is a block diagram of an example system 100 configured to implement I2C communications between an example primary device 105 and example first and second target devices 110 and 115 to modify device addresses of the target devices 110 and 115. In the example of FIG. 1, the system 100 includes the primary device 105, the first target device 110, the second target device 115, an example serial data line (SDA) 120, and an example serial clock line (SCL) 125.

[0018] The primary device 105 is coupled to the target devices 110 and 115 via a serial data line 120 and a serial clock line 125. The primary device 105 includes an example controller 126 and an example storage 128. In some example implementations, the primary device 105 may be a processing circuit, an integrated circuit, a microcontroller, or the like. The primary device 105 is configured to generate a clock signal on the serial clock line 125 such that the devices 105-115 may communicate serial data using the same clock signal. The primary device 105 may send data to the devices 110 and 115 by driving the serial data line 120 so that the devices 110 and 115 may receive data from the primary device 105 by monitoring the serial data line 120. The primary device 105 is configured for an I2C protocol to communicate with the target devices 110 and 115. The controller 126 is configured to drive the serial data line 120 to enable the primary device 105 to send and / or receive I2C commands on the serial data line 120. The primary device 105 may be coupled to the serial data line 120 by a general purpose input / output (GPIO) pin. The primary device 105 may be configured to provide a clock signal to the serial clock line 125. The primary device 105 is configured to send I2C commands to the target devices 110 and 115 by synchronously driving the serial data line 120. The primary device 105 may receive data from the target devices 110 and 115 by monitoring the serial data line 120 for an external driver. The storage 128 may be configured to store data received from the target devices 110 and 115 such that the controller 126 sends the received data to the target devices 110 and 115.

[0019] The first target device 110 is coupled to the primary device 105 and the second target device 115 via a serial data line 120 and a serial clock line 125. In some example implementations, the first target device 110 may be an integrated circuit, a sensor, a peripheral device, or the like. The first target device 110 may send data to the primary device 105 by driving the serial data line 120. The first target device 110 may receive data from the primary device 105 by monitoring the serial data line 120. The first target device 110 includes an example first register 130, a second register 135, a third register 140, and a fourth register 145. Alternatively, the first target device 110 may include any number of registers configured to store any number of bits. The first target device 110 is configured to store an example first device address in the first register 130. For example, the first register 130 may be set to an 8-bit value representing a first device address. Alternatively, the device address may be stored and / or set in registers 135-145. The second register 135 may be configured to store an example first universally unique identifier (UUID). For example, the second register 135 may be set to a 32-bit value representing a first UUID of the first target device 110. The third register 140 may be configured to store an example first inverse UUID (UUIDbar). The first inverse UUID is configured to be bitwise not the first UUID. For example, the third register 140 may be set to a first inverse of the UUID stored in the second register 135. Alternatively, the first inverse UUID may be stored and / or set in registers 130, 135, and / or 145. The fourth register 145 may be configured to store a second device address. For example, the fourth register 145 may be set to an 8-bit value representing the second device address, or the second device address may be stored and / or set in the registers 130-140.

[0020] The second target device 115 is coupled to the devices 105 and 110 via a serial data line 120 and a serial clock line 125. In some example implementations, the second target device 115 may be an integrated circuit, a sensor, a peripheral device, or the like. The second target device 115 may transmit data to the primary device 105 by driving the serial data line 120. The second target device 115 may receive data from the primary device 105 by monitoring the serial data line 120. The second target device includes a fifth register 150, a sixth register 155, a seventh register 160, and an eighth register 165. Alternatively, the second target device 115 may include any number of registers configured to store any number of bits. The second target device 115 is configured to store a first device address in the fifth register 150. For example, the fifth register 150 may be set to an 8-bit value representing the first device address. Alternatively, the device address may be stored and / or set in the registers 155-165. The sixth register 155 may be configured to store a second UUID. For example, the sixth register 155 may be set to a 32-bit value representing the second UUID of the second target device 115. The seventh register 160 may be configured to store a second inverse UUID. The second inverse UUID is configured to be a bitwise non-inverse of the second UUID. For example, the seventh register 160 may be set to the inverse of the second UUID stored in the sixth register 155. Alternatively, the second inverse UUID may be stored and / or set in the registers 150, 155, and / or 165. The eighth register 165 may be configured to store a second device address. For example, the eighth register 165 may be set to an 8-bit value representing the second device address. Alternatively, the second device address may be stored and / or set in the registers 150-160.

[0021] 2A illustrates an example read command 202 configured to read a value from a register of a target device. The read command 202 is configured to define an example data exchange between a primary device (e.g., primary device 105 of FIG. 1) and a target device (e.g., first target device 110 of FIG. 1, second target device 115 of FIG. 1, etc.) over a serial data line (e.g., serial data line 120 of FIG. 1). For the primary device to read a register value (e.g., a value stored and / or set in a register 130-165), the primary device is configured to transmit a read command 202 that includes a device address of the target device, a register address corresponding to the register value, and an acknowledgement from the target device. The target device is configured to respond to the read command 202 by transmitting the value of the register identified in the read command 202.

[0022] In the example of FIG. 2A , the read command 202 includes an example first start bit 204, an example first device address 206, an example first instruction bit 208, an example first acknowledge bit 210, an example first register address 212, a second acknowledge bit 214, a second start bit 216, a second device address 218, a second instruction bit 220, a third acknowledge bit 222, an example first value 224, a fourth acknowledge bit 226, and an example stop bit 228. The primary device is configured to send and / or receive portions of the read command over the serial data line 120 such that the primary device and the target device may communicate by monitoring the serial data line 120. In the example of FIG. 2A , the read command 202 is configured to read as a first value 224 the value of a register corresponding to the first register address 212 in a device corresponding to the device addresses 206 and 218.

[0023] The read command 202 is initiated by driving the serial data line to indicate a first start bit 204. The first start bit 204 is a one-bit transmission that indicates the beginning of a transmission. For example, the first start bit 204 may be transmitted by driving the serial data line 120 to a common potential (e.g., ground) based on an active low serial data line. The first start bit 204 is configured as a one-bit indication such that the first start bit 204 has a duration of approximately one clock cycle of the serial clock line. Alternatively, the first start bit 204 may be indicated by the primary device driving the serial data line to a supply voltage.

[0024] The first start bit 204 is followed by a first device address 206. The first device address 206 is a number of bits configured to correspond to a device coupled to the serial data line that is to be accessed by the device driving the transmission. For example, the primary device 105 may communicate with the first target device 110 by driving the serial data line 120 to indicate the 7-bit device address of the first target device 110. The device driving the serial data line may transmit a message to multiple devices coupled to the serial data line in response to the multiple devices sharing the same device address as the first device address 206.

[0025] The first device address 206 is followed by a first indication bit 208. The first indication bit 208 is a one-bit indication of whether the command is a read command or a write command. For example, the primary device 105 may drive the serial data line 120 to a supply voltage to indicate that the read command 202 includes a write operation, or the primary device 105 may drive the serial data line 120 to a common potential to indicate that the read command 202 is a read operation.

[0026] The first instruction bit 208 is followed by a first acknowledge bit 210. The first acknowledge bit 210 is a one-bit transmission to indicate that the device identified by the first device address 206 received the first instruction bit 208. For example, the first target device 110 may drive the serial data line 120 to a common potential as a result of the first device address 206 corresponding to the first target device 110.

[0027] The first acknowledgement bit 210 is followed by a first register address 212. The first register address 212 is a number of bits to indicate a register within the device indicated by the first device address 206. For example, the primary device 105 may transmit a 7-bit value corresponding to the second register 135 of the first target device 110. Alternatively, the first register address 212 may correspond to any register including the device identified by the first device address 206.

[0028] The first register address 212 is followed by a second acknowledge bit 214. The second acknowledge bit 214 is a one-bit transmission to indicate that the device identified by the first device address 206 received the first register address 212. For example, the first target device 110 may drive the serial data line 120 to a common potential as a result of determining that the first device address 206 corresponds to the first target device 110 and that the first register address 212 is a valid register address. Alternatively, the device identified by the first device address 206 may drive the serial data line to a voltage supply to indicate an error in the first register address 212 or in the transmission of the I2C command. In the example of a read command 202, the first register address 212 is a value to be written to the device corresponding to the first device address 206.

[0029] The second acknowledge bit 214 is followed by a second start bit 216. The second start bit 216 is a one-bit transmission to indicate the beginning of a command transmission. For example, the second start bit 216 may be transmitted by driving the serial data line 120 to a common potential (e.g., ground) based on an active low serial data line. The second start bit 216 is configured as a one-bit indication such that the second start bit 216 has a duration of approximately one clock cycle of the serial clock line. Alternatively, some applications are configured such that the second start bit 216 is indicated by driving the serial data line 120 to a supply voltage.

[0030] The second start bit 216 is followed by a second device address 218. The second device address 218 is a number of bits configured to correspond to a device coupled to the serial data lines that is to be accessed by the device driving the transmission. For example, the primary device 105 may communicate with the first target device 110 by driving the serial data lines 120 to indicate a 7-bit device address of the first target device 110. The device driving the serial data lines may transmit a value to multiple devices coupled to the serial data lines as a result of the multiple devices sharing the same device address as the second device address 218.

[0031] The second device address 218 is followed by a second indication bit 220. The second indication bit 220 is a one-bit indication of whether the command is a read command or a write command. For example, the primary device 105 may drive the serial data line 120 to a supply voltage to indicate a write to a register, or the primary device 105 may drive the serial data line 120 to a common potential to indicate a read operation to a register.

[0032] The second instruction bit 220 is followed by a third acknowledgement bit 222. The third acknowledgement bit 222 is a one-bit transmission to indicate that the device identified by the second device address 218 received the second instruction bit 220. For example, the first target device 110 may drive the serial data line 120 to a common potential as a result of the second device address 218 corresponding to the first target device 110.

[0033] The third acknowledgement bit 222 is followed by a first value 224. The first value 224 is configured to be a number of bits representing a value of a register identified by the first register address 212 of the device of the first device address 206. For example, the first target device 110 may transmit a 32-bit value corresponding to the value of the second register 135 of the first target device 110. Alternatively, the first value 224 may be transmitted in 8-bit segments separated by acknowledgement bits (e.g., acknowledgement bits 210, 214, and 222) such that the transmission of the first value 224 may be acknowledged by the device for which it is intended. Advantageously, the transmission of the first value 224 may be acknowledged by the acknowledgement bits separating the first value 224.

[0034] The first value 224 is followed by a fourth acknowledgement bit 226. The fourth acknowledgement bit 226 is a one-bit transmission to indicate that the device identified by the second device address 218 has received the second instruction bit 220. For example, the first target device 110 may drive the serial data line 120 to a common potential as a result of the second device address 218 corresponding to the first target device 110. Alternatively, the acknowledgement bits 228 and 248 may be referred to as not-acknowledge (NACK) bits.

[0035] The fourth acknowledge bit 226 is followed by a stop bit 228. The stop bit 228 is a one-bit value that indicates the end of the read command 202. For example, the primary device 105 may drive the serial data line 120 to the supply voltage to indicate the end of the command.

[0036] 2B illustrates an example write command 230 configured to set a value in a register of a target device. The write command 230 is configured to define an example data exchange between a primary device (e.g., primary device 105 of FIG. 1) and a target device (e.g., first target device 110 of FIG. 1, second target device 115 of FIG. 1, etc.) over a serial data line (e.g., serial data line 120 of FIG. 1). In order for the primary device to write a register value (e.g., a value to be stored and / or set in registers 130-165), the primary device is configured to transmit a write command 230 that includes a device address of the target device, a register address corresponding to the register to which the value is to be written, and an acknowledgement from the target device. The target device is configured to respond to the write command 230 by setting and / or storing the value in the register indicated by the write command 230.

[0037] 2B example, the write command 230 includes a third start bit 232, a third device address 234, a third instruction bit 236, a fifth acknowledge bit 238, a second register address 240, a sixth acknowledge bit 242, a second value 244, a seventh acknowledge bit 246, and a second stop bit 248. The primary device is configured to transmit and / or receive portions of the write command 230 over the serial data line 120 such that the primary device and the target device may communicate by monitoring the serial data line 120.

[0038] The write command 230 is initiated by driving the serial data line to indicate a third start bit 232. The third start bit 232 is a one-bit transmission to indicate the start of a transmission. For example, the third start bit 232 may be transmitted by driving the serial data line 120 to a common potential (e.g., ground) based on an active low serial data line. The third start bit 232 is configured as a one-bit indication such that the third start bit 232 has a duration of approximately one clock cycle of the serial clock line. Alternatively, the third start bit 232 may be indicated by the primary device driving the serial data line to a supply voltage.

[0039] The third start bit 232 is followed by a third device address 234. The third device address 234 is a number of bits configured to correspond to a device coupled to the serial data lines that is destined to be accessed by the device driving the transmission. For example, the primary device 105 may communicate with the first target device 110 by driving the serial data lines 120 to indicate the 7-bit device address of the first target device 110. The device driving the serial data lines may transmit a message to multiple devices coupled to the serial data lines in response to the multiple devices sharing the same device address as the third device address 234.

[0040] The third device address 234 is followed by a third indication bit 236. The third indication bit 236 is a one-bit indication that the write command 230 is a read command or a write command. For example, the primary device 105 may drive the serial data lines 120 to a supply voltage to indicate that the write command 230 is a write operation, or the primary device 105 may drive the serial data lines 120 to a common potential to indicate that the write command 230 is a read operation.

[0041] The third instruction bit 336 is followed by a fifth acknowledge bit 238. The fifth acknowledge bit 238 is a one-bit transmission to indicate that the device identified by the third device address 234 received the third instruction bit 236. For example, the first target device 110 may drive the serial data line 120 to a common potential as a result of the third device address 234 corresponding to the first target device 110.

[0042] The fifth acknowledgement bit 238 is followed by a second register address 240. The second register address 240 is a number of bits to indicate a register within the device indicated by the third device address 234. For example, the primary device 105 may transmit a 7-bit value corresponding to a value to be stored and / or set in the second register 135 of the first target device 110. Alternatively, the second register address 240 may correspond to any register comprising the device as identified by the third device address 234. The second register address 240 corresponds to a register associated with a value to be written by the write command 230.

[0043] The second register address 240 is followed by a sixth acknowledge bit 242. The sixth acknowledge bit 242 is a one bit transmission to indicate that the device identified by the third device address 234 received the second register address 240. For example, the first target device 110 may drive the serial data lines 120 to a common potential as a result of determining that the third device address 234 corresponds to the first target device 110 and that the second register address 240 is within the first target device 110. Alternatively, the device identified by the third device address 234 may drive the serial data lines to a voltage supply to indicate an error in the second register address 240 or in the transmission of the I2C command.

[0044] The sixth acknowledgement bit 242 is followed by a second value 244. The second value 244 is configured to be a number of bits representing a value to be set and / or stored in a register identified by the second register address 240 of the device identified by the third device address 234. For example, the primary device 105 may transmit a 32-bit value to be stored in the second register 135 of the first target device 110. The second value 244 may be limited based on the register corresponding to the second register address 240. Alternatively, the second value 244 may be transmitted in 8-bit segments separated by acknowledgement bits (e.g., acknowledgement bits 210, 214, and 222) such that the transmission of the second value 244 may be acknowledged by the receiving device. Advantageously, the transmission of the second value 244 may be acknowledged by the acknowledgement bits separating the second value 244.

[0045] The second value 244 is followed by a seventh acknowledge bit 246. The seventh acknowledge bit 246 is a one-bit transmission to indicate that the device identified by the third device address 234 has received, set, and / or stored the second value 244 in the register corresponding to the second register address 240. For example, the first target device 110 may drive the serial data line 120 to a common potential as a result of the third device address 234 corresponding to the first target device 110 and the value of the register corresponding to the second register address 240 being set to the second value 244. Alternatively, the acknowledge bits 238, 242, and 246 may be referred to as not-acknowledge (NACK) bits.

[0046] The fourth acknowledge bit 226 is followed by a second stop bit 248. The second stop bit 248 is a one-bit value that represents the end of the write command 230. For example, the primary device 105 may drive the serial data lines 120 to the supply voltage to indicate the end of the command. Alternatively, the second stop bit 248 may be configured to be at the end of the write command 230.

[0047] 3 is a communication diagram 300 of an example command exchange for modifying an example first device address of the first target device 110 of FIG. 1 and / or a second device address of the second target device 115 of FIG. 1. In the example of FIG. 3, the first device address of the first target device 110 and the second device address of the second target device 115 are configured to be shared device addresses, and registers configured to store and / or set device addresses (e.g., registers 130-165) are the same value in both target devices 110 and 115. In the example of FIG. 3, the communication diagram 300 includes an example first read request 305, an example first read value 310, a first write command 315, a second read request 320, a second read value 325, a second write command 330, and example blocks 335-360. The communication diagram 300 is configured to modify the device addresses of the devices 110 and / or 115 using the system 100 of FIG. 1 configured for I2C communication. The communication diagram 300 is configured to display an exchange of commands between the primary device 105 and the target devices 110 and 115. A read command (e.g., the read command of FIG. 2A) may consist of a read request (e.g., read requests 305 and 320) followed by a read value (e.g., read value 310 and 325). The read request includes bits 204-214 of the read command 202 of FIG. 2A such that the primary device 105 may request for the value of a register corresponding to the first register address 212 of the device corresponding to the first device address 206. The read value includes bits 216-228 of the read command 202 of FIG. 2A such that the device at the device address corresponding to the second device address 218 may transmit the value of the register corresponding to the first register address 212.

[0048] In the example of FIG. 3, the primary device 105 transmits a first read request 305 to the target devices 110 and 115 as a result of the first device address 206 being equal to the value of the shared device address. For example, the primary device 105 may transmit the first read request 305 by sending bits 204-214 to the target devices 110 and 115 by driving the serial data lines 120 of FIG. 1 such that the first device address 206 is equal to the shared device address. The first read request 305 includes bits 204-214 of the read command 202. The first read request 305 is configured to request that the target devices 110 and 115 transmit the value of a register corresponding to a register address (e.g., the first register address 212 of FIG. 2). The first read request 305 is configured to include a register address corresponding to a register configured to store and / or set the UUID of each of the target devices 110 and 115. For example, primary device 105 transmits a first read request 305 over serial data line 120 that includes the device addresses of target devices 110 and 115 and the register addresses of registers 135-155. Advantageously, first read request 305 is received by all of the target devices that are configured with a device address equal to the shared device address.

[0049] The first read request 305 is followed by a first read value 310. The first read value 310 includes bits 216-228 of the read command 202 of FIG. 2. The primary device 105 is configured to transmit the shared device address as a value of the second device address 218 such that the target devices 110 and 115 transmit the value of the register corresponding to the first register address 212 of the first read request 305. For example, the target devices 110 and 115 transmit the UUIDs stored and / or configured in the registers 135 and 155 in response to the primary device 105 transmitting the values ​​stored in the registers 130 and 150 corresponding to the shared device address. Advantageously, the target devices 110 and 115 are configured to individually transmit the first value 224 of FIG. 2 during the same interval in response to the first read request 305. The serial data line 120 is configured as an active low communication line such that a logical AND of the data from each device is transmitted as a result of multiple devices driving the serial data line 120. For example, the primary device 105 is configured to read a logical low as a result of the first target device 110 driving the serial data line 120 to a common voltage (e.g., ground) during the same interval that the second target device 115 may drive the serial data line 120 to a supply voltage. Advantageously, the first value 224 of the first read request is equal to the logical AND of the UUIDs of the target devices 110 and 115.

[0050] The first read request 310 is followed by a first write command 315. The first write command 315 includes bits 232-248 of the write command 230. The first write command 315 is configured to include a shared device address of the target devices 110 and 115, followed by a shared register address, which corresponds to a register for storing a value representing a logical AND of the UUID of the first target device 110 and the UUID of the second target device 115 based on the first read value 310. For example, the primary device 105 transmits the logical AND of the UUIDs stored and / or set in the registers 135 and 155 in response to the target devices 110 and 115 transmitting the UUIDs stored in the registers 135 and 155 of the target devices 110 and 115.

[0051] The first write command 315 is followed by a second read request 320. The second read request 320 consists of bits 204-214 of the read command 202 of FIG. 2. The second read request 320 is configured to set a device address (e.g., second device address 218 of FIG. 2) to the shared device address. The second read request 320 stores and / or sets a register address (e.g., first register address 212 of FIG. 2) in a register configured to store and / or set the reverse UUID (UUIDbar) of each of the target devices 110 and 115. For example, the primary device 105 transmits the second read request 320 over the serial data line 120, including the device addresses of the target devices 110 and 115 and the register addresses of the registers 140 and 160.

[0052] The second read request 320 is followed by a second read value 325. The second read value 325 consists of bits 216-228 of the read command 202 of FIG. 2. The primary device 105 transmits device addresses for the target devices 110 and 115 such that the devices 110 and 115 transmit values ​​of registers configured to store and / or set the reverse UUID. For example, the target devices 110 and 115 transmit the reverse UUID stored and / or set in registers 140 and 160 in response to the primary device 105 transmitting values ​​stored in registers 130 and 150 corresponding to the shared device address. Advantageously, the target devices 110 and 115 are configured to transmit the reverse UUID during the same transmission. The serial data line 120 is configured as an active low communication line such that a logical AND of data from each device is transmitted as a result of multiple devices driving the serial data line 20. For example, the primary device 105 may be configured to read a logic low as a result of the first target device 110 driving the serial data line 120 to a common potential (e.g., ground) during the same interval that the second target device 115 may drive the serial data line 120 to a supply voltage.

[0053] The second read value 325 is followed by a second write command 330. The second write command 330 includes bits 232-248 of the write command 230. The second write command 330 is configured to include the shared device address of the target devices 110 and 115, followed by a register address that corresponds to a register for storing a value representing the logical AND of the inverse UUID of the first target device 110 and the inverse UUID of the second target device 115 from the second read value 325. For example, the primary device 105 transmits the logical AND of the inverse UUIDs stored and / or configured in the registers 140 and 160 in response to the target devices 110 and 115 transmitting the UUIDs stored and / or configured in the registers 140 and 160 of the target devices 110 and 115.

[0054] Advantageously, commands 305-330 are configured to provide a logical AND of the UUIDs and inverse UUIDs of target devices 110 and 115 to both target devices 110 and 115. Alternatively, commands 305-330 may be configured to include additional commands, including additional exemplary read and / or write commands, to access multiple registers.

[0055] In block 335, the first target device 110 determines the UUID of the second target device 115. The first target device 110 may determine the UUID of the second target device 115 by comparing the logical AND of the UUID (the value transmitted in the first write command 315) and / or the logical AND of the inverse UUID (the value transmitted in the second write command 330) with the first UUID stored and / or set in register 135 and / or the first inverse UUID stored and / or set in register 140. The first target device 110 may determine each bit of the UUID of the second target device 115 by determining that the possible values ​​of each bit are a logical 0, a logical 1, or indeterminable. For example, the first target device 110 may determine that the first bit of the UUID of the second target device 115 is a logical 0 as a result of the first bit of the UUID of the first target device 110 being determined to be a logical 1 and the first bit of the logical AND of the UUIDs being determined as a logical 0.

[0056] The first target device 110 may be configured to compare a bit of the UUIDbar of the first target device 110 to a logical AND of the UUIDbar as a result of determining that the possible values ​​of a bit are undetermined. For example, the first target device 110 may determine the second bit of the UUID of the second target device 115 to be a logical 1 as a result of the second bit of the UUID of the first target device 110 being a logical 0 and the second bit of the logical AND of the UUIDbar being a logical 0. Alternatively, the first target device 110 may determine the second bit of the UUID of the second target device 115 to be a logical 1 as a result of the second bit of the UUIDbar of the first target device 110 being a logical 1 and the second bit of the logical AND of the UUIDbar being a logical 0. Such possible values ​​for the second bit of the UUID of the second target device 115 are undeterminable based on comparing the logical AND of the UUIDs to the UUID of the first target device 110. Advantageously, the first target device 110 may determine the UUID of the second target device 115 by comparing the logical AND of the UUIDs to the logical AND of the inverse UUID. Block 335 is followed by block 340.

[0057] In block 340, the first target device 110 determines a device address. The first target device 110 may determine to modify the device address stored and / or configured in the first register 130. For example, the first target device 110 may be configured to set the value of the first register 130 to a new device address stored and / or configured in the fourth register 145 as a result of the UUID of the second target device 115 being greater than the UUID of the first target device 110. Alternatively, the target devices 110 and 115 may determine to modify the device address based on any comparison of the UUIDs of the target devices 110 and 115. Advantageously, the target devices 110 and 115 are configured to determine and set the device addresses stored and / or configured in the registers 130 and 150 such that the target devices 110 and 115 can receive commands individually.

[0058] In block 345, the second target device 115 determines the UUID of the first target device 110. The second target device 115 may determine the UUID of the first target device 110 by comparing the logical AND of the UUID (the value transmitted in the first write command 315) and / or the logical AND of the inverse UUID (the value transmitted in the second write command 330) with the first UUID stored and / or set in the sixth register 155 and the first inverse UUID stored and / or set in the seventh register 160. The second target device 114 may determine each bit of the UUID of the first target device 110 by determining that each bit's possible values ​​are a logical 0, a logical 1, or indeterminable. For example, the second target device 115 may determine that the first bit of the UUID of the first target device 110 is a logical 0 as a result of the first bit of the UUID of the second target device 115 being determined to be a logical 1 and the first bit of the logical AND of the UUIDs being determined to be a logical 0.

[0059] The second target device 115 may be configured to compare a bit of the UUIDbar of the second target device 115 with a logical AND of the UUIDbar as a result of determining that the possible values ​​of a bit are indeterminable. For example, the second target device 115 may determine the second bit of the UUID of the first target device 110 to be a logical 1 as a result of the second bit of the UUID of the second target device 115 being a logical 0 and the second bit of the logical AND of the UUIDbar being a logical 0. Such a possible value of the second bit of the UUID of the first target device 110 is indeterminable based on comparing the logical AND of the UUIDs with the UUID of the second target device 115. Advantageously, the second target device 115 may determine the UUID of the first target device 110 by comparing the logical AND of the UUIDs with the logical AND of the inverse UUID. Block 345 is followed by block 350.

[0060] In block 350, the second target device 115 determines a device address. The second target device 115 may determine to modify the device address stored and / or configured in the fifth register 150. For example, the second target device 115 may be configured to set the value of the fifth register 150 to a new device address stored and / or configured in the eighth register 165 as a result of the UUID of the first target device 110 being greater than the UUID of the second target device 115. Alternatively, the target devices 110 and 115 may determine to modify the device address based on any comparison of the UUIDs of the target devices 110 and 115. Advantageously, the second target device 115 is configured to determine and set the device address stored and / or configured in the fifth register 150 such that the target devices 110 and 115 can receive commands individually. Advantageously, the target devices 110 and 115 may modify each device address without additional coupling.

[0061] Although an example method is described with reference to Figure 3, many other methods may alternatively be used in this description. For example, the order of execution of the blocks may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Similarly, additional operations may be included in the manufacturing process before, between, or after the blocks shown in the illustrated example.

[0062] Alternatively, the method described in FIG. 3 may be modified to consider more than two target devices. For example, the method of FIG. 3 may be implemented with three devices with shared device addresses coupled to the same I2C bus, with the method of FIG. 3 being repeated twice to determine the two highest UUIDs. In some such examples, the method of FIG. 3 may be implemented to configure a first device (e.g., the device with the highest UUID) to have an individual device address once, and then repeat the method of FIG. 3 to determine a second individual device address of a second device (e.g., the device with the second highest UUID) such that the device with the lowest UUID may still respond to the shared device address. Advantageously, the method of FIG. 3 may be modified to configure device addresses of more than two device addresses.

[0063] Figure 4 is a flow chart representing an example process that may be implemented using machine-readable instructions that may be executed and / or configured by hardware to implement the primary device of Figure 1 to perform the command exchange of Figure 3. In the example of Figure 4, the process is configured to exchange I2C commands between a primary device (e.g., primary device 105 of Figures 1 and 3) and multiple target devices (e.g., target devices 110 and 115 of Figures 1 and 3) such that the target devices start at a shared device address and end at individual device addresses. The process begins at block 405.

[0064] At block 405, the primary device sends a first read command to a device address. The first read command is configured based on the read command 202 of FIG. 2 such that the first device address 206 of FIG. 2 is a shared device address of the target device and the first register address 212 of FIG. 2 is a register address of a register in the target device configured to store and / or set a UUID. For example, the first read request 305 of FIG. 3 includes the device addresses of registers 130 and 150 and the register addresses corresponding to registers 135 and 155, such that registers 135 and 155 are configured to store the target device UUID. The primary device may send the first read command to the device by driving a serial data line (e.g., serial data line 120 of FIG. 1) such that the serial data line is coupled to the target device. The process proceeds to block 410.

[0065] At block 410, the primary device reads the logical AND of the first UUID and the second UUID. The primary device may read the logical AND of the first UUID from the first target device (e.g., first target device 110) and the second UUID from the second target device (e.g., second target device 115) as a result of the transmission of the first read command at block 405 and the shared device address (e.g., second device address 218 of FIG. 2) on the serial data lines. The read at block 410 may be configured similarly to bits 216-228 of the read command 202 of FIG. 2. For example, the first read value 310 of FIG. 3 includes the shared device address, followed by the logical AND of the UUID of the first target device 110 and the UUID of the second target device 115. Advantageously, the target devices simultaneously drive the serial data lines such that the primary device reads the logical AND of the values ​​from the target devices. The process proceeds to block 415.

[0066] At block 415, the primary device sends a first write command to the device address. The first write command is configured similarly to write command 330 of FIG. 3, such that the primary device transmits a value representing the logical AND of the UUIDs to the shared device address as second value 244 of FIG. 2. For example, primary device 105 drives a serial data line to transmit the shared device address followed by a value representing the logical AND of the UUIDs of target devices 110 and 115. Advantageously, primary device 105 may transmit the logical AND of the UUIDs of the target devices to all of the target devices in a single command. Alternatively, the primary device may be configured to send the first write command any time after blocks 405 and 410. The process proceeds to block 420.

[0067] At block 420, the primary device sends a second read command to the device address. The second read command is configured based on the read command 202 such that the first device address 206 is the shared device address of the target device and the first register address 212 is a register address of a register in the target device configured to store and / or set a reverse UUID. For example, the second read request 320 of Figure 3 includes the device addresses of registers 130 and 150 and the register addresses corresponding to registers 140 and 160 such that registers 140 and 160 are configured to store the target device reverse UUID. The process proceeds to block 425.

[0068] At block 425, the primary device reads the logical AND of the first UUIDbar and the second UUIDbar. The primary device may read the logical AND of the first UUIDbar from the first target device and the second UUID from the second target device as a result of the transmission of the second read command at block 420 and the shared device address (e.g., second device address 218) on the serial data lines. The read performed at block 425 may be configured similarly to bits 216-228 of the read command 202 of FIG. 2. For example, the second read value 325 of FIG. 3 includes the shared device address followed by the logical AND of the UUIDbar of the first target device 110 and the UUIDbar of the second target device 115. Advantageously, the target devices drive the serial data lines simultaneously such that the primary device reads the logical AND of the values ​​from both target devices. The process proceeds to block 430.

[0069] In block 430, the primary device sends a second write command to the shared device address. The second write command is configured similarly to write command 330 of FIG. 3, with the primary device sending a value representing the logical AND of the UUIDbar to the shared device address as second value 244. For example, primary device 105 drives the serial data lines to transmit the shared device address followed by a value representing the logical AND of the UUIDbars of target devices 110 and 115. Advantageously, the primary device may transmit the logical AND of the UUIDbars of the target devices to all of the target devices in a single command. The process ends. Alternatively, the primary device may send the second write command of block 430 at any time after blocks 420 and 425.

[0070] Although an example method is described with reference to the flowchart illustrated in Figure 4, many other methods may alternatively be used in this description. For example, the order of execution of the blocks may be changed, and / or some of the described blocks may be changed, eliminated, or combined. Similarly, additional operations may be included in the manufacturing process before, between, or after the blocks shown in the illustrated example.

[0071] Figure 5 is a flow chart representing an example process that may be implemented using machine-readable instructions that may be executed and / or configured by hardware to implement the first target device of Figure 1 and / or the second target device of Figure 1 to perform the command exchange of Figure 3. In the example of Figure 5, the process is configured to exchange I2C commands between a primary device (e.g., primary device 105 of Figures 1 and 3) and multiple target devices (e.g., target devices 110 and 115 of Figures 1 and 3) such that the target devices start at a shared device address and end at individual device addresses. The process begins at block 505.

[0072] At block 505, the target device receives a first read command. The first read command is configured based on bits 204-214 of the read command 202 of FIG. 2 such that the first device address 206 of FIG. 2 is the shared device address of the target device and the first register address 212 of FIG. 2 is the register address of a register in the target device configured to store and / or set a UUID. For example, the first read request 305 of FIG. 3 includes the device addresses of registers 130 and 150 and the register addresses corresponding to registers 135 and 155 such that registers 135 and 155 are configured to store the target device UUID. The target device can read and / or send I2C commands to the device address by driving a serial data line (e.g., serial data line 120 of FIG. 1) such that the serial data line is coupled to separate target and primary devices. The process proceeds to block 510.

[0073] At block 510, the target device writes a first UUID. The write at block 510 may be configured similarly to bits 216-228 of the read command 202 of FIG. 2 such that the first value 224 of FIG. 2 is the first UUID of the target device. For example, the first target device 110 writes the value of the second register 135 of FIG. 1 in response to receiving the shared device address as part of the first read value 310 of FIG. 3. Blocks 505 and 510 include a first read command configured to include bits 204-228 of the read command 202 of FIG. 2. Advantageously, the target devices may simultaneously drive the serial data lines such that the primary device reads the logical AND of the values ​​from the target devices. The process proceeds to block 515.

[0074] At block 515, the target device receives a first write command. The first write command is configured similarly to the first write command 315 of Figure 3, such that the primary device transmits a value representing the logical AND of the UUIDs to the shared device address. For example, the target device receives a value representing the logical AND of the UUIDs of target devices 110 and 115. Advantageously, the target device may receive the logical AND of the target device's UUIDs in a single command. The process proceeds to block 520.

[0075] At block 520, the target device receives a second read command. The second read command is constructed based on bits 204-214 of the read command 202 such that the first device address 206 is the shared device address of the target device and the first register address 212 is a register address of a register in the target device configured to store and / or set a reverse UUID. For example, the second read request 320 of FIG. 3 includes device addresses of registers 130 and 150 and register addresses corresponding to registers 140 and 160 such that registers 140 and 160 are configured to store the target device reverse UUID. The process proceeds to block 525.

[0076] At block 525, the target device writes UUIDbar. The write at block 525 may be configured similarly to the read command 202 of FIG. 2. For example, the second read value 325 of FIG. 3 includes the shared device address followed by a logical AND of the UUIDbar of the first target device 110 and the UUIDbar of the second target device 115. Blocks 520 and 525 include a second read command configured to include bits 204-228 of the read command 202 of FIG. 2. Advantageously, the target devices write the UUIDbar value onto the serial data line simultaneously such that the primary device can read the logical AND of the values ​​from both target devices. The process proceeds to block 530.

[0077] At block 530, the target device receives a second write command. The second write command is configured similarly to write command 330 of FIG. 3 such that the target device receives a value representing the logical AND of the UUIDbar. For example, primary device 105 drives the serial data lines to transmit the shared device address followed by a value representing the logical AND of the UUIDbars of target devices 110 and 115. Advantageously, the target device receives the logical AND of the target device's UUIDbars in a single command. The process proceeds to block 535.

[0078] At block 535, the target device determines a second UUID. The target device may determine the second UUID in a manner similar to that described in blocks 335 and 345 of FIG. 3 such that the target device may determine the UUID of a separate target device. For example, the first target device 110 determines the UUID of the second target device 115 based on determining possible values ​​for each bit of the UUID of the second target device 115 by comparing the UUID of the first target device 110 to a logical AND of the UUIDs of the target devices 110 and 115. Advantageously, the target device may determine the UUID of another target device without sending a separate target device command. The process proceeds to block 540.

[0079] At block 540, the target device determines a device address based on the first UUID and the second UUID. The target device compares the first UUID to the second UUID, similar to the method described in blocks 340 and 350 of FIG. 3, such that the target device may determine whether the device address of the target device should be modified. For example, the first target device 110 may modify the device address of the first target device 110 to a new device address as a result of determining that the UUID of the second target device 115 is greater than the UUID of the first target device 110. The process proceeds to block 545.

[0080] At block 545, the target device configures a device address. For example, the first target device 110 may alter the value of a register corresponding to the device address as a result of comparing the first UUID to the second UUID. Advantageously, the target devices coupled to the serial data line include individual device addresses so that the primary device can send and / or receive I2C commands to each target device individually.

[0081] Although an example method is described with reference to the flowchart illustrated in Figure 5, many other methods may alternatively be used in this description. For example, the order of execution of the blocks may be changed, and / or some of the described blocks may be changed, eliminated, or combined. Similarly, additional operations may be included in the manufacturing process before, between, or after the blocks shown in the illustrated example.

[0082] Figure 6 is a block diagram of an example processing platform including processor circuitry configured to execute example machine-readable instructions and / or example operations of Figures 4 and 5 for implementing the device address alteration of Figures 1 and 3 using the commands of Figure 2. The processor platform 600 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., neural networks), a mobile device (e.g., a mobile phone, a smart phone, a tablet such as an iPad™), a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a game console, a personal video recorder, a set-top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.), or other wearable device, or any other type of computing device.

[0083] The processor platform 600 of the illustrated example includes processor circuitry 612. The processor circuitry 612 of the illustrated example is hardware. For example, the processor circuitry 612 may be implemented by one or more of an integrated circuit, logic circuit, FPGA microprocessor, CPU, GPU, DSP, and / or microcontroller from any desired family or manufacturer. The processor circuitry 612 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices.

[0084] The processor circuitry 612 of the illustrated example includes a local memory 613 (e.g., cache, registers, etc.). The processor circuitry 612 of the illustrated example communicates with a main memory including a volatile memory 614 and a non-volatile memory 616 by a bus 618. The volatile memory 614 may be implemented by a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), a RAMBUS® dynamic random access memory (RDRAM®), and / or any other type of RAM device. The non-volatile memory 616 may be implemented by a flash memory and / or any other type of memory device. Access to the main memory 616, 616 of the illustrated example is controlled by a memory controller 617. Alternatively, the primary device 105 of FIG. 1 and FIG. 3 may be included in the processor circuitry 612.

[0085] The processor platform 600 of the illustrated example also includes an interface circuit element 620. The interface circuit element 620 may be implemented by hardware in any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, a Bluetooth® interface, a Near Field Communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and / or a Peripheral Component Interconnect Express (PCIe) interface. In the example of FIG. 6, the primary device 105 is included within the interface circuit element 620. Alternatively, the primary device 105 may be included in the processor platform 600.

[0086] In the illustrated example, target devices 110 and 115 are connected to interface circuitry 620. Target devices 110 and 115 are configured to communicate with interface circuitry 620 using an I2C protocol. Target devices 110 and 115 may be implemented as peripheral devices capable of I2C communication (e.g., sensors, Electrically Erasable Programmable Read Only Memory (EEPROM), receivers, etc.).

[0087] In the illustrated example, one or more input devices 622 are coupled to the interface circuitry 620. The input devices 622 allow a user to input data and / or commands to the processor circuitry 612. The input devices 622 may be implemented by, for example, audio sensors, microphones, cameras (still or video), keyboards, buttons, a mouse, a touch screen, a trackpad, a trackball, an isopoint device, and / or a voice recognition system.

[0088] One or more output devices are also connected to the interface circuitry 620 of the illustrated example. The output device 626 may be implemented by, for example, a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-plane switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Thus, the interface circuitry 620 of the illustrated example includes a graphics driver card, a graphics driver chip, and / or graphics processor circuitry such as a GPU.

[0089] The interface circuitry 620 of the illustrated example also includes transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces to facilitate data exchange with external equipment (e.g., any type of computing device) over the network 626. Communications may be by way of, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-site wireless system, a cellular phone system, an optical connection, etc.

[0090] The processor platform 600 of the illustrated example also includes one or more mass storage devices 628 for storing software and / or data. Examples of such mass storage devices 628 include magnetic storage devices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-ray disk drives, Redundant Array of Independent Disks (RAID) systems, flash memory devices and / or solid state storage devices such as SSDs, and DVD drives.

[0091] Machine-executable instructions 632, which may be implemented by the machine-readable instructions of Figures 4 and 5, may be stored in mass storage device 628, volatile memory 616 (614?), non-volatile memory 616, and / or a removable non-transitory computer-readable storage medium such as a CD or DVD.

[0092] The term "couple" is used throughout the specification. This term may encompass any connection, communication, or signal path that allows for a functional relationship consistent with this description. For example, in a first example, device A is coupled to device B if device A provides a signal to control device B to perform a certain action, or in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal provided by device A, where the intervening component C does not substantially change the functional relationship between device A and device B.

[0093] A device that is "configured to" perform a certain task or function may be configured (e.g., programmed and / or hardwired) at the time of manufacture by a manufacturer to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through the device's firmware and / or software programming, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0094] As used herein, "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are used generally to mean an interconnection or termination between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0095] A circuit or device described herein as including certain components may instead be adapted to be combined with those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (voltage and / or current sources) may instead include only the semiconductor elements in a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be combined with at least some of the passive elements and / or sources to form the described structure during or after manufacture, e.g., by an end user and / or a third party.

[0096] Although the use of particular transistors is described herein, other transistors (or equivalent devices) may be substituted. For example, a p-type field effect transistor ("PFET") may be substituted for an n-type field effect transistor ("NFET") with little or no modification to the circuit. Also, other types of transistors may be used, such as bipolar transistors (BJTs).

[0097] The circuits described herein are reconfigurable to include replaced components to provide functionality at least partially similar to that available prior to the replacement of the components. A component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown, unless otherwise noted. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor.

[0098] Use of the term "ground" in the preceding description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, shared ground, and / or any other form of ground connection applicable or suitable to the teachings of the present description. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10 percent of the stated value.

[0099] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the appended claims.

Claims

1. 1. A system comprising: a first device having a terminal, sending a first command including a first address to the terminal; receiving, after sending the first command, a first value at the terminal comprising a bitwise logical AND of a first identifier of a second device and a second identifier of a third device; in response to receiving the first value, sending a second command to the terminal including the first address and an indication of the first value; sending a third command including the first address to the terminal; receiving, after sending the third command, a second value at the terminal comprising a bitwise logical AND of a third identifier of the first device and a fourth identifier of the third device; sending a fourth command to the terminal in response to receiving the second value, the fourth command including an indication of the first address and the second address; a first device configured to:

2. 10. The system of claim 1, The system, wherein the first command is a read command that includes a register address of a first register of the second device and a register address of a second register of the third device.

3. 10. The system of claim 1, The system, wherein the second command is a write command that includes a register address of a register of the second device and a register address of a register of the third device.

4. 10. The system of claim 1, the second device; and the third device; and a data line coupled to the terminal, the second device, and the third device; a clock line coupled to the first device, the second device, and the third device; The system further comprises:

5. 10. The system of claim 1, The first device is an inter-integrated circuit (I ２ C) The system further configured to communicate using the protocol.

6. 10. The system of claim 1, The system, wherein the first address is a device address shared by the second device and the third device, and the second device and the third device are configured to receive and send commands simultaneously.

7. 10. The system of claim 1, The first device comprises: sending a fifth command including a second address to said terminal; receiving a seventh value at the terminal after sending the fifth command; The system further comprises:

8. 1. A system comprising: A first device including a first resistor, a second resistor, and a terminal, receiving a first read command at said terminal; sending a first identifier of the first device to the terminal after receiving the first read command at the terminal; receiving a first write command at the terminal that includes a first value; in response to receiving the first write command at the terminal, storing the first value in the first register, the first value being a logical AND of a first identifier of the first device and a second identifier of a second device; receiving a second read command at said terminal; sending the inverse of the first identifier to the terminal after receiving the second read command at the terminal; receiving a second write command at the terminal that includes a second value; in response to receiving the second write command at the terminal, storing the second value in the second register, the second value being the logical AND of the inverse of a first identifier of the first device and the inverse of a second identifier of the second device; determining a third identifier of the second device based on the first value and the second value; a first device configured to:

9. 9. The system of claim 8, The first device is an inter-integrated circuit (I ２ C) The system further configured to communicate with the second device using a protocol.

10. 9. The system of claim 8, The system, wherein the first read command includes a register address of a third register of the first device, the third register configured to store a first identifier of the first device.

11. 9. The system of claim 8, The system determines that the first identifier is different from the second identifier and that a value representing the first identifier and the second identifier is to be stored in a third register of a shared register address.

12. 9. The system of claim 8, The system is further configured: the first device compares the first identifier with the second identifier; and determines a device address of the second device based on the comparison.

13. 9. The system of claim 8, The system, wherein the second read command includes a register address of a third register configured to store an inverse of a first identifier of the first device.

14. 9. The system of claim 8, The system, wherein the first identifier is a first universally unique identifier (UUID) of the first device and the second identifier is a second UUID of the second device.

15. A method comprising: receiving, by a first device, a first write command at a first terminal, the first write command including a first value; storing, by the first device in a first register in response to receiving the first write command, the first value being a logical AND of a first identifier of the first device and a second identifier of a second device; receiving, by the first device, a second write command at the first terminal, the second write command including a second value; storing, by the first device in response to receiving the second write command, the second value in a second register, the second value being the logical AND of the inverse of a first identifier of the first device and the inverse of a second identifier of the second device; determining, by the first device, a third identifier of the second device based on the first value and the second value; A method comprising:

16. The method of claim 15, transmitting the first identifier in response to receiving a first read command; transmitting the inverse of the first identifier in response to receiving a second read command; The method further comprises:

17. The method of claim 16, The method, wherein the first identifier is a universally unique identifier (UUID).

18. The method of claim 16, reading the first identifier from a third register; reading the reciprocal of the first identifier from a fourth register; The method further comprises:

19. The method of claim 15, Determining a third identifier determining the second identifier based on the first identifier, the first value, and the second value; determining the third identifier based on a comparison of the first identifier and the second identifier; A method comprising:

20. The method of claim 15, The method further comprising storing the third identifier in a register.

21. 1. A system comprising: a first device, a first register configured to store a first address; a second register configured to store the first device UUID; a third register configured to store a first value adapted to be a logical AND of the first device UUID and a second device UUID; a first circuit coupled to the first register, the second register, and the third register, determining the second device UUID based on the first device UUID in the second register and the first value in the third register; responsive to determining the second device UUID, comparing the first device UUID to the second device UUID; determining a second address after comparing the first device UUID with the second device UUID; after determining the second address, setting the first register to store the second address; the first circuit configured as follows: the first device comprising: a second device, a fourth register configured to store the first address; a fifth register configured to store the second device UUID; a sixth register configured to store the first value; a second circuit coupled to the fourth register, the fifth register, and the sixth register, determining the first device UUID based on the second device UUID in the fifth register and the first value in the sixth register; responsive to determining the first device UUID, comparing the first device UUID to the second device UUID; determining a third address after comparing the first device UUID with the second device UUID; after determining the third address, setting the first register to store the third address; the second device configured as follows: Including, the system.

22. 22. The system of claim 21, The system, wherein the first device further includes a seventh register configured to store a second value, the second value representing a logical AND of the inverse of the first device UUID and the inverse of the second device UUID.

23. 22. The system of claim 21, The system, wherein the first circuit is further configured to determine whether the first device UUID is greater than the second device UUID.

24. 22. The system of claim 21, The system, wherein the second device further includes a seventh register configured to store a second value, the second value representing a logical AND of the inverse of the first device UUID and the inverse of the second device UUID.

25. 22. The system of claim 21, The system, wherein the second circuit is further configured to determine whether the first device UUID is greater than the second device UUID.

26. 22. The system of claim 21, The system, wherein the first address is equal to the third address, and the third address represents only the second device.

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