A Traffic-Aware Adaptive Precharge Scheduler for Efficient Refresh Management in DRAM Memory Controllers

Abstract

A memory controller with adaptive precharge scheduling is described herein. In one aspect, the memory controller includes a refresh scheduler configured to send refresh commands to DRAM banks of a dynamic random access memory (DRAM) memory system, the DRAM memory system including DRAM banks arranged in a set of DRAM banks, each set of DRAM banks including one or more DRAM banks. The memory controller includes an adaptive precharge scheduler configured to determine a priority score for each DRAM bank group based on a set of parameters, and select and close a particular DRAM bank group based on the priority score for each DRAM bank group, and send a precharge command to at least one DRAM bank of the particular DRAM group so that each DRAM bank in the DRAM bank group can be refreshed by the refresh scheduler.

Description

[Technical field]

[0001] This specification relates to a memory controller for a dynamic random access memory (DRAM). [Background technology]

[0002] A DRAM cell is a memory cell that typically includes an access transistor and a capacitor to store a bit of data. The capacitor can be charged or discharged to represent the binary value of the bit, zero or one. The capacitor has a tendency to leak accumulated charge over time. Thus, without intervention, data stored in the DRAM would be lost. To prevent this data loss, data stored in the DRAM is periodically refreshed, for example, using a refresh command issued by the DRAM memory controller. Each DRAM cell must be periodically refreshed according to DRAM standards, for example, JEDEC memory standards. Refreshing a DRAM cell typically involves reading and rewriting data into the DRAM cell, which restores the capacitor to its previous charge.

[0003] The refresh process adversely affects the performance and power usage / dissipation of the DRAM cells. For example, the DRAM cells of a DRAM bank are stalled during the refresh process and data cannot be read from or written to the DRAM bank. The refresh process also increases the amount of power used and dissipated by the memory system due to reading and rewriting data to the DRAM cells. Summary of the Invention

[0004] This specification relates to a memory controller for a dynamic random access memory (DRAM). The memory controller may include a refresh scheduler that schedules refreshes to DRAM banks, for example, on a bank-by-bank basis and / or for all banks managed by the memory controller. The refresh scheduler typically issues a per-bank refresh command (REFpb) command to DRAM banks that are closed unless the refresh interval of the DRAM system expires and they are closed. The refresh scheduler may then issue a refresh all-banks command (REFab) command to refresh all DRAM banks. This causes all banks in the DRAM system to be unavailable until all of the DRAM banks are refreshed.

[0005] REFpb involves a targeted refresh of a bank or bank pair, allowing traffic to continue to other banks, while REFab requires traffic to all banks to stall and requires all banks to be idle before the REFab command begins. Also note that one REFab can be the equivalent of issuing eight REFpb commands and has the same effect.

[0006] Issuing more REFpb commands than REFab commands when memory traffic is ongoing is desirable as it aids system performance by avoiding blackout periods in the DRAM system. The JEDEC standard provides flexibility in choosing the order to select bank pairs while issuing REFpb commands per cycle, and this order may vary from cycle to cycle. Each cycle is defined as one iteration through all banks within the refresh (tREFI) window. A memory controller can typically only issue REFpb to a bank pair once during a cycle, and the memory controller must finish iterating through all bank pairs before initiating another cycle. This allows memory controllers to implement schemes that may result in better system performance by selecting an improved or optimal order of DRAM banks to refresh during each cycle.

[0007] As described herein, the memory controller can include an adaptive precharge scheduler that monitors traffic and intelligently inserts precharges into the traffic stream to assist the refresh scheduler in scheduling per-bank refresh commands in a sequence that minimizes impact to the quality of service of the DRAM system. A precharge (PRE) command can close a row of DRAM cells in a DRAM bank, allowing the refresh scheduler to issue a REFpb command to the DRAM bank.

[0008] The adaptive precharge scheduler may interface with the transaction buffer (to determine traffic conditions), obtain information about the page status of each DRAM bank, obtain information about impending refresh requirements (e.g., in the frontloading or backloading phase or close to the tREFi deadline), and incorporate all this data into the decision logic that generates a precharge (PRE) command on the main data interface. If the refresh scheduler determines that the bank pair is idle, it proceeds to refresh the bank pair, and the adaptive precharge scheduler and refresh scheduler may use the normal REFpb command to complete one complete refresh cycle, thereby avoiding the REFab blackout that would otherwise occur.

[0009] By adding adaptive precharge intelligence, a single interface handles the scheduling of both normal traffic and precharge (PRE) in support of per-bank refresh, protecting the system from conflicting decisions that could occur if the refresh scheduler independently scheduled precharge without considering the current traffic-based decisions made by the demand scheduler.

[0010] The adaptive precharge scheduler can constantly identify the status (open / closed) of each DRAM bank. All other things being equal, it is preferable to select a bank pair that is already closed to refresh. Thus, a single DRAM bank (out of a bank pair where one bank is already in a closed state) can preemptively become closed, taking into account the traffic conditions to that bank pair, in order to assist in issuing refreshes to that bank pair.

[0011] The adaptive precharge scheduler also tracks the number of transactions with priority bits set for each DRAM bank. All things being equal, it is desirable to avoid sending refresh commands to banks with priority transactions. This results in not precharging a bank pair with a priority request, and instead a different bank is selected and the refresh scheduler is instructed to issue a refresh command (e.g., REFpb) to the different bank pair.

[0012] The adaptive precharge scheduler also ensures that a bank pair is not active during the period in which it selectively precharges a bank or bank pair to prepare it for the refresh scheduler to issue a refresh command (e.g., REFpb) to the bank pair. The memory controller can include a custom interface that enables this communication between the adaptive precharge scheduler and the refresh scheduler.

[0013] In general, one innovative aspect of the subject matter described herein may be embodied in a memory controller including a refresh scheduler configured to send refresh commands to DRAM banks of a dynamic random access memory (DRAM) memory system including DRAM banks arranged in a set of DRAM banks, each of the set of DRAM banks including one or more DRAM banks. The memory controller includes an adaptive precharge scheduler configured to determine a priority score for each of the DRAM banks based on a set of parameters including at least one of (i) one or more status parameters indicative of a status of the one or more DRAM banks, or (ii) one or more traffic condition parameters indicative of a characteristic of data traffic of the one or more DRAM banks, and to select and close a particular DRAM bank group based on the priority score for the DRAM bank group so that each DRAM bank in the DRAM bank group can be refreshed by the refresh scheduler, and to send a precharge command to at least one DRAM bank of the particular DRAM bank. Other implementations of this aspect include corresponding methods, apparatus, and systems.

[0014] These and other embodiments may each optionally include one or more of the following features: In some aspects, the refresh scheduler is configured to detect that the at least one DRAM bank is closed and to send a refresh command to the at least one DRAM bank in response to detecting that the at least one DRAM bank is closed. In some aspects, detecting that the at least one DRAM bank is closed includes receiving data from the adaptive precharge scheduler indicating that the at least one DRAM bank is closed.

[0015] In some aspects, the one or more status parameters for each DRAM bank group include a parameter indicating a number of DRAM banks of the DRAM banks group that are open. The one or more traffic condition parameters for each DRAM bank group can include a number of memory requests received for the DRAM banks group. The one or more traffic condition parameters for each DRAM bank group can include a number of priority memory requests received for the DRAM banks group. The one or more traffic condition parameters for each DRAM bank group can include a number of memory request conflicts detected for the DRAM banks group. The one or more traffic condition parameters for each DRAM bank group can include a number of priority memory request conflicts detected for the DRAM banks group.

[0016] In some aspects, the priority score for each group of DRAM banks is represented by a score vector that orders the set of parameters in the score vector based on the relative importance of each parameter. In some aspects, the one or more status parameters for each group of DRAM banks include a refresh status that indicates whether the DRAM bank is in an advance phase, a postpone phase, or is nearing a refresh deadline for the DRAM bank.

[0017] Another innovative aspect of the subject matter described herein may be embodied in methods that include: sending, by a refresh scheduler of a memory controller, refresh commands to DRAM banks of a dynamic random access memory (DRAM) memory system, the DRAM memory system including DRAM banks arranged in a set of DRAM bank groups, each set of DRAM bank groups including one or more DRAM banks; determining, by an adaptive precharge scheduler of the memory controller, a priority score for each DRAM bank group based on a set of parameters including at least one of (i) one or more status parameters indicative of a status of the one or more DRAM banks or (ii) one or more traffic condition parameters indicative of a characteristic of data traffic of the one or more DRAM banks; selecting and closing certain DRAM banks by the adaptive precharge scheduler and based on the priority score for each DRAM bank group such that each DRAM bank in the DRAM bank group can be refreshed by the refresh scheduler; and sending, by the adaptive precharge scheduler, a precharge command to at least one DRAM bank of the particular DRAM group. Other implementations of this aspect include corresponding apparatus, systems, and computer programs configured to perform aspects of the methods encoded on computer storage devices.

[0018] These and other embodiments may each optionally include one or more of the following features. Some aspects may include detecting, by a refresh scheduler, that the at least one DRAM bank is closed and sending a refresh command to the at least one DRAM bank in response to detecting that the at least one DRAM bank is closed. In some aspects, detecting that the at least one DRAM bank is closed includes receiving data from an adaptive precharge scheduler indicating that the at least one DRAM bank is closed.

[0019] In some aspects, the one or more status parameters for each group of DRAM banks include a parameter indicative of a number of open DRAM banks of the group of DRAM banks. In some aspects, the one or more traffic condition parameters for each group of DRAM banks include a number of memory requests received for the group of DRAM banks. The one or more traffic condition parameters for each group of DRAM banks can include a number of priority memory requests received for the group of DRAM banks. The one or more traffic condition parameters for each group of DRAM banks can include a number of memory request conflicts detected for the group of DRAM banks. The one or more traffic condition parameters for each group of DRAM banks can include a number of priority memory request conflicts detected for the group of DRAM banks.

[0020] In some aspects, the priority score for each group of DRAM banks is represented by a score vector that orders the set of parameters in the score vector based on the relative importance of each parameter. In some aspects, the one or more status parameters for each group of DRAM banks include a refresh status that indicates whether the DRAM bank is in an advance phase, a postpone phase, or is nearing a refresh deadline for the DRAM bank.

[0021] The subject matter described herein may be implemented in certain embodiments to achieve one or more of the following advantages: The memory controller may include an adaptive precharge scheduler that obtains information about the DRAM banks and uses that information to intelligently issue PRE commands to assist in REFpb refresh, thereby reducing the number of REFab commands that stall traffic to all DRAM banks of the DRAM system. This improves performance, including bandwidth efficiency, of the DRAM system by reducing the percentage of time that the DRAM banks are inaccessible for refresh. This also improves performance of applications and / or hardware comments that use the data by significantly reducing the latency in accessing data stored in the DRAM that would otherwise occur during all bank refresh. Using a single interface to handle both normal memory traffic and precharge to assist in per-bank refresh prevents conflicting decisions that may otherwise occur if the refresh scheduler independently schedules precharge without considering the current traffic-based decision made by the request scheduler. For example, this prevents the request scheduler from opening a row of a DRAM bank to access data immediately after the adaptive precharge scheduler closes the DRAM bank to refresh the bank. Preventing this conflicting action increases the likelihood that each DRAM bank can be refreshed in each refresh cycle without the need to refresh the entire bank.

[0022] Various features and advantages of the foregoing subject matter are described below with reference to the drawings. Additional features and advantages will be apparent from the subject matter described herein and from the claims. [Brief description of the drawings]

[0023] [Figure 1A]1 illustrates an exemplary memory system in which a memory controller controls access to a DRAM and refreshes DRAM cells of the DRAM. [Figure 1B] 1B illustrates the exemplary DRAM of FIG. 1A. [Diagram 2] 4 is a flow chart of an exemplary process for refreshing a DRAM cell. [Diagram 3] 1 is a graph illustrating improved bandwidth efficiency using a traffic-aware adaptive precharge scheduler. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Like reference symbols and designations in the various drawings indicate like elements. FIG. 1A illustrates an exemplary memory system 100 in which a memory controller 110 controls access to a DRAM 150 and refreshes DRAM cells of the DRAM 150. The DRAM may include multiple DRAM banks, each of which includes one or more rows of DRAM cells. Each row may include multiple DRAM cells. A DRAM cell typically includes an access transistor and a capacitor for storing a value of a bit of data, e.g., a value of 1 when charged and a value of 0 when discharged. The DRAM 150 may be implemented as a low power double data rate (LPDDR) DRAM or other suitable type of DRAM. Although the exemplary memory system 100 includes a DRAM, the memory system 100 and its components and functions may be implemented in other types of memory that require refreshing.

[0025] Each DRAM bank can be arranged as a two-dimensional array of DRAM cells having multiple rows and columns. A DRAM row can also be referred to as a DRAM page. The DRAM banks can be arranged in groups that are refreshed together as a group. For example, the DRAM banks can be arranged as bank pairs, where each bank pair includes two DRAM banks.

[0026] 1B, an exemplary DRAM 150 includes "N" DRAM bank pairs 155-1 through 155-N. Each DRAM bank pair 155 includes two DRAM banks 156-1 and 156-2, with each DRAM bank including DRAM cells 156 arranged in eight rows 157-1 through 157-8 and eight columns. In other examples, the DRAM 150 may include a single DRAM bank or a collection of DRAMs each having more than two DRAM banks, and / or each DRAM bank may include a different number of rows and / or a different number of columns. For example, another DRAM system may have DRAM bank pairs including 16×16 DRAM banks, 32×32 DRAM banks, or other suitable sizes of DRAM banks.

[0027] 1A, memory controller 110 includes refresh scheduler 112, bank status module 114, transaction buffer 116, request scheduler 118, and adaptive precharge scheduler 120. Of course, memory controller 110 and memory system 100 may include additional components not shown in FIG. 1, such as decoders, address buffers, registers, etc.

[0028] Transaction buffer 116 receives incoming requests to read data from and write data to DRAM 150 and temporarily stores those requests. For example, the requests may be received from a central processing unit (CPU), a graphics processing unit (GPU), or another type of processor or component, such as via a memory bus or other interface connecting the processor or component to memory system 100.

[0029] An incoming request may have a corresponding priority level, for example, at which the request is provided. For example, the processor may send to memory controller 110 a request that includes a command to read data from or write data to DRAM 150 and a priority level that corresponds to the request. The priority level may be represented by a number in a numerical range (e.g., 0 to 10) or another suitable range, or as a particular level, for example, low, medium, or high. In another example, the processor may label some requests as priority requests and either label non-priority requests as low priority requests or not include a label for non-priority requests.

[0030] A request scheduler 118 monitors the transaction buffer 116 for incoming requests that are buffered in the transaction buffer 116. The request scheduler 118 also generates and transmits requests to access DRAM cells of the DRAM 150, such as requests to read data from the DRAM cells and requests to write data to the DRAM cells. In some DRAM systems, an access to the DRAM 150 typically includes an activate (ACT) command to open a row of a DRAM bank, a column COL read or write command to perform a read / write operation on a subset of the DRAM cells in the row, and a precharge (PRE) command to close the row. Once a row is open, it can be accessed multiple times through a series of COL commands. Once a row is closed using the PRE command, it can be reopened using the ACT command so that the row can be accessed again.

[0031] The bank status module 114 can maintain a status of each DRAM bank and / or row of banks. As described above, the DRAM banks can be arranged as bank pairs. The status of a bank pair can indicate whether one of the DRAM banks of the bank pair is open. For example, the status can be a bit having a first value (e.g., one) if one DRAM bank is open and a second value (e.g., zero) if either both DRAM banks are open or both DRAM banks are closed. In another example, the status can indicate the number of banks that are open (e.g., zero, one, or two).

[0032] The bank status module 114 can be updated by the request scheduler 118. For example, the request scheduler 118 can forward a request to the bank status module 114, which can update the status of a DRAM bank, bank pair, or row based on the request. For example, if the request is an ACT command for a row, the bank status module 114 can update the status of the row and the DRAM bank that contains the row to a status of "open". The bank status module 114 can determine which DRAM banks are currently open and how many DRAM banks are open in the bank pair that contains the row, and update the status of the bank pair based on the determined number. The status information for DRAM bank "b" is represented as "bank_status[b]".

[0033] Refresh scheduler 112 schedules refreshes and issues refresh commands (e.g., REFpb and REFab) to DRAM banks of DRAM 150. As described above, the REFpb command is a command to refresh a particular DRAM bank "b" or pair of banks, and the REFab command is a command to refresh all banks of DRAM 150 in memory system 100. In general, refresh scheduler 112 issues REFpb commands to DRAM banks that are closed during the refresh interval of DRAM 150 to eliminate or delay the need to issue REFab commands to refresh all banks. When issuing REFpb commands to pairs of banks, refresh scheduler 112 may issue REFpb commands to pairs of banks where both banks are closed.

[0034] Refresh scheduler 112 may be configured to identify DRAM banks that are closed based on the status of the DRAM banks and issue REFpb commands to the banks that are closed during a refresh interval. If refresh scheduler 112 successfully refreshes all banks of DRAM 150 using REFpb commands during a refresh interval, refresh scheduler 112 may not need to issue REFab commands to the DRAM during that refresh interval and may move on to the next refresh interval. Refresh scheduler 112 may not issue refresh commands to banks that are open because they may be in the process of being accessed.

[0035] Adaptive precharge scheduler 120 can close a DRAM bank, e.g., proactively, so that refresh scheduler 112 can refresh the DRAM bank using a REFpb command. In some implementations, adaptive precharge scheduler 120 can close a DRAM bank or bank pair of DRAM 150 by issuing a PRE command to the bank or bank pair, or to each row of the bank or bank pair that is open. Once closed, refresh scheduler 112 can issue a REFpb command to the DRAM bank or bank pair.

[0036] The adaptive precharge scheduler 120 and the refresher scheduler 112 can communicate through an interface, for example a custom interface that can be implemented using conductors of a chip that includes a memory controller. The adaptive precharge scheduler 120 can use the interface to notify the refresh scheduler 112 when it closes a DRAM bank or bank pair. In another example, the adaptive precharge scheduler 120 can update the status of the bank with the bank status module 114. In this example, the refresh scheduler 112 can detect that the DRAM bank or bank pair is closed (or that the DRAM bank or bank pair was recently closed) and issue a REFpb command to the DRAM bank or bank pair.

[0037] The adaptive precharge scheduler 120 can issue and / or schedule PRE commands to DRAM banks or bank pairs based on the priority scores of the banks or bank pairs. The adaptive precharge scheduler 120 includes a scoring module 122 that determines the priority scores, and a PRE request generator 124 that selects the DRAM banks for precharging and sends PRE commands to the DRAM banks.

[0038] The scoring module 122 may determine a priority score for a DRAM bank or bank pair based on, for example, traffic conditions of the DRAM bank or bank pair. For ease of subsequent description, the priority scores are described with reference to bank pairs, although the same or similar scoring may be used for a single DRAM bank or a group of DRAM banks including more than two DRAM banks.

[0039] The adaptive precharge scheduler 120 can interface with the transaction buffer 116, for example using a data communication interface implemented using one or more conductors, to obtain information regarding the status of the bank pair and the traffic conditions of the bank pair and generate parameters for the bank pair. The scoring module 122 can determine a priority score for the bank pair based on the parameters related to the status and / or traffic conditions.

[0040] One exemplary parameter that may be used to determine the priority score of a bank pair is the number of requests received by memory controller 110 for the DRAM banks of the bank pair. Adaptive precharge scheduler 120 may monitor requests received by transaction buffer 116 to determine, for example, the number of requests received to access the bank pair over a particular period of time. The period of time may be a running period of time, for example, the previous second, the previous 10 seconds, the previous minute, or another suitable period of time. The number of requests received over a period of time is a traffic condition that indicates the level of activity of the DRAM banks in the bank pair. Adaptive precharge scheduler 120 may determine the number of requests for a DRAM bank by keeping a count of the number of requests received for the DRAM bank over a particular period of time. The number of requests is represented in FIG. 1A as “hits[b]” for the DRAM bank with bank identifier “b”. Adaptive precharge scheduler 120 may determine the number of requests per bank pair over a particular period of time by monitoring the number of requests per DRAM bank and determining a sum of the number for each DRAM bank of the bank pair.

[0041] The number of requests allows adaptive precharge scheduler 120 to distinguish between low and high activity bank pairs, for example, the lower the number of requests, the more likely adaptive precharge scheduler 120 will select the bank pair for precharging.

[0042] Referring to FIG. 1B, if the number of requests received to access DRAM cells 158 of bank pair 155-2 is greater than the number of requests to access DRAM cells of bank pair 155-1, the priority score of bank pair 155-1 may be greater than the priority score of bank pair 155-2, for example, all other parameters of bank pairs 155-1 and 155-2 being equal.

[0043] Another parameter that can be used to determine the priority score of a bank pair is the number of priority requests received by the memory controller 110 for the DRAM banks of the bank pair. A priority request can be a request identified by the processor as a priority request or a request with a corresponding priority level that meets a threshold. For example, if a numeric range is used, a priority request can be a request with a priority level of at least 5, where the range is from zero to 10, with 10 being the highest level. The number of priority requests received over a period of time is a traffic condition parameter that indicates the level of high priority activity for the DRAM bank. The adaptive precharge scheduler 120 can monitor requests received by the transaction buffer 116 to determine the number of priority requests received to access the bank pair, for example, over a particular period of time. The adaptive precharge scheduler 120 can determine the number of priority requests for a DRAM bank by keeping a count of the number of priority requests received for the DRAM bank during a particular period of time. The number of priority requests is represented in FIG. 1A as “priority_hits[b]” for the DRAM bank with bank identifier “b.” The adaptive precharge scheduler 120 can determine the number of requests per bank pair over a particular period of time by monitoring the number of requests per DRAM bank and determining the sum of the numbers for each DRAM bank of the bank pair.

[0044] Another parameter that can be used to determine the priority score of a bank pair is the number of conflicts detected by the adaptive precharge scheduler 120 for the DRAM banks of the bank pair. The number of conflicts represents the number of requests for accessing the DRAM banks of the bank pair that conflict with each other, e.g., received over a certain period of time. An example of a conflict is, for example, two requests that are to request access to two different rows of the same DRAM bank at the same time or within such a short period of time that the row of the first arriving request is still open when the subsequent request is received. In some DRAM systems, only one row of a DRAM bank can be open at a time. In this example, if the two requests are to request two different rows of the same DRAM bank to be open at the same time, a conflict exists and only one of the two requests can be processed at a time. For example, referring to FIG. 1B, if a first request is to access data stored in row 157-4 of bank pair 155-1 and a second request is to access data stored in row 157-8 of bank pair 155-1, these two requests are considered to be conflicting requests.

[0045] Adaptive precharge scheduler 120 can detect conflicts by determining which row of each DRAM bank each request is requesting access to and comparing those rows to other requests. For example, if two requests request access to different rows of the same DRAM bank within a given period, adaptive precharge scheduler 120 can determine that a conflict exists for the DRAM bank. In another example, if a request is received to access a row of a DRAM bank where a different row is open, adaptive precharge scheduler 120 can determine that a conflict exists for the DRAM bank upon receiving the request.

[0046] The adaptive precharge scheduler 120 may also determine the number of conflicts and / or the number of priority conflicts detected per bank pair, e.g., over a particular period of time. The number of bank pair conflicts over a period of time and the number of priority conflicts over a period of time are traffic condition parameters. The adaptive precharge scheduler 120 may determine the number of conflicts for a DRAM bank by keeping a count of the number of conflicts detected by the adaptive precharge scheduler 120 for a DRAM bank over a particular period of time. Similarly, the adaptive precharge scheduler 120 may determine the number of priority conflicts for a DRAM bank by keeping a count of the number of conflicts involving at least one priority request among the conflicting requests detected by the adaptive precharge scheduler 120 for a DRAM bank over a particular period of time. The number of conflicts is represented in FIG. 1A as “conflicts[b]” for DRAM bank “b” and the number of priority conflicts is represented in FIG. 1A as “priority_conflicts[b]” for DRAM bank “b”. The adaptive precharge scheduler 120 can determine the number of conflicts for a bank pair by determining the sum of the number of conflicts for each DRAM bank in the bank pair. Similarly, the adaptive precharge scheduler 120 can determine the number of priority conflicts for a bank pair by determining the sum of the number of priority conflicts for each DRAM bank in the bank pair.

[0047] The number of conflicts can play an important role in determining which bank pairs need to be precharged. For example, the bank pair with the highest number of conflicts can be selected for precharge among a set of bank pairs that have received few or no requests.

[0048] The specific time periods for various parameters can be the same or different, for example, the time period for counting the number of request parameters can be the same as or different from the time period for counting the number of conflict parameters.

[0049] An exemplary status parameter that can be used to determine the priority score of a bank pair is whether one of the DRAM banks of the bank pair is open. As described above, this status information can be obtained from the bank status module 114. At any time, a bank pair can be in three configurations: both banks open, both banks closed, or only one bank open. If any row of the bank is open, the bank can be considered open. In general, the adaptive precharge scheduler 120 may not or cannot send a precharge command to a bank that is closed because the bank is already closed. If both banks are open, this may involve the issuance of two PRE commands, and if one bank is open, this involves only one PRE command, among two other cases. Issuing a PRE command to a bank pair with one bank open may require less time than issuing a PRE command to a bank pair with two banks open, because two PRE commands may require more time than one PRE command. Therefore, by selecting a bank pair in which one bank is open, it is possible to reduce the latency when issuing a refresh command.

[0050] Another status parameter that can be used to determine the priority score of a bank pair is the refresh status of each DRAM bank of the bank pair. The refresh status can indicate, for example, whether the DRAM bank is in an early loading phase, a late loading phase, or is close to the refresh deadline of the DRAM bank within a threshold time that needs to be refreshed per the applicable DRAM standard. Refresh scheduler 118 can provide data indicative of the refresh status of each DRAM bank to adaptive precharge scheduler 120, for example, via a custom interface between refresh scheduler 118 and adaptive precharge scheduler 120.

[0051] The scoring module 122 may determine a priority score for each bank pair based on one or more of the traffic condition parameters and / or one or more of the status conditions of the bank pair. The scoring module 122 may use any combination of these parameters to determine the priority score for the bank pair. The scoring module 122 may determine the priority score for the bank pair using a weighted combination of the parameters. In this example, each parameter may be represented as an individual score, and each of the individual scores may be weighted based on its relative importance in determining the priority score. The scoring module 122 may determine a weighted score for the parameters by determining a product of the individual scores and their corresponding weights. The scoring module 122 may then determine the priority score by aggregating, e.g., averaging, the weighted scores for the parameters. To obtain the individual scores, the scoring module 122 may convert the various parameters of the bank pair into numerical values ​​that represent the parameters if the parameters are not already represented using numbers.

[0052] In some implementations, the priority score for a bank pair is represented by a score vector, with each parameter represented by a vector. The binary value (or converted decimal value) of the score vector can be the priority score or directly proportional to the priority score. An example of a 13-bit score vector for a bank pair is shown in Table 1 below:

[0053] [Table 1]

[0054] In this example, a higher number of bits represent more significant bits in the priority score represented by the score vector, and therefore represent a higher priority parameter of the priority score. That is, in this example, the number of priority requests has a greater impact on the priority score than each of the other parameters in the score vector. The single bit for one bank status open can have a value of 1 if one DRAM bank in the bank pair is open, and a value of 0 if either both banks are open or both banks are closed.

[0055] The memory controller 110 can use other arrangements of parameters in the score vector. For example, the score vector can include one or more additional bits to represent whether any DRAM bank in a bank pair is in the prepone stage, the postpone stage, or a request to refresh the bank is imminent. In another example, the parameters can be reordered in the score vector so that other parameters have a greater impact on the priority score. For example, the number of conflicts, if it is the highest priority parameter, can be represented by bits 12 and 11. The arrangement of parameters and the parameters included in the score vector can vary based on the implementation or use case.

[0056] The scoring module 122 may continuously or periodically determine the priority scores of the bank pairs and provide those priority scores to the PRE request generator 124. The priority scores of the banks are represented as “Score[b]” in FIG.

[0057] The PRE request generator 124 includes a scheduling module 126 that can select a next bank pair for sending a PRE command based on the priority score. For example, the scheduling module 126 can determine a schedule of the bank pairs for precharging based on the priority scores of the bank pairs. The schedules can be ordered from highest priority score to lowest priority score. For example, the PRE request generator 124 can issue a PRE command to each DRAM bank of the bank pair having the highest priority score.

[0058] As described above, the PRE command closes a row of DRAM banks. The refresh scheduler 112 can then send a refresh command, such as a REFpb command, to the closed DRAM bank pair to refresh the DRAM bank pair.

[0059] In some implementations, the adaptive precharge scheduler 120 can select one or more bank pairs for sending a PRE command based on one or more of the traffic condition parameters and / or the status parameters, for example, without determining a score and / or without ranking or ordering the bank pairs. The adaptive precharge scheduler 120 can always access each DRAM bank whether it is open or closed. All other parameters being equal, it may be advantageous to select a DRAM bank that is already closed. Thus, the PRE request generator 124 can preemptively send a PRE command to a bank pair whose DRAM bank is already closed in consideration of the traffic condition to close the single DRAM bank of the bank pair to assist in issuing a refresh to the bank pair.

[0060] It may also be advantageous to avoid sending refresh commands to DRAM banks with priority transactions. Adaptive precharge scheduler 120 can use the number of priority requests to avoid precharging bank pairs with priority requests and instead select a different bank pair. Adaptive precharge scheduler 120 can instruct refresh scheduler 112 to refresh a different bank pair.

[0061] Also, during the period when adaptive precharge scheduler 120 is selectively precharging a bank or bank pair and is ready to issue a refresh for that bank pair, adaptive precharge scheduler 120 can ensure that an activate command does not go through the DRAM bank. For example, adaptive precharge scheduler 120 can instruct request scheduler 118 not to send an activate command to the DRAM bank during that period or until adaptive precharge scheduler 120 indicates, e.g., via a communication interface between adaptive precharge scheduler 120 and request scheduler 118, that it has completed the refresh of the DRAM bank. In another example, adaptive precharge scheduler 120 can block the activate command from reaching the DRAM bank until it has completed the refresh, e.g., by communicating with logic (not shown) downstream from request scheduler 118.

[0062] 2 is a flow chart of an example process 200 for refreshing DRAM cells. Process 200 may be performed by a memory controller of a DRAM system, such as memory controller 110 of FIG. 1A. The DRAM may include DRAM banks arranged in DRAM bank groups, with each DRAM bank group including one or more DRAM banks. For example, each DRAM bank group may be a bank pair, as described above.

[0063] An adaptive precharge scheduler, such as adaptive precharge scheduler 120 of FIG. 1, obtains traffic and / or status information for each DRAM bank of the DRAM system (202). This information may include a set of parameters. The set of parameters may include, for example, one or more status parameters indicative of a status of one or more DRAM banks and / or one or more traffic condition parameters indicative of a characteristic of data traffic for one or more DRAM banks.

[0064] As described above, the status parameter may indicate the number of DRAM banks that are open within the group of DRAM banks. The traffic condition parameters may include the number of requests received for the group of DRAM banks, the number of priority requests received for the group of DRAM banks, the number of conflicts detected for the group of DRAM banks, and / or the number of priority conflicts detected for the group of DRAM banks. These traffic condition parameters may be determined for a particular period of time, such as the previous second, the previous 10 seconds, the previous minute, or another suitable period of time.

[0065] The adaptive precharge scheduler determines a priority score for each DRAM bank (204). The adaptive precharge scheduler may determine the priority scores for the DRAM banks based on a set of parameters for the DRAM banks. As noted above, in some implementations, the adaptive precharge scheduler generates a score vector representing the priority scores for the group of DRAM banks. In another example, the adaptive precharge scheduler may determine a weighted combination of the parameters, e.g., a weighted average of the parameters, as the priority score for the group of banks.

[0066] The adaptive precharge scheduler selects the DRAM banks (206). The adaptive precharge scheduler may select and close the DRAM banks such that a DRAM bank(s) of the DRAM banks can be refreshed by a refresh scheduler, e.g., refresh scheduler 112 of FIG. 1A. The adaptive precharge scheduler may select the DRAM banks based on the priority scores of the DRAM banks. For example, the adaptive precharge scheduler may select the DRAM banks with the highest priority scores.

[0067] The adaptive precharge scheduler sends a precharge command to at least one DRAM bank of the selected group of DRAM banks (208). The adaptive precharge scheduler may send a precharge command to each DRAM bank or each row that is open in the selected group of DRAM banks. For example, if only one DRAM bank of a selected group of DRAM banks having multiple DRAM banks is open, the adaptive precharge scheduler may send a precharge command only to the DRAM bank that is open. In another example, if a proper subset of rows of DRAM banks of a group of DRAM banks are open, the adaptive precharge scheduler may send a precharge command to each row in the proper subset, for example, without sending a precharge command to any closed rows of the group of DRAM banks.

[0068] The adaptive precharge scheduler or refresh scheduler sends a refresh command to the selected group of DRAM banks (210). The refresh command can be sent to each DRAM bank in the group of DRAM banks. For example, the refresh scheduler can detect that a DRAM bank(s) of the group of DRAM banks is closed and issue a refresh command to the DRAM bank(s) in response to detecting that they are closed. In another example, the adaptive precharge scheduler can notify the refresh scheduler that a DRAM bank pair is ready for refresh and in response to receiving the notification, the refresh scheduler can issue a refresh command to the DRAM bank(s).

[0069] 3 is a graph 300 illustrating improved bandwidth efficiency using a traffic-aware adaptive precharge scheduler. Graph 300 illustrates the relative bandwidth efficiency of a DRAM system for various types of traffic when refresh is disabled, when refresh is enabled without adaptive precharge scheduling, and when refresh is enabled with adaptive precharge scheduling. In particular, the left bar 301 for each traffic type represents the bandwidth efficiency when refresh is disabled, the center bar 302 for each traffic type represents the bandwidth efficiency when refresh is enabled without adaptive precharge scheduling, and the right bar 303 for each traffic type represents the bandwidth efficiency when refresh is enabled with adaptive precharge scheduling.

[0070] As shown in this graph 300, when refresh is disabled and memory cells never need to be refreshed, the bandwidth is highest because there are no blackout periods during which memory cells cannot be accessed, which is not possible in DRAM memory systems or other memory systems that require refresh. Using adaptive precharge scheduling as described above improves bandwidth efficiency when refresh is required compared to not using adaptive precharge scheduling for most types of traffic represented by graph 300.

[0071] Bandwidth efficiency is an important metric in determining the performance of a memory controller. Bandwidth efficiency can be determined by dividing the total bandwidth by the peak bandwidth. The total bandwidth can be the sum of the read bandwidth and the write bandwidth. The read bandwidth can be determined as the product of the number of read transactions and the size of the data of the transaction divided by the total time required to process the transaction. Similarly, the write bandwidth can be determined as the product of the number of write transactions and the size of the data of the transaction divided by the total time required to process the transaction. Peak bandwidth refers to the maximum bandwidth that can be achieved during a particular operating mode of a given memory type.

[0072] The subject matter and functional operations described herein may be implemented in digital electronic circuitry, in tangibly embodied computer software or firmware, in computer hardware including the structures disclosed herein and structural equivalents thereof, or in one or more combinations thereof. The subject matter described herein may be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a tangible, non-transitory program carrier for execution by or control of the operation of a data processing apparatus. Alternatively, or additionally, the program instructions may be encoded in an artificially generated propagated signal, e.g., a mechanically generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to a receiving device suitable for execution by the data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or one or more combinations thereof.

[0073] The processes and logic flows described herein may be performed by one or more programmable computers running one or more computer programs to perform functions by performing operations on input data to generate output. The processes and logic flows may also be performed by, and apparatus may be implemented as, special purpose logic circuitry, such as a field programmable gate array (FPGA), or an application specific integrated circuit (ASIC), or a general purpose graphics processing unit (GPGPU).

[0074] A computer suitable for executing a computer program can include, for example, be based on, a general-purpose or dedicated microprocessor or both, or any other type of central processing unit. Typically, the central processing unit receives instructions and data from a read-only memory, a random access memory, or both. The basic elements of a computer are a central processing unit for implementing and executing instructions, and one or more memory devices for storing instructions and data. Typically, a computer also includes one or more mass storage devices, such as magnetic disks, magneto-optical disks, or optical disks, for storing data, or is operatively connected to receive data from or transmit data to, or both. However, such devices are not required for a computer. Furthermore, a computer can be embedded in other devices, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device, such as a universal serial bus (USB) flash drive, to name a few examples.

[0075] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices, magnetic disks such as internal hard disks or removable disks, magneto-optical disks, and CD-ROM and DVD-ROM disks. The processor and the memory may be supplemented by, or incorporated in, special purpose logic circuitry.

[0076] Although the present specification contains many specific implementation details, these should not be construed as limiting the scope or claimable content of any invention, but as descriptions of features that may be inherent to a particular embodiment of a particular invention. Certain features described in the context of separate embodiments herein may also be implemented in combination in a single embodiment. Conversely, various features of the invention described in the context of a single embodiment may also be provided in multiple embodiments separately or in any suitable subcombination. Furthermore, even if features may be described above as functioning in a particular combination and originally claimed as such, one or more features from the claimed combination may in some cases be deleted from the combination, and the claimed combination may be directed to a subcombination or a variation of the subcombination.

[0077] Similarly, although operations are shown in a particular order in the figures, this should not be understood as requiring that such operations be performed in the particular order or sequential order shown, or that all of the operations shown be performed, to achieve desirable results. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the program components and systems described may generally be integrated into a single software product or packaged into multiple software products.

[0078] Specific embodiments of the present invention have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims may be performed in a different order and still achieve desirable results. By way of example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

Claims

1. 1. A memory controller, comprising: a refresh scheduler configured to send refresh commands to dynamic random access memory (DRAM) banks of a DRAM memory system; the DRAM memory system includes DRAM banks arranged in a set of DRAM bank groups, each of the DRAM bank groups including one or more DRAM banks; The memory controller includes: further comprising an adaptive precharge scheduler; The adaptive precharge scheduler comprises: determining a priority score for each group of DRAM banks based on a set of parameters including at least one of: (i) one or more status parameters indicative of a status of the one or more DRAM banks; or (ii) one or more traffic condition parameters indicative of a characteristic of data traffic of the one or more DRAM banks; selecting and closing certain groups of DRAM banks so that each DRAM bank in the group of DRAM banks can be refreshed by the refresh scheduler based on a priority score for each group of DRAM banks; sending a precharge command to at least one DRAM bank of the particular group of DRAM banks.

2. the refresh scheduler detecting that the at least one DRAM bank is closed; in response to detecting that the at least one DRAM bank is closed, sending a refresh command to the at least one DRAM bank; The memory controller of claim 1 configured to:

3. 3. The memory controller of claim 2, wherein detecting that the at least one DRAM bank is closed comprises receiving data from the adaptive precharge scheduler indicating that the at least one DRAM bank is closed.

4. 4. The memory controller according to claim 1, wherein the one or more status parameters for each DRAM bank group include a parameter indicating a number of open DRAM banks in the DRAM bank group.

5. The memory controller of claim 1 , wherein the one or more traffic condition parameters for each group of DRAM banks comprises a number of memory requests received for the group of DRAM banks.

6. The memory controller of claim 1 , wherein the one or more traffic condition parameters for each group of DRAM banks comprises a number of priority memory requests received for the group of DRAM banks.

7. 7. The memory controller of claim 1, wherein the one or more traffic condition parameters for each group of DRAM banks include a number of memory request conflicts detected for the group of DRAM banks.

8. 8. The memory controller of claim 1, wherein the one or more traffic condition parameters for each group of DRAM banks comprises a number of priority memory request conflicts detected for the group of DRAM banks.

9. 9. The memory controller of claim 1, wherein the priority score for each group of DRAM banks is represented by a score vector, and the set of parameters within the score vector is ordered based on the relative importance of each parameter.

10. 10. The memory controller of claim 1, wherein the one or more status parameters for each group of DRAM banks include a refresh status indicating whether the DRAM bank is in an advance phase, an advance phase, or is nearing a refresh deadline for the DRAM bank.

11. 1. A method comprising: sending refresh commands to dynamic random access memory (DRAM) banks of the DRAM memory system by a refresh scheduler of the memory controller; the DRAM memory system includes DRAM banks arranged in a set of DRAM bank groups, each of the DRAM bank groups including one or more DRAM banks; The method comprises: determining, by an adaptive precharge scheduler of the memory controller, a priority score for each group of DRAM banks based on a set of parameters including at least one of: (i) one or more status parameters indicative of a status of the one or more DRAM banks; or (ii) one or more traffic condition parameters indicative of a characteristic of data traffic of the one or more DRAM banks; selecting, by the adaptive precharge scheduler, to close certain groups of DRAM banks based on a priority score for each of the groups of DRAM banks so that each DRAM bank in the groups of DRAM banks can be refreshed by the refresh scheduler; The method further comprising sending, by the adaptive precharge scheduler, a precharge command to at least one DRAM bank of the particular group of DRAM banks.

12. detecting, by the refresh scheduler, that the at least one DRAM bank is closed; 12. The method of claim 11, further comprising: in response to detecting that the at least one DRAM is closed, sending a refresh command to the at least one DRAM bank.

13. 13. The method of claim 12, wherein detecting that the at least one DRAM bank is closed comprises receiving data from the adaptive precharge scheduler indicating that the at least one DRAM bank is closed.

14. The method of any one of claims 11 to 13, wherein the one or more status parameters for each group of DRAM banks includes a parameter indicative of a number of open DRAM banks in the group of DRAM banks.

15. The method of any one of claims 11 to 14, wherein the one or more traffic condition parameters for each group of DRAM banks comprises a number of memory requests received for the group of DRAM banks.

16. The method of any one of claims 11 to 15, wherein the one or more traffic condition parameters for each group of DRAM banks comprises a number of priority memory requests received for the group of DRAM banks.

17. The method of any one of claims 11 to 16, wherein the one or more traffic condition parameters for each group of DRAM banks comprises a number of memory request conflicts detected for the group of DRAM banks.

18. The method of any one of claims 11 to 17, wherein the one or more traffic condition parameters for each group of DRAM banks comprises a number of priority memory request conflicts detected for the group of DRAM banks.

19. The method of any one of claims 11 to 18, wherein the priority score for each group of DRAM banks is represented by a score vector, and the set of parameters within the score vector is ordered based on the relative importance of each parameter.

20. 20. The method of claim 11, wherein the one or more status parameters for each group of DRAM banks include a refresh status indicating whether the DRAM bank is in an advance phase, a postpone phase, or is approaching a refresh deadline for the DRAM bank.

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