Heteroepitaxial wafers for depositing gallium nitride

Abstract

A heteroepitaxial wafer comprising: (1) a substrate made of silicon having a thickness diameter and resistivity and including an embedded gettering layer of hydrogen; (2) a 3C-SiC layer; and (3) an aluminum nitride nucleation layer including, in a predetermined order, a first nitrogen-rich aluminum nitride region, an aluminum nitride region, and a second nitrogen-rich aluminum nitride region.

Description

[Technical field]

[0001] The present invention relates to a heteroepitaxial wafer optimized for the deposition of gallium nitride thereon. [Background technology]

[0002] 2. Description of Related Art Gallium nitride (GaN) offers several fundamental advantages over silicon. In particular, its higher critical electrical breakdown field is highly attractive for power semiconductor devices with significant specific dynamic on-state resistance and smaller capacitance compared to silicon MOSFETs. GaN HEMTs are therefore superior for high speed switching. This allows for higher operating frequencies, improving power density as well as overall system efficiency, not only because of the resulting power savings and total system cost reduction.

[0003] During the growth of GaN pn junction diodes using Metal-Organic Chemical Vapor Deposition (MOCVD), it is very challenging to grow p-type material with good structural, optical, and electrical integrity at the same time. The p-type region of GaN junction diodes is typically grown in an MOCVD reactor by adding magnesium (Mg) to achieve the desired electrical conductivity.

[0004] However, a common problem is the electrical passivation of acceptors such as Mg, zinc (Zn) and carbon (C) by hydrogen atoms, which are believed to diffuse into the GaN material where they neutralize the Mg acceptors and the holes generated by Mg.

[0005] The passivation process leaves the Mg acceptors inactive, so that the material is insulating or weakly p-type in its as-grown state. Passivation of the p-type region results in significant performance problems for the diode. Hydrogen passivation of acceptors and donors has been reported for a wide variety of semiconductors, including silicon [see S. J. Pearton et al., Appl. Phys. A 43, 153 (1987)], gallium arsenide [N. M. Johnson et al., Phys. Rev. B 33, 1102 (1986); W. C. Deutremont-Smith, Mater. Res. Soc. Symp. Proc. 104, 313 (1988)], indium phosphide [G. R. Antell et al., Appl. Phys. Lett., 53, 758 (1988)], and cadmium telluride [L. Svob et al., J. Cryst. Growth 86, 815 (1988)].

[0006] Passivation has been demonstrated both intentionally and unintentionally as a result of the epitaxial growth process. The growth of GaN diodes represents an example where hydrogen passivation plays an important role. Acceptor passivation has been shown to occur after growth, during the reactor cool-down stage [G Rantell et al., Appl. Phys. Lett. 73, 2953 (1998)]. In MOCVD reactors, hydrogen generation is common during the growth of GaN material and the subsequent reactor cool-down, and typically comes from two sources. Hydrogen is commonly used as a carrier gas for the growth source gases during growth.

[0007] Additionally, ammonia (NH3) is used as a source gas of nitrogen (N) during the growth of GaN material and also to stabilize the GaN material during reactor cool-down. Hydrogen is produced as a by-product of ammonia decomposition during growth and cool-down. During conventional GaN growth processes, sufficient hydrogen is available in the reactor to cause passivation of the p-type regions during cool-down.

[0008] As disclosed in US Pat. No. 5,891,790, passivation of the p-type regions can theoretically be avoided by removing the hydrogen source from the reactor before cooling.

[0009] However, GaN crystals are unstable at growth temperatures and the p-type GaN regions are susceptible to decomposition, resulting in surface damage. The conventional method to avoid this decomposition is to maintain a flow of NH3 during reactor cooling.

[0010] However, the presence of NH3 during reactor cool-down will generate hydrogen, leading to passivation. Therefore, it was felt that removal of all hydrogen sources was not practical and passivation during reactor cool-down could not be avoided.

[0011] US Pat. No. 6,498,111 discloses a method for producing a passivation barrier layer to prevent or reduce the passivation of doping species during semiconductor growth processes and thus eliminate or at least reduce the above-mentioned effects.

[0012] From the standpoint of the possibility of closer integration of GaN-based devices with silicon-based devices, as well as from the standpoint of substrate cost, it is advantageous to grow GaN layers heteroepitaxially on silicon substrates.

[0013] Such GaN-on-silicon (GOS) growth is difficult to produce due to both the lattice mismatch and the mismatch in the linear thermal expansion coefficient between the nitride material and the silicon substrate.

[0014] During high temperature processes such as epitaxial growth, thermal expansion mismatch can cause substrate warping and bowing. Bowing is a measure of the vertical displacement of the substrate surface and becomes more significant as the substrate diameter increases unless the thickness of the silicon substrate is significantly increased to provide the greater stiffness required to withstand the larger thermal mismatch stresses.

[0015] However, the diameter and thickness of silicon substrates are standardized and are of little concern for GOS applications.

[0016] As a result, high temperature GaN growth, which induces approximately 300 μm of warpage in a substrate with a diameter of 200 mm and a thickness of 725 μm, can induce more than 650 μm of warpage in a substrate with a diameter of 300 mm and a thickness of 775 μm, which is unacceptable for modern device manufacturing processes.

[0017] Hydrogen is also known to have a fairly high diffusion coefficient in silicon at high temperatures, and therefore the quality of a GaN layer deposited on a silicon substrate is degraded by hydrogen, which can diffuse through the substrate and into the GaN layer. Summary of the Invention [Problem to be solved by the invention]

[0018] It is the object of the present invention to provide a substrate made of silicon which can be coated with doped GaN without causing the described passivation effect of the dopant caused by hydrogen. [Means for solving the problem]

[0019] This solution is given by the features of the present claims. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Detailed Description With some technical measures in place known in the prior art, the inventors have realized that hydrogen diffusion in GaN is still a problem on Si wafers. This diffusion leads to quality defects, especially with respect to GaN dopants. The inventors have come to realize (without presenting scientific evidence) that hydrogen diffusion through the backside of the wafer (through the silicon) is the cause.

[0021] Preferably, the improvement is achieved by a combination of gettering, barrier, and layers capable of preventing diffusion by passivation / neutralization of the deleterious effects of hydrogen on the dopants.

[0022] The patented US Patent No. 6,498,111 teaches a method for producing a passivation barrier layer to prevent or reduce the passivation of doping species during a semiconductor growth process, thus eliminating the need for an in-situ or ex-situ annealing step. However, the present inventors have recognized that the methods presented in the prior art are not sufficient to completely solve the problem.

[0023] Preferably, substrates that can be used for heteroepitaxial wafers include silicon substrates oriented in the <1-1-1> direction.

[0024] Preferably, the thickness of the substrate is greater than 700 μm and less than 1100 μm. Preferably, the diameter of the substrate is greater than 125 mm and less than 310 mm.

[0025] The resistivity of the silicon substrate layer depends on the power device application. For many power device applications, a conductive substrate is preferred. When a conductive substrate is required, the resistivity is preferably less than 10 mOhmcm. When a semi-insulating or insulating substrate for RF HEMT devices is required, the resistivity is preferably higher than 1000 Ohmcm, with O i The concentration is preferably 2×10 17 At / cm 3 Therefore, the resistivity of the silicon substrate is preferably less than 10 mOhmcm or more than 1000 Ohmcm.

[0026] The inventors have found that the interstitial oxygen content is 2×10 17 At / cm 3 (ASTM-Norm F121-83) while at the same time the resistivity of the silicon substrate is greater than 1000 Ohmcm.

[0027] Preferably, the silicon substrate includes an intermediate or buried gettering layer capable of gettering the diffusing species of hydrogen.

[0028] The gettering layer preferably comprises a stress field or an implanted helium or oxygen layer to disturb the crystal and thus getter the hydrogen species. More preferably, the gettering layer comprises a "stable getter", which is understood to be a crystalline defect acting as a gettering centre for the metal, and which maintains its gettering properties even after high temperature processing steps lasting up to 30 minutes at temperatures up to 1200°C.

[0029] As an example of the above-mentioned stable getter, voids can be created by helium implantation into the crystal, and these voids can be stabilized by co-implantation of oxygen, it being understood that the implanted oxygen atoms form silicon oxide on the surface of the inner walls of the created voids, thus stabilizing them.

[0030] To determine the efficiency of gettering, a test can be carried out in which the back side of the wafer to be tested is intentionally contaminated with metal ions ("graph test"). The impurities are then forced into the crystal lattice by heating the semiconductor wafer. If no effective getter centers are present, they can reach the front side of the semiconductor wafer, where they can be detected by etching and scattered light measurements (haze measurements). This test can be carried out, for example, with impurities such as copper (Cu), iron (Fe), nickel (Ni) or palladium (Pd). This test is carried out using metals as contaminants. However, the inventors have come to the conclusion that this test is also valid for hydrogen.

[0031] The inventors have realised (without scientific evidence) that damage at the edge of the range during the implantation process can create some getter centres for hydrogen species. This approach is effective even at the high temperatures typical during device fabrication processes. More preferably, the gettering layer contains voids.

[0032] Preferably, the silicon substrate is covered by a 3C-SiC epitaxial layer, and even more preferably, the epitaxial layer is covered by a layer of aluminium nitride.

[0033] The aluminum nitride layer produced by MOCVD preferably comprises, in a predetermined order, a first nitrogen-rich aluminum nitride region, an aluminum nitride region and a second nitrogen-rich aluminum nitride region.

[0034] Therefore, a region of nitrogen-rich aluminum nitride is preferred in contact with the 3C-SiC layer, which is believed to act as a passivation layer.

Claims

1. (1) a substrate made of silicon having a thickness, diameter and resistivity and including a buried gettering layer for hydrogen; (2) a 3C-SiC layer; (3) A heteroepitaxial wafer comprising an aluminum nitride nucleation layer including, in a predetermined order, a first nitrogen-enriched aluminum nitride region, an aluminum nitride region, and a second nitrogen-enriched aluminum nitride region.

2. The heteroepitaxial wafer of claim 1 , wherein the gettering layer contains voids.

3. The heteroepitaxial wafer of claim 1 , wherein the gettering layer includes an edge of a damaged area.

4. 2. The heteroepitaxial wafer according to claim 1, wherein the crystal orientation of the substrate is <1-1-1>.

5. 2. The heteroepitaxial wafer of claim 1, wherein said diameter is greater than 125 mm and less than 310 mm.

6. 2. The heteroepitaxial wafer of claim 1, wherein said thickness is greater than 700 μm and less than 1100 μm.

7. 2. The heteroepitaxial wafer of claim 1, wherein the resistivity of the silicon substrate is less than 10 mOhmcm.

8. 2. The heteroepitaxial wafer of claim 1, wherein the resistivity of the silicon substrate is greater than 1000 Ohm-cm.

9. The oxygen content of the silicon substrate (ASTM-Norm F121-83) is 2×10 １７ At / cm ３ The heteroepitaxial wafer of claim 8 , wherein the thickness of the heteroepitaxial wafer is less than 100 nm.

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