Silicon-on-insulator wafer and its manufacturing method, semiconductor device

Abstract

A silicon-on-insulator wafer and a method for manufacturing the same and a semiconductor device are disclosed, the silicon-on-insulator wafer including a first substrate and an upper silicon layer, the first substrate including a first surface, where the first substrate has a maximum dimension D along a first direction. max and the first surface has a second dimension D2 along the first direction, and 100 μm≦D max -D2≦500 μm, and the top silicon layer is disposed on the first surface. The silicon-on-insulator wafer provided herein provides a suitable position for manufacturing the top silicon layer by optimizing edge sizes of the first substrate and the first surface, which helps to obtain a silicon-on-insulator wafer with a narrow step width. The present application further provides a method for manufacturing the silicon-on-insulator wafer, and a semiconductor device including the silicon-on-insulator wafer.

Description

[Technical field]

[0001] This application claims priority to a Chinese patent application filed with the China Patent Office on December 27, 2022, bearing application number 202211652519.9 and entitled "Silicon-on-insulator wafer and its manufacturing method, and semiconductor device," the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the field of semiconductor wafer technology, and more particularly to a silicon-on-insulator wafer and its manufacturing method, and a semiconductor device. [Background technology]

[0003] At present, the manufacturing of silicon-on-insulator wafers mainly includes oxygen injection separation technology, intelligent stripping technology, and bonded thinning technology. Among them, bonded thinning technology is a process of bonding a support substrate and a device layer substrate to thin the device layer substrate, which has attracted attention because of its simple process and low cost. However, due to the process conditions during thinning, the unbonded parts at the edge of the device layer substrate need to be removed by additional grinding or etching processes, which makes it difficult to precisely control the size and uniformity of the device layer substrate, which directly affects the performance of silicon-on-insulator wafers. Summary of the Invention [Problem to be solved by the invention]

[0004] The present application provides a silicon-on-insulator wafer, a manufacturing method thereof, and a semiconductor device, in which an unbonded region at the edge of a device layer substrate is automatically dropped off during a thinning process by optimizing an edge size of a first substrate, thereby obtaining a silicon-on-insulator wafer with a narrow step width. [Means for solving the problem]

[0005] According to a first aspect, the present silicon-on-insulator wafer comprises a first substrate and an upper silicon layer, the first substrate comprising a first surface, the first substrate having a maximum dimension D along a first direction. max and the first surface has a second dimension D along a first direction. 2 and 100μm≦D max -D 2 ≦500 μm, and the top silicon layer is disposed on the first surface.

[0006] In some embodiments, the maximum dimension D max and the second dimension D 2 100μm≦D max -D 2 Meets ≦160μm. In some embodiments, the top silicon layer has a first dimension D along a first direction. 1 D max -D 1 Meet ≦2mm. In some embodiments, the top silicon layer is formed by chemical mechanical polishing to a bonding region, the bonding region having an eighth dimension D along a first direction. 0 and the top silicon layer has a first dimension D along a first direction. 1 D 1 -D 0 Meets the requirement of ≦0.1mm.

[0007] In some embodiments, the top silicon layer has a first dimension D along a first direction. 1 and the first dimension D 1 , the second dimension D 2 , and maximum dimension D max teeth, 0.1≦(D max -D 2 ) / (D max -D 1 )≦1.

[0008] In some embodiments, the first substrate further includes a second surface disposed away from the first surface along a second direction, the second surface having a third dimension D along the first direction. 3 having 1≦D 2 / D 3 ≦1.5.

[0009] In some embodiments, a first arcuate second surface is provided from an edge of the first surface toward an edge of the first substrate, and a second arcuate second surface is provided from an edge of the second surface toward an edge of the first substrate, the second surface of the first arcuate second surface having a fifth dimension L in the first direction. 5 The second surface of the second arcuate surface has a sixth dimension L in the first direction. 6 having 0.01≦L 5 / L 6 <= 1.

[0010] In some embodiments, the silicon-on-insulator wafer further comprises: 50μm≦L 5 ≦80 μm, and / or 220μm≦L 6 Meets ≦450μm.

[0011] In some embodiments, the semiconductor device further includes a first oxide layer and a second oxide layer, the first oxide layer being between the first substrate and the top silicon layer, the first oxide layer contacting the first surface, and the second oxide layer being on a side of the first substrate away from the top silicon layer, the second oxide layer contacting the second surface.

[0012] In some embodiments, the top silicon layer has a thickness along a second direction, the second direction being perpendicular to the first direction, the top silicon layer has a thickness in the second direction of 3-20 μm, and / or the distance between the first surface and the second surface is 400-1000 μm, and / or the first oxide layer has a thickness in the second direction of 0.1-2 μm, and / or the second oxide layer has a thickness in the second direction of 0.1-2 μm.

[0013] According to a second aspect, the present application further provides a method for manufacturing a silicon-on-insulator wafer, comprising the steps of: providing a first substrate, said first substrate comprising a first surface, said first substrate having a maximum dimension D along a first direction; max and the first surface has a second dimension D along a first direction. 2 having 100μm≦D max -D 2 Meets ≦500μm, A second substrate is provided, the second substrate including a third surface, the third surface being contacted with the first surface, and the second substrate is bonded and annealed to the first substrate such that the second substrate includes a bonding region and a separation region, the separation region being disposed to surround the bonding region and connected to an edge of the bonding region, the side of the second substrate away from the third surface is thinned such that the separation region is removed, a step is formed where the separation region is removed, the step surrounds the bonding region, and the bonding region forms an upper silicon layer on the first substrate.

[0014] In some embodiments, the maximum dimension D max and the second dimension D 2 teeth, 100μm≦D max -D 2 Meets ≦160μm. The top silicon layer has a first dimension D along a first direction. 1 having D max -D 1Meet ≦2mm.

[0015] In some embodiments, after thinning the side of the second substrate away from the third surface, the side of the second substrate away from the third surface includes a stress damage layer, and the step of forming a top silicon layer on the first substrate at the bonding region includes performing chemical mechanical polishing on the side of the second substrate away from the third surface to first remove the stress damage layer, and then continuing polishing to a target thickness and a surface roughness reaching a level of a conventionally polished silicon wafer, and after the bonding region is chemically mechanically polished, the top silicon layer is formed.

[0016] In some embodiments, the bonding region has an eighth dimension D along the first direction. 0 and the top silicon layer has a first dimension D along a first direction. 1 D 1 -D 0 In some embodiments, the top silicon layer has a first dimension D along a first direction. 1 having 0.1≦(D max -D 2 ) / (D max -D 1 )≦1.

[0017] In some embodiments, the first substrate further includes a second surface disposed away from the first surface along a second direction, and the second substrate further includes a fourth surface disposed away from the third surface along a second direction, where the second surface has a third dimension D along the first direction. 3 and the fourth surface has a fourth dimension D along the first direction. 4 having 1≦D 2 / D 3 ≦1.5, and / or 1≦D 2 / D 4 ≦1.5.

[0018] In some embodiments, a first arcuate second surface is provided from an edge of the first surface toward an edge of the first substrate, and a second arcuate second surface is provided from an edge of the second surface toward an edge of the first substrate, the second surface of the first arcuate second surface having a fifth dimension L in the first direction. 5 The second surface of the second arcuate surface has a sixth dimension L in the first direction. 6 and 0.01≦L 5 / L 6 <= 1.

[0019] In some embodiments, a third arcuate surface is provided from an edge of the third surface toward an edge of the second substrate, and a fourth arcuate surface is provided from an edge of the fourth surface toward an edge of the second substrate, the third arcuate surface being connected to the fourth arcuate surface, and the third arcuate surface having a seventh dimension L in the first direction. 7 The fourth arcuate surface has a sixth dimension L in the first direction. 8 having 0.01≦L 7 / L 8 ≦1, and / or 0.01≦L 7 / L 5 <= 1.

[0020] In some embodiments, after the first substrate is provided, the method further comprises performing an oxidation process on the first substrate to form a first oxide layer on the first surface and / or a second oxide layer on the second surface.

[0021] In some embodiments, the annealing refers to increasing the temperature to 900-1200°C at a rate of 2-5°C / min in a nitrogen or oxygen atmosphere and holding the temperature for 4-6 hours. In some embodiments, in thinning the second substrate on the side away from the third surface, the thinning is performed by mechanical grinding. In some embodiments, the removal amount by the chemical mechanical polishing is 4-5 μm.

[0022] According to a third aspect, the present application further provides a semiconductor device, the semiconductor device including the silicon-on-insulator wafer described above, or the semiconductor device including a silicon-on-insulator wafer obtained by the manufacturing method described above. Effect of the Invention

[0023] In comparison with the prior art, the silicon-on-insulator wafer of the present application includes a first substrate and an upper silicon layer, the first substrate including a first surface, where the first substrate has a maximum dimension D along a first direction. max and the first surface has a second dimension D along the first direction. 2 and 100μm≦D max -D 2 ≦500 μm, and a top silicon layer is disposed on the first surface. The silicon-on-insulator wafer provided herein provides a suitable position for fabricating the top silicon layer by optimizing the edge size of the first substrate, which helps to obtain a silicon-on-insulator wafer with a narrow step width.

[0024] A method for manufacturing a silicon-on-insulator wafer according to the present disclosure includes the steps of: providing a first substrate, the first substrate including a first surface, the first substrate having a maximum dimension D along a first direction; max and the first surface has a second dimension D along the first direction. 2 and 100μm≦D max -D 2≦500μm, a second substrate is provided, the second substrate includes a third surface, the third surface is brought into contact with the first substrate, and the second substrate is bonded and annealed to the first substrate such that the second substrate includes a bonding region and a separation region, the separation region is arranged to surround the bonding region and connect to the edge of the bonding region, the side of the second substrate away from the third surface is thinned so that the separation region falls off, the position where the separation region falls off forms a step, the step surrounds the bonding region, and the bonding region forms an upper silicon layer on the first substrate. The manufacturing method of the present application can increase the bonding strength of the edge region of 1-3mm by optimizing the annealing process of the first substrate and the second substrate, and optimize the grinding process during the mechanical thinning process so that the unbonded region of the edge falls off automatically during the thinning process, and the width of the automatic fall off does not exceed 1mm, resulting in a non-uniformity of the width of the upper silicon layer of ≦5%. In this way, the edge step width can be minimized by optimizing the substrate shape and bonding / thinning process without requiring special chamfer grinding or chamfer etching processes, which not only reduces process costs but also enables the production of silicon-on-insulator wafers with narrow step widths. [Brief description of the drawings]

[0025] [Figure 1] 1 is a schematic diagram of the structure of a silicon-on-insulator wafer provided in an embodiment of the present application. [Diagram 2] 1 is a schematic diagram of a partial structure of a silicon-on-insulator wafer provided in an embodiment of the present application. [Diagram 3] FIG. 2 is a structural schematic diagram of a first substrate provided in an embodiment of the present application. [Figure 4] FIG. 2 is a structural schematic diagram of a second substrate provided in an embodiment of the present application. [Diagram 5] FIG. 2 is a structural schematic diagram of a first substrate and a second substrate after bonding provided in an embodiment of the present application. [Figure 6] FIG. 2 is a structural schematic diagram of the thinning of the second substrate provided in an embodiment of the present application. [Figure 7]FIG. 2 is a schematic diagram of the automatic shedding of the separation region provided in the examples of the present application. [Figure 8] 1 is a comparison of step width uniformity between Example 1 of the present application and Comparative Example 4. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] The present application provides a silicon-on-insulator wafer and a manufacturing method thereof, and a semiconductor device. In order to make the objectives, technical solutions and effects of the present application clearer, the present application will be described in more detail below with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application, and are not used to limit the present application.

[0027] Silicon-on-insulator wafers, due to their unique structure, can achieve true physical isolation vertically through a buried oxide layer (BOX) and lateral isolation laterally through a deep trench oxide layer (DTI), allowing components to be placed on different isolation islands, reducing or eliminating the leakage and latch-up effects commonly found in bulk silicon power devices and improving circuit integration density. At the same time, silicon-on-insulator wafer technology has lower leakage current than bulk silicon components, allowing it to operate at higher voltages and temperatures. While taking advantage of the advantages of bulk silicon integrated circuits, silicon-on-insulator wafers completely eliminate the latch-up effect and parasitic capacitance, and completely block leakage channels to the substrate, providing excellent characteristics such as high speed and low power consumption, and are becoming the first choice for manufacturing semiconductor integrated circuit devices with high integration, high speed, low power consumption, and high reliability.

[0028] At present, the manufacturing technologies of silicon-on-insulator substrate materials mainly include oxygen implantation separation technology, intelligent stripping technology, and bond thinning technology. Although the thickness of the top silicon and the thickness of the buried oxide layer of the wafer produced by oxygen implantation separation technology are very uniform, due to the limitations of the oxygen ion implantation process, the thickness of the silicon layer of the device cannot exceed 300nm, and the thickness of the buried oxide layer cannot exceed 240nm. In addition, discontinuous silicon island defects are often found in the buried oxide layer, which makes the breakdown voltage of the buried oxide layer much lower than that of traditional thermal oxidation, limiting the product application and technological development of oxygen implantation separation technology. Intelligent stripping technology has the characteristics of mature process, good uniformity of the device layer, and low process cost, and has become the mainstream manufacturing technology for 8-inch power insulator silicon substrate materials. Bond thinning technology has the characteristics of simple process and low cost, and the wafer-on-insulator produced by it has the same crystal defect density and surface quality as bulk silicon wafers, and can be widely adjusted. However, due to the thinning process, it is difficult to precisely control the thickness uniformity of the silicon layer of the device, and its non-uniformity is generally ±0.5μm, so it is mainly used in the fields of high-voltage power devices and MEMS devices, and most of them are concentrated in 4~6 inches.

[0029] For the silicon-on-insulator wafers produced by the three technologies, the oxygen implantation separation technology is based on the implantation and annealing process of the polished wafer, except that it retained the initial edge shape of the substrate wafer, that is, there is no step at the edge; the silicon-on-insulator wafers produced by the two technologies of intelligent stripping technology and bonded thinning technology, after bonding and thinning, have a circular step at the edge of the silicon layer of the upper device, which is formed by removing the edge part of the silicon layer of the device to release the edge stress, and the width of the step is affected by the process and may be different in width. Take the intelligent stripping technology as an example, the edge step width of the final silicon-on-insulator wafer will range from 1mm to 2.8mm. If the step width is too wide, it will reduce the effective silicon layer area of ​​the device, reduce the chip yield, and make it easy to cause edge defects in the subsequent process, affecting the quality and electrical performance parameters of the product.

[0030] In the bond thinning process, there are edge chamfering process and alkaline etching process to remove the edge part of the silicon layer of the device, but the addition of the chamfering process and alkaline etching process also significantly increases the process cost of the silicon-on-insulator wafer, and the alkaline etching process is prone to corrosion defects. Therefore, achieving a narrow and uniform step width and reducing the process cost are very important in improving the quality of silicon-on-insulator wafers.

[0031] 1, the present application provides a silicon-on-insulator wafer, comprising a first substrate 1 and a top silicon layer 2, the first substrate 1 comprising a first surface 11, and the top silicon layer 2 disposed on the first surface 11. Here, the first substrate 1 has a maximum dimension D along a first direction X. max and the first surface 11 has a second dimension D along the first direction X. 2 and 100μm≦D max -D 2 Meets ≦500μm.

[0032] In some embodiments, optimizing the edge size of the first substrate 1 and the first surface 11 provides a suitable position for manufacturing the top silicon layer 2, which helps to obtain a silicon-on-insulator wafer with a narrow step width. Note that the first direction X is the direction of the horizontal arrow in FIG. 1, and the second direction Y is the direction of the vertical arrow in FIG. 1. The first direction and the second direction are shown diagrammatically to show the positional relationship and size between the first substrate 1 and the top silicon layer 2, and the first direction and the second direction are not limited to the directions shown in the drawings, but intersect in space, and are preferably perpendicular to each other. The first direction and the second direction in this embodiment refer to the arrangement in FIG. 1.

[0033] In some embodiments, the maximum dimension D max and the second dimension D 2 100μm≦D max -D 2 In some embodiments, the upper silicon layer 2 has a first dimension D along a first direction X of preferably ≦160 μm. 1 D max -D 1 Meets ≦2mm. D max -D 1 By satisfying ≦2 mm, the quality of the upper silicon layer 2 is ensured and a narrow and uniform step width is obtained. In some embodiments, the upper silicon layer 2 is formed by chemical mechanical polishing on the bonding region 501. The bonding region 501 has an eighth dimension D along the first direction X. 0 and the upper silicon layer 2 has a first dimension D along a first direction. 1 D 1 -D 0 ≦0.1mm, where D 0 <D 1 .It is.

[0034] In some embodiments, the chemical mechanical polishing process is controlled to reduce the first dimension D 1 and the eighth dimension D 0 D 1 -D 0In some embodiments, the first dimension D is adjusted to ≦50 μm by controlling the chemical mechanical polishing process. 1 and the eighth dimension D 0 are equal, i.e. D 0 =D 1 In some embodiments, the top silicon layer 2 may have a first dimension D along a first direction X. 1 and a first dimension D 1 , the second dimension D 2 , and maximum dimension D max teeth, 0.1≦(D max -D 2 ) / (D max -D 1 )≦1.

[0035] In some embodiments, (D max -D 2 ) / (D max -D 1 If (D) is less than 0.1, the step width of the upper silicon layer 2 becomes large, while the edge of the support substrate may be chipped. max -D 2 ) / (D max -D 1 If 0.1≦(D) is greater than 1, the edge of the upper device layer cannot be automatically shed during the thinning process, and chipping of the silicon edge of the upper device layer may occur. max -D 2 ) / (D max -D 1 )≦1, it is guaranteed that a silicon-on-insulator wafer having a narrow step width and free from edge chipping can be obtained. More preferably, (D max -D 2 ) / (D max -D 1 ) range is 0.1≦(D max -D 2 ) / (D max -D 1 )≦0.5, and more preferably, (D max -D 2 ) / (D max -D 1 ) range is 0.1≦(Dmax -D 2 ) / (D max -D 1 )≦0.3.

[0036] In some embodiments, to ensure the integrity of the first substrate 1, the first substrate 1 further includes a second surface 12 disposed away from the first surface 11 along a second direction, the second surface 12 having a third dimension D along the first direction. 3 and 1≦D 2 / D 3 ≦1.5. The second surface 12 may be a surface having the same area as the first surface 11, or may be a surface having a different area.

[0037] In some embodiments, in order to facilitate processing, both the first surface 11 and the second surface 12 of the first substrate 1 need to be chamfered, and after chamfering, an arc surface is formed on the edge of the first substrate 1. Referring to FIG. 2 , a first arc surface 13 is provided from the edge of the first surface 11 toward the edge of the first substrate 1, and a second arc surface 14 is provided from the edge of the second surface 12 toward the edge of the first substrate 1, and the first arc surface 13 has a fifth dimension L in a first direction. 5 The second arcuate surface 14 has a sixth dimension L in the first direction. 6 and 0.01≦L 5 / L 6 ≦1. L 5 / L 6 When the value of L is 1, it means that the chamfers of the first surface 11 and the second surface 12 of the first substrate 1 are vertically symmetrical. 5 / L 6 When the value is less than 1, it means that the chamfers of the first surface 11 and the second surface 12 of the first substrate 1 are asymmetric.

[0038] In some embodiments, the silicon-on-insulator wafer further comprises a thickness of 50 μm≦L 5 ≦80μm, 220μm≦L 6 ≦450μm. A more preferable range is 60μm≦L 5 ≦70μm, 300μm≦L 62, the silicon-on-insulator wafer further includes a first oxide layer 3 and a second oxide layer 4, the first oxide layer 3 being located between the first substrate 1 and the top silicon layer 2, the first oxide layer 3 contacting the first surface 11. The second oxide layer 4 is located on a side of the first substrate 1 away from the top silicon layer 2, the second oxide layer 4 contacting the second surface 12.

[0039] In some embodiments, the upper silicon layer 2 has a thickness along a second direction Y, the second direction Y being perpendicular to the first direction X, the thickness of the upper silicon layer 2 in the second direction Y being 3-20 μm, the distance between the first surface 11 and the second surface 12 being 400-1000 μm, the thickness of the first oxide layer 3 in the second direction Y being 0.1-2 μm, and the thickness of the second oxide layer 4 in the second direction Y being 0.1-2 μm. More preferably, the thickness of the upper silicon layer 2 in the second direction Y is 5-10 μm, the distance between the first surface 11 and the second surface 12 being 600-800 μm, the thickness of the first oxide layer 3 in the second direction Y being 0.5-1 μm, and the thickness of the second oxide layer 4 in the second direction Y being 0.5-1 μm.

[0040] In some embodiments, the present application further provides a method for manufacturing a silicon-on-insulator wafer, the method including the steps of: Referring to Figures 1 and 3, a first substrate 1 is provided, the first substrate 1 including a first surface 11, where the first substrate 1 has a maximum dimension D along a first direction X; max and the first surface 11 has a second dimension D along the first direction X. 2 and 100μm≦D max -D 2≦500 μm. Referring to FIG. 4, a second substrate 5 is provided, the second substrate 5 including a third surface 51. Referring to FIG. 5, FIG. 6 and FIG. 7, the third surface 51 is brought into contact with the first surface 11, and the second substrate 5 is bonded and annealed to the first substrate 1 such that the second substrate 5 includes a bonding region 501 and an isolation region 502. The isolation region 502 is disposed to surround the bonding region 501 and connects to an edge of the bonding region 501. The side of the second substrate 5 away from the third surface 51 is thinned such that the isolation region 502 falls off. The bonding region 501 forms an upper silicon layer 2 on the first substrate 1.

[0041] In some embodiments, the bonding strength of the edge region of 1-3 mm can be increased by optimizing the annealing process of the first substrate 1 and the second substrate 5, and the grinding process during the mechanical thinning process can be optimized so that the unbonded region 501 at the edge automatically falls off during the thinning process, and the width of the automatically falling off does not exceed 1 mm, resulting in a width non-uniformity of the upper silicon layer 2 of ≦5%. In this way, the edge step width can be minimized by optimizing the substrate shape and the bonding and thinning process without requiring special chamfer grinding or chamfer etching processes.

[0042] In some embodiments, the upper silicon layer 2 has a step structure with respect to the first substrate 1, and the distance between the edge of the upper silicon layer 2 and the edge of the first substrate 1 is the width of the step structure, and the width is (D max -D 1 ) / 2, where the size of the width determines the overall size of the upper silicon layer 2, and since some of the isolation region 502 may automatically fall off during the thinning process, a smaller width can ensure that the thickness of the upper silicon layer 2 at the edge portion is constant in any direction, and the uniformity of the width of the upper silicon layer 2 can be achieved.

[0043] In some embodiments, the first substrate 1 refers to a conventionally polished silicon wafer or a thermally oxidized wafer with a silicon dioxide film formed on the surface by dry oxygen oxidation or wet oxygen oxidation. One side of the first substrate 1 is a polished surface, the doping type and resistivity are not limited, and the edge shape is a symmetrical or asymmetrical chamfer. The second substrate 5 can be a conventionally polished silicon wafer or a silicon epitaxial wafer. One side of the second substrate 5 is a polished surface, the doping type and resistivity are not limited, and the edge shape is a symmetrical or asymmetrical chamfer.

[0044] 7 and 1, in some embodiments, the side of the second substrate 5 away from the third surface 51 is thinned such that the separation region 502 falls off, and due to the thinning, the side of the second substrate 5 away from the third surface 51 includes a stress damage layer. The step of forming the top silicon layer 2 on the first substrate 1 with the bonding region 501 includes performing chemical mechanical polishing on the side of the second substrate 5 away from the third surface 51 to first remove the stress damage layer, and after the bonding region 501 is chemical mechanical polished, the top silicon layer 2 is formed.

[0045] In some embodiments, referring to FIG. 7, the bonding region 501 has an eighth dimension D along the first direction. 0 and the upper silicon layer 2 has a first dimension D along a first direction X. 1 D 1 -D 0 4, the second substrate 5 further includes a fourth surface 52 disposed away from the third surface 51 along the second direction Y, where the fourth surface 52 has a fourth dimension D along the first direction. 4 and 1≦D 2 / D 4 ≦1.5.

[0046] 4, a third arcuate surface 53 is provided from an edge of the third surface 51 toward an edge of the second substrate 5, and a fourth arcuate surface 54 is provided from an edge of the fourth surface 52 toward an edge of the second substrate 5, and the third arcuate surface 53 is connected to the fourth arcuate surface 54. The third arcuate surface 53 has a seventh dimension L in the first direction X. 7 and the fourth arcuate surface 54 has a sixth dimension L 8 and 0.01≦L 7 / L 8 ≦1, 0.01≦L 7 / L 5 ≦1, where L 7 / L 8 When the value of L is 1, it means that the chamfers of the third surface 51 and the fourth surface 52 of the second substrate 5 are vertically symmetrical. 7 / L 8 When the value of L is less than 1, it means that the chamfers of the third surface 51 and the fourth surface 52 of the second substrate are asymmetric. 7 / L 5 By further specifying the range, it is possible to avoid an impact on the quality of the upper silicon layer 2 caused by the chamfer dimension on the third surface 51 of the second substrate 5 being too large or too small relative to the chamfer dimension on the first surface 11 of the first substrate 1, because if the size is too large, the chamfered area is unlikely to fall off automatically in the thinning process after bonding, but if the size is too small, the step width of the upper silicon layer 2 will be too large, which will affect the performance of the device subsequently manufactured.

[0047] In some embodiments, referring to FIG. 3, after the first substrate 1 is provided, the method further includes performing an oxidation process on the first substrate 1 to form a first oxide layer 3 on the first surface 11 and a second oxide layer 4 on the second surface 12.

[0048] In some embodiments, in the bonding and annealing of the second substrate 5 and the first substrate 1, the bonding refers to laminating the first surface 11 of the first substrate 1 and the third surface 51 of the second substrate 5, and the annealing refers to increasing the temperature to 900 to 1200°C at a rate of 2 to 5°C / min in a nitrogen or oxygen atmosphere and maintaining the temperature for 4 to 6 hours. 2 / O 2 The bonding annealing process can be performed by passing the substrate through a vertical furnace or a horizontal furnace, and then heating the bonded first substrate 1 and second substrate 5 together to a temperature of more than 1000°C, controlling the heating rate to not exceed 6°C / min, and annealing the substrate at a temperature of more than 1000°C. Nitrogen or oxygen can be introduced during the annealing process, and the annealing time is more than 2 hours. The preferred annealing temperature is 1150°C, the heating rate is 3°C / min, the annealing time is 5h, and the introduced gas is oxygen.

[0049] In some embodiments, referring to Figures 6 and 7, in thinning the side of the second substrate 5 away from the third surface 51, the thinning is performed by mechanical grinding, and during the mechanical grinding process, the unbonded parts of the edge are automatically and uniformly shed off due to the strong contact of the grinding wheel, i.e., the separation region 502 is automatically shed off.

[0050] In some embodiments, the thinning is performed by mechanical grinding, which refers to mechanically grinding the fourth surface 52 of the second substrate 5 on a single-chip thinning device by driving a grinding wheel through a high-speed rotating spindle, first using a coarse grinding wheel to remove most of the substrate silicon, then using a fine grinding wheel to grind away a smaller amount of removal, and controlling the removal amount and feed / discharge speed of fine grinding to achieve a target thickness of not more than 40 μm for the final device layer silicon thickness. During the thinning process, the unbonded parts of the silicon edge of the device automatically fall off uniformly, and finally a uniform width edge step is formed with a step width ≦1 mm.

[0051] In some embodiments, during thinning and removal, using a coarse grinding wheel for coarse grinding and a fine grinding wheel for fine grinding, the mesh number of the coarse grinding wheel is ≦500 mesh, the mesh number of the fine grinding wheel is ≧3000 mesh, and the feed / discharge rate of the fine grinding process is controlled not to exceed 5 μm / s to grind to the target thickness. The preferred coarse grinding wheel is 300-400 mesh, the preferred fine grinding wheel is 5000-8000 mesh, and the preferred feed / discharge rate of the fine grinding process is 3-4 μm / s. In some embodiments, the removal amount by mechanical grinding is ≧600 μm.

[0052] In some embodiments, the bonding region 501 is chemically mechanically polished to form the top silicon layer 2, and the removal amount by chemical mechanical polishing is 4-5 μm. The preferred polishing method is chemical mechanical polishing (CMP), which refers to the use of single-tip polishing to remove surface stress damage caused by mechanical grinding in the previous thinning process while improving the surface roughness to reach the surface roughness level of conventional polishing sheets. Because the edge bonding force is large enough, the edge step width does not change significantly after chemical mechanical polishing, i.e., D 1 -D 0 ≦0.1mm, while maintaining a narrow step width and excellent width uniformity. By chemically and mechanically polishing the ground bonded substrate, the grinding-induced stress damage layer can be completely removed, fully meeting the surface roughness requirements, while controlling the polishing removal amount to reduce the degradation effect caused by uneven thickness of the silicon layer of the device. The preferred polishing removal amount is 4-5μm. The polishing process basically has no effect on the edge width of the device layer, and the change in width before and after is ≦0.1mm, which can maintain the regularity of the edge width.

[0053] In some embodiments, the present application further provides a semiconductor device, which includes the above-mentioned silicon-on-insulator wafer. According to the above-mentioned manufacturing method, a number of groups of silicon-on-insulator wafers, specifically including Examples 1 to 16 and Comparative Examples 1 to 3, are manufactured, and the obtained width data are shown in Table 1. In the table, △D is (D max -D2 ) / (D max -D 1 ) and the range of ΔD in Comparative Examples 1 to 3 is outside the range set in this example.

[0054] [Table 1]

[0055] As can be seen from Table 1, D of Examples 1 to 16 max -D 2 Meets the requirements of 100 to 500 μm, (D max -D 2 ) / (D max -D 1 ) satisfies the limit range of 0.1 to 1, which allows the width of the upper silicon layer 2 from the edge to be reliably controlled within a narrower range, and a silicon-on-insulator wafer with a narrow step width can be obtained. max -D 2 ) / (D max -D 1 ) is less than 0.1, the width of the upper silicon layer 2 from the edge increases, the uniformity of the width of the upper silicon layer 2 is impaired, and the performance of the subsequent device is also affected.

[0056] Comparative Example 4 A silicon-on-insulator wafer is manufactured using Smart-cut technology, that is, a bonded wafer is implanted with hydrogen ions and bonded to another silicon wafer at a specific temperature. When the bonding heat treatment temperature is about 500°C, continuous cavities are formed at the hydrogen ion implantation sites, which are automatically peeled off to form a silicon-on-insulator wafer. Comparing the silicon-on-insulator wafer of Comparative Example 4 and that of Example 1 of the present application, as shown in FIG. 8, the edge step widths in four directions are equal and show very good width uniformity in Example 1 of the present application, but the edge step widths in four directions are different due to Smart-cut technology in Comparative Example 4. Therefore, the manufacturing method of the present application optimizes the grinding process so that the unbonded region of the edge, i.e., the separation region 502, automatically falls off during the thinning process, and the width of the automatic fall-off does not exceed 1 mm, and the width non-uniformity of the upper silicon layer 2 is also small. In this way, the edge step width can be reduced to the maximum by optimizing the shape of the substrate and the bonding and thinning process without requiring special chamfer grinding or chamfer etching processes.

[0057] The above is a detailed introduction of the silicon-on-insulator wafer and its manufacturing method, and semiconductor device provided in the examples of the present application, in which specific examples are used to explain the principles and embodiments of the present application. The description of the above examples is only used to understand the technical solutions and core ideas of the present application, and it should be understood that those skilled in the art can modify the technical solutions recorded in the above examples or make equivalent substitutions for some technical features, and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the examples of the present application. [Explanation of symbols]

[0058] 1 First Substrate 2. Top Silicon Layer 3 First oxide layer 4 Second Oxide Layer 5 Second Board 11 First Surface 12 The Second Surface 13 First circular arc surface 14 Second arc surface 51 The Third Surface 52 The Fourth Surface 53 Third arc surface 54 Fourth Arc Surface 501 Combined area 502 Separation area

Claims

1. A silicon-on-insulator wafer comprising a first substrate (1) and a top silicon layer (2); The first substrate (1) comprises a first surface (11), wherein the first substrate (1) has a maximum dimension D along a first direction. ｍａｘ and the first surface (11) has a second dimension D along a first direction. ２ and 100 μm≦D ｍａｘ -D ２ ≦500 μm, A silicon-on-insulator wafer, characterized in that said top silicon layer (2) is disposed on said first surface (11).

2. The maximum dimension D ｍａｘ and the second dimension D ２ 100 μm≦D ｍａｘ -D ２ 2. The silicon-on-insulator wafer of claim 1, wherein the thickness satisfies ≦160 μm.

3. The upper silicon layer (2) has a first dimension D along a first direction. １ D ｍａｘ -D １ 3. The silicon-on-insulator wafer according to claim 1, wherein the thickness satisfies ≦2 mm.

4. The upper silicon layer (2) is formed by chemical mechanical polishing to a bonding region (501), the bonding region (501) having an eighth dimension D along a first direction. ０ and the upper silicon layer (2) has a first dimension D along a first direction. １ D １ -D ０ 4. The silicon-on-insulator wafer according to claim 1, wherein the thickness satisfies ≦0.1 mm.

5. The upper silicon layer (2) has a first dimension D along a first direction. １ and the first dimension D １ , the second dimension D ２ , and the maximum dimension D ｍａｘ 0.1≦(D ｍａｘ -D ２ ) / (D ｍａｘ -D １ 5. The silicon-on-insulator wafer according to claim 1, wherein the following condition is satisfied: 1) n<=1.

6. The first substrate (1) further includes a second surface (12) disposed away from the first surface (11) along a second direction, the second surface (12) having a third dimension D along the first direction. ３ and 1≦D ２ / D ３ 6. The silicon-on-insulator wafer according to claim 1, wherein the silicon-on-insulator wafer satisfies ≦1.

5.

7. A first arcuate surface (13) is provided from an edge of the first surface (11) toward an edge of the first substrate (1), and a second arcuate surface (14) is provided from an edge of the second surface (12) toward an edge of the first substrate (1), and the first arcuate surface (13) has a fifth dimension L in the first direction. ５ and the second arcuate surface (14) has a sixth dimension L in the first direction. ６ and 0.01≦L ５ / L ６ 7. The silicon-on-insulator wafer of claim 6, wherein: ≦1.

8. The silicon-on-insulator wafer further comprises: ５ ≦80 μm, 220 μm≦L ６ 8. The silicon-on-insulator wafer of claim 7, wherein the thickness satisfies ≦450 μm.

9. Further comprising a first oxide layer (3) and a second oxide layer (4), the first oxide layer (3) is located between the first substrate (1) and the upper silicon layer (2), the first oxide layer (3) being in contact with the first surface (11); 9. The silicon-on-insulator wafer according to claim 6, wherein the second oxide layer (4) is located on a side of the first substrate (1) facing away from the upper silicon layer (2), and the second oxide layer (3) is in contact with the second surface (12).

10. The silicon-on-insulator wafer of any one of claims 1 to 9, characterized in that the upper silicon layer (2) has a thickness along a second direction, the second direction being perpendicular to the first direction, and the thickness of the upper silicon layer (2) in the second direction is 3 to 20 μm.

11. A silicon-on-insulator wafer according to any one of claims 6 to 9, characterized in that the distance between the first surface (11) and the second surface (12) is between 400 and 1000 μm.

12. 11. The silicon-on-insulator wafer of claim 10, wherein the first oxide layer (3) has a thickness in the second direction of 0.1 to 2 μm, and the second oxide layer (4) has a thickness in the second direction of 0.1 to 2 μm.

13. A method for manufacturing a silicon-on-insulator wafer, comprising the steps of: Providing a first substrate (1), said first substrate (1) comprising a first surface (11), wherein said first substrate (1) has a maximum dimension D along a first direction. ｍａｘ and the first surface (11) has a second dimension D along a first direction. ２ and 100 μm≦D ｍａｘ -D ２ ≦500 μm; providing a second substrate (5), said second substrate (5) comprising a third surface (51); bonding and annealing the second substrate (5) to the first substrate (1) by contacting the third surface (51) with the first surface (11) such that the second substrate (5) comprises a bonding region (501) and a separation region (502), the separation region (502) being disposed around the bonding region (501) and connecting to an edge of the bonding region (501); thinning the side of the second substrate (5) facing away from the third surface (51) such that the separation regions (502) fall off; The bonding region (501) comprises the steps of forming a top silicon layer (2) on the first substrate (1); 1. A method for producing a silicon-on-insulator wafer, comprising:

14. The maximum dimension D ｍａｘ and the second dimension D ２ 100 μm≦D ｍａｘ -D ２ The method for producing a silicon-on-insulator wafer according to claim 13, characterized in that the thickness satisfies ≦160 μm.

15. The upper silicon layer (2) has a first dimension D along a first direction. １ D ｍａｘ -D １ 15. The method for producing a silicon-on-insulator wafer according to claim 13, wherein the thickness satisfies ≦2 mm.

16. 16. The method for manufacturing a silicon-on-insulator wafer according to claim 13, characterized in that after a step of thinning the side of the second substrate (5) remote from the third surface (51), the side of the second substrate (5) remote from the third surface (51) comprises a stress damage layer, and the step of forming a top silicon layer (2) on the first substrate (1) comprises the steps of performing chemical mechanical polishing on the side of the second substrate (5) remote from the third surface (51) to first remove the stress damage layer and to form the top silicon layer (2) after the bonding region (501) has been chemical mechanically polished.

17. The bonding area (501) has an eighth dimension D along a first direction. ０ and the upper silicon layer (2) has a first dimension D along a first direction. １ D １ -D ０ The method for producing a silicon-on-insulator wafer according to any one of claims 13 to 16, characterized in that the thickness satisfies ≦0.1 mm.

18. The upper silicon layer (2) has a first dimension D along a first direction. １ and 0.1≦(D ｍａｘ -D ２ ) / (D ｍａｘ -D １ 18. The method for producing a silicon-on-insulator wafer according to claim 13, wherein the following condition is satisfied: 1) ≦1.

19. the first substrate (1) further comprises a second surface (12) disposed away from the first surface (11) along a second direction, and the second substrate (5) further comprises a fourth surface (52) disposed away from the third surface (51) along a second direction; wherein the second surface (12) has a third dimension D along the first direction ３ and the fourth surface (52) has a fourth dimension D along the first direction. ４ and 1≦D ２ / D ３ ≦1.5, 1≦D ２ / D ４ The method for producing a silicon-on-insulator wafer according to any one of claims 13 to 18, characterized in that the ratio satisfies ≦1.

5.

20. A first arcuate surface (13) is provided from an edge of the first surface (11) toward an edge of the first substrate (1), and a second arcuate surface (14) is provided from an edge of the second surface (12) toward an edge of the first substrate (1), and the first arcuate surface (13) has a fifth dimension L in the first direction. ５ and the second arcuate surface (14) has a sixth dimension L in the first direction. ６ and 0.01≦L ５ / L ６ 20. The method for producing a silicon-on-insulator wafer according to claim 19, wherein the following is satisfied: ≦1.

21. A third arcuate surface (53) is provided from an edge of the third surface (51) toward an edge of the second substrate (5), and a fourth arcuate surface (54) is provided from an edge of the fourth surface (52) toward an edge of the second substrate (5), the third arcuate surface (53) is connected to the fourth arcuate surface (54), and the third arcuate surface (53) has a seventh dimension L in the first direction. ７ and the fourth arcuate surface (54) has a sixth dimension L in the first direction. ８ and 0.01≦L ７ / L ８ ≦1, 0.01≦L ７ / L ５ 20. The method for producing a silicon-on-insulator wafer according to claim 19, wherein the following is satisfied: ≦1.

22. After the step of providing the first substrate (1), 22. The method for producing a silicon-on-insulator wafer according to any one of claims 19 to 21, further comprising the step of performing an oxidation process on the first substrate (1) to form a first oxide layer (3) on the first surface (11) and / or a second oxide layer (4) on the second surface (12).

23. 22. The method for producing a silicon-on-insulator wafer according to claim 13, wherein the annealing comprises increasing the temperature to 900 to 1200° C. at a rate of 2 to 5° C. / min in a nitrogen or oxygen atmosphere and holding the temperature for 4 to 6 hours.

24. A method for producing a silicon-on-insulator wafer according to any one of claims 13 to 22, characterized in that the step of thinning the side of the second substrate (5) facing away from the third surface (51) is performed by mechanical grinding.

25. 17. The method for producing a silicon-on-insulator wafer according to claim 16, wherein the removal amount by the chemical mechanical polishing is 4 to 5 μm.

26. A semiconductor device comprising the silicon-on-insulator wafer according to any one of claims 1 to 12, or the semiconductor device comprising a silicon-on-insulator wafer obtained by the method for producing a silicon-on-insulator wafer according to any one of claims 13 to 25.

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