Semiconductor Devices

Abstract

The semiconductor device (10, 10', 10'') comprises a first circuit layer (12) having at least an integrated circuit, and a second circuit layer (14, 14', 14'') having at least a current supply section (14s) configured to supply electrical energy to the integrated circuit (12i), and a second main surface (12h2) of the first circuit layer (12) is connected to a first or second main surface (14h2) of the second circuit layer (14, 14', 14'').

Description

[Technical field]

[0001] Embodiments of the present invention relate to semiconductor devices, in particular those with a three-dimensional integrated face-to-face current supply. Further embodiments relate to corresponding manufacturing methods. [Background technology]

[0002] Up to now, the current supply of integrated circuits, or circuits in general or 3D stacked circuits, has been realized by external current supplies, for example DC-DC converters, or by on-chip DC-DC converters, which can be located, for example, in the same circuit layer or in the same 3D stacked circuit layer. Summary of the Invention [Problem to be solved by the invention]

[0003] In modern circuit technologies, e.g. 3nm technologies, on-chip DC-DC converters are no longer feasible (technically). The reason is that the corresponding transistors no longer exhibit sufficient dielectric strength and / or current carrying capacity. Even external DC-DC converters can no longer guarantee the necessary stability of the supply voltage. The reason is that while supply voltages have repeatedly decreased over the past years, the permissible deviations from the slight supply voltage have remained roughly the same, while the requirements for the overall product have increased significantly. Realizing this using external current supplies is usually not possible, since in this case the supply lines would be too long. Therefore, an improved approach is needed.The objective underlying the present invention is to provide a current supply for modern circuit technologies, such as 3 nm technology, which eliminates or minimizes the drawbacks related to manufacturability and supply voltage stability. [Means for solving the problem]

[0004] This object is achieved by the subject matter of the independent claims. An embodiment of the present invention provides a semiconductor device comprising a first circuit layer and a second circuit layer. The first circuit layer comprises at least an integrated circuit, such as a memory and / or logic. The second circuit layer comprises at least a current supply configured to supply electrical energy to the integrated circuit, where a second main surface (such as a front side, top side, etc.) of the first circuit layer is connected to a first or second main surface (such as a front side or bottom side (top or bottom) depending on the embodiment) of the second circuit layer.

[0005] The embodiments of the invention are based on the finding that using novel packaging technologies such as 3D integration, it is possible to manufacture a very compact implementation of different components in a chip stack. In 3D integration, circuits are stacked one above the other. The circuit or circuits to which the actual logic or memory functions are given are arranged in a first circuit layer and assembled as a three-dimensional stack. Novel manufacturing technologies such as 3nm technology can be used for this or these circuit layers. The current supplies are respectively arranged in a second circuit layer. The two circuit layers are arranged directly adjacent to each other, for example by using bonding or copper pillars, so that extremely short line lengths and, as a result, voltage stability depending on the situation of use can be achieved. The use of separate circuit layers allows the use of different manufacturing technologies in the first circuit layer, which is also advantageous in terms of manufacturing powerful current supplies. Furthermore, the embodiments of the invention advantageously allow a voltage supply to be carried out directly at the user's location.

[0006] According to an embodiment, the integrated circuit of the first circuit layer (or the first circuit layer in general) is manufactured using a first semiconductor manufacturing technology (such as a 3 nm technology), and at least one current supply of the second current layer, or the second circuit layer in general, is manufactured using a second semiconductor manufacturing technology. The first semiconductor manufacturing technology is different from the second semiconductor manufacturing technology. According to an embodiment, the first semiconductor manufacturing technology can include, for example, a 3 nm technology or an improved or further miniaturized semiconductor manufacturing technology.

[0007] Subsequently, three exemplary embodiments of 3D integration are described. According to a first variant, the second circuit layer can be connected to the first circuit layer face-to-back, with a first main surface of the second circuit layer being connected to a second main surface of the first circuit layer. According to a second variant, the first and second circuit layers can be connected face-to-face, with the second main surface of the first circuit layer being connected to the second main surface of the second circuit layer, whereby, for example, the material, in particular the semiconductor material, of the two circuit layers can be approximately the same width so that a three-dimensional structure is produced. According to a third variant, it is also conceivable that the second circuit layer comprises a molding material, where for example the two circuit layers are connected face-to-face by the molding, which again means that the second main faces of the first and second circuit layers are connected to each other.

[0008] According to an embodiment, the connection between the second main surface of the first circuit layer and the first or second main surface of the second circuit layer is a direct connection, a direct bond connection, a bond connection, a connection at a contact pad, or a connection at a copper contact pad (or a copper pillar). According to an embodiment, the second circuit layer covers (the entirety of) the surface of the first circuit layer. In other words, this means that these two circuit layers are of the same size. According to an embodiment, the second circuit layer comprises a semiconductor material covering the entire width of the first circuit layer. According to another embodiment, the second circuit layer comprises at least a first region having a semiconductor material and a second region having a molding material. Several second regions may be provided so as to be laterally adjacent to the semiconductor region. In this case, the first and second regions may extend, for example, over the (entire) width of the first circuit layer. Alternatively, each of the two regions may have one or more sub-regions so that the entire width is filled by the first and second regions, and the sub-regions may be provided differently.

[0009] According to a further embodiment, the first main surface of the second circuit layer comprises a contact or a contact sheet if the second main surface serves to connect to the first circuit layer. Alternatively, the second main surface of the second circuit layer comprises a contact or a contact sheet if the first main surface serves to connect to the first circuit layer. According to an embodiment, the contact is configured to be connected to an unstabilized voltage source. According to an embodiment, the current supply is configured to provide a stabilized voltage on the side of the second main surface of the first circuit layer, via its first or second main surface depending on its structure, starting from an unstabilized voltage applied from an unstabilized voltage source, thereby supplying electrical energy (current supply) to the integrated circuit.

[0010] According to an embodiment, the second circuit layer comprises one or more vias extending through the thickness of the second circuit layer and configured to provide signal contacts of the integrated circuit. According to an embodiment, the one or more vias can extend through the semiconductor material of the second circuit layer or through the molding material of the second circuit layer. This means that these two embodiments advantageously provide that the connection of the signals of the integrated circuit of the first circuit layer is carried out through a main surface of the second circuit layer facing away from the first circuit layer. As mentioned above, each circuit layer may comprise one or more floors such that a three-dimensional integrated circuit corresponding to that circuit layer is formed. According to an embodiment, the second main surface of the first circuit layer and / or the second main surface of the second circuit layer may comprise a redistribution sheet and / or a device sheet. Connections to other circuit layers are made, for example, via this redistribution sheet.

[0011] According to a further embodiment, the semiconductor device comprises a further circuit layer disposed on the first major surface of the first circuit layer, For example, the further circuit layer may comprise integrated circuits, logic and / or memory. Further embodiments provide a method for manufacturing the aforementioned semiconductor device. The manufacturing method comprises a step of connecting a first circuit layer to a second circuit layer. According to an embodiment, the connection may be made by bonding, direct bonding, or by creating contact pads or copper pillar connections. According to an embodiment, the connection is performed by face-to-back or face-to-face techniques.

[0012] Embodiments of the present invention are described below with reference to the accompanying drawings. [Brief description of the drawings]

[0013] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device with a face-to-back arrangement according to an embodiment. [Diagram 2] 1 is a schematic cross-sectional view of a semiconductor device with a face-to-face arrangement according to another embodiment. [Diagram 3] 13 is a schematic cross-sectional view of a semiconductor device having a mold with a face-to-face arrangement according to a further embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Before describing the following embodiments of the present invention with reference to the accompanying drawings, it should be noted that like elements and structures are given like reference numerals and therefore their descriptions are mutually applicable or interchangeable.

[0015] FIG. 1 shows a semiconductor device 10 comprising at least two circuit layers 12 and 14. These two circuit layers are arranged one above the other, i.e. directly adjacent to each other, connected to each other or directly connected to each other. The two circuit layers 12 and 14 can, for example, have the same, similar or at least equal widths and together form a chip or semiconductor device 10. Optionally, a third circuit layer 16 may be provided. A detailed description of the third circuit layer 16 in relation to the basic embodiment will not be given here. For example, the first circuit layer 12 is the top circuit layer and the circuit layer 14 is the bottom circuit layer. The top circuit layer 12 is connected to the second circuit layer 14 at its second main surface 12h2, i.e. at its bottom. Here, the second main surface 12h2 of the first circuit layer is connected to the first main surface 14h1 of the second surface layer 14. Major surface 12h2 is the front side of first circuit layer 12, and circuit layer 14h1 can be referred to as the back side of second circuit layer 14. The front side of front circuit layer 14 is labeled 14h2. The depicted arrangement is a so-called face-to-back arrangement of the two circuit layers 12 and 14, resulting in a three-dimensional stacking of circuits.

[0016] Of course, the two circuit layers 12 and 14 may also comprise more sheets of regions, such as semiconductor regions, doped regions, insulating regions or conductive regions (metallization sheets), for example, to create electrical devices provided in the respective circuit layers 12 and 14. The device or circuit layer 12 comprises one or more integrated circuits 12i, for example constituting logic or memory. According to an embodiment, the entire circuit layer 12 is manufactured by a manufacturing technique, such as, for example, a 3 nm semiconductor manufacturing technique, so that the circuit layer 12 comprises a common semiconductor material (in different sheets) and can be, for example, a device or a chip.

[0017] The circuit layer 14 includes a current supply 14s, such as a DC-DC converter. The current supply 14 serves to supply a stabilized voltage corresponding to the current to the integrated circuit 12i. For example, the current supply 14s is electrically coupled to any redistribution sheet 12u of the circuit layer 12 via a contact 14sk on the face 14h1. This results in a very short line length, which is advantageous for voltage stabilization. By creating the current supply 14s in a separate device or in a separate circuit layer 14, it is possible to use a manufacturing technology different from that of the circuit layer 12, for example an older circuit technology, or in general a technology that is advantageous for manufacturing devices for current supply.

[0018] Thus, the embodiment can be described in terms of the two circuit layers 12 and 14 being connected to each other in a face-to-back arrangement, which can use direct bond techniques (direct bonding, or more generally, bonding) or can use copper pillars, or more generally, connection pads or copper pillows.

[0019] It should be noted here that, according to an embodiment, the current supply unit 14s can include one or more DC-DC converters. For example, since the current supply unit 14s is assumed to be supplied with an unregulated voltage from the bottom part 14h2 (second main surface), the DC-DC converter 14s can adjust the voltage so that a highly regulated voltage is supplied with sufficient electrical energy without large variations. The unregulated voltage may be applied, for example, via the connection terminal 14sk2.

[0020] Furthermore, according to a further embodiment, the circuit layer 14 may comprise one or more through connections or vias (tsv), e.g., referenced 14tsv, for direct connection (electrical connection) from the second main surface 14h2 to the first main surface 14h1. Here, signals from the outside may be input to the integrated circuit 12i. The signal vias are referenced 14tsvs.

[0021] According to further embodiments, a further circuit layer 16 can be arranged similarly, for example with its bottom part 16h2 (second main surface) on the first main surface 12h1 (top surface), and according to embodiments can comprise integrated circuits, for example logic or memory (not shown). In the embodiment presented here, the bottom parts 16h2, 14h2 and 12h2 can be characterized as comprising redistribution sheets 12u, 16u or 14u. The redistribution sheets serve to electrically connect to the individual devices in the semiconductor area and may be implemented, for example, as metallization. Of course, instead of redistribution sheets, transistor sheets, for example of the type in which parts of the transistors are also formed in the semiconductor area, may be provided. The redistribution sheets serve, for example, to connect from the outside, as can be seen in particular in the redistribution sheet 14u.

[0022] A further embodiment is described below with reference to FIG. FIG. 2 shows a semiconductor device 10' also comprising two circuit layers 12 and 14' and an optional circuit layer 16. The circuit layer 12 essentially corresponds to the circuit layer 12 of FIG. 1 and comprises, for example, an integrated circuit 12i. The circuit layer 12 is connected to the circuit layer 14' via its second main surface 12h2. The circuit layer 14' is essentially similar to the circuit layer 14 of FIG. 1 and also comprises, for example, a DC converter 14s as a current supply. However, in this embodiment, the circuit layer 14' is connected to the circuit layer 12 at the main surface 14h2, not at the main surface 14h1. As mentioned above, this second main surface 14h2 can comprise, for example, a redistribution sheet 14u.

[0023] This arrangement is called face-to-face arrangement. By using this arrangement, the path from the DC-DC converter 14s to the actual circuit 12i becomes extremely short. Furthermore, the DC-DC converter 14s can be manufactured with old circuit technology. The system is supplied with an unregulated voltage from the bottom (circuit layer 14 side) (see terminal 14sk2), and voltage regulation within the circuit is performed by the DC-DC converter 14h2. The "normal" signals of the circuit 12i with logic and memory are transmitted to the outside through the circuit 14' with the DC-DC converter 14s using vias 14tsvs.

[0024] The so-called face-to-face arrangement using a mold is described below with reference to Figure 3. Figure 3 shows a semiconductor device 10'' having circuit layers 12, 14'' and optional circuit layer 16. The circuit layer 14'' is a further development of the circuit layer 14' and comprises an additional material apart from the semiconductor material or the main material in the area of ​​the voltage supply portion 14s. This additional material is referenced by the symbols 14m1 and 14m2 and may include, for example, a molding material. The sheet 14'' is then bonded with its second main surface 14h2 to the second main surface 12h2 of the first circuit layer 12. This means that the embodiment shown here provides a so-called face-to-face arrangement with a molded arrangement. The line length from the DC-DC converter to the "normal" circuit 12i is still very short. In addition, it is also guaranteed that the DC-DC converter 14 or the general current supply 14s can be manufactured using old or adapted circuit technology.

[0025] It is noted here that both the semiconductor device 10' of FIG. 2 and the semiconductor device 10'' of FIG. 3 may also include the further features "vias 14tsv or 14tsvs" and "voltage contacts 14sk2". As can be recognized from the embodiment of FIG. 3, the vias 14tsv may extend into the molding materials 14m1 and 14m2, and may also extend through the semiconductor material 14h. For example, the voltage supply vias (see contacts 14sk2) extend through the semiconductor material 14h to the redistribution sheet 14u, whereby the unregulated voltage of the current supply unit 14s is supplied through this redistribution sheet 14u, and the current supply unit 14s performs voltage regulation thereon. It is noted that, regarding the vias 14tsv, 14tsvs extending from the molding materials 14m1, 14m2, the vias 14tsv, 14tsvs protrude into the redistribution sheet 12u, while the via 12sk2 penetrating the semiconductor material 14h protrudes into the redistribution sheet 14u. In the embodiment of FIG. 2, all the vias extend, for example, to the redistribution sheet 14u (see 14tsv, 14tsvs, 14sk2).

[0026] According to a preferred embodiment, vias 14tsv and 14tsvs are used in the molded areas 14m1 and 14m2 for signal transmission (logic, memory control signals), and vias 14sk2 serve to transmit current, voltage signals. Thus, external current or voltage signals to the current supply 14s can be provided through these vias 14sk2. According to an embodiment, contacts are provided on the main surface 14h1 (the surface not facing the circuit layer 12), i.e. in the areas 14m1 and 14m2 or in the area 14h. The contacts in the area 14h serve for current, voltage supply. The contacts in the areas 14m1 and 14m2 serve for connecting signals. Here, it is advantageous that the signals are transmitted through the molded material, thereby being as far away as possible from the influence of interference from the chip receiving the current supply. The insulating properties of the molded material also have a beneficial technical effect.

[0027] In all the above embodiments of Figures 1 to 3, the two circuit layers 12 and 14 can be connected by direct bonding or copper pillars, which are labeled with 13k, but it should be pointed out here that other connection methods are also feasible. Common to all embodiments is that a very compact implementation of different components in a chip stack is made possible by novel packaging techniques of 3D integration. In 3D integration, circuits are stacked one above the other. In this case, it is one or more circuits that are given the actual (logic or memory) function and assembled as a 3D stack. External components that fulfill different requirements, such as voltage supplies 14s, can be transferred to further circuit layers.

[0028] It is pointed out here that the above embodiments always envisage two or three circuit layers, and more circuit layers (i.e. more than three) are naturally feasible. In particular, any circuit layer 16 may also be arranged rotated with respect to the other circuit layers 12 and 14 (or 14' or 14''). In the above embodiments, it was assumed that the second circuit layer 14 is either the sheet 14h1 or the sheet 14h2 (see circuit configurations 10' and 10''). On the side of the first circuit layer 12, the main surface 12h2 is always used. According to further embodiments, it is also conceivable to couple to the second circuit layer 14 via the main surface 12h1, while the connection via the main surface 12h2 has the advantage that a redistribution sheet 12u is provided here, via which the supply voltage can be easily supplied to the integrated circuit 12i. The above-mentioned applications of three-dimensional integration are, for example, semiconductor devices that may at least partially include semiconductor materials such as silicon or gallium arsenide. The applications are not limited by their core function, i.e. any device, both memory device or processor (logic), is a potential application field for three-dimensional integration.

[0029] Further embodiments relate to a method for manufacturing the aforementioned embodiments 10, 10', 10''. The manufacturing method comprises the main steps of connecting the first and second circuit layers, 12 and 14, or 12 and 14', or 12 and 14'', i.e. using face-to-back techniques, face-to-face techniques, or face-to-face techniques including molding. As mentioned before, the connection can be made by contact pads or copper pillars, but also using bonding or direct bonding. It is noted that even if the embodiments are described in particular with reference to an apparatus (semiconductor device, 3D sheet stack or chip), the description of individual product features may at the same time substitute for a description of the corresponding method steps. Conversely, the description of method steps may also be considered as a description of product steps. The scope of protection is defined by the appended claims.

Claims

1. A semiconductor device (10, 10', 10'') comprising: a first circuit layer (12) comprising at least an integrated circuit; a second circuit layer (14, 14', 14'') comprising at least a current supply (14s) configured to supply electrical energy to said integrated circuits (12i), said second circuit layer (14, 14', 14'') comprising at least a first region having a semiconductor material and a second region having a molding material (14m1, 14m2), said first and second regions extending across a width of said first circuit layer (12); a second main surface (12h2) of the first circuit layer (12) is connected to a first or second main surface (14h2) of the second circuit layer (14, 14', 14''); The second circuit layer (14, 14', 14'') comprises one or more vias (14tsv, 14tsvs) extending through a thickness of the second circuit layer (14, 14', 14'') and configured to provide signal contacts for the integrated circuit, the one or more vias (14tsv, 14tsvs) extending through a molding material (14m1, 14m2) of the second circuit layer (14, 14', 14'').

2. 2. The semiconductor device (10, 10', 10'') of claim 1, wherein a connection between the second main surface (12h2) of the first circuit layer (12) and the first or second main surface (14h2) of the second circuit layer (14, 14', 14'') comprises a direct connection, a direct bond connection, a bond connection, a connection at a contact pad (13k), or a connection at a copper pillar.

3. The semiconductor device (10, 10', 10'') of claim 1 or 2, wherein the integrated circuit (12i) comprises logic or memory.

4. The semiconductor device (10, 10', 10'') according to any one of the preceding claims, wherein the current supply (14s) comprises a DC-DC converter.

5. the second circuit layer (14, 14', 14'') covering the face of the first circuit layer (12); and / or The semiconductor device (10, 10', 10'') of any one of claims 1 to 4, wherein the second circuit layer (14, 14', 14'') comprises semiconductor material spanning a width of the first circuit layer (12).

6. 5. The semiconductor device (10, 10', 10'') according to claim 1, wherein the first main surface (14h1) of the second circuit layer (14, 14', 14'') is provided with a contact when the second main surface serves to connect with the first circuit layer (12), or the second main surface (14h2) of the second circuit layer (14, 14', 14'') is provided with a contact when the first main surface serves to connect with the first circuit layer (12).

7. the semiconductor device includes a contact on a major surface of the second circuit layer opposite the second circuit layer; 7. The semiconductor device (10, 10', 10'') according to any one of claims 1 to 6, wherein the contacts are arranged in the first region and configured to carry a current, a voltage signal, and / or the contacts are arranged in the second region and configured to carry a control signal.

8. the current supply (14s) is configured to provide a stabilized voltage on the side of the second main surface (12h2) of the first circuit layer (12) for the current supply (14s) to the integrated circuit (12i), starting from an unregulated voltage applied from an unregulated voltage source; and / or In use with an unregulated voltage source, the contact (14sk2) is configured to be connected to the unregulated voltage source.

9. The semiconductor device (10, 10', 10'') according to any one of claims 1 to 8, wherein the one or more vias (14tsv, 14tsvs) penetrate a semiconductor material of the second circuit layer (14, 14', 14'').

10. the one or more vias of the second circuit layer are configured to carry a control signal; and / or The semiconductor device (10, 10', 10'') of any one of claims 1 to 9, wherein the second circuit layer comprises one or more further vias extending through the first region and configured to convey a current, voltage signal to the current supply.

11. The semiconductor device (10, 10', 10'') of any one of claims 1 to 10, wherein the second major surface (12h2) of the first circuit layer (12) and / or the second major surface (14h2) of the second circuit layer (14, 14', 14'') comprises a redistribution sheet and / or a device sheet.

12. 12. The semiconductor device (10, 10', 10'') of any one of claims 1 to 11, wherein a further circuit layer having integrated circuits, logic, and / or memory is disposed on the first major surface (12h1) of the first circuit layer (12).

13. the integrated circuits (12i) of the first circuit layer (12) are fabricated using a first semiconductor fabrication technology, and at least one of the at least one current supply unit (14s) of the second circuit layer (14, 14', 14'') is fabricated using a second semiconductor fabrication technology; 13. The semiconductor device (10, 10', 10'') of any one of claims 1 to 12, wherein the first manufacturing technology is different from the second manufacturing technology and / or the first semiconductor manufacturing technology comprises a 3 nm technology or better.

14. 14. A method for manufacturing a semiconductor device (10, 10', 10'') according to any one of claims 1 to 13, comprising the step of connecting the first circuit layer (12) to the second circuit layer (14, 14', 14'').

15. The method of claim 14, wherein the connection is made by bonding, direct bonding, or by making contact pad connections or copper pillar connections.

16. The manufacturing method according to claim 15 or 16, wherein the connection is performed by face-to-back or face-to-face technique.

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