Stacked Semiconductor Devices

Abstract

The stacked semiconductor device includes a bottom semiconductor device having a backside and a flip top semiconductor device having a backside opposite the bottom semiconductor device backside. The flip top semiconductor device further includes a backside residual semiconductor-on-insulator (SOI) layer and a stressed dielectric portion thereon. The stacked semiconductor device may be formed by stacking and bonding the flip top semiconductor device to the bottom semiconductor device, removing one or more semiconductor-on-insulator (SOI) layers from the backside of the flip top semiconductor device while retaining the exposed backside residual SOI layer of the flip top semiconductor device, forming a stressed dielectric layer on the exposed backside residual SOI layer, and patterning the stressed dielectric layer.

Description

[Technical field]

[0001] Various embodiments of the present application generally relate to semiconductor device fabrication methods and resulting structures. More particularly, various embodiments may relate to a first semiconductor device including a FET having a strained channel vertically stacked on an underlying second semiconductor device. Summary of the Invention

[0002] According to one aspect of the present invention, a stacked semiconductor device is provided. The device includes a bottom semiconductor device including a first metallization layer having a first metallization layer through interconnect. The device further includes a flip top semiconductor device including a second metallization layer having a second metallization layer through interconnect in contact with the first metallization layer through interconnect. The flip top semiconductor device further includes a backside residual semiconductor-on-insulator (SOI) layer and a first stressed dielectric portion on the backside residual SOI layer that provides an intrinsic strain in the backside residual SOI layer.

[0003] According to another aspect of the invention, a stacked semiconductor device is presented. The device includes a bottom semiconductor device including a first metallization layer having a first metallization layer through interconnect. The device further includes a flip top semiconductor device including a second metallization layer having a second metallization layer through interconnect in contact with the first metallization layer through interconnect. The flip top semiconductor device further includes a backside residual semiconductor-on-insulator (SOI) layer and a first stressed dielectric portion on the backside residual SOI layer that provides an intrinsic strain in a first channel region below the backside residual SOI layer. The flip top semiconductor device further includes a second stressed dielectric portion on the backside residual SOI layer that provides an intrinsic compressive strain in a second channel region below the backside residual SOI layer.

[0004] According to another aspect of the present invention, a stacked semiconductor device fabrication method is presented. The method includes stacking and bonding a flip top semiconductor device with a backside to a bottom semiconductor device. The method further includes removing one or more semiconductor-on-insulator (SOI) layers from the backside of the flip top semiconductor device while retaining an exposed backside residual SOI layer of the flip top semiconductor device. The method further includes forming a stressed dielectric layer on the exposed backside residual SOI layer of the flip top semiconductor device and forming one or more stressed dielectric portions by patterning and removing portions of the stressed dielectric layer.

[0005] These and other embodiments, features, aspects, and advantages will become better understood with reference to the following description, appended claims, and accompanying drawings. [Brief description of the drawings]

[0006] [Figure 1] 1A-1D are cross-sectional views of a semiconductor device shown after respective fabrication operations in accordance with one or more embodiments. [Diagram 2] 1A-1D are cross-sectional views of a semiconductor device shown after respective fabrication operations in accordance with one or more embodiments. [Diagram 3] 1A-1D are cross-sectional views of a stacked semiconductor device shown after respective fabrication operations according to one or more embodiments. [Figure 4] 1A-1D are cross-sectional views of a stacked semiconductor device shown after respective fabrication operations according to one or more embodiments. [Diagram 5] 1A-1D are cross-sectional views of a stacked semiconductor device shown after respective fabrication operations according to one or more embodiments. [Figure 6] 1A-1D are cross-sectional views of a stacked semiconductor device shown after respective fabrication operations according to one or more embodiments. [Figure 7]1A-1D are cross-sectional views of a semiconductor device shown after respective fabrication operations in accordance with one or more embodiments. [Figure 8] 1A-1D are cross-sectional views of a semiconductor device shown after respective fabrication operations in accordance with one or more embodiments. [Figure 9] 1A-1D are cross-sectional views of a semiconductor device shown after respective fabrication operations in accordance with one or more embodiments. [Figure 10] FIG. 13 is an exemplary plot of in-plane lattice deformation versus fin depth in accordance with one or more embodiments. [Figure 11] FIG. 1 is an exemplary flow diagram illustrating a method for fabricating a stacked semiconductor device, according to one or more embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] As the size of metal-oxide-semiconductor field-effect transistors (MOSFETs) and other devices decreases, the dimensions of the device's source / drain regions, channel regions, and electrodes generally also decrease. The design of increasingly smaller transistors with short channel lengths requires providing very shallow source / drain junctions. Shallow junctions are necessary to avoid lateral diffusion of implanted dopants into the channel, because such diffusion detrimentally contributes to leakage current and poor breakdown voltage performance. Generally, shallow source / drain junctions with thicknesses of about 30 nm to 100 nm are required for acceptable performance in short channel devices. Silicon-on-insulator (SOI) technology enables the formation of high-speed, shallow junction devices. In addition, SOI devices improve performance by reducing parasitic junction capacitance.

[0008] Although a detailed description of an exemplary fully depleted silicon-on-insulator (FDSOI) semiconductor IC device is provided herein that includes a FET vertically stacked on a second, lower IC device, it should be understood that practice of the teachings described herein is not limited to the particular device architecture described herein. Rather, embodiments of the present invention may be practiced in conjunction with other suitable types of SOI semiconductor IC devices that are vertically stacked on a second, lower IC device.

[0009] Various embodiments of the present invention are described herein with reference to the associated drawings. Alternative embodiments may be devised without departing from the scope of the present invention. Please note that in the following description and drawings, various connections and positional relationships between elements (e.g., above, below, adjacent, etc.) are shown. Those connections and / or positional relationships can be direct or indirect unless otherwise specified, and the present invention is not intended to be limited in this respect. Thus, the connection of entities can refer to either direct or indirect connections, and the positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, in this description, reference to forming a layer "A" on a layer "B" includes the situation where one or more intermediate layers (e.g., layer "C") are between layers "A" and "B", as long as the relevant properties and functions of layers "A" and "B" are not significantly altered by the intermediate layers.

[0010] In the following, for purposes of explanation, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives refer to the described structures and methods as oriented in the drawings. The terms "overlying", "atop", "on top", "positioned on" or "positioned atop" mean that a first element, such as a first structure, is on a second element, such as a second structure, and an intervening element, such as an interface structure, may be between the first and second elements. Terms such as "direct contact" mean that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating or semiconducting layer at the interface between the two elements. It should be noted that the term "selective to", e.g., "a first element selective to a second element", means that the first element can be etched and the second element can act as an etch stop.

[0011] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with the measurement of a particular quantity based on equipment available at the time of filing. For example, substantial coplanarity between various materials can include appropriate manufacturing tolerances of ±8%, ±5%, ±2%, etc., difference between coplanar materials.

[0012] For the sake of brevity, conventional techniques related to semiconductor device and IC fabrication may or may not be described in detail herein. Additionally, various operations and process steps described herein may be incorporated into more comprehensive procedures or processes that include additional steps or functions not described in detail herein. In particular, because the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, for the sake of brevity, many conventional steps are described herein only briefly or omitted entirely, without providing details of the well-known processes.

[0013] In general, the various processes used to form the microchips that are packaged into ICs fall into four general categories: deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. For example, materials can be deposited by any of the following processes: physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), or various variants thereof, such as plasma enhanced chemical vapor deposition (PECVD), metalorganic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), electron beam physical vapor deposition (EB-PVD), and plasma enhanced atomic layer deposition (PE-ALD). Deposition can be an epitaxial process, and the deposited material can be crystalline. In various embodiments, the formation of the layers may be by one or more deposition processes; for example, a conformal layer can be formed by a first process (e.g., ALD, PE-ALD, etc.) and the fill can be formed by a second process (e.g., CVD, electrodeposition, PVD, etc.). Removal / etching is any process that removes material from the wafer. Examples include etching processes (either wet or dry), chemical-mechanical planarization (CMP), etc. Semiconductor doping is generally the modification of electrical properties by doping, for example, the source and drain of a transistor, by diffusion or by ion implantation, or both. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). The annealing serves to activate the implanted dopants. Films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and separate transistors and their components. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be altered by the application of a voltage.By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the formation of a three-dimensional relief image or pattern on a semiconductor substrate for subsequent transfer of the pattern to a substrate. In semiconductor lithography, the pattern is formed by a light-sensitive polymer called a photoresist. The steps of lithography and etching pattern transfer are repeated multiple times to build the complex structures that make up the transistors, and the many wires that connect the millions of transistors in a circuit. Each pattern printed on the wafer is aligned with the patterns already formed, slowly building up conductors, insulators, and selectively doped regions to form the final device.

[0014] FIG. 1 is a cross-sectional view of a semiconductor device 100 including an SOI substrate 102, in accordance with one embodiment of the present invention.

[0015] The SOI substrate 102 includes a semiconductor substrate 104, a buried insulator 106 on the semiconductor substrate 104, and a semiconductor layer 108 on the buried insulator 106. The buried insulator 106 is formed directly on the semiconductor substrate 104. The buried insulator 106 may be formed of silicon nitride (SiN), silicon oxide (SiO2), or the like. The semiconductor layer 108 may be an ultra-thin semiconductor-on-insulator (ETSOI) layer 108 formed on the buried insulator 106. The semiconductor layer 108, the ETSOI layer 108, or the like, may be referred to herein as a residual SOI layer. The term "residual SOI layer" is defined herein as a layer of an SOI substrate that has been retained with one or more of the other layers of the SOI substrate removed.

[0016] In one or more embodiments, the substrate 104 can be a semiconductor or an insulator with an active surface semiconductor layer. The substrate 104 can be crystalline, semi-crystalline, microcrystalline, or amorphous. The substrate 104 can be essentially (e.g., except for contaminants) a single element (e.g., silicon), predominantly (e.g., with doping) a single element, e.g., silicon (Si) or germanium (Ge), or the substrate 104 can include a compound, e.g., Al2O3, SiO2, GaAs, SiC, or SiGe. The substrate 104 can also have multiple layers of material, e.g., a semiconductor-on-insulator substrate (SeOI), a silicon-on-insulator substrate (SOI), a germanium-on-insulator substrate (GeOI), or a silicon germanium-on-insulator substrate (SGOI). The substrate 104 can also have other layers forming the substrate 104, including high-k oxides and / or nitrides. In one or more embodiments, the substrate 104 may be a silicon wafer. In an embodiment, the substrate 104 is a single crystal silicon wafer.

[0017] The ETSOI layer 108 may comprise any semiconductor material, including but not limited to Si, strained Si, SiC, SiGe, SiGeC, Si alloys, Ge, Ge alloys, GaAs, InAs, and InP, or any combination thereof. The ETSOI layer 108 may be thinned to a desired thickness by planarization, polishing, wet etching, dry etching, oxidation followed by an oxide etch, or any combination thereof. One method of thinning the ETSOI layer 108 is to oxidize the Si by a thermal dry or wet oxidation process and then wet etch the oxide layer using a hydrofluoric acid mixture. This process may be repeated to obtain a desired thickness. In one embodiment, the ETSOI layer 108 may have a thickness in the range of 1.0 nm to 25.0 nm. In another embodiment, the ETSOI layer 108 may have a thickness in the range of 5.0 nm to 15.0 nm. In a further embodiment, the ETSOI layer 108 may have a thickness in the range of 6.0 nm to 10.0 nm. The term "ETSOI substrate" is defined herein as a semiconductor-on-insulator (SOI) substrate in which the SOI layer (eg, layer 108) has a thickness of 25 nm or less.

[0018] A dummy gate (not shown) having sidewall spacers 126 may be formed on the ETSOI channel region 116. Raised source / drain regions 130 and raised drain / source regions 132 may be formed on the mating ETSOI source / drain region 112 and mating ETSOI drain / source region 114. The raised source / drain regions 130 and raised drain / source regions 132 may be formed adjacent to the dummy gate according to one embodiment of the present invention.

[0019] In various embodiments, fabrication of semiconductor device 100 can be followed by forming isolation 110 (e.g., shallow trench isolation (STI)), forming a dummy gate (not shown), forming sidewall spacers 126 on either end of the dummy gate, forming ETSOI source / drain regions 112, forming ETSOI source / drain regions 114, forming raised source / drain regions 130, and forming raised drain / source regions 132.

[0020] The ETSOI channel region 116 may be formed between the ETSOI source / drain region 112 and the ETSOI drain / source region 114. In addition, a dummy gate may be placed on a dummy gate oxide (not shown) that may be formed on the ETSOI channel region 116. The dummy gate oxide may be further positioned between the lower portions of the spacers 126. The dummy gate has a thickness greater than the thickness of the dummy gate oxide. The ETSOI channel region 116 has a thickness approximately equal to the thicknesses of the ETSOI source / drain region 112 and the ETSOI drain / source region 114. The raised source / drain region 130 and the raised drain / source region 132 may have a thickness greater than the thicknesses of the ETSOI source / drain region 112 and the ETSOI drain / source region 114, respectively.

[0021] The isolation region 110 is formed by etching a trench in the substrate 102 using a conventional dry etching process, such as RIE or plasma etching. The trench may optionally be lined with a conventional liner material, such as silicon nitride or silicon oxynitride, and then CVD or another similar deposition process is used to fill the trench with silicon oxide or another such as an STI dielectric material. The STI dielectric may optionally be densified after deposition. A conventional planarization process, such as chemical mechanical polishing (CMP), may optionally be used to provide a planar structure.

[0022] In various embodiments, the dummy gate may be formed by forming and then patterning a dummy gate layer. The dummy gate may include a stack of overlapping materials, such as a dummy gate dielectric (e.g., silicon oxide), amorphous silicon, and a dielectric cap (e.g., silicon nitride). Later in the process sequence, the dummy gate is removed and replaced with a functional gate structure having one or more gate dielectrics and at least one gate conductor. The dummy gate has a thickness that is greater than the thicknesses of the raised source / drain regions 130 and the raised drain / source regions 132. The top surface of the dummy gate may be coplanar with the top surface of the spacer 126.

[0023] The spacers 126 may be formed by performing a directional etch (e.g., RIE) after deposition. The spacers 126 may be formed along the sidewalls of the dummy gate. For example, a spacer material such as a nitride (e.g., silicon nitride) may be deposited by a conventional method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Other techniques that may be suitable for depositing the nitride layer include low pressure CVD (LPCVD) and atmospheric pressure CVD (APCVD). A portion of the deposited nitride layer is then etched away in a conventional manner to form the spacers 126. The spacer material may be silicon oxide, silicon oxynitride, silicon nitride, SiBCN, SiOCN, SiOC, or any suitable combination of these materials.

[0024] The dummy gate and spacers 126 may be formed before the ETSOI source / drain regions 112 and the ETSOI drain / source regions 114. In various embodiments, the ETSOI source / drain regions 112 and the ETSOI drain / source regions 114 may be formed by doping the appropriate ETSOI layer 108 regions with an appropriate N-type or P-type dopant. The dopants may be provided to the ETSOI source / drain regions 112 and the ETSOI drain / source regions 114 by ion implantation. The ETSOI source / drain regions 112 and the ETSOI drain / source regions 114 may then be annealed. In various embodiments, the doped ETSOI source / drain regions 112 and the doped ETSOI drain / source regions 114 may be n-doped or p-doped.

[0025] In various embodiments, the doped regions 112, 114 may be doped in situ or ex situ, for example, by ion implantation or thermal diffusion of dopants into the ETSOI layer 108. The source dopants may be activated by annealing. Other suitable doping techniques may also be used, including, but not limited to, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid phase doping, solid phase doping, or combinations thereof.

[0026] Forming the raised source / drain regions 130 and the raised drain / source regions 132 may include forming an epitaxial semiconductor material doped in situ on the doped regions 112, 114. The term "epitaxial semiconductor material" refers to a semiconductor material formed using an epitaxial deposition or growth process. "Epitaxial growth and / or deposition" refers to the growth of a semiconductor material on a deposition surface of the semiconductor material, where the growing semiconductor material has substantially the same crystalline properties as the semiconductor material on the deposition surface. In some embodiments, when the chemical reactants are controlled and the system parameters are set correctly, the deposited atoms arrive at the deposition surface with sufficient energy to travel across the surface and orient themselves in the crystalline conformation of the atoms on the deposition surface. Thus, in some instances, an epitaxial film deposited on a {100} crystal plane will be {100} oriented. In some embodiments, the epitaxial deposition process is a selective deposition process, where epitaxial semiconductor material is formed only on the semiconductor material deposition surface. The epitaxial deposition process does not form epitaxial semiconductor material on the dielectric surface.

[0027] In some embodiments, the epitaxial semiconductor material providing the source and drain regions 112, 114 may be comprised of silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon doped silicon (Si:C), or combinations thereof. In one example, the p-type source and drain regions are provided by silicon germanium (SiGe) epitaxial semiconductor material. In one embodiment, several different sources may be used for the epitaxial deposition of the epitaxial semiconductor material on the source and drain regions 112, 114.

[0028] Examples of silicon containing source gases include silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, and combinations thereof.

[0029] Examples of germanium containing source gases for epitaxially forming germanium containing semiconductor epitaxial semiconductor materials include germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof.

[0030] Epitaxial deposition can be performed in a chemical vapor deposition system, such as a metalorganic chemical vapor deposition (MOCVD) system or a plasma enhanced chemical vapor deposition (PECVD) system. Temperatures for epitaxial deposition typically range from 550°C to 900°C. Higher temperatures typically result in faster deposition, but faster deposition can lead to crystal defects and film cracking.

[0031] The epitaxial semiconductor material providing the raised source / drain regions 130 and the raised drain / source regions 132 may be doped in situ for p-type or n-type conductivity. The term "in situ" indicates that a dopant, e.g., an n-type or p-type dopant, is introduced into the base semiconductor material, e.g., silicon or silicon germanium, during the formation of the substrate. For example, an in situ doped epitaxial semiconductor material may introduce a p-type dopant into the material being formed during an epitaxial deposition process that includes a p-type source gas.

[0032] As used herein, "p-type" refers to the addition of an impurity to an intrinsic semiconductor that creates a deficiency of valence electrons. For Group IV semiconductors such as silicon, examples of p-type dopants, or impurities, include, but are not limited to, boron, aluminum, gallium, and indium. A p-type gas dopant source can include diborane (B2H6).

[0033] As used herein, "n-type" refers to the addition of impurities that contribute free electrons to an intrinsic semiconductor. In Group IV semiconductors such as silicon, examples of n-type dopants, or impurities, include, but are not limited to, antimony, arsenic, phosphorus, etc.

[0034] The term "raised" as used to describe the raised source / drain regions 130 and the raised drain / source regions 132 means that the undersides of the raised source and drain regions 130, 132 are in direct physical contact with the surface of the ETSOI substrate 108. The raised source / drain regions 130, 132 may be formed using a selective epitaxial growth process. The process is selective meaning that the deposited semiconductor material grows only on the exposed semiconductor regions and not on the dielectric, such as silicon oxide. The epitaxial growth process may be continued until the raised source and drain regions 130, 132 have a height in the range of 5 nm to 50 nm, as measured from the top surface of the ETSOI substrate 108. Typically, the raised source and drain regions 130, 132 are composed of a silicon-containing material, such as silicon, silicon germanium, or carbon-doped silicon (Si:C).

[0035] However, several different sources can be used for the deposition of the semiconductor material that forms the raised source and drain regions 130, 132. In some embodiments in which the semiconductor material that forms the raised source / drain regions 130, 132 is composed of silicon, the silicon gas source for epitaxial deposition can be selected from the group consisting of hexachlorodisilane (Si2Cl6), tetrachlorosilane ((SiCl4), dichlorosilane (Cl2SiH2), trichlorosilane (Cl3SiH)), methylsilane ((CH3)SiH3), dimethylsilane ((CH3)2SiH2), ethylsilane ((CH3CH2)SiH3), methyldisilane ((CH3)Si2H5), dimethyldisilane ((CH3)2Si2H4), hexamethyldisilane ((CH3)6Si2), and combinations thereof. In some embodiments, when the semiconductor material forming the raised source / drain regions 130, 132 is comprised of germanium, the germanium gas source for epitaxial deposition may be selected from the group consisting of germane (GeH4), digermane (Ge2H6), halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. In some embodiments in which the semiconductor material forming the raised source / drain regions 130, 132 is composed of silicon germanium, the silicon source for epitaxial deposition may be selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, and combinations thereof, and the germanium gas source may be selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof.

[0036] In various embodiments, following fabrication of the semiconductor device 100, an interlevel dielectric (ILD) layer 140 can be formed over the raised source / drain regions 130, 132 and the dummy gate can be removed to define the recesses. The ILD 140 can have a dielectric liner (e.g., silicon nitride) and a fill dielectric material (e.g., silicon oxide).

[0037] In various embodiments, an oxide fill of the ILD 140 is performed. The ILD 140 may be planarized. The ILD 140 encompasses, covers, or surrounds the entire raised source / drain regions 130, 132. The ILD 140 engages the outer surface of the sidewall spacer 126. In one embodiment, the ILD 140 extends to the top point of the spacer 126. Stated differently, the ILD 140 is flush with the distal end of the spacer 126. Alternatively, as shown, the ILD 140 may have a thickness greater than the height of the spacer 126. Additionally, the dummy gate may be removed, providing a gap or recess between the inner sidewalls of the spacer 126.

[0038] In one or more embodiments, the ILD 140 can have a thickness in the range of about 20 nm to about 150 nm, or in the range of about 30 nm to about 50 nm.

[0039] The ILD 140 may be selected from the group consisting of silicon containing materials such as SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, and SiCH compounds, the above silicon containing materials where some or all of the Si is replaced with Ge, carbon doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon containing materials, organic-inorganic materials such as spin-on glass and silsesquioxane based materials, and diamond-like carbon (DLC, also known as amorphous hydrogenated carbon, α-C:H). Additional options for the ILD 140 include any of the aforementioned materials in porous form or in forms that change from porous and / or permeable to non-porous and / or non-permeable during processing.

[0040] In various embodiments, the height of the ILD 140 can be selectively reduced by chemical mechanical polishing (CMP) and / or etching. Thus, the planarization process can be provided by CMP. Other planarization processes can include grinding and polishing.

[0041] As used herein, the term "selective" in relation to a material removal process refers to a rate of material removal for a first material that is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied. For example, in one embodiment, a selective etch may include an etch chemistry that selectively removes a first material relative to a second material by a ratio of 10:1 or more, such as 100:1 or more, or 1000:1 or more.

[0042] In various embodiments, following fabrication of the semiconductor device 100, a replacement gate structure 120 may be formed in the recess formed by removal of the dummy gate in accordance with an embodiment of the present invention.

[0043] In various embodiments, the newly formed gate structure 120 includes a gate dielectric (not shown) deposited within the recess, a gate conductor 122, and a gate cap 124. The gate dielectric may contact the inner surfaces of the sidewall spacers 126 and a portion of the top surface of the semiconductor layer 108. The gate conductor 122 is then filled into the gate dielectric. The gate conductor 122 may be formed by deposition followed by planarization (e.g., CMP) so that it is flush with or below the top surface of the gate spacers 126.

[0044] The gate conductor 122 may be any conductive metal, including but not limited to W, Ni, Ti, Mo, Ta, Cu, Pt, Ag, Au, Ru, Jr, Rh, and Re, and alloys containing at least one of the aforementioned conductive elemental metals. The gate conductor 122 typically resides on a gate dielectric. The gate dielectric may be a dielectric material such as SiO2, SiN, BNi, or a high-k dielectric such as an oxide of Ta, Zr, Al, or a combination thereof. In another embodiment, the gate dielectric may be composed of an oxide such as ZrO2, Ta2O5, or Al2O3. In one embodiment, the gate dielectric has a thickness in the range of 1 nm to 10 nm. In another embodiment, the gate dielectric has a thickness in the range of 1.5 nm to 2.5 nm. In a preferred embodiment, the gate dielectric is a high-k material (a material that has a high dielectric constant (κ, kappa) compared to silicon dioxide). Further examples of high-k materials include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k may further include dopants such as lanthanum, aluminum, etc.

[0045] The gate conductor 122 may be doped polycrystalline or amorphous silicon, germanium, silicon germanium, metals (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), conductive metal composites (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials. The gate conductor 122 may further include dopants incorporated during or after deposition.

[0046] The gate structure 120 may further include a gate work function setting layer (not shown) between the gate dielectric and the gate conductor 122. The gate work function setting layer may be a metal composite, including but not limited to titanium nitride (TiN), hafnium nitride (HfN), hafnium silicon nitride (HfSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), a carbide, including but not limited to titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), hafnium carbide (HfC), and combinations thereof.

[0047] The gate structure 120 may further include a gate cap 124. The gate cap 124 may be formed on the gate conductor 122. The gate cap 124 may be a hard mask, or the like. Exemplary gate cap 124 materials may include SiN, SiO2, a combination of SiN and SiO2, SiON, SICN, SIOCN, or the like. The gate cap 124 may be formed by known deposition techniques, such as PVD, CVD, ALD, or the like. The gate cap 124 material may have a thickness of about 1 nm to about 200 nm, although other thicknesses are within contemplated ranges.

[0048] The gate structure 120 functions to switch the semiconductor device 100 from an on state to an off state and vice versa. The gate structure 120 may be formed in alignment with the ETSOI channel 116. The gate structure 120 typically includes at least a gate dielectric that is also aligned with the ETSOI channel 116.

[0049] The gate structure 120 may be planarized (eg, by CMP) to be flush with the top surface of the ILD 140 .

[0050] In various embodiments, following fabrication of the semiconductor device 100, contacts 150, 152, 155 may be formed on the raised source / drain regions 130, the raised drain / source regions 132, and the gate structure 120, respectively, and further a middle-of-the-line (MOL) or back-end-of-the-line (BEOL) layer 160, hereinafter referred to as metallization layer 160, may be formed according to one embodiment of the present invention.

[0051] Contacts 150, 152 may be formed in the ILD 140. Contact 150 may be formed on and in physical contact with the raised source / drain region 130. Contact 152 may be formed on and in physical contact with the raised drain / source region 132. Contact 155 (not shown) may be formed on and in physical contact with the gate structure 120.

[0052] A metallization layer 160 may be deposited on the top surfaces of the contacts 150, 152, 155 and on the top surface of the ILD 140. The thickness of the metallization layer 160 may be greater than the thickness of the ETSOI layer 108.

[0053] For the metallization layer 160, a layer of dielectric material may be blanket deposited over the entire substrate and planarized. The blanket dielectric may be selected from the group consisting of silicon-containing materials such as SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, and SiCH compounds, the above silicon-containing materials with some or all of the Si substituted with Ge, carbon-doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon-containing materials, organic-inorganic materials such as spin-on glass and silsesquioxane-based materials, and diamond-like carbon (DLC, also known as amorphous hydrogenated carbon, α-C:H). Additional options for the blanket dielectric include any of the aforementioned materials in porous form or in forms that change from porous and / or permeable to non-porous and / or non-permeable during processing.

[0054] Blanket dielectrics can be formed by a variety of methods well known to those skilled in the art, including but not limited to spinning from solution, jetting from solution, CVD, PECVD, sputter deposition, reactive sputter deposition, ion beam deposition, and evaporation.

[0055] The deposited blanket dielectric may then be patterned and etched to form holes or openings for the various contacts 150, 152, 155 and / or other underlying conductive wiring features. Following via formation, conductive interconnects 162, 165 (not shown), 167 (not shown), 169 (not shown) are formed by depositing a conductive metal in the via holes using conventional processes such as CVD or plating. The conductive metal may include, but is not limited to, tungsten, copper, aluminum, silver, gold, and alloys thereof. The BEOL layer may comprise one or more stacks of wires / vias that may form the interconnects 162, 165, 167, or 169, or combinations thereof. The conductive interconnect 162 may be formed on and physically connected to the underlying conductive wiring features. The conductive interconnect 165 may be formed on and physically connected to the underlying contacts 150. Conductive interconnect 167 may be formed on and physically connected to underlying contact 152. Conductive interconnect 169 may be formed on and physically connected to underlying contact 155.

[0056] FIG. 2 is a cross-sectional view of a semiconductor device 200 in accordance with an embodiment of the present invention.

[0057] Semiconductor device 200 may generally be a wafer, a carrier, an interposer, etc. In some embodiments, semiconductor device 200 may be a semiconductor device including one or more FETs (e.g., finFETs, nanowire FETs, nanosheet FETs, gate-all-around FETs, etc.).

[0058] As further described herein, semiconductor device 100 may be stacked and bonded to semiconductor device 200 to form stacked semiconductor device 299. Stacked integrated circuits (e.g., 3D ICs) are integrated circuits fabricated by stacking silicon wafers and / or dies and interconnecting them vertically, for example using through silicon vias (TSVs), so that they act as a single device to achieve increased performance at reduced power and in a smaller footprint than traditional two-dimensional processes. 3D ICs are only one of many 3D integration schemes that utilize the z-direction to achieve electrical performance advantages. Three-dimensional semiconductor and packaging technologies using through silicon vias (TSVs) are used to stack thinned semiconductor chips and to integrate heterogeneous semiconductor technologies into microelectronic modules.

[0059] An exemplary semiconductor device 200 is illustrated and described herein, including a SOI substrate 202. The SOI substrate 202 includes a semiconductor substrate 204, a buried insulator 206 on the semiconductor substrate 204, and a semiconductor layer 208 on the buried insulator 206. The buried insulator 206 may be formed directly on the semiconductor substrate 204. The semiconductor layer 208 may be formed directly on the buried insulator 206.

[0060] In one or more embodiments, substrate 204 is the same type of substrate as substrate 104, the description of which will not be repeated herein. Similarly, buried insulator 206 may be the same or similar type of layer as buried insulator 106, the description of which will not be repeated herein. Similarly, semiconductor layer 208 may be the same or similar type of layer as ETSOI layer 108, the description of which will not be repeated herein. In embodiments, such as the illustrated finFET embodiment, the thickness of semiconductor layer 208 may be greater than the thickness of ETSOI layer 108. One or more fins may be formed by removing portions of semiconductor layer 208 and retaining other portions of semiconductor layer 208. The retained portions of semiconductor layer 208 may form fins.

[0061] In various embodiments, following fabrication of semiconductor device 200, a dummy gate (not shown) may be formed, sidewall spacers 226 may be formed on either end of the dummy gate, fin source / drain regions 212 may be formed, fin drain / source regions 214 may be formed, and fin channel regions 216 may be formed.

[0062] A fin channel region 216 may be formed between the fin source / drain region 212 and the fin drain / source region 214. In addition, a dummy gate may be disposed on a dummy gate oxide (not shown) that may be formed on the fin channel region 216. The dummy gate oxide may further be positioned between a lower portion of the spacers 226. The dummy gate has a thickness that is greater than a thickness of the dummy gate oxide.

[0063] In various embodiments, the dummy gate may be formed by forming and then patterning a dummy gate layer. The dummy gate may include a stack of overlapping materials, such as a dummy gate dielectric (e.g., silicon oxide), amorphous silicon, and a dielectric cap (e.g., silicon nitride). Later in the process sequence, the dummy gate is removed and replaced with a functional gate structure having one or more gate dielectrics and at least one gate conductor. The dummy gate has a thickness greater than the thickness of the raised fin. The top surface of the dummy gate may be coplanar with the top surface of the spacer 226.

[0064] The spacers 226 may be formed by performing a directional etch (e.g., RIE) after deposition. The spacers 226 may be formed along the sidewalls of the dummy gate. For example, a spacer material such as a nitride (e.g., silicon nitride) may be deposited by a conventional method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Other techniques that may be suitable for deposition of the nitride layer include low pressure CVD (LPCVD) and atmospheric pressure CVD (APCVD). A portion of the deposited nitride layer is then etched away in a conventional manner to form the spacers 226. The spacer material may be silicon oxide, silicon oxynitride, silicon nitride, SiBCN, SiOCN, SiOC, or any suitable combination of these materials.

[0065] The dummy gate and spacers 226 may be formed before the fin source / drain regions 212, the fin drain / source regions 214, and the fin channel region 116. The fin source / drain regions 212 and the fin drain / source regions 214 may be formed by doping the applicable fin regions with a suitable N-type or P-type dopant. The dopant may be provided to the fin regions by ion implantation. The fin source / drain regions 212 and the fin drain / source regions 214 may then be annealed. In various embodiments, the doped fin source / drain regions 212 and the fin drain / source regions 214 may be n-doped or p-doped.

[0066] In various embodiments, the doped regions 212, 214 may be doped in situ or ex situ, for example by ion implantation or thermal diffusion of dopants into the fin. The source dopants may be activated by annealing. Other suitable doping techniques may also be used, including, but not limited to, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid phase doping, solid phase doping, or combinations thereof.

[0067] In various embodiments, following fabrication of the semiconductor device 200, the ILD layers 238, 240 can be formed and the dummy gates can be removed to define the recesses. The ILDs 238, 240 can have a dielectric liner (e.g., silicon nitride) and a fill dielectric material (e.g., silicon oxide).

[0068] In various embodiments, an oxide fill of the ILDs 238, 240 is performed. The ILDs 238, 240 may be planarized. The ILDs 238 include, cover, or surround the entire fin and / or dummy gate structure. The ILDs 240 include, cover, or surround the entire dummy gate structure. The ILDs 240 engage the outer surface of the sidewall spacer 226. In one embodiment, the ILDs 240 extend to the top point of the spacer 226. Stated differently, the ILDs 240 are flush with the distal end of the spacer 226. Alternatively, as shown, the ILDs 240 may have a thickness greater than the height of the spacer 226. Additionally, the dummy gate may be removed, providing a gap or recess between the inner sidewalls of the spacer 226.

[0069] In one or more embodiments, the ILD 240 may have a thickness ranging from about 20 nm to about 150 nm, or from about 30 nm to about 50 nm. The ILDs 238, 240 may be the same type of material as the ILD 240, the description of which will not be repeated herein. In various embodiments, the height of the ILD 240 may be selectively reduced by CMP and / or etching. Other planarization processes may include grinding and polishing.

[0070] In various embodiments, following fabrication of the semiconductor device 200, a replacement gate structure 220 may be formed in the recess formed by removal of the dummy gate according to an embodiment of the present invention. The shape and material of the replacement gate structure 220 may be the same as the respective materials of the replacement gate structure 120, and the description of which will not be repeated herein.

[0071] The gate structure 220 functions to switch the semiconductor device 200 from an on state to an off state and vice versa. The gate structure 220 may be formed in alignment with the fin channel region 216. The gate structure 220 typically includes at least a gate dielectric that is also aligned with the fin channel region 216. The gate structure 220 may be planarized (e.g., by CMP) to be flush with an upper surface of the ILD 240.

[0072] In various embodiments, following fabrication of semiconductor device 200, contacts 250, 252, 255 may be formed on fin source / drain region 212, fin drain / source region 214, and gate structure 220, respectively, and further formed middle-of-line (MOL) and / or back-end-of-line (BEOL) layers 260, hereinafter referred to as metallization layer 260, according to one embodiment of the present invention.

[0073] Contacts 250, 252, 255 may be formed in ILD 240. Contact 250 may be formed on and in physical contact with fin source / drain region 212. Contact 252 may be formed on and in physical contact with fin drain / source region 214. Contact 255 (not shown) may be formed on and in physical contact with gate structure 220.

[0074] A metallization layer 260 may be deposited on the top surfaces of the contacts 250, 252, 255 and on the top surface of the ILD 240. The thickness of the metallization layer 260 may be greater than the thickness of the semiconductor layer 208.

[0075] For the metallization layer 260, a layer of dielectric material may be blanket deposited over the entire substrate and planarized. The blanket dielectric may be selected from the group consisting of silicon-containing materials such as SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, and SiCH compounds, the above silicon-containing materials with some or all of the Si substituted with Ge, carbon-doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon-containing materials, organic-inorganic materials such as spin-on glass and silsesquioxane-based materials, and diamond-like carbon (DLC, also known as amorphous hydrogenated carbon, α-C:H). Additional options for the blanket dielectric include any of the aforementioned materials in porous form or in forms that change from porous and / or permeable to non-porous and / or non-permeable during processing.

[0076] Blanket dielectrics can be formed by a variety of methods well known to those skilled in the art, including but not limited to spinning from solution, jetting from solution, CVD, PECVD, sputter deposition, reactive sputter deposition, ion beam deposition, and evaporation.

[0077] The deposited blanket dielectric may then be patterned and etched to form holes or openings for the various contacts 250, 252, 255 and / or other conductive wiring features underneath. Following via formation, conductive interconnects 262, 265 (not shown), 267 (not shown), 269 (not shown) are formed by depositing a conductive metal in the via holes using conventional processes such as CVD or plating. The conductive metal may include, but is not limited to, tungsten, copper, aluminum, silver, gold, and alloys thereof. The metallization layer 260 may comprise one or more stacks of wires / vias that may form the interconnects 262, 265, 267, or 269, or combinations thereof. The conductive interconnects 262 may be formed on and physically connected to the underlying conductive wiring features. The conductive interconnects 265 may be formed on and physically connected to the underlying contacts 250. Conductive interconnect 267 may be formed on and physically connected to underlying contact 252. Conductive interconnect 269 may be formed on and physically connected to underlying contact 255.

[0078] 3 is a cross-sectional view of a stacked semiconductor device 299 shown after respective fabrication operations according to one or more embodiments. At this stage of fabrication, semiconductor device 100 is stacked and bonded to semiconductor device 200 to form stacked semiconductor device 299.

[0079] Semiconductor device 100 may be vertically stacked and bonded at the wafer level to semiconductor device 200. Semiconductor device 100 may be flipped or oriented relative to semiconductor device 200 such that the backside of semiconductor device 100 (i.e., semiconductor substrate 104) faces up, as shown.

[0080] Semiconductor device 100 can be stacked and bonded onto semiconductor device 200 by known 3D or stacked IC device integration schemes that utilize the z-direction to achieve electrical performance advantages. For example, interconnects 162 and interconnects 262 can be TSVs and can be physically and electrically connected by known bonding materials such as solder. One or more adhesion layers can further bond the top surface of semiconductor device 100 to the top surface of semiconductor device 200. For example, an adhesion layer (not shown) can bond metallization layer 160 to metallization layer 260.

[0081] 4 is a cross-sectional view of a stacked semiconductor device 299 shown after respective fabrication operations according to one or more embodiments, at this stage of fabrication, where the backside of the ETSOI layer 108 is exposed.

[0082] The backside of the ETSOI layer 108 may be exposed by selectively removing the semiconductor substrate 104 and at least partially selectively removing the buried insulator 106, while retaining the semiconductor structure 100 beneath the backside of the ETSOI layer 108, as shown. For example, the semiconductor substrate 104 is selectively etched away, while retaining the other semiconductor structure 100 materials beneath it. Then, in a different etching step, the buried insulator 106 is selectively etched away, while retaining the underlying isolation region 110 and the ETSOI layer 108, as well as the other semiconductor structure 100 materials.

[0083] 5 is a cross-sectional view of a stacked semiconductor device 299 shown after respective fabrication operations according to one or more embodiments, at this stage of fabrication, a stress layer 300 is formed on the exposed backside of the ETSOI layer 108.

[0084] The stress layer 300 may be formed by depositing a dielectric material over the isolation region 110 and / or the ETSOI layer 108. The stress layer 300 may have a thickness of about 10 nm to about 200 nm. Exemplary stress layer materials may be, but are not limited to, SiN, SiC, SiON, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN, SiOx, alternative metals on liners as insulators, combinations thereof, and the like. Additionally, the stress layer 300 may be a low-k material.

[0085] After forming the stress layer 300, the excess stress layer 300 material may be removed by an etching or polishing process, such as CMP. Removal of the excess stress layer 300 material may be accomplished using, for example, a selective wet etching process, or a selective dry etching process, or other subtractive removal techniques, as known in the art.

[0086] The stress layer 300 has an internal or inherent tension or stress such that there is an internally generated tensile stress or an internally generated compressive stress, as desired.

[0087] Compressive forces may be created by pre-generating an internal tensile stress by spacing the constituent atoms of the stress layer 300 farther apart than their equilibrium position. Such a material will then attempt to contract (to return to equilibrium), generating an inward pulling force within the stress layer 300 (e.g., laterally toward the center of the page). Similarly, internal compressive stress may be created by pre-generating an internal compressive stress by spacing the constituent atoms of the stress layer 300 closer together than their equilibrium position. Such a material will then attempt to expand (to return to equilibrium), generating an outward pulling force within the stress layer 300 (e.g., laterally toward the left and right sides of the page).

[0088] When the stress layer 300 has an initial intrinsic tensile stress, the resulting stress layer 300 causes the underlying ETSOI layer 108 to contract laterally toward the center of the page. This results in the atoms in the ETSOI layer 108 being spaced closer together. Thus, the stress layer 300 may generate or result in an intrinsic inward compressive stress in the ETSOI layer 108 laterally toward the center of the page. This resulting compressive stress in the ETSOI layer 108 may improve hole mobility therein. Specifically, the resulting intrinsic compressive stress in the ETSOI layer 108 may improve hole mobility through the channel region 116 in a p-type FET.

[0089] When the stress layer 300 has an initial intrinsic compressive stress, the resulting stress layer 300 pulls the underlying ETSOI layer 108 laterally toward the left and right sides of the page. This results in the atoms in the ETSOI layer 108 being spaced further apart. Thus, the stress layer 300 may generate or result in an intrinsic outward tensile stress in the ETSOI layer 108 laterally toward the left and right sides of the page. This resulting tensile stress in the ETSOI layer 108 may improve electron mobility therein. Specifically, the resulting intrinsic tensile stress in the ETSOI layer 108 may improve electron mobility through the channel region 116 in an n-type FET.

[0090] The stress layer 300 may be formed by plasma enhanced chemical vapor deposition (PECVD) or the like, such that the respective process parameters such as the carrier and reactive gas composition, substrate temperature, deposition pressure, and especially ion bombardment during deposition can greatly affect the final resulting intrinsic stress of the stress layer 300.

[0091] The high level of intrinsic tensile stress in the stress layer 300 can be generated by an annealing or curing step that induces contraction of the material of the stress layer 300, resulting in a subsequent tensile expansion (to return to equilibrium). This additional step can be performed immediately after the material deposition of the stress layer 300, or later in the process flow. In one example, such an additional annealing or curing step displaces hydrogen from within the material of the stress layer 300, generating internally contracted chemical bonds, resulting in a high level of intrinsic tensile stress. For example, when the stress layer 300 is deposited and annealed, a high intrinsic tensile stress of up to 2 GPa or significantly more can be achieved, for example, by displace hydrogen during or after deposition, or by reducing ion bombardment by establishing a deposition atmosphere with a low level of radio frequency (RF) power to obtain the desired internally generated tensile stress.

[0092] 6 illustrates a cross-sectional view of a stacked semiconductor device 299 shown after respective fabrication operations according to one or more embodiments, in which the stress layer 300 is patterned, thereby removing portions of the stress layer 300 while retaining other portions of the stress layer 300.

[0093] The patterned stress layer 300 may be formed by known patterning and etching techniques, such as forming a mask (not shown) on the stress layer 300, patterning the mask, and etching or removing unwanted portions of the stress layer 300 through the patterned mask. Removing portions of the stress layer 300 may expose underlying materials of the semiconductor device 100 (e.g., the ETSOI layer 108, the isolation 110, etc.).

[0094] In embodiments of the invention, the retained portion of the stress layer 300, sometimes referred to herein as stress portion 300, may be vertically aligned with a channel region of the mating FET (as illustratively shown in FIG. 8) or may be vertically aligned with a source / drain region of the mating FET (as illustratively shown in FIG. 7). For example, the sidewalls of the stress portion 300 may be between respective sidewalls of the underlying gate spacers.

[0095] 7 is a cross-sectional view of a stacked semiconductor device 299 shown after respective fabrication operations according to one or more embodiments. At this stage of fabrication, the semiconductor device 100 includes a stressed portion 300 formed from a first stress layer 300 to have an intrinsic tensile stress in the nFET channel region 116 in the nFET region 402 and a stressed portion 300 formed from a second stress layer 300 to have an intrinsic compressive stress in the pFET channel region 116 in the pFET region 404.

[0096] In the nFET region 402, the first stress portion 300 is vertically aligned with the source / drain region 130 and the drain / source region 132, respectively, and has an initial internal tensile stress that, after equilibration, causes the underlying ETSOI layer 108 to contract in the horizontal direction toward the source / drain region. As a result, the atoms in the ETSOI layer 108 are spaced closer together. Thus, the first stress portion 300 creates an intrinsic inwardly pulling compressive stress in the ETSOI layer 108 between the first stress portion 300 and the source / drain region 130 and the drain / source region 132, respectively, in the horizontal direction toward the source / drain region, as shown. This intrinsic compressive stress in the ETSOI layer 108 results in a tensile stress in the ETSOI channel region 116. Specifically, the intrinsic tensile stress in the ETSOI channel region 116 improves the electron mobility in the n-type FET in the nFET region 402.

[0097] In the pFET region 404, the second stress portion 300 is vertically aligned with the source / drain region 130 and the drain / source region 132, respectively, and has an internal compressive stress that pulls the underlying ETSOI layer 108 horizontally toward the center of the channel region 116 early on after equilibration. This results in the atoms in the ETSOI layer 108 being spaced further apart. Thus, the second stress portion 300 may create an internal outward pulling tensile stress in the ETSOI layer 108 between the second stress portion 300 and the source / drain region 130 and the drain / source region 132, respectively, horizontally toward the center of the channel region 116, as shown. This internal tensile stress in the ETSOI layer 108 creates a compressive stress in the ETSOI channel region 116. Specifically, the intrinsic compressive stress in the ETSOI channel region 116 improves hole mobility in the p-type FET in the pFET region 404 .

[0098] 8 is a cross-sectional view of a stacked semiconductor device 299 shown after respective fabrication operations according to one or more embodiments. At this stage of fabrication, the semiconductor device 100 includes a stressed portion 300 formed from a first stress layer 300 to have an intrinsic tensile stress in the nFET channel region 116 in the nFET region 402 and a stressed portion 300 formed from a second stress layer 300 to have an intrinsic compressive stress in the pFET channel region 116 in the pFET region 404.

[0099] In the nFET region 402, the first stress portion 300 is vertically aligned with the channel region 116 and has an initial internal compressive stress that, after equilibration, pulls the underlying ETSOI region 108 horizontally toward the source / drain regions. This results in the atoms in the ETSOI layer 108 moving further apart. Thus, the first stress portion 300 generates an internal tensile stress that pulls outwardly in the ETSOI layer 108 horizontally toward the source / drain regions as shown. This internal tensile stress in the ETSOI layer 108 may improve the electron mobility therein. Specifically, the internal tensile stress in the ETSOI layer 108 may improve the electron mobility through the channel region 116 in the n-type FET in the nFET region 402.

[0100] In the pFET region 404, the second stress portion 300 is vertically aligned with the channel region 116 and has an initial internal tensile stress that, after equilibration, causes the underlying ETSOI region 108 to contract horizontally in a direction toward the center of the channel region 116. This results in the atoms in the ETSOI layer 108 being spaced closer together. In this manner, the second stress portion 300 may generate an internally inwardly pulling compressive stress in the ETSOI layer 108 horizontally in a direction toward the center of the channel region 116, as shown. This internal compressive stress in the ETSOI layer 108 may improve hole mobility therein. Specifically, the internal compressive stress in the ETSOI layer 108 may improve hole mobility through the channel region 116 in the p-type FET in the pFET region 404.

[0101] In alternative embodiments, the stressed portions 300 can be formed in the same stress layer. For example, the stressed portion 300 having an early intrinsic compressive stress can be formed aligned with the channel region 116 in the nFET region 402 and aligned with the source / drain region with the pFET region 404. Alternatively, the stressed portion 300 having an early intrinsic tensile stress can be formed aligned with the source / drain region in the nFET region 402 and aligned with the channel region 116 with the pFET region 404.

[0102] FIG. 9 is a cross-sectional view of a semiconductor device 500 including an SOI substrate 102, in accordance with one embodiment of the present invention.

[0103] The SOI substrate 102 includes a semiconductor substrate 104, a buried insulator 106 on the semiconductor substrate 104, and a semiconductor layer 108 on the buried insulator 106. In this embodiment, the semiconductor layer 108 may be a finFET fin layer 108 formed on the buried insulator 106.

[0104] The semiconductor layer 108 may include any of the semiconductor materials, similar to the ETSOI layer 108, the description of which will not be repeated herein. The finFET fin layer 108 may be thicker than the ETSOI layer 108.

[0105] A dummy gate (not shown) having sidewall spacers 126 may be formed on the channel region 116 of the FinFET fin 508. A raised source / drain region 130 and a raised drain / source region 132 may be formed on the mating source / drain region 112 of the FinFET fin 508 and the mating drain / source region 114 of the FinFET fin 508. The raised source / drain region 130 and the raised drain / source region 132 may be formed adjacent to the dummy gate according to an embodiment of the invention. The raised source / drain region 130 and the raised drain / source region 132 may be epitaxially formed using the sidewalls of the FinFET fin 508 as a source or growth plane, resulting in a diamond-shaped raised source / drain region 130 and a diamond-shaped raised drain / source region 132 as shown.

[0106] In various embodiments, fabrication of semiconductor device 500 may be followed by forming isolation 110 (e.g., shallow trench isolation (STI)), forming a dummy gate (not shown), forming sidewall spacers 126 on either end of the dummy gate, forming FinFET fin 508 source / drain regions 112, forming FinFET fin 508 drain / source regions 114, forming raised source / drain regions 130, and forming raised drain / source regions 132.

[0107] FinFET fin 508 channel region 116 may be formed between FinFET fin 508 source / drain region 112 and FinFET fin 508 drain / source region 114. In addition, a dummy gate may be placed on a dummy gate oxide (not shown), which may be formed on FinFET fin 508 channel region 116. The dummy gate oxide may be further positioned between a lower portion of spacers 126. The dummy gate has a thickness greater than a thickness of the dummy gate oxide.

[0108] The isolation region 110 may be formed by etching a trench in the substrate 102 using a conventional dry etching process, such as RIE or plasma etching. The trench may optionally be lined with a conventional liner material, such as silicon nitride or silicon oxynitride, and then CVD or another similar deposition process is used to fill the trench with silicon oxide or another such as an STI dielectric material. The STI dielectric may optionally be densified after deposition. A conventional planarization process, such as chemical mechanical polishing (CMP), may optionally be used to provide a planar structure.

[0109] In various embodiments, the dummy gate may be formed by forming and then patterning a dummy gate layer. The dummy gate may include a stack of overlapping materials, such as a dummy gate dielectric (e.g., silicon oxide), amorphous silicon, and a dielectric cap (e.g., silicon nitride). Later in the process sequence, the dummy gate is removed and replaced with a functional gate structure having one or more gate dielectrics and at least one gate conductor. The dummy gate has a thickness that is greater than the thicknesses of the raised source / drain regions 130 and the raised drain / source regions 132. The top surface of the dummy gate may be coplanar with the top surface of the spacer 126.

[0110] The spacers 126 may be formed by deposition followed by a directional etch (e.g., RIE). The spacers 126 may be formed along the sidewalls of the dummy gate. For example, a spacer material such as a nitride (e.g., silicon nitride) may be deposited by a conventional method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Other techniques that may be suitable for deposition of the nitride layer include low pressure CVD (LPCVD) and atmospheric pressure CVD (APCVD). A portion of the deposited nitride layer is then etched away in a conventional manner to form the spacers 126. The spacer material may be silicon oxide, silicon oxynitride, silicon nitride, SiBCN, SiOCN, SiOC, or any suitable combination of these materials.

[0111] The dummy gate and spacers 126 may be formed before the FinFET fin 508 source / drain regions 112 and the FinFET fin 508 drain / source regions 114. In various embodiments, the FinFET fin 508 source / drain regions 112 and the FinFET fin 508 drain / source regions 114 may be formed by doping the relevant FinFET fin 508 regions with an appropriate N-type or P-type dopant. The dopant may be provided to the FinFET fin 508 source / drain regions 112 and the FinFET fin 508 drain / source regions 114 by ion implantation. The FinFET fin 508 source / drain regions 112 and the FinFET fin 508 drain / source regions 114 may then be annealed. In various embodiments, the doped FinFET fin 508 source / drain regions 112 and the FinFET fin 508 drain / source regions 114 may be n-doped or p-doped.

[0112] In various embodiments, the doped regions 112, 114 may be doped in situ or ex situ, for example, by ion implantation or thermal diffusion of dopants into the FinFET fin 508. The source dopants may be activated by annealing. Other suitable doping techniques may also be used, including, but not limited to, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid phase doping, solid phase doping, or combinations thereof.

[0113] Forming the raised source / drain regions 130 and the raised drain / source regions 132 may include forming an in situ doped epitaxial semiconductor material on or around the doped regions 112, 114. The term "epitaxial semiconductor material" refers to a semiconductor material formed using an epitaxial deposition or growth process.

[0114] In various embodiments, following fabrication of the semiconductor device 500, an interlevel dielectric (ILD) layer 140 can be formed over the raised source / drain regions 130, 132 and the dummy gate can be removed to define the recesses. The ILD 140 can have a dielectric liner (e.g., silicon nitride) and a fill dielectric material (e.g., silicon oxide).

[0115] In various embodiments, an oxide fill of the ILD 140 is performed. The ILD 140 may be planarized. The ILD 140 encompasses, covers, or surrounds the entire raised source / drain regions 130, 132. The ILD 140 engages the outer surface of the sidewall spacer 126. In one embodiment, the ILD 140 extends to the top point of the spacer 126. Stated differently, the ILD 140 is flush with the distal end of the spacer 126. Alternatively, as shown, the ILD 140 may have a thickness greater than the height of the spacer 126. Additionally, the dummy gate may be removed, providing a gap or recess between the inner sidewalls of the spacer 126. In various embodiments, the height of the ILD 140 may be selectively reduced by chemical mechanical polishing (CMP) and / or etching. Thus, the planarization process may be provided by CMP. Other planarization processes may include grinding and polishing.

[0116] In various embodiments, following fabrication of the semiconductor device 500, a replacement gate structure 120 may be formed in the recess formed by removal of the dummy gate according to an embodiment of the present invention. In various embodiments, the newly formed gate structure 120 includes a gate dielectric (not shown) deposited in the recess, a gate conductor 122, and a gate cap 124. The gate dielectric may contact the inner surfaces of the sidewall spacers 126 and a portion of the top surface of the semiconductor layer 108. The gate conductor 122 is then filled into the gate dielectric. The gate conductor 122 may be formed by deposition followed by planarization (e.g., CMP) so that it is flush with or below the top surface of the gate spacers 126.

[0117] In various embodiments, following fabrication of the semiconductor device 500, contacts 150, 152, 155 may be formed on the raised source / drain regions 130, the raised drain / source regions 132, and the gate structure 120, respectively, and an intermediate metallization layer 160 may be formed in accordance with an embodiment of the present invention.

[0118] Contacts 150, 152 may be formed in the ILD 140. Contact 150 may be formed on and in physical contact with the raised source / drain region 130. Contact 152 may be formed on and in physical contact with the raised drain / source region 132. Contact 155 (not shown) may be formed on and in physical contact with the gate structure 120.

[0119] A metallization layer 160 may be deposited on the top surfaces of the contacts 150, 152, 155 and on the top surface of the ILD 140. The thickness of the metallization layer 160 may be greater than the thickness of the ETSOI layer 108.

[0120] With respect to the metallization layer 160, a layer of dielectric material may be blanket deposited over the entire substrate and planarized. The deposited blanket dielectric may then be patterned and etched to form holes or openings for the various contacts 150, 152, 155 and / or other conductive wiring features underneath. Following via formation, conductive interconnects 162 (not shown), 165 (not shown), 167 (not shown), 169 (not shown) are formed by depositing a conductive metal in the via holes using conventional processes such as CVD or plating. Conductive metals may include, but are not limited to, tungsten, copper, aluminum, silver, gold, and alloys thereof. The BEOL layer may comprise one or more stacks of wires / vias that may form the interconnects 162, 165, 167, or 169, or combinations thereof. The conductive interconnects 162 may be formed on and physically connected to the underlying conductive wiring features. Conductive interconnect 165 may be formed on and physically connected to underlying contact 150. Conductive interconnect 165 may be formed on and physically connected to underlying contact 152. Conductive interconnect 169 may be formed on and physically connected to underlying contact 155.

[0121] For clarity, as described herein, semiconductor device 500 may replace semiconductor device 100 in stacked semiconductor device 299. Thus, as described herein with respect to semiconductor device 100, semiconductor substrate layer 104 and BOX layer 106 may be removed, and stress layer 300 may be formed on at least a backside surface of one or more FinFET fins 508.

[0122] FIG. 10 illustrates an example plot of in-plane lattice deformation versus fin depth for a FinFET fin 508 of a semiconductor device 500, according to one or more embodiments. As illustrated, when the FinFET fin 508 includes induced channel stress from source / drain stressors and other materials fabricated on the SOI substrate, there is a non-uniform induced stress distribution through the depth of the FinFET fin 308, with the highest amount of stress at the top of the FinFET fin 508. However, if a backside stressor 300 is also applied to the backside of the FinFET fin 508, along with the source / drain stressors and other materials fabricated on the SOI substrate, a more uniform stress distribution through the thickness of the FinFET fin 508 may be achieved. This uniform stress distribution through the thickness of the FinFET fin 508 may improve the distribution of electron or hole mobility, such as through the channel region 116 of the FinFET fin 508. In other words, the electron or hole mobility through the thickness of the FinFET fin 508 may be made more uniform with both the frontside and backside fin stressors 300 as shown.

[0123] For clarity, the surface opposite the exposed backside of the semiconductor layer 108 on which the stress portion 300 is formed may be referred to herein as the frontside of the semiconductor layer 108. Additionally, the bottom surface of the semiconductor device 200 as shown may be referred to herein as the backside of the semiconductor device 200. Similarly, the backside of such a semiconductor device 100, 500, etc. may be the top surface of the stacked semiconductor device 299 due to the semiconductor device 100, 500, etc. being "flipped" and bonded to the lower semiconductor device 200. Thus, the backside of the semiconductor device 100 may face opposite or be opposite the backside of the semiconductor device 100, 500, etc.

[0124] 11 is a flow diagram illustrating a semiconductor device fabrication method 600 according to one or more embodiments. The method 600 may be illustratively utilized to fabricate the semiconductor device 299. The method 600 may begin at block 602, followed by forming a first IC semiconductor device on or with a first SOI substrate (block 604). For example, a first ETSOI semiconductor device 100 including an SOI substrate 102 may be formed, a first FinFET semiconductor device 500 including an SOI substrate 102 may be formed, a first nanosheet FET semiconductor device including an SOI substrate 102 may be formed, etc.

[0125] The method 600 may continue by forming a second IC semiconductor device on or including a second substrate (block 606). For example, a wafer, carrier, interposer, etc. may be formed. In some embodiments, the semiconductor device 200 may be formed including one or more FETs (e.g., finFETs, nanowire FETs, nanosheet FETs, gate-all-around FETs, etc.).

[0126] The method 600 may continue by flipping, stacking and bonding the semiconductor device of the first IC to a second IC semiconductor device (block 608). For example, TSV 262 in metallization layer 260 of semiconductor device 200 may be bonded to TSV 162 in metallization layer 160 of semiconductor device 100, TSV 262 in metallization layer 260 of semiconductor device 200 may be bonded to TSV 162 in metallization layer 160 of semiconductor device 500, etc.

[0127] The method 600 may continue with selective removal of the semiconductor substrate layer and the buried oxide layer of the first IC semiconductor device (block 610). For example, the semiconductor layer 104 and the buried oxide layer 106 on top of the backside surface of the semiconductor layer 108 of the semiconductor device 100, 500, etc. are removed. For example, the semiconductor substrate layer 104 is removed first, and then the buried oxide layer 106 on top of the backside surface of the semiconductor layer 108 is removed. Such removal may generally expose the backside surface of the first IC semiconductor device (e.g., the backside surface of the semiconductor layer 108 as exemplarily shown in FIG. 4).

[0128] The method 600 may continue by forming a stress layer on the exposed backside surface (block 612). For example, the stress layer 300 may be formed on the backside of the semiconductor layer 108. The first stress layer 300 may provide a tensile stress to the underlying semiconductor layer 108 in the nFET region 402 and a compressive stress to the underlying semiconductor layer 108 in the pFET region 404.

[0129] The method 600 may continue by patterning the stress layer (block 614). For example, a first stress portion 300 may be formed in the nFET region 402 that imparts an intrinsic tensile stress in the channel region 116 therein, and a second stress portion 300 may be formed in the pFET region 404 that imparts an intrinsic compressive stress in the channel region 116 therein. The method 600 may end at block 616.

[0130] The method flow diagrams illustrated herein are exemplary. There may be many variations of the diagrams or operations described therein without departing from the scope of the embodiments. For example, operations may be performed in a different order, operations may be added, deleted, or modified. All of these variations are considered a part of the applicable claimed embodiments.

[0131] The description of various embodiments of the present invention is presented for illustrative purposes, but is not intended to be exhaustive and is not limited to the described embodiments. Many changes and modifications will be apparent to those skilled in the art without departing from the scope of the present invention. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, or to allow other skilled in the art to understand the embodiments described in this specification.

Claims

1. a lower semiconductor device comprising a first metallization layer comprising a first metallization layer through-interconnect; a flip top semiconductor device comprising: a second metallization layer with a second metallization layer through interconnect in contact with the first metallization layer through interconnect, a backside channel, and a first stressed dielectric portion on the backside channel providing an intrinsic strain in the backside channel; A stacked semiconductor device comprising:

2. 2. The stacked semiconductor device of claim 1, wherein the backside channel is a backside residual semiconductor-on-insulator (SOI) layer.

3. 3. The stacked semiconductor device of claim 2, wherein the first stressed dielectric portion is positioned in vertical alignment with an underlying first source / drain region and provides an intrinsic tensile strain within the first portion of the backside residual SOI layer.

4. 4. The stacked semiconductor device of claim 3, wherein the first stressed dielectric portion is on the first portion of the backside residual SOI layer in an n-type field effect transistor (FET) region.

5. 5. The stacked semiconductor device of claim 4, further comprising a second stressed dielectric portion on a second portion of the backside residual SOI layer in a p-type field effect transistor (FET) region.

6. 6. The stacked semiconductor device of claim 5, wherein the second stressed dielectric portion is vertically aligned with the second portion of the backside residual SOI layer and provides an intrinsic compressive strain within the second portion of the backside residual SOI layer.

7. The stacked semiconductor device of claim 6 , wherein a top surface of the second stressed dielectric portion is coplanar with a top surface of the first stressed dielectric portion.

8. 2. The stacked semiconductor device of claim 1, wherein a sidewall of the first stressed dielectric portion is vertically midway of an underlying first gate spacer.

9. 6. The stacked semiconductor device of claim 5, wherein a sidewall of the second stressed dielectric portion is vertically midway of an underlying second gate spacer.

10. 2. The stacked semiconductor device of claim 1, wherein the first stressed dielectric portion is vertically aligned with an underlying first channel region of the backside residual SOI layer to provide an intrinsic tensile strain within the underlying first channel region.

11. 11. The stacked semiconductor device of claim 10, wherein the first stressed dielectric portion is on the backside residual SOI layer in an n-type field effect transistor (FET) region.

12. 12. The stacked semiconductor device of claim 11, further comprising a second stressed dielectric portion on the backside residual SOI layer in a p-type field effect transistor (FET) region.

13. 13. The stacked semiconductor device of claim 12, wherein the second stressed dielectric portion is vertically aligned with an underlying second channel region of the backside residual SOI layer and provides an intrinsic compressive strain within the underlying second channel region.

14. 14. The stacked semiconductor device of claim 13, wherein a top surface of the second stressed dielectric portion is coplanar with a top surface of the first stressed dielectric portion.

15. 11. The stacked semiconductor device of claim 10, wherein a sidewall of the first stressed dielectric portion is vertically midway of an underlying first gate spacer.

16. 13. The stacked semiconductor device of claim 12, wherein a sidewall of the second stressed dielectric portion is vertically midway of an underlying second gate spacer.

17. a lower semiconductor device comprising a first metallization layer comprising a first metallization layer through-interconnect; a flip-top semiconductor device comprising: a second metallization layer comprising a second metallization layer through-interconnect in contact with the first metallization layer through-interconnect; a backside residual semiconductor-on-insulator (SOI) layer; a first stressed dielectric portion on the backside residual SOI layer providing an intrinsic tensile strain in a first channel region underlying the backside residual SOI layer; and a second stressed dielectric portion on the backside residual SOI layer providing an intrinsic compressive strain in a second channel region underlying the backside residual SOI layer; A stacked semiconductor device comprising:

18. 20. The stacked semiconductor device of claim 17, wherein the first stressed dielectric portion is vertically aligned with an underlying first source / drain region and the second stressed dielectric portion is vertically aligned with an underlying second source / drain region.

19. 20. The stacked semiconductor device of claim 17, wherein the first stressed dielectric portion is vertically aligned with a first channel region of the underlying layer and the second stressed dielectric portion is vertically aligned with a second channel region of the underlying layer.

20. stacking and bonding a flip top semiconductor device with a backside to a bottom semiconductor device; removing one or more semiconductor-on-insulator (SOI) layers from the backside of the flip top semiconductor device while preserving an exposed backside residual SOI layer of the flip top semiconductor device; forming a stressed dielectric layer on the exposed backside residual SOI layer of the flip-top semiconductor device; patterning and removing portions of the stressed dielectric layer to form one or more stressed dielectric portions; A method for fabricating a stacked semiconductor device comprising the steps of:

Images