MEMORY STRUCTURE WITH THREE-DIMENSIONAL NOR MEMORY STRINGS OF JUNCTIONLESS FERROELECTRIC MEMORY TRANSISTORS AND METHOD FOR MANUFACTURING SAME - Patent application

Abstract

According to the present disclosure, a memory structure including a three-dimensional NOR memory string and a method for fabricating the same are provided. In some implementations, the memory structure of the present disclosure includes randomly accessible ferroelectric storage transistors configured as a horizontal NOR memory string. The NOR memory strings are formed on a semiconductor substrate in a plurality of scalable memory stacks of thin-film storage transistors. The three-dimensional memory stacks are fabricated using a method that includes forming working trenches for vertical local word lines and forming auxiliary trenches to facilitate back-array metal replacement and channel isolation by a selective backside etching process. In some embodiments, the ferroelectric storage transistor is a junctionless field effect transistor (FeFET) having a ferroelectric polarization layer as a gate dielectric layer formed adjacent to a semiconductor oxide layer as a channel region.

Description

[Technical field]

[0001] The present invention relates to high density memory structures, and in particular to high density, low read latency memory structures and fabrication processes formed by interconnected thin film storage elements (e.g., three-dimensional arrays of thin film storage transistors), including those configured as NOR type memory strings ("NOR memory strings"). [Background technology]

[0002] A NOR type memory string includes storage transistors that share a common source region and a common drain region, and each storage transistor can be individually addressed and accessed. U.S. Patent No. 10,121,553, entitled "Capacitively Coupled Nonvolatile Thin Film Transistor NOR Strings in a Three-Dimensional Array," issued on November 6, 2018, discloses storage transistors (or memory transistors) configured as a three-dimensional array of NOR memory strings formed above a plane of a semiconductor substrate. The disclosure of U.S. Patent No. 10,121,553 is incorporated herein by reference in its entirety for all purposes. The NOR memory string disclosed in U.S. Patent No. 10,121,553 includes multiple thin film storage transistors that share a common bit line and a common source line. In particular, U.S. Patent No. 10,121,553 discloses a NOR memory string that includes (i) common source and drain regions that extend longitudinally along a horizontal direction, and (ii) a gate electrode of each storage transistor that extends along a vertical direction. As used herein, the term "vertical" refers to a direction perpendicular to a surface of a semiconductor substrate, and the term "horizontal" refers to a direction parallel to a surface of a semiconductor substrate. In a three-dimensional array, NOR memory strings are provided on multiple planes (e.g., 8 or 16 planes) above a semiconductor substrate, and the NOR memory strings on each plane are arranged in a column. In the case of a charge trapping type storage transistor, data is stored in each storage transistor using a charge storage film as a gate dielectric material. For example, the charge storage film includes a tunnel dielectric layer, a charge trapping layer, and a blocking layer, which can be realized as a multilayer body of silicon oxide, silicon nitride, and silicon oxide stacked in that order, and is called an ONO layer. An electric field applied to the charge storage film changes the threshold voltage of the storage transistor by adding or removing charge to or from the charge trapping layer of the charge storage film, thereby encoding a given logic state in the storage transistor.

[0003] Advances in electrically polarizable materials ("ferroelectric materials"), especially those used in semiconductor manufacturing processes, suggest new potential applications in ferroelectric memory circuits. For example, the paper "Ferroelectricity in Hafnium Oxide: CMOS compatible Ferroelectric Field Effect Transistors," by TS Boscke et al., published in 2011 International Electron Devices Meeting (IEDM), pp. 24.5.1-24.5.4, discloses a ferroelectric field effect transistor ("FeFET") that uses hafnium oxide as the gate insulating film material. By controlling the polarization direction of the ferroelectric gate dielectric layer, the FeFET can be programmed to have one of two threshold voltages. Each threshold voltage of the FeFET constitutes a state that represents a specified logic value, e.g., a "programmed" state and an "erased" state. Such FeFETs have been applied in high-density memory circuits. For example, U.S. Patent No. 9,281,044, entitled “Apparatus Having a Ferroelectric Field Effect Transistor Memory Array and Related Methods,” by DV Nirmal Ramaswamy et al., filed May 17, 2013, discloses a three-dimensional array of FeFETs. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Pat. No. 10,121,553 [Patent Document 2] U.S. Patent No. 9,281,044 Summary of the Invention [Means for solving the problem]

[0005] In accordance with the present disclosure, a memory structure including a 3D NOR memory string of junctionless ferroelectric memory transistors and a method for fabricating the same are provided, as substantially described, for example, with reference to at least one of the drawings and more fully set forth in the claims.

[0006] In some embodiments, the present disclosure provides a three-dimensional memory structure formed on a plane of a semiconductor substrate. The three-dimensional memory structure of the present disclosure includes a plurality of memory stacks arranged along a first direction generally parallel to the plane of the semiconductor substrate. Each memory stack is separated from an adjacent memory stack along the first direction by a trench, and each memory stack and each trench extends in a second direction orthogonal to the first direction and generally parallel to the plane of the semiconductor substrate. Each memory stack includes at least one active layer, the active layer including a first conductive layer and a second conductive layer spaced apart from each other by a first insulating layer. The trenches include a first type of trench and a second type of trench alternately arranged along the first direction.

[0007] The three-dimensional memory structure of the present disclosure further comprises a plurality of gate electrode structures disposed in the first type of trenches and spaced apart from one another in a second direction. The gate electrode structures extend in a third direction substantially perpendicular to the plane of the semiconductor substrate. Each gate electrode structure includes (i) a semiconductor oxide layer formed on a sidewall of the first type of trench and in contact with the first conductive layer and the second conductive layer, (ii) a ferroelectric layer disposed adjacent to the semiconductor oxide layer, and (iii) a gate conductor layer formed adjacent to the ferroelectric layer. The three-dimensional memory structure of the present disclosure further comprises an insulating material disposed in the second type of trenches.

[0008] Each active layer in the memory stack forms a plurality of thin-film ferroelectric memory transistors arranged as a NOR memory string, each thin-film ferroelectric memory transistor formed at an intersection of an active layer and a gate electrode structure, and the plurality of memory stacks form a plurality of NOR memory strings within the first type of trenches.

[0009] These and other advantages, aspects and novel features of the present invention, as well as details of illustrated embodiments thereof, will become more fully understood by reference to the following description and accompanying drawings. [Brief description of the drawings]

[0010] Various embodiments of the present invention are disclosed in the following detailed description and in the accompanying drawings, which depict various embodiments of the present invention, but which are not intended to be limited to the depicted embodiments. It should be understood that like reference numerals indicate like structural elements in the drawings, and that the depictions in the drawings are not necessarily drawn to scale.

[0011] [Figure 1] FIG. 1 is a perspective view of a memory structure including a three-dimensional array of NOR memory strings according to some embodiments. [Figure 1A] FIG. 1A illustrates a detailed structure of a storage transistor formed in the memory structure shown in FIG. 1 according to some embodiments. [Diagram 2] FIG. 2 is a cross-sectional view of a tile in the memory device of FIG. 1 in the YZ plane in an embodiment of the present invention. [Diagram 3] FIG. 3 illustrates the application of the memory device of the present invention as an embedded memory device in some embodiments. [Figure 4A] FIG. 4A illustrates a process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 4B]FIG. 4B illustrates a process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 4C] FIG. 4C illustrates a process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 4D] FIG. 4D illustrates a process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 4E] FIG. 4E illustrates a process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 4E-1] FIG. 4E-1 illustrates a process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 4F] FIG. 4F illustrates a process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 4G] FIG. 4G illustrates a process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 4H] FIG. 4H illustrates a process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 4I] FIG. 4I illustrates a process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 4J] FIG. 4J illustrates a process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 4K] FIG. 4K illustrates a process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 4L] FIG. 4L illustrates a process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 4M] FIG. 4M illustrates a process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 4M-1] FIG. 4M-1 illustrates a process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 4N] FIG. 4N illustrates a process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 4O] FIG. 4O illustrates a process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 4O-1] FIG. 4O-1 illustrates a process for fabricating a memory structure including an HNOR memory string in an embodiment of the present invention. [Figure 4P] FIG. 4P illustrates a process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 5A] FIG. 5A is a cross-sectional view of a portion of a memory structure in the XY plane showing a NOR memory string with pre-charge transistors in accordance with an embodiment of the present invention. [Figure 5B] FIG. 5B is a cross-sectional view of a portion of a memory structure in the XY plane showing a NOR memory string with precharge transistors in an embodiment of the present invention. [Figure 5C] FIG. 5C is a cross-sectional view of a portion of a memory structure in the XY plane showing a NOR memory string with precharge transistors in an embodiment of the present invention. [Figure 6A] FIG. 6A is a detailed structural diagram of a junctionless ferroelectric storage transistor in another embodiment. [Figure 6B] FIG. 6B is a detailed structural diagram of a junctionless ferroelectric storage transistor in another embodiment. [Figure 6C]FIG. 6C is a detailed structural diagram of a junctionless ferroelectric storage transistor in another embodiment. [Figure 6D] FIG. 6D is a detailed structural diagram of a junctionless ferroelectric storage transistor in another embodiment. [Figure 6E] FIG. 6E is a detailed structural diagram of a junctionless ferroelectric storage transistor in another embodiment. [Figure 6F] FIG. 6F is a detailed structural diagram of a junctionless ferroelectric storage transistor in another embodiment. [Figure 7] FIG. 7 is a cross-sectional view of a memory structure including a three-dimensional array of NOR memory strings in another embodiment of the present invention. [Figure 8A] FIG. 8A illustrates another process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 8B] FIG. 8B illustrates another process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 9] FIG. 9 illustrates a memory structure formed using dummy layers to isolate channel layers for global word line connections in accordance with some embodiments. [Figure 10A] FIG. 10A illustrates another process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 10B] FIG. 10B illustrates another process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 10C] FIG. 10C illustrates another process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 10D] FIG. 10D illustrates another process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 10E] FIG. 10E illustrates another process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 10F] FIG. 10F illustrates another process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 10G] FIG. 10G illustrates another process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. [Figure 10H] FIG. 10H illustrates another process for fabricating a memory structure including an HNOR memory string in accordance with an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] In an embodiment of the invention, a memory structure includes randomly accessible ferroelectric storage transistors organized as horizontal NOR memory strings formed on a semiconductor substrate in multiple scalable memory stacks of thin-film storage transistors. The three-dimensional memory stacks are fabricated by a process that includes forming working trenches for vertical local word lines and selective backside etching to form auxiliary trenches to facilitate back array metal replacement and channel isolation.

[0013] In some embodiments, the ferroelectric storage transistor is a thin-film ferroelectric field effect transistor (FeFET) having a ferroelectric polarization layer as a gate dielectric layer. The ferroelectric polarization layer, also called a "ferroelectric gate dielectric layer", is formed adjacent to a semiconductor oxide layer as a channel region. The ferroelectric storage transistor includes a source region and a drain region. Both the source region and the drain region are formed from a metallic conductive material and are in electrical contact with the semiconductor oxide channel region. The ferroelectric storage transistor thus formed is a junctionless transistor that does not have a p / n junction in the channel and the threshold voltage is modulated by the polarization of the mobile carriers in the ferroelectric polarization layer. In the memory structure of the present invention, the ferroelectric storage transistor in each NOR memory string is controlled by an individual control gate electrode to allow individual addressing and access. In some embodiments, the ferroelectric polarization layer is formed from a doped hafnium oxide material and the semiconductor oxide channel region is formed from an amorphous metal oxide semiconductor material.

[0014] As used herein, the term "storage transistor" is used interchangeably with the term "memory transistor" to refer to memory devices formed in the memory structures described herein. In some embodiments, the memory structures of the present disclosure, including NOR memory strings of randomly accessible storage transistors (or memory transistors), can have applications in computer systems, e.g., as main memory, where data storage locations are directly accessible by the processor of the computer system, in the role played by traditional random access memories (RAMs), such as dynamic RAMs (DRAMS) and static RAMs (SRAMs). For example, the memory structures of the present disclosure can be applied to computer systems to function as random access memory to support the operation of microprocessors, graphical processors, and artificial intelligence processors. In other embodiments, the memory structures of the present disclosure can also be applied to form storage systems, such as solid state drives or hard drive replacements, to provide long-term data storage for computer systems.

[0015] As used herein, the term "semiconductor oxide layer" (also referred to as "oxide semiconductor layer" or "metal oxide semiconductor layer") refers to a thin film semiconductor material made from a conductive metal oxide such as zinc oxide or indium oxide, or any suitable conductive metal oxide having charge carriers with electron mobility that can be modified or tuned by proper preparation or the inclusion of suitable impurities.

[0016] In an embodiment of the present invention, a memory structure includes a memory stack, each memory stack including a plurality of NOR memory strings formed vertically stacked on top of each other. In some implementations, the stack of NOR memory strings is formed by a group of thin films deposited successively on a plane of a semiconductor substrate, each group of thin films being referred to herein as an "active layer." The active layers in each stack of NOR memory strings are stacked on top of each other, each active layer being separated from the other active layers by an interlayer insulating layer. Each active layer includes a common drain line and a common source line vertically spaced apart from each other by a channel spacer dielectric layer. Both the common source line and the common drain line run along a horizontal direction.

[0017] The storage transistors in each NOR memory string share a common source line and a common drain line. The channel layers of the storage transistors are formed on the sidewalls of the memory stacks and are in contact with the common source line and the common drain line of each NOR memory string. The gate dielectric and gate conductor layers of the storage transistors are formed vertically in narrow working trenches between the memory stacks to form storage transistors in multiple parallel planes of each stack. A storage transistor is formed at each intersection of the gate conductor layer and the common source line and common drain line of the memory strings. The gate conductor layer is also referred to herein as a local word line (LWL), and the working trench is also referred to herein as an "LWL trench." That is, the working trench or LWL trench is the trench in which the gate conductor layer of the local word line is formed and the storage transistor is fabricated. As mentioned above, the term "vertical" refers to a direction perpendicular to the surface of the semiconductor substrate, and the term "horizontal" refers to any direction parallel to the surface of the semiconductor substrate.

[0018] In this embodiment, the storage transistors in the NOR memory string are ferroelectric field effect transistors that include a ferroelectric thin film as a gate dielectric layer, also referred to as a ferroelectric polarization layer, a ferroelectric gate dielectric layer, or a ferroelectric layer. In a ferroelectric field effect transistor (FeFET), the polarization direction of the ferroelectric gate dielectric layer is controlled by an electric field applied between the drain terminal of the transistor and the gate electrode of the transistor, and the change in polarization direction changes the threshold voltage of the FeFET. In some embodiments, an electric field is applied to both the drain and source terminals of the transistor relative to the transistor gate electrode. For example, an FeFET can be programmed to have one of two threshold voltages, and each threshold voltage of the FeFET can be used to encode a given logic state. For example, two threshold voltages of the FeFET can be used to encode a "programmed" state and an "erased" state, each of which represents a specified logic value. In one embodiment, the programmed state is associated with a lower threshold voltage and the erased state is associated with a higher threshold voltage. In some embodiments, more than two threshold voltages may be used to represent more than two memory states in each FeFET.

[0019] The memory structure of the present invention provides many advantages over known or existing memory structures and devices.

[0020] First, ferroelectric storage transistors fabricated on vertical sidewalls are very compact and can be fabricated in 3D memory stacks at low temperatures compatible with logic back-end-of-line (BEOL) processes. Ferroelectric storage transistors can operate at lower voltages than conventional charge-trapping storage transistors. These properties of ferroelectric storage transistors allow for easy integration of memory arrays of 3D horizontal NOR (HNOR) memory strings directly above digital and analog integrated circuits built on the surface of a semiconductor substrate. Until recently, ferroelectric transistors had limited endurance. Recent advances in ferroelectric memory research have enabled the fabrication of ferroelectric storage transistors with endurance of up to 1×1011 Erase / write endurance exceeding 10 cycles, as well as fast erase and program operations, have been demonstrated, enabling the use of ferroelectric storage transistors in embedded memory applications. 10 We have demonstrated ferroelectric memory transistors formed on crystalline silicon channels with endurance exceeding 1010 cycles (see, for example, Ava Jiang Tan et al., "Ferroelectric HfO2 Memory Transistors with High-K Interfacial Layer and Write Endurance Exceeding 1010 Cycles," arXiv:2103.08806 [physics.app-ph], submitted March 16, 2021, available at https: / / arxiv.org / abs / 2103.08806).

[0021] In some embodiments, the ferroelectric storage transistors of the present disclosure provide high endurance, long data retention, and relatively low voltage operation (e.g., ±5.0 volts or less) for both erase and programming operations. By combining ferroelectric or polarization properties with three-dimensional configurations (e.g., thin film NOR memory strings as described herein), the ferroelectric storage transistor memory structures of the present disclosure achieve the additional benefits of high density, low cost memory arrays with the advantages of high speed random access memory circuits with low read latency.

[0022] Second, the three-dimensional memory structure of the present invention includes a ferroelectric storage transistor that uses a semiconductor oxide layer (or a metal oxide semiconductor layer) as a junctionless channel region, which eliminates the need for a highly doped polysilicon layer for the source and drain regions. As a result, the thickness of each active layer in the memory stack is reduced compared to a storage transistor formed using a conventional polysilicon channel region with a highly doped semiconductor layer as the source and drain regions. In particular, the semiconductor oxide channel has the advantage of high electron mobility, which results in higher switching performance and no concern of electron or hole tunneling compared to a conventional polysilicon channel. In addition, the ferroelectric storage transistor with the junctionless semiconductor oxide channel supports shorter channel lengths than are possible with polysilicon doped channels, while providing low channel leakage and reduced GIDL (Gate Induced Drain Leakage) effects.

[0023] More specifically, the length of the junctionless channel of the ferroelectric transistor can be made significantly shorter than the length of the polysilicon channel, which allows the ferroelectric memory structure of the present disclosure to be more scalable in stack height, facilitating deposition and etching of multiple layers of 3D ferroelectric memory strings that make up taller memory stacks. In particular, thinner active layers allow for smaller aspect ratios (ARs) for etching deep trenches between memory stacks. The smaller aspect ratio also allows for more memory planes to be built for a given total height of the 3D memory structure.

[0024] In some embodiments, the memory structures of one or more memory layers (or memory planes) of ferroelectric storage transistors can be configured to function as high density embedded memories within logic integrated circuits. This high density is made possible by the fact that the ferroelectric storage transistors are formed along the vertical sidewalls of the memory stack, thereby requiring little physical space in the horizontal XY dimensions. For example, the three-dimensional ferroelectric memory structures of the present invention can be configured in a "super tall" form, which allows for the formation of large capacity memory circuits embedded within logic integrated circuits. The incorporation of the memory structures of the present invention is possible at the relatively low temperatures required to build ferroelectric memory stacks (typically less than 500°C), thereby minimizing damage to transistors that make up the logic integrated circuits sharing the same substrate.

[0025] Third, the memory structure of the present invention is formed in a fabrication process in which the channel layer is deposited as a continuous layer on the sidewalls of the memory stack, followed by a selective backside etch process with access through a series of auxiliary trenches to separate and isolate each memory string in the stack. Note that, as used herein, "auxiliary trenches" refer to trenches formed between memory stacks in which no storage transistors are formed. In embodiments of the present invention, the auxiliary trenches are advantageously used to facilitate a selective backside etch that separates and isolates the channel layer for each memory string. In some embodiments, the auxiliary trenches may also be used to facilitate a selective backside etch that separates the ferroelectric layer in addition to the channel layer formed on the sidewalls of the memory stack. Additionally, in some embodiments, the auxiliary trenches may also be used to facilitate metal replacement of the common source and drain lines.

[0026] More specifically, in an embodiment of the present invention, the channel layer is isolated for each active layer (i.e., each memory plane) by etching through an access opening provided by a sacrificial layer formed between the active layers and replaced by an interlayer dielectric layer in a subsequent process step. The sacrificial layer is removed in an intermediate processing step, thereby providing an access opening on the backside of the channel layer. In one embodiment, the memory stack is formed by a group of thin films (active layers) separated by an interlayer sacrificial layer, which is later replaced by an interlayer dielectric layer. In one embodiment, the interlayer sacrificial layer is an undoped amorphous silicon layer, a silicon germanium layer, or a carbon layer, and the interlayer dielectric layer replaced instead of the sacrificial layer can be a low-K dielectric layer, or an air gap cavity. In an intermediate processing step, the interlayer sacrificial layer is removed, thereby providing an access opening to the channel layer formed in the sidewall of the stack in the region between adjacent active layers. The exposed portions of the channel layer in each stack (referred to herein as the back side of the channel layer) are etched through access openings to isolate and insulate the channel layer from each active layer, thereby allowing channel regions for NOR memory strings to be formed in multiple planes.

[0027] Fourth, in embodiments of the present invention, memory structures can be constructed using air gaps as vertical insulation between active layers forming NOR memory strings. Air gaps have a dielectric constant of about 1.0, which is much lower than most dielectric materials, and therefore can effectively reduce vertical parasitic capacitance between adjacent pairs of NOR memory strings in a memory stack. The use of air gaps as insulation between active layers improves the insulation between adjacent NOR memory strings, thereby improving the performance of memory devices formed therefrom. In some embodiments, the interlayer insulation layer between the active layers includes an air gap liner layer for passivating the surfaces of the exposed cavities, with the remaining unfilled portions of the cavities forming the air gap insulation.

[0028] Additionally, in some embodiments, the memory structure may implement one or two levels of air gap isolation. As discussed above, interlayer air gap isolation may be incorporated to provide isolation between active layers in the active stack. In some embodiments, the memory structure includes a second level of air gap isolation that caps the cavity between the active layers, with the remaining unfilled portion of the cavity forming the air gap isolation in the auxiliary trench. The air gap isolation in the auxiliary trench provides isolation and reduces parasitic capacitive coupling between the active stacks in the memory structure.

[0029] Fifth, in some embodiments, each storage transistor in a stack of NOR memory strings is isolated from other storage transistors in both the horizontal and vertical directions. In particular, each NOR memory string in a memory stack is isolated from other NOR memory strings in the same stack by an interlayer dielectric layer, which may be air gap insulation. The storage transistors in each NOR memory string are further separated and isolated from each other along the NOR memory string (horizontally). For example, portions of the channel layer between adjacent local word lines formed in the LWL trenches are removed to isolate the storage transistors from each other horizontally along the NOR memory string. In this way, each storage transistor is fully isolated from other storage transistors in the same NOR memory string or from storage transistors in NOR memory strings formed in other planes in the same memory stack. The storage transistors in each NOR memory string are controlled by individual gate conductors (also referred to as local word lines or LWLs) to allow them to be individually addressed and accessed. In some embodiments, the storage transistors may be isolated only vertically by the interlayer dielectric layer, with the channel layer between adjacent local word lines remaining in the LWL trenches. Isolating the storage transistors in the NOR memory strings in the horizontal direction is optional and may be omitted in some embodiments.

[0030] These and other advantages of the memory structure of the present invention are further described below. In this description, for ease of reference to the drawings, a Cartesian coordinate reference system is used in which the Z direction is orthogonal to the plane of the semiconductor surface, and the X and Y directions are orthogonal to the Z direction, as shown in the figures.

[0031] Additionally, the drawings provided herein are idealized depictions for purposes of illustrating embodiments of the present disclosure and are not intended to be actual depictions of specific components, structures, or devices. The drawings are not drawn to scale, and thicknesses and dimensions of some layers may be exaggerated for clarity. Variations from the shapes shown are expected. For example, regions depicted as box-shaped may generally have rough and / or non-linear features. Sharp angles depicted may be rounded. Like reference characters refer to like components throughout.

[0032] FIG. 1 is a perspective view of a memory structure including a three-dimensional array of NOR memory strings in some embodiments. The memory structure can be used to realize a portion of a semiconductor memory device in some implementations. With reference to FIG. 1, the memory structure 10 includes a number of active layers 16 formed on a plane of a semiconductor substrate 12. An insulating layer 14 may be provided between the semiconductor substrate 12 and the active layers 16 formed thereon. The active layers 16 are stacked in the Z direction (i.e., along a direction perpendicular to the plane of the substrate 12) and separated from each other by an interlayer insulating layer 15. The active layers 16 are divided in the X direction into narrow strips ("active strips") that are stacked on top of each other to form a stack 17 of active strips ("active stacks") extending in the Y direction. The active stacks 17 are also referred to herein as memory stacks.

[0033] In this embodiment, each active stack 17 of the memory structure 10 is separated from the others by narrow trenches, including operating trenches 18 (also referred to as "LWL trenches") and auxiliary trenches 19. In particular, each active stack 17 is separated from the others by alternating operating trenches 18 and auxiliary trenches 19. As used herein, operating trenches 18 are narrow trenches disposed between adjacent active stacks 17. Storage transistors are formed by providing local word line structures in the operating trenches 18. Auxiliary trenches 19 are narrow trenches disposed between active stacks 17 in which no storage transistors are formed.

[0034] Each active layer 16 includes first and second low resistance conductive layers (e.g., tungsten (W) lined with titanium nitride (TiN)) separated from each other by a channel spacer dielectric layer (e.g., silicon oxide). In an intermediate processing step, the active layer may include a sacrificial layer (e.g., silicon nitride) that is later replaced by a conductive layer. Subsequent processing steps form a channel layer, a gate dielectric layer, and a gate conductor layer in the working trenches 18 between adjacent active stacks. The gate conductor layer and the gate dielectric layer are formed as columnar structures extending in the Z direction. The gate conductor layer is also referred to herein as a "local word line," and the combination of the gate conductor layer and the gate dielectric layer is collectively referred to as a "local word line (LWL) structure" 13. The first and second conductive layers of each active strip form the drain region ("common bit line") and source region ("common source line") of a storage transistor, respectively. In this embodiment, the storage transistor is formed along the vertical sidewall of the active stack 17 facing the working trench 18. In particular, storage transistors 20 are formed at the intersections of the active strips with the channel layers and LWL structures 13. The local word line structures 13 within each LWL trench 18 are separated from each other by dielectric filled shafts.

[0035] FIG. 1A illustrates a detailed structure of a storage transistor 20 formed in the memory structure 10 shown in FIG. 1 in some embodiments. In particular, FIG. 1A illustrates a pair of storage transistors 20-1 and 20-2 on two adjacent sides of an active stack 17, also referred to as a memory stack. Referring to FIG. 1A, the storage transistor 20 includes a first conductive layer 22 forming a drain region (common drain line or common bit line) and a second conductive layer 24 forming a source region (common source line), which are spaced apart by a channel spacer dielectric layer 23. The storage transistor 20 further includes a channel layer 26 formed vertically along the sidewall of the memory stack and in contact with both the first conductive layer 22 and the second conductive layer 24. A gate dielectric layer 27 and a gate conductor layer 28 are formed on the sidewall of the memory stack. The storage transistor 20 is insulated from adjacent storage transistors in the memory stack by an interlayer insulating layer 15. Storage transistors configured in this manner, sharing a common source line and a common bit line, form a NOR memory string (also referred to herein as a "horizontal NOR memory string" or "HNOR memory string") along each active strip (in the Y direction).

[0036] In an embodiment of the present invention, the storage transistors in the memory structure 10 are junctionless ferroelectric storage transistors. Thus, each storage transistor 20 includes only conductive layers as source and drain regions, and does not include a semiconductor layer. The first and second conductive layers are formed using a metal conductive material with low resistivity. In some embodiments, the first and second conductive layers are metal layers, such as a tungsten (W) layer lined with titanium nitride (TiN), a tungsten (W) layer lined with tungsten nitride (WN), a molybdenum (Mo) layer lined with molybdenum nitride (MoN), a linerless tungsten layer, a linerless molybdenum layer, a linerless cobalt layer, or other metal layers. The channel spacer dielectric layer 23 between the first and second conductive layers can be a low-k dielectric layer, such as silicon oxide (SiO2). The channel layer 26 is a semiconductor oxide layer. In some embodiments, the channel layer 26 is formed using an amorphous oxide semiconductor material, such as indium gallium zinc oxide (InGaZnO or IGZO), indium zinc oxide (IZO), indium tungsten oxide (IWO), or indium tin oxide (ITO), or other such semiconductor oxide materials. Semiconductor oxide channel regions have the advantage of high electron mobility, which allows for high switching performance and is free of electron and hole tunneling concerns. For example, an IGZO film can have a lattice field of 10.0-100.0 cm, depending on the relative composition of indium, gallium, zinc, and oxygen. 2 / V.

[0037] To form a ferroelectric storage transistor, the storage transistor 20 includes a ferroelectric gate dielectric layer or ferroelectric polarization layer 27 in contact with the channel layer 26. The ferroelectric polarization layer 27 functions as the storage layer of the storage transistor. In some embodiments, an interface layer 25 may be provided between the semiconductor oxide channel layer 26 and the ferroelectric polarization layer 27. The interface layer 25 is a thin layer and may have a thickness of 0.5 nm to 2 nm. In some embodiments, the interface layer is formed using a material having a high dielectric constant (K) (also referred to as a "high K" material). In some embodiments, the interface layer 25 may be a silicon nitride (Si3N4) layer, a silicon oxynitride layer, or an aluminum oxide (Al2O3) layer. In one example, if the interface layer is present and the ferroelectric polarization layer 27 has a thickness of 4 to 5 nm, the interface layer may have a thickness of 1.5 nm. The inclusion of the interface layer 25 in FIG. 1A is for illustration only and is not intended to be limiting. The interface layer 25 is optional and may be omitted in other embodiments of the present invention. In other embodiments, if an interfacial layer 25 is provided, it may be formed as multiple layers of different dielectric materials. As used herein, high-k or high-K materials refer to materials that have a dielectric constant higher than that of silicon dioxide.

[0038] In some embodiments, the ferroelectric polarization layer 27 is formed from a doped hafnium oxide material, such as zirconium doped hafnium oxide (HfZrO or "HZO"). In other embodiments, the hafnium oxide may be doped with silicon (Si), iridium (Ir), or lanthanum (La). In some embodiments, the ferroelectric polarization layer 27 is a material selected from zirconium doped hafnium oxide (HZO), silicon doped hafnium oxide (HSO), aluminum zirconium doped hafnium oxide (HfZrAlO), aluminum doped hafnium oxide (HfO2:Al), lanthanum doped hafnium oxide (HfO2:La), hafnium zirconium oxynitride (HfZrON), hafnium zirconium aluminum oxide (HfZrAlO), and any hafnium oxide containing zirconium impurities.

[0039] The ferroelectric polarization layer 27 is in contact with the channel layer 26 on one side and with the gate conductor layer 28 on the other side. In some embodiments, the gate conductor layer 28 includes a conductive liner 28a as an adhesion layer and a low resistance conductor 28b. In some implementations, the conductive liner 28a is a titanium nitride (TiN) layer, a tungsten nitride (WN) layer, or a molybdenum nitride (MoN) layer, and the low resistance conductor 28b is formed using tungsten, molybdenum, or other metals. In some implementations, the conductive liner 28a is not required and the gate conductor layer 28 includes only a low resistance conductor 28b, such as a linerless tungsten or molybdenum layer. In other implementations, the low resistance conductor 28b may be heavily doped n-type or p-type polysilicon and may be used with or without a conductive liner. The gate conductor layer 28, including the conductive liner 28a (if present) and the conductor 28b, forms the control gate electrode of the storage transistor and serves as a local word line in the memory structure.

[0040] The semiconductor oxide channel layer 26 thus configured forms an N-type unipolar channel region where the first conductive layer 22 and the second conductive layer 24, which form the drain and source terminals, are in direct contact with the channel region. The ferroelectric storage transistor thus formed is a depletion mode device that is normally on (i.e., conducting) and can be turned off (i.e., non-conducting) by depleting the channel region of N-type carriers. The threshold voltage of the ferroelectric storage transistor is a function of the thickness (X-direction) of the semiconductor oxide channel layer 26. That is, the threshold voltage of the ferroelectric storage transistor is the amount of voltage required to deplete the carriers within the thickness of the semiconductor oxide channel region to shut off the ferroelectric storage transistor.

[0041] Each storage transistor 20 is insulated from adjacent storage transistors along the active stack (in the Z direction) by an interlayer insulating layer 15. In this embodiment, the interlayer insulating layer 15 is an air gap insulation formed by an air gap cavity 15a and an optional air gap liner 15b. The air gap liner 15b is a dielectric layer used to cover or passivate the exposed surfaces of the air gap cavity 15a. In some embodiments, the air gap liner 15b is a silicon nitride layer or an aluminum oxide (Al2O3) layer. The thickness of the air gap liner 15b can be 1 nm to 3 nm. In FIG. 1A, elements may be exaggerated for illustrative purposes only. It should be understood that the depictions in this and other figures are not necessarily to scale. The air gap cavity 15a forming the interlayer insulating layer 15 provides effective isolation between adjacent storage transistors 20 along the memory stack. In an embodiment of the present invention, the interlayer insulating layer 15 is also used to provide physical separation between the channel layer 26 of a storage transistor in the same memory stack and the channel layer of the storage transistor above or below it, thereby providing isolation for each storage transistor in the memory stack.

[0042] Returning to FIG. 1, in an exemplary embodiment as shown, the memory structure 10 includes a dielectric layer 44 that serves as a capping layer capping the air gap cavity 15a. In some embodiments, the dielectric layer 44 is a non-conformally deposited dielectric layer, such as a silicon oxide (SiO2) layer or a silicon nitride (Si3N4), formed to cap the end of the interlayer cavity facing the auxiliary trench 19. The memory structure 10 further includes a dielectric layer 46 as a capping layer capping the top of the auxiliary trench 19. In some embodiments, the dielectric layer 46 is formed from the same dielectric material as the dielectric layer 44. The memory structure 10 thus fabricated includes two levels of air gap insulation. A first level of air gap insulation is provided as the interlayer air gap insulation 15a between the active layers 16 in the memory stack. The first level of air gap insulation provides insulation between the storage transistors formed in the memory stack 17. A second level of air gap insulation is provided in the auxiliary trench 19 to provide insulation between adjacent memory stacks 17 and reduce parasitic capacitance.

[0043] In an embodiment of the present invention, a three-dimensional array of NOR memory strings of ferroelectric storage transistors can be applied to realize a non-volatile or quasi-volatile memory device. For example, a quasi-volatile memory has an average retention time of 100 milliseconds or more, e.g., about 10 minutes, or several hours, while a non-volatile memory device may have a minimum data retention time of more than 5 years. As a quasi-volatile memory, the ferroelectric storage transistor 20 needs to be refreshed from time to time to restore the intended programmed and erased polarization states. For example, the ferroelectric storage transistor 20 in the memory structure 10 can be refreshed every few minutes or hours. In particular, the ferroelectric storage transistor of the present disclosure can fabricate a quasi-volatile memory device with a refresh interval on the order of several hours, which is significantly longer than the refresh interval of a DRAM, which requires very frequent refresh, such as tens of milliseconds.

[0044] A notable feature of the ferroelectric storage transistor 20 is that the storage transistor has a very short channel length, which allows for increased voltage separation between different threshold voltages. As a result, the memory structure 10 can be fabricated without the need for expensive lithography techniques to achieve the short channel length. In particular, the channel length of the ferroelectric storage transistor 20 is determined by the thickness L1 of the channel spacer dielectric layer 23 (FIG. 1A). The thickness L1 can be precisely controlled during the deposition of the sub-layers 22, 23, 24 that form the initial memory stack. The ability to control the thickness L1 by the deposition process, together with the very low channel leakage of the semiconductor oxide channel layer, allows for the provision of a ferroelectric storage transistor 20 with a very short channel length, such as a 5 nm channel length, without the use of expensive lithography techniques, such as extreme ultraviolet scanners (EUV), that are required to pattern the short channel in a planar transistor. In some embodiments, the thickness L1, i.e., the channel length of the storage transistor, can be in the range of 5 nm to 20 nm, or in the range of 5 nm to 7 nm.

[0045] Referring again to FIG. 1, to complete the memory circuit, various types of circuits are formed in or on the semiconductor substrate 12 to support the operation of the HNOR memory string. Such circuits are referred to as “circuitry under the array” (“CuA”) and include digital and analog circuits such as decoders, drivers, sense amplifiers, sequencers, state machines, exclusive-or circuits, memory caches, multiplexers, voltage level shifters, voltage sources, latches and registers, and connectors to perform repetitive local operations such as processing random addresses, activate, erase, program, read, and refresh commands with the memory array formed on the semiconductor substrate 12. In some embodiments, the transistors in the CuA are constructed using processes optimized for control circuits, such as advanced fabrication processes optimized for forming low-voltage, high-speed logic circuits. In some embodiments, the CuA is constructed using fin field effect transistors (FinFETs) or gate-all-around field effect transistors (GAAFETs) to achieve compact circuit layers and improved transistor performance.

[0046] In some embodiments, the CuA provides a data path to and from the memory array, and further to a memory controller, which may be constructed on the same semiconductor substrate as the CuA. Alternatively, the memory controller may reside on a separate semiconductor substrate, in which case the CuA and its associated data path are electrically connected to the memory controller using various bonding techniques. In some implementations, the memory controller includes control circuitry for accessing and operating storage transistors in the memory array connected thereto, performing other memory control functions such as data routing and error correction, and providing interface functionality with systems that interact with the memory array.

[0047] The memory structure 10 of FIG. 1 illustrates the structure of a three-dimensional array of NOR memory strings in some embodiments. In some embodiments, the memory structure 10 is fabricated in a process that realizes advantageous features of the memory structure. First, the memory structure 10 is formed such that the storage transistors in the three-dimensional array of NOR memory strings are individually isolated from the other storage transistors. In particular, each storage transistor is vertically isolated by an interlayer dielectric layer, as shown in FIG. 1, and optionally also horizontally by isolating the channel layer to each local word line structure 13. By isolating each storage transistor individually, the performance characteristics of the storage transistors can be improved. Second, the channel layer can be conformally deposited, and then channel isolation between active layers in the memory stack is achieved by etching the channel backside through the access openings formed by the sacrificial layer. As a result, a simplified and more reliable process for forming the channel layer is provided. Third, after removing the interlayer sacrificial layer for channel isolation, the cavity remaining between the active layers allows for air gap isolation to be formed between the active layers, which provides better isolation than most dielectric materials.

[0048] In embodiments of the present disclosure, the memory structure includes a memory array portion constructed as described above to form a three-dimensional array of NOR memory strings. To complete the memory device, the memory structure includes stepped portions at the ends (in the Y direction) of the memory strings, as shown in FIG. 2 below. The thin film storage transistors of the NOR memory strings are formed in the memory array portion, and the stepped portions on either side of the array portion include stepped structures that provide connections to common bit lines and optionally common source lines of the NOR memory strings through conductive vias. In some embodiments, the common source line is precharged to act as a virtual voltage reference source during programming, reading, and erasing operations, thereby eliminating the need for continuous electrical connections to support circuitry during such operations. The common source line is described herein as being electrically floating to mean that there is no continuous electrical connection to the common source line. Various processing steps can be used to form the stepped structures in the memory structure in embodiments of the present disclosure. The processing steps to form the stepped structures can be performed before, after, or between the processing steps to form the memory array portion.

[0049] The memory structure 10 of FIG. 1 illustrates the structure of a memory array including a three-dimensional array of NOR memory strings. The memory structure 10 can be used as a building block for fabricating large capacity and high density memory devices. In an embodiment of the present disclosure, the memory structure 10 represents modular memory units called "tiles," and the memory device is formed using an array of modular memory units. In an exemplary embodiment, the memory device is configured as a two-dimensional array of tiles arranged along the X and Y directions, with each tile including a three-dimensional array of ferroelectric storage transistors with support circuitry for each tile formed thereunder. More specifically, the memory device includes a plurality of memory arrays of thin-film ferroelectric storage transistors configured as a two-dimensional array of "tiles" (i.e., the tiles are arranged in rows and columns) formed on a planar semiconductor substrate. Each tile can be configured to be addressed individually and independently, or a larger memory segment (e.g., a column of tiles or a two-dimensional block of tiles) can be formed and addressed on a per-memory-segment basis. In some implementations, each row of tiles ("tile row") is configured to form an operational unit called a "bank." Groups of banks then form a "bank group." This configuration allows banks within a bank group to share a data I / O bus in a multiplexed manner. Configured in this way, tiles are modular units that allow flexibility in configuring the memory module to suit the requirements of an application.

[0050] 2 is a cross-sectional view in the YZ plane of a tile in the memory device of FIG. 1 in an embodiment of the present invention. Referring to FIG. 2, a tile 101 is formed on a semiconductor substrate 100. The memory structures of the tile 201 are formed in an insulating film 111, on which a protective film 112 (passivation film) is formed. In some embodiments, the insulating film 111 is made of silicon oxide (SiO x) and protective film 112 is formed from polyimide. The memory structure includes a three-dimensional array of junctionless ferroelectric storage transistors ("memory array") configured as described above with reference to memory structure 10 of FIG.

[0051] A P-type or N-type diffusion region 121 is formed on the top surface of the semiconductor substrate 100. Other structures (not shown in FIG. 2), such as isolation structures or shallow trench isolation (STI) structures, may also be formed in the semiconductor substrate 100. A gate electrode 122 is formed on the semiconductor substrate 100. The gate electrode 122 is insulated from the semiconductor substrate by a gate dielectric layer. The gate dielectric layer may be, for example, a thin silicon oxide. The gate electrode 122 together with the P-type and N-type diffusion regions 121 form a transistor in the semiconductor substrate 100. The transistor may be used to form a circuit element. For example, the transistor may be used to form support circuitry for operating storage transistors in a 3D NOR memory array formed in the tile 101. The circuit elements are interconnected by contacts 123 connecting interconnects 124 and vias 125 formed in the insulating film 111 of the lower interconnect portion 132 to form the support circuitry. In some embodiments, the support circuitry of the semiconductor memory device is formed in the circuit element portion 131 and the lower interconnect portion 132.

[0052] In the tile 101, a three-dimensional NOR memory array 110 is formed in a memory array portion 133. An upper interconnect portion 134 is formed above the memory array portion 133. An insulating film 111 of the upper interconnect portion 134 is provided with interconnects 126 and vias 127 for forming further electrical connections. In some embodiments, a conductive pad 128 is provided on the upper interconnect portion 134 for connecting to a circuit element outside the semiconductor memory device. For example, a protective film 112 is formed above the upper interconnect portion 134, seals the upper interconnect portion 134, and has an opening that exposes at least a part of the conductive pad 128.

[0053] In the memory array portion 133, the thin-film storage transistors are arranged as a three-dimensional array of NOR memory strings in the memory array portion 102. The memory array portion 102 is provided between the stepped portion 103a and the stepped portion 103b. The connections of the NOR memory strings to a common bit line and optionally a common source line through conductive vias are provided in the stepped portion 103a and the stepped portion 103b. In some embodiments, the common source line is precharged and then maintained at a relatively constant voltage to act as a virtual voltage reference during programming, erasing, and reading operations, thereby eliminating the need for continuous electrical connections to support circuitry during such operations. In FIG. 2, the array portion 102, the stepped portion 103a, and the stepped portion 103b are not drawn to scale. For example, the array portion 102 may be much larger in area than either the stepped portion 103a or the stepped portion 103b.

[0054] In the memory array portion 102, thin film storage transistors are formed at the intersections of common drain and source lines (collectively designated 104) and local word lines 105. A gate dielectric layer 106 is formed between the conductive local word lines and a channel layer (not shown in FIG. 2). The common drain and source lines are arranged in multiple planes extending in the Y direction, and the local word lines 105 are arranged in the Y direction as columnar structures extending in the Z direction. This results in a three-dimensional array of storage transistors arranged in multiple rows in the X direction on multiple planes in the Z direction along each memory string in the Y direction. In FIG. 2, global word line conductors 108 provide electrical connection between circuitry 122 underneath the memory array 110 and the local word lines 105 associated with the three-dimensional memory stack.

[0055] In the above embodiment, the support circuits are described as being formed under the memory array portion 133. Such a configuration is merely exemplary and is not intended to be limiting. For example, in other embodiments, both the memory array portion and the support circuits may be formed directly on the semiconductor substrate 100. In this case, for example, the support circuits may be located around the memory array portion. In other embodiments, the support circuits may be formed on a separate semiconductor substrate. In this case, for example, the semiconductor substrate on which the memory array portion is formed and the semiconductor substrate on which the support circuits are formed are bonded to each other after forming the respective memory elements and circuit elements.

[0056] FIG. 2 illustrates one exemplary embodiment of a tile or modular unit of a memory array. The depiction of a tile 101 in FIG. 2 is for illustration only and is not intended to be limiting. FIG. 2 is provided to illustrate incorporating the memory structure 10 of FIG. 1 to form a modular memory unit ("tile") that can be used to fabricate a memory device including multiple arrays of three-dimensional junctionless ferroelectric storage transistors to provide desired memory capacity at high density levels.

[0057] FIG. 3 illustrates the application of the memory device of the present invention as an embedded memory device in some embodiments. Referring to FIG. 3, a memory device 150 is constructed as described above with reference to FIGS. 1 and 2. The memory device 150 includes a two-dimensional array of tiles 101, each of which includes a memory array that is a three-dimensional array of junctionless ferroelectric storage transistors. The memory array in the tile 101 is formed on a semiconductor substrate 155. An insulating layer 153 may be provided between the semiconductor substrate 155 and the memory array (tile 101) formed thereon. The semiconductor substrate 155 is provided with support circuitry (CuA) for operating the storage transistors in the memory array. In some embodiments, the support circuitry for the ferroelectric storage transistors of each tile is provided for modularization in a portion of the semiconductor substrate below each tile.

[0058] In some embodiments, the memory devices interact with a memory controller to perform memory operations. As discussed above, the memory controller includes control circuitry for accessing and operating storage transistors in the memory devices, performing memory control functions, and managing interface functions for host access. In some embodiments, a memory module is formed from memory devices formed on one semiconductor die and a memory controller formed on another semiconductor die. The memory dies and memory controller die can be integrated using a variety of integration technologies, such as TSVs, hybrid bonds, exposed contacts, interposers, printed circuit boards, and other suitable interconnect technologies, especially those for high density interconnects.

[0059] In this embodiment, the memory controller is integrated into the semiconductor substrate of the logic integrated circuit 160. In particular, the logic integrated circuit 160 may have digital or analog logic circuitry 162, such as a core processor, formed thereon. The memory controller circuitry 166 is integrated into the logic integrated circuit 160 and formed in a portion of the semiconductor substrate of the logic integrated circuit 160. The memory device 150 is coupled and electrically connected to the memory controller circuitry 166 using various bonding techniques. In this illustration, the memory device 150 includes an array of connectors 156 that are coupled to corresponding mating connectors 158 formed on the logic integrated circuit 160. In some embodiments, the connectors 156 and 158 are hybrid integrated bonds, such as copper-to-copper bonds, and may have a pitch of less than 2 μm or less than 1 μm.

[0060] The memory device 150 configured in this manner operates as an embedded memory circuit in the logic integrated circuit 160 via the embedded memory controller 166. The memory controller circuit 166 can be directly connected to the digital or analog circuit 162 on the logic integrated circuit 160 via interconnect lines 168 formed in the logic integrated circuit without an interface circuit. Thus, the ferroelectric storage transistors in the memory device 150 can utilize the circuitry of the logic integrated circuit 160 with minimal delay. That is, the storage transistors can be accessed with low latency via the direct connectors 168 between the memory controller circuit 166 and the logic circuit 162. Such a configuration is also referred to as "in-memory computing". In-memory computing is particularly desirable in artificial intelligence and machine learning applications that are data intensive and require large amounts of memory in close proximity to CPU and GPU core processors, which may be formed as logic circuits 162 in the logic integrated circuit 160. In an embodiment of the present invention, the memory device 150 including an array of 3-dimensional NOR memory strings of ferroelectric storage transistors can be used to form an embedded memory circuit, thereby achieving low latency and large capacity in memory computing systems for data intensive applications.

[0061] In some embodiments, memory device 150 may be constructed directly on logic integrated circuit 160 on the same semiconductor substrate. For example, memory device 150 may be constructed on an insulating layer formed on the logic integrated circuit to protect the already fabricated circuitry. For example, the insulating layer may be a protective layer such as a silicon oxide or polyimide layer. Direct electrical connection between memory device 150 and memory control circuitry or other application specific logic circuitry is provided through vias formed in the insulating layer. In this case, bonding of memory device 150 through connector 156 is not required.

[0062] 4A-4P, including 4E-1, 4M-1, and 4O-1, are diagrams showing a process for fabricating a memory structure including an HNOR memory string in an embodiment of the present invention. Each of 4A-4O-1 includes two views, (i) and (ii): (i) is a horizontal cross-sectional view (i.e., XY plan view) taken along line AA' in (ii), and (ii) is a vertical cross-sectional view (i.e., XZ plan view) taken along line AA' in (i).

[0063] 4A, first, a semiconductor substrate 52 is provided, and any circuitry formed in the semiconductor substrate 52, such as CuA and interconnect conductors, is provided in or on the semiconductor substrate 52. An insulating layer 54 is formed on the semiconductor substrate 52 to cover and protect the semiconductor substrate 52 and the circuitry formed in the semiconductor substrate 52. In some embodiments, the insulating layer 54 is a dielectric layer that also serves as an etch stop layer for subsequent processing steps. In some embodiments, the insulating layer 54 is a silicon oxycarbide (SiOC) layer or an aluminum oxide (Al2O3) layer. The insulating layer 54 can be formed using any material that has suitable selectivity for the subsequent etching process.

[0064] The memory structure 50 is then formed by successively depositing (i) a multilayer film 51 and (ii) an interlayer sacrificial layer 70 on the plane of the semiconductor substrate 52, and in particular on the insulating layer 54 formed on the semiconductor substrate 52. The multilayer film 51 includes three sublayers in the Z-direction: (a) a first sacrificial layer 72, (b) a channel spacer dielectric layer 63, and (c) a second sacrificial layer 74, in that order. FIG. 4A shows the memory structure 50 after deposition of an initial layer of thin films. The multilayer film 51 is also referred to as the "active layer" in this detailed description. View (i) of FIG. 4A shows a horizontal cross-section of the first sacrificial layer 72 in view (ii) along the line AA'. View (ii) of FIG. 4A shows a vertical cross-section of the memory structure 50 along the line AA' shown in view (i). The first sacrificial layer 72 and the second sacrificial layer 74 are replaced by respective conductive layers in subsequent processing. As described in more detail below, the interlayer sacrificial layer 70 (also referred to herein as a third sacrificial layer) is replaced with an insulating material in subsequent processing to form an interlayer insulating layer that provides isolation between active layers. In one embodiment, each sublayer in the multilayer film 51 and the interlayer sacrificial layer 70 generally have a thickness of 30 nm or less. In another embodiment, each sublayer in the multilayer film 51 and the interlayer sacrificial layer 70 do not have the same thickness as each other. The dimensions herein are provided for illustrative purposes only and are not intended to be limiting. In practical implementation, any suitable thickness or dimensions can be used.

[0065] In some embodiments, the first sacrificial layer 72 and the second sacrificial layer 74 are each silicon nitride layers. The channel spacer dielectric layer 63 is an insulating dielectric material such as silicon oxide (SiO2). The third sacrificial layer 70 is a sacrificial material selected from carbon, amorphous silicon (aSi), and silicon germanium (SiGe).

[0066] In some embodiments, dummy sacrificial layers may be provided as the bottom and top layers of the memory stack 50 that are not necessarily part of the active layers. In the embodiment shown in FIG. 4A, a dummy sacrificial layer 71 is provided between the insulating layer 54 and the first interlayer sacrificial layer 70 as the bottom layer of the memory stack 50. The dummy sacrificial layer 71 is formed of the same material as the first sacrificial layer 72 and the second sacrificial layer 74, and is replaced by a metal layer in subsequent processing. As will be described in more detail below, the dummy sacrificial layer 71 is provided to form a dummy metal layer on the insulating layer 54 in subsequent processing steps to provide bracing and anchoring support for the memory stack formed thereon. As used herein, a dummy metal layer refers to a metal layer that is not used for memory circuit-related functions in the memory structure, but provides mechanical support for the memory stack formed thereon. In other embodiments, a dummy metal layer may be provided as the top layer of the memory stack. The use of a dummy metal layer is optional and may be omitted in other embodiments. The embodiment shown in FIG. 4A is illustrative only and is not intended to be limiting. If no dummy metal layer is used for memory stack fixation, the dummy sacrificial layer 71 is omitted from the memory structure 50 of FIG. 4A.

[0067] After the memory structure 50 is formed with the desired number of multi-layers 51 with the third sacrificial layer 70 in between, a capping layer 76 is formed on top of the memory structure 50. The capping layer 76 is used as a masking layer in subsequent processing, such as for use as a self-aligned mask to form local word line structures. In some embodiments, the capping layer 76 is a silicon oxide or silicon carbide (SiOC) layer. A mask 78 is applied over the memory structure (over the capping layer 76) to define trenches to be formed in the memory structure. In some embodiments, the mask 78 is an amorphous hard mask, such as an amorphous carbon hard mask. The mask 78 is patterned, for example, using a photolithographic patterning step, to define openings 79 for forming trenches in the memory structure. Note that the mask 78 is not drawn to scale in FIG. 4A. It should also be understood that a sufficient thickness of the amorphous hard mask is provided in the high aspect ratio etching process of the multi-layer memory structure 50.

[0068] The use of the patterned mask 78 in this embodiment is illustrative and not intended to be limiting. Other photolithography and patterning processes may be used to define openings for forming trenches in the memory structure. In another embodiment, a two-mask process may be used, with a first mask patterned to expose openings for forming a series of operation trenches (or LWL trenches) and openings for forming a series of auxiliary trenches, alternating in the X direction across the memory structure, and a second mask patterned to cover the openings for forming the series of auxiliary trenches and expose only the openings for the series of operation trenches. The fabrication process continues with the auxiliary trench openings covered by the second mask until the auxiliary trenches are formed.

[0069] Referring to FIG. 4B, the patterned mask 78 is used to form a first type of trench 80 in the memory structure 50, for example, using a selective anisotropic etching process with the mask 78 as a masking layer. After the trench etching process, the remaining portions of the mask 78 are removed. The resulting structure is shown in FIG. 4B. The first type of trenches 80 are arranged in the X-direction across the memory structure 100. The anisotropic etching process etches or removes all layers in the areas exposed by the mask 78, stopping on the insulating layer 54, which serves as an etch stop layer. The first type of trenches 80 are referred to herein as working trenches, or active trenches, or local word line trenches (LWTs), because the trenches will ultimately house active ferroelectric storage transistors. In one embodiment, each trench 80 has a width of about 60 nm at the top of the trench and a pitch of 230 nm, with adjacent trenches spaced 170 nm apart. In other words, the working trenches 80 are separated by 170 nm mesas. In subsequent processing, auxiliary trenches are formed in the mesas between adjacent pairs of trenches 80. The auxiliary trenches are formed at equal intervals between adjacent pairs of operating trenches 80. In one embodiment, the auxiliary trenches have a width of about 60 nm, resulting in a mesa width of about 55 nm between the operating trenches 80 and the auxiliary trenches, with the remaining mesas forming the active stacks in the memory structure, as described in more detail below.

[0070] Referring to FIG. 4C, a channel layer 66 is deposited on the sidewall of the working trench 80 thus formed. For example, the channel layer 66 is conformally deposited on the sidewall of the trench 80. In one embodiment, the channel layer 66 is deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or a combination thereof. In this embodiment, the channel layer 66 is a semiconductor oxide layer, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tungsten oxide (IWO), or indium tin oxide (ITO). In other examples, the channel layer 66 can be formed using other semiconductor oxide materials that are compatible with indium gallium zinc oxide (IGZO). Furthermore, in some embodiments, the channel layer 66 can have a thickness of 1.5 nm to 10 nm in the X direction. In one example, the channel layer 66 has a thickness of 6 nm in the X direction. A liner layer 81 is deposited to cover the channel layer 66, and the remaining space in the trench 80 is filled with a sacrificial material 82. In one embodiment, the liner layer 81 is a silicon nitride layer or an undoped amorphous silicon layer and may have a thickness of 3-5 nm. In one embodiment, the sacrificial material 82 is silicon germanium or carbon. To optimally protect the channel layer 66, the liner layer 81 is preferably deposited in the same deposition tool to avoid exposing the channel layer 66 to oxidation. After the deposition step, excess material is removed from the top of the memory structure 50, for example using chemical mechanical polishing (CMP). The resulting memory structure 50 is shown in FIG. 4C.

[0071] The memory structure 50 is then patterned to form local word line structures. Herein, the local word line structures refer to columnar structures formed by the ferroelectric layer and the gate conductor layer. Herein, the term "gate electrode structure" is used to refer to the local word line structures and the portions where the channel layer intersects the local word line structures. Referring to view (i) of FIG. 4D, a mask (e.g., an amorphous hard mask) having openings 86 is applied to the memory structure 50. The mask openings 86 expose regions for forming deep shafts used to isolate storage transistors formed along the memory strings. In this embodiment, the mask openings 86 have a first dimension d1 in the Y direction and an elongated second dimension d4 in the X direction. Adjacent openings 86 are spaced apart in the Y direction by a dimension d2. In one embodiment, the pitch d3 is the sum of the dimensions d1 and d2 and may be used to define the pitch of global word line conductors formed above the memory array (not shown) to connect to local word line gate conductors that are not yet formed. Typically, the pitch of the global word lines is about 100 nm or less, with d1 being about 50 nm and d2 being about 50 nm. The mask openings 86 thus formed are used to remove the sacrificial material 82, such as by a selective anisotropic etching process. Then, the exposed liner layer 81 is removed, such as by a selective wet etching process. Finally, the semiconductor oxide channel layer 66 is removed in the areas defined by the mask openings 86, such as by a selective anisotropic dry etching, atomic layer etching (ALE), or a controlled selective wet etching process. As a result, a shaft 88 is formed in the LWL trench between the areas where the LWL structure is to be formed, as shown in FIG. 4D. In particular, the mask openings 86 overlap the mesas of the memory structures 50, and the etching process is self-aligned to the edges of the capping layer 76 to form the shaft 88 only in the areas of the LWL trench.

[0072] More specifically, the etching of the channel layer 66 should be done to limit unintended lateral etching into the active stack of the multilayer 51 at the faces of the vertical sidewalls of the LWL trenches that become exposed to the etchant when the channel material 66 is etched away. Removal of the channel material in the shaft 88 provides physical separation in the Y direction of each storage transistor formed along each memory string.

[0073] Referring to FIG. 4E, the shaft 88 is filled with a dielectric material to form a dielectric filled shaft 98. For example, the dielectric material can be a low dielectric constant oxide such as silicon oxide (SiO2). The dielectric filled shaft 98 serves as a dielectric isolation between adjacent local word lines or gate conductors formed in the LWL trenches. Storage transistors are formed in the spaces between adjacent dielectric filled shafts 98 along each adjacent active stack in the LWL trench (Y direction).

[0074] In the above-described embodiment, the channel layer 66 is removed during the etching process applied to the mask opening 86 to form the shaft 88. In other embodiments, the etching process may remove only the sacrificial material 82 and the liner layer 81 without removing the channel layer 66. FIG. 4E-1 illustrates another embodiment in which the channel layer 66 is not removed from the shaft 88, and a subsequently formed dielectric-filled shaft 98 is bound in the X-direction by the channel layer 66. Thus, in the memory structure 50a, the channel layer 66 is a continuous layer along the NOR memory string in the Y-direction. The portion of the channel layer 66 that remains adjacent to the dielectric-filled shaft 98 has only a minor effect on the operation of the storage transistor of the NOR memory string.

[0075] To form the local word line structures, the sacrificial material 82 and the liner layer 81 are selectively etched away from the regions between adjacent dielectric filled shafts 98, exposing the channel layer 66 remaining on the sidewalls of the mesa. The fabrication process then proceeds to form the gate dielectric layer of the storage transistors. Referring to FIG. 4F, a gate dielectric layer 67 is deposited on the sidewalls of the cut cavities in the LWL trenches on the channel layer 66. For example, the gate dielectric layer 67 can be deposited using atomic layer deposition. A gate conductor layer 68 is then deposited in the remaining space of the cut cavities. After the deposition step, excess material is removed from the top of the memory structure 50, for example using chemical mechanical polishing (CMP). The resulting memory structure 50 is shown in FIG. 4F. Between each pair of dielectric filled trenches 98, the conductive layer 68 provides a vertical local word line (LWL) that serves as the gate electrode for each storage transistor vertically aligned in the same active stack.

[0076] In this embodiment, the memory structure 50 is used to form a ferroelectric storage transistor, and the gate dielectric layer 67 is a ferroelectric polarization layer. The ferroelectric polarization layer 67 may be deposited using atomic layer deposition (ALD) techniques and may have a thickness of 2 nm to 8 nm. A thermal annealing process is performed to form a ferroelectric phase in the deposited ferroelectric material. In some embodiments, the thermal annealing of the ferroelectric polarization layer 67 is performed with a conductive capping layer formed thereon. For example, in some embodiments, the gate conductor layer 68 may function as a conductive capping layer. In one embodiment, the ferroelectric polarization layer is formed from a doped hafnium oxide material, such as zirconium doped hafnium oxide (HfZrO or "HZO"). In other embodiments, the hafnium oxide may be doped with silicon (Si), iridium (Ir), or lanthanum (La). In some embodiments, the ferroelectric polarizing layer is a material selected from zirconium doped hafnium oxide (HZO), silicon doped hafnium oxide (HSO), aluminum zirconium doped hafnium oxide (HfZrAlO), aluminum doped hafnium oxide (HfO2:Al), lanthanum doped hafnium oxide (HfO2:La), hafnium zirconium oxynitride (HfZrON), hafnium zirconium aluminum oxide (HfZrAlO), and any hafnium oxide with zirconium impurities.

[0077] In some embodiments, an interface layer 65 is provided between the semiconductor oxide channel layer 66 and the ferroelectric polarization layer 67. In some embodiments, the interface layer 65 is formed using a material having a high dielectric constant (K) (a "high-K" material). In some embodiments, the interface layer 65 may be a silicon nitride (Si3N4) layer, a silicon oxynitride layer, or an aluminum oxide (Al2O3) layer and may have a thickness of 1-2 nm. The material forming the interface layer 65 may be indium tungsten oxide. In some embodiments, the interface layer 65 may be deposited using an atomic layer deposition (ALD) technique. Furthermore, in some embodiments, the interface layer 65 may be deposited in the same process chamber as the ferroelectric polarization layer 67 without breaking vacuum between the deposition of the two layers. The formation of the interface layer 65 is optional and may be omitted in other embodiments of the present invention. In one embodiment, the interface layer 65 is an aluminum oxide (Al2O3) layer and is annealed to obtain an amorphous film with the desired properties. In some embodiments, the aluminum oxide (Al2O3) layer is annealed in oxygen (O2), ozone (O3), nitrous oxide (NO), forming gas (H2N2), or argon (Ar). In some embodiments, an optional interfacial layer (not shown) similar to interfacial layer 65 is deposited on ferroelectric polarization layer 67.

[0078] In this embodiment, the gate conductor layer 68 is a metal layer and includes a conductive liner 68a and a conductive filler 68b. The conductive liner 68a can be a titanium nitride (TiN) liner or a tungsten nitride (WN) liner. The conductive filler 68b can be a metal such as tungsten (W) or molybdenum (Mo), or a highly doped n-type or p-type polysilicon. In an embodiment of the present invention, the gate conductor layer 68 deposited on the ferroelectric polarization layer 67 has the beneficial effect of acting as a capping layer for the ferroelectric polarization layer and exerting a tensile or compressive stress on the ferroelectric polarization layer to aid in the crystallization of the ferroelectric polarization layer and the formation of a desired ferroelectric crystallization phase (orthorhombic phase) in the ferroelectric film. In some embodiments, the gate conductor layer 68 is formed by a single conductive layer such as a titanium nitride (TiN) layer or a tungsten nitride (WN) layer. The single conductive layer is deposited in a cut cavity on the ferroelectric polarization layer 67. The single conductive layer exerts a tensile or compressive stress on the ferroelectric polarization layer, aiding in the crystallization of the ferroelectric polarization layer and the formation of the desired orthorhombic ferroelectric crystallization phase in the ferroelectric film.

[0079] In some embodiments, the gate conductor layer 68, including the conductive liner 68a and the conductive filler 68b, is deposited using atomic layer deposition at a relatively low temperature, such as a temperature in the range of 300-400°C. In another embodiment, after deposition of the ferroelectric polarization layer 67, at least the conductive liner 68a is deposited at a low temperature, such as a temperature below 350°C, to prevent crystallization of the ferroelectric polarization layer. Thereafter, a thermal annealing process is performed on the ferroelectric polarization layer, with at least the conductive liner 68a as a conductive capping layer, to achieve a desired ferroelectric crystallization phase (orthorhombic phase) in the ferroelectric film.

[0080] The fabrication process described above formed vertical local word lines in the LWL trenches. The mask used in the local word line fabrication process is removed. Referring to FIG. 4G, a mask 83 was applied to cover the LWL trenches and protect the local word line structures formed therein while exposing openings for forming auxiliary trenches. In some embodiments, the mask is an amorphous hard mask, such as an amorphous carbon hard mask. With mechanical support from the dielectric fill shaft 98 and the local word line structures therebetween, a second type of trench 84 is formed using substantially the same techniques as described in connection with FIG. 4A and FIG. 4B above. For example, the memory structure is selectively anisotropically etched with the patterned mask 83 as a masking layer. The anisotropic etching process etches or removes all layers in the areas exposed by the patterned mask 83 and stops at the etch stop layer 54. After the trench etching process, the remaining portions of the mask were removed. The resulting memory structure 50 is shown in FIG. 4H. The second type of trench 84 is called an auxiliary trench.

[0081] In some embodiments, the width of the auxiliary trenches 84 may be 60 nm. Each of the second type of trenches 84 is cut between a pair of adjacent LWL trenches (trench 80), and each of the second type of trenches 84 is cut between a pair of adjacent first type trenches 80 at substantially equal intervals. As a result of the trenches 80 and 84 being cut in the multi-layer structure, memory stacks are formed in the multi-layer structure, which are referred to herein as "active stacks". In some embodiments, the width of each active stack is about 40 nm, which is the width of a bit line. The narrow strips formed as a result of cutting the multi-layer film 51 are referred to herein as "active strips", and the multi-layer film 51 is also referred to as the "active layer".

[0082] In an embodiment of the present invention, the LWL trench formed by the fabrication process accommodates a local word line structure for forming a storage transistor with an active stack adjacent thereto. The fabrication process also forms auxiliary trenches to facilitate metal replacement and channel isolation processes. The auxiliary trenches do not include local word line structures and do not form a storage transistor with the adjacent active stack. The fabrication process uses the auxiliary trenches 84 thus formed to remove the first sacrificial layer 72 and the second sacrificial layer 74, and then performs a metal replacement to replace each sacrificial layer with a first conductive layer and a second conductive layer.

[0083] Referring to FIG. 4I, the first sacrificial layer 72 and the second sacrificial layer 74 are removed, for example, using a selective dry etching process or a selective wet etching process, thereby forming a cavity 172 between the channel spacer dielectric layer 63 and the interlayer sacrificial layer 70. At the same time, the dummy sacrificial layer 71 is also removed, forming the cavity 172 between the insulating layer 54 and the first interlayer sacrificial layer 70. When the first sacrificial layer 72 and the second sacrificial layer 74 (and the dummy sacrificial layer 71) are removed, the back surface of the channel layer 66 is exposed through the cavity 172. In one embodiment, the first sacrificial layer 72, the second sacrificial layer 74, and the dummy sacrificial layer 71 are silicon nitride layers, and are removed using a selective wet etching process using hot phosphoric acid. The remaining channel spacer dielectric layer 63 and the interlayer sacrificial layer 70 are typically 30 nm or less in thickness and 30 nm to 60 nm in length. These layers are held in place by bonding to the channel layer 66, the ferroelectric layer 67, and the conductive liner 68a. All these layers are supported by stiff metallic vertical local word lines 68b that are repeated at the local word line pitch (as shown in view (i) of FIG. 4I) along the entire length of each memory string. The feature of having strong mechanical support by metallic local word lines throughout the depth of a very tall and narrow memory stack provides physical stability to the stack, which allows the height of the memory stack to be scaled up even for very high aspect ratio memory structures.

[0084] Next, referring to FIG. 4J, a conductive layer 176 is deposited on the memory structure 50. Prior to the deposition process, surface oxidation of the exposed backside of the channel layer 66 is removed without damaging the channel layer. In some embodiments, the conductive layer 176 is deposited using chemical vapor deposition or atomic layer deposition. The conductive layer 176 fills the cavity 172 in the multi-layer structure. The conductive layer 176 is also formed on the sidewalls of the auxiliary trenches 84 and on the top surface of the multi-layer structure. Excess material formed on the sidewalls 174 and top surface of the multi-layer structure is removed by dry selective etching, followed in some embodiments by a selective wet etching process to remove remaining metal residues or stringers. The resulting structure is shown in FIG. 4K.

[0085] Referring to FIG. 4K, as a result of the metal replacement process, a first conductive layer 62 and a second conductive layer 64 are formed. The first conductive layer 62 and the second conductive layer 64 are in contact with the channel layer 66. The first conductive layer 62 and the second conductive layer 64 are also spaced apart from each other by a channel spacer dielectric layer 63. In each multi-layer film 51, the first conductive layer 62 forms a common drain (bit) line of the subsequently formed NOR memory string, and the second conductive layer 64 forms a common source line of the subsequently formed NOR memory string. In some embodiments, the first conductive layer 62 and the second conductive layer 64 are each a metal layer, which may be a titanium nitride (TiN) liner and a tungsten (W) layer, a tungsten nitride (WN) liner and a tungsten (W) layer, a molybdenum layer or a cobalt layer, or other conductive materials as described above. Furthermore, in this embodiment, the memory structure 50 includes a dummy metal layer 61 formed on the insulating layer 54. In particular, dummy metal layer 61 is formed between the bottom active layer and insulating layer 54. Dummy metal layer 61 is formed in the same metal replacement process as first conductive layer 62 and second conductive layer 64, and therefore has the same material composition as first conductive layer 62 and second conductive layer 64. Dummy metal layer 61, formed directly on insulating layer 54, provides mechanical support for the memory stack formed thereon.

[0086] After the metal replacement process, auxiliary trenches 84 are used to separate the channel layers 66 between each multilayer 51 in a process called channel isolation. Referring to FIG. 4L, the fabrication process uses auxiliary trenches 84 to expose the interlayer sacrificial layer 70 from the side of the active stack to remove the third sacrificial layer 70, leaving a cavity 180 where the third sacrificial layer 70 was. Depending on the material used for the third sacrificial layer 70, various removal processes are used. For example, if the sacrificial layer 70 is a carbon layer, the carbon layer can be removed by ashing in an oxygen atmosphere. If the sacrificial layer 70 is amorphous silicon or silicon germanium, a selective wet or dry etching process can be used. The resulting memory structure 50 is shown in FIG. 4L. FIG. 4L illustrates the function of the dummy metal layer 61 to provide structural support for the memory stack, especially during the channel isolation process after the sacrificial layer 70 is removed. The dummy metal layer 61 provides mechanical support for the memory stack against the insulating layer 54, thereby enhancing the stability of the memory stack during the channel isolation process.

[0087] As shown in FIG. 4L, the cavity 180 thus formed exposes a portion of the channel layer 66 between the multilayer films 51 in the active stack. In particular, the back surface of the channel layer 66 is exposed through the auxiliary trench 84 and the cavity 180. The auxiliary trench 84 and the cavity 180 are then used to remove (in the Z direction) the exposed portion of the channel layer 66 that spans two adjacent multilayer films 51 in the active stack. Referring to FIG. 4M, the fabrication process uses the auxiliary trench 84 and the cavity 180 to supply an etchant with high etching selectivity to the back surface of the channel layer 66, and selectively etches the exposed portion of the channel layer 66, as shown by the dotted circle in FIG. 4M. As a result, the channel layer 66 is separated in the Z direction from each multilayer film 51. In some embodiments, the channel layer 66 is a semiconductor oxide such as IGZO, and the fabrication process selectively etches the exposed portion of the channel layer 66 in a wet etching process, for example, using sulfuric acid, citric acid, acetic acid, or ammonium hydroxide. In some embodiments, the memory structure 50 includes an interfacial layer 65, and the backside etch of the channel layer 66 is selective to the interfacial layer 65 such that the interfacial layer acts as an etch stop for the backside etch process. That is, exposed portions of the channel layer 66 are etched through the auxiliary trenches 84 and the cavities 180, and the etch process stops when the interfacial layer 65 is reached. In one embodiment, the interfacial layer 65 is an aluminum oxide (Al2O3) layer. In another embodiment, the backside etch process is implemented as a multi-step etch process including an atomic layer etch step used to remove the last 1-2 nm of the channel layer, where the atomic layer etch step stops on the interfacial layer 65 or stops on the ferroelectric polarization layer 67.

[0088] Returning to the embodiment shown in FIG. 4M, the channel isolation process stops when the exposed portions of the channel layer 66 are removed, and the channel region is physically isolated and insulated from each multilayer 51 in each active stack. In some embodiments, the channel isolation process can continue to remove the now exposed portions of the ferroelectric polarization layer 67 by modifying the etchant chemistry or process, as shown in FIG. 4M-1. In the memory structure 50b of FIG. 4M-1, the ferroelectric polarization layer 67, which functions as a storage layer for the storage transistor, is also physically isolated and insulated from each multilayer 51 in each active stack. Isolation of the ferroelectric polarization layer 67 is optional and may be omitted in other embodiments of the invention. In some implementations, care can be taken to minimize excessive undercutting by side etching of the channel layer 66 or the ferroelectric layer 67.

[0089] Referring to FIG. 4N, after the channel isolation process, the exposed surfaces of the memory structure 50 may be passivated, such as by forming a thin liner layer 92. The liner layer 92 is a thin dielectric layer having a thickness on the order of about 1-2 nm. The liner layer 92 is a silicon oxide, silicon nitride, or aluminum oxide layer, and functions to passivate or seal the exposed surfaces in the cavity 180 and the auxiliary trench 84. In some embodiments, the liner layer 92 is conformally deposited and may be deposited using an atomic layer deposition (ALD) process. This thin liner layer 92 is also referred to herein as an air gap liner layer. In some embodiments, the liner layer 92 is formed from the same material as the interface layer 65. In one embodiment, the interface layer 65 and the liner layer 92 are both aluminum oxide layers.

[0090] Referring to FIG. 4O, the remaining cavities in the memory structure 50 are filled with a low K dielectric material 185, such as silicon oxide. The dielectric layer 185 fills the cavities 180 between the active layers and also fills the auxiliary trenches 84. A cap oxide layer 97 is formed over the completed memory structure 50. In some embodiments, the cap oxide layer 97 is a silicon oxide layer and may have a thickness between 100 nm and 200 nm. FIG. 4O shows the resulting memory structure 50.

[0091] In another embodiment, the remaining cavity 93 in the memory structure 50 is not filled. Instead, the auxiliary trench 84 is used to provide air gap isolation in the memory structure 50. Referring to FIG. 4O-1, the memory structure 50c implements two levels of air gap isolation. First, a dielectric layer 94 is non-conformally deposited in the auxiliary trench 84 covering the sidewalls of the trench 84 (i.e., covering the liner layer 92 on the trench sidewalls) while capping the ends of the interlayer cavity 180 facing the auxiliary trench 84. The dielectric layer 94 serves as a capping layer to form an interlayer air gap isolation region between adjacent active layers 51 of each memory stack. In some embodiments, the dielectric layer 94 is a non-conformally deposited dielectric layer, such as a silicon oxide (SiO2) layer or a silicon nitride (Si3N4) layer. In some embodiments, the dielectric layer 94 may have a thickness of 5-10 nm in the X-direction. The dielectric layer 94 provides a first level of air gap isolation by providing vertical isolation between the storage transistors formed in the active stacks, and also provides mechanical support for the multilayer 51 at the ends facing the auxiliary trenches 84.

[0092] Second, a dielectric layer 96 is formed on top of the auxiliary trenches 84, such as by non-conformal deposition of a dielectric layer. In some embodiments, a dielectric layer, such as a silicon oxide (SiO2) layer, is deposited on top of the auxiliary trenches 84 around the trenches. The deposition process continues by growing the dielectric layer until it meets in the center of the trenches 84, thereby forming a capping layer that covers the remaining cavity 93 of the trenches 84. A cap oxide layer 97 is formed over the completed memory structure 50. The dielectric layer 96 forms air gap isolation in the cavity 93 between the active stacks adjacent the auxiliary trenches 84. The dielectric layer 96 provides isolation between adjacent memory stacks and reduces parasitic capacitance therebetween, thereby achieving a second level of air gap isolation. In particular, the first level of air gap isolation has the effect of minimizing parasitic capacitive coupling between a first conductive layer (bit line) in one memory plane and a second conductive layer (source line) in an adjacent memory plane. The second level of air gap isolation has the effect of minimizing parasitic capacitance (Cp) between adjacent active stacks. In some embodiments, dielectric layer 96 and dielectric layer 94 are formed from the same dielectric material. In other embodiments, dielectric layer 96 and dielectric layer 94 are formed from different dielectric materials. Dielectric layer 96 and cap oxide layer 97 cooperate with each other to prevent tilting or collapse of long strings of tall and narrow memory stacks, thereby providing additional mechanical strength and stability to memory array 50c.

[0093] In further embodiments, the memory structure can be configured to include either two levels of air gap isolation. That is, the memory structure can form a first level of air gap isolation using a dielectric capping layer 94, and the remaining cavity 93 in the auxiliary trench 84 is filled with a low-K dielectric material such as silicon oxide (SiO2). Alternatively, the memory structure can form a second level of air gap isolation without a first level of air gap isolation by filling the interlayer cavity 180 with a low-K dielectric material such as silicon oxide (SiO2) and capping the remaining cavity 93 with a dielectric capping layer 96. The type of insulating material used for the interlayer cavity and auxiliary trench cavity can be selected based on the amount of parasitic isolation desired between the storage transistors in each active stack and between the active stacks.

[0094] With reference to Figures 4O and 4O-1, the memory structure 50 or 50b thus formed includes storage transistors arranged in NOR memory strings in multiple planes. In particular, the storage transistors have the same structure as the storage transistors 20 described with reference to Figure 1. Vias and interconnects are formed in and on the cap oxide layer 97 to form interconnects between the storage transistors and control circuitry, such as CuA formed in the semiconductor substrate 52. For example, the bit lines and local word lines of the memory stack are connected to the control circuitry, selection circuitry, and sense circuitry formed in the CuA of the semiconductor substrate. In one embodiment, global word lines constructed using copper metallization processes and materials can be formed on the cap oxide layer 97 to connect the local word lines to respective word line drivers formed in the CuA of the semiconductor substrate 52. In one embodiment, Figure 4P illustrates a memory structure 50c having a global word line metallization layer 194 formed on the cap oxide layer 97 and connected to the local word lines 68 formed in the memory structure through vias 192 formed in the cap oxide layer 97. In some embodiments, the global word line metallization layer 194 is formed of copper, tungsten, molybdenum, cobalt, other metals, or one of their compounds. The vias 192 are filled with a metal layer, such as copper or other suitable metal. Each global word line 194 thus configured is connected to a group of local word lines 68 and provides control signals to gate electrodes of storage transistors formed in multiple memory planes associated with the respective vertical local word line. More specifically, the global word lines 194 extend in an X direction perpendicular to the common bit lines 62 extending in the Y direction. Each global word line is connected to local word lines arranged in a row in the X direction, as shown in view (i) of FIG. 4P. Meanwhile, bit lines from different memory planes of each active stack are connected to a bit line selector through a staircase structure formed at the Y end of the memory structure. The bit line selector connects the bit lines to sense amplifiers and voltage driver circuits typically provided in CuA formed under the staircase structure.

[0095] It should be noted that FIG. 4P is merely illustrative and is not intended to show the exact via and interconnect structure. For example, the vias 192 connecting the local word lines 68 to the global word lines 194 need to be insulated with respect to the channel layer 66 so as not to short the gate conductor with the channel region of the storage transistor. Various methods of forming the vias while providing isolation can be used. In one embodiment, the channel layer 66 is recessed into the top of the memory array. In another embodiment, an additional dummy layer may be provided in the memory structure above the memory array (in the Z direction) to terminate the channel layer 66 while extending each gate contactor layer for connection to the vias that provide electrical connection to the global word lines 194.

[0096] FIG. 9 illustrates a memory structure formed using a dummy layer to insulate a channel layer for global word line connection in some embodiments. Referring to FIG. 9, the memory structure 500 includes a dummy insulating layer 154 and a dummy dielectric layer 156. In the initial stack formation, the dummy insulating layer 154 is provided as an interlayer sacrificial layer as described above (e.g., in FIG. 4A), and is then replaced with an interlayer insulating layer such as an air gap insulation. The dummy dielectric layer 156 serves as a capping layer for the dummy insulating layer 154 during the replacement process. In particular, during the intermediate processing step, the dummy insulating layer 154 as an interlayer sacrificial layer is removed to provide an access opening to the back side of the channel layer 66. The channel layer 66 is selectively etched through the access opening. The channel layer 66 thus configured is insulated against the layers of the storage transistor. Next, a liner layer 92 (a thin dielectric layer) is formed around the exposed cavity of the access opening, and the remaining portion forms the air gap insulation. Thus, in this embodiment, the dummy insulating layer 154 is also an air gap insulation backed by the liner layer 92. In other embodiments, the interlayer insulating layer may be a dielectric layer and the dummy insulating layer 154 may also be a dielectric layer. With such a configuration, the channel layers 66 for the memory strings in the top layer of the memory structure 500 are separated and insulated by the dummy insulating layer 154. A cap oxide layer 106 is formed above the memory array. Vias 112 are formed to contact the local word lines (gate conductor layer 68) without concern for possible electrical shorts to the channel layer. A metallization layer 114 is formed on the cap oxide layer 106 to form global word lines. Each global word line 114 is connected to a local word line through the vias 112 and provides a control signal to the gate electrodes of storage transistors formed in the multiple memory planes associated with each vertical local word line.

[0097] In the above embodiments, a memory structure is formed using a semiconductor oxide layer as a channel layer of the storage transistor. In some embodiments, the semiconductor oxide channel layer is formed as a two-layer channel including a first semiconductor oxide layer formed on the trench sidewalls and in electrical contact with the conductive layers forming the drain and source lines, and a second semiconductor oxide layer formed on the first semiconductor oxide layer. The first semiconductor oxide layer and the second semiconductor oxide layer cooperate with each other to form a channel layer and function as a channel region of each storage transistor. The first semiconductor oxide layer functions as a low contact resistance contact layer to the drain and source conductive layers it contacts. The second semiconductor oxide layer functions as a main channel layer providing the desired high electron mobility and high on-current to the channel region of the storage transistor. In some embodiments, the first semiconductor oxide layer is a metal oxide semiconductor material that provides a lower contact resistance to the conductive layer than the contact resistance provided by the second semiconductor oxide layer. In one embodiment, the first semiconductor oxide layer is, for example, an indium aluminum zinc oxide (InAlZnO or IAZO) layer having a thickness of about 1 nm to 2 nm, and the second semiconductor oxide layer is an IGZO layer having a thickness of about 6 nm. In other embodiments, other semiconductor oxide materials that provide a desired low contact resistance to the metal layer may be used as the first semiconductor oxide layer. In particular, it is desirable to use a metal oxide semiconductor material for the first semiconductor oxide layer that is highly resistant to deoxidation of the channel layer by the source / drain conductive layer and suppresses oxidation of the source / drain conductive layer during heat treatment.

[0098] In the above embodiments, various memory structures including multiple active layers (or memory planes) have been described. Each memory structure includes multiple memory stacks, each of which includes multiple active layers, resulting in a three-dimensional array of NOR memory strings. The memory structures of the present disclosure can be used as basic building blocks for fabricating large capacity, high density memory devices including multiple three-dimensional arrays of NOR memory strings. For example, the three-dimensional array of NOR memory strings can be arranged as a two-dimensional array of tiles, each of which includes a three-dimensional array of NOR memory strings constructed using several of the memory structures described above. Each tile also includes staircase sections and other support circuitry, such as interconnect wiring via global word lines at the top or bottom of each tile.

[0099] In an embodiment of the present disclosure, a memory structure can be formed using a single active layer. That is, the memory structure can include an array of NOR memory strings formed using a single layer of storage transistors in a vertical direction. The storage transistor is a junctionless ferroelectric storage transistor having an oxide semiconductor as a channel and a ferroelectric polarization layer as a gate dielectric layer. In this case, an interlayer insulating layer is not required. Alternatively, a single interlayer insulating layer may be provided between the semiconductor substrate and the single active layer. In a single layer storage transistor, channel isolation is not required. Auxiliary trenches are used to perform metal replacement to form first and second conductive layers that function as common drain and source lines. In practice, a single memory plane memory structure forms a two-dimensional array of NOR memory strings. A memory device can be formed using such a memory structure. The memory device includes a two-dimensional array of tiles, each tile including a two-dimensional array of NOR memory strings formed using a single memory plane of storage transistors and other support circuitry. If a single layer is used, no staircase structure is required, or alternatively, a staircase structure having only a single staircase step may be used to connect to the bitlines of each NOR memory string. Alternatively, a single or two-layer ferroelectric memory tile may connect its first layer bitlines and second layer bitlines directly to logic circuitry in the substrate below the bitlines through embedded contacts that function as vias. In some embodiments, a memory device configured in this manner is suitable for use as an embedded memory to provide high capacity memory in less than 10 μm spacing of a connector directly above one or more processor cores for low latency data-intensive applications. Thus, in one embodiment, a memory device including one or two memory planes may be integrated and embedded in the same semiconductor substrate of a logic integrated circuit to function as embedded memory for the processing circuitry of the logic integrated circuit.

[0100] In the above embodiment, the channel layer 66 is formed after the formation of the LWL trench (FIG. 4C), and is then protected by a sacrificial material, which is then removed in a subsequent process to form the ferroelectric polarization layer 67 on the channel layer 66. In some embodiments, the ferroelectric polarization layer can be formed simultaneously with the channel layer 66, which avoids the oxidation of the channel layer 66 when exposed to oxygen or during high temperature annealing. In some implementations, the two layers can be formed simultaneously and efficiently by forming the two layers in the same process chamber without breaking vacuum. FIGS. 8A and 8B are diagrams illustrating another process for fabricating a memory structure including an HNOR memory string in an embodiment of the present invention. FIGS. 8A and 8B show a memory structure 50d constructed in substantially the same manner as described above, and for simplicity, the structure and construction method will not be repeated. Similar elements in FIGS. 8A and 8B and the above described figures are given similar reference numerals and will not be described.

[0101] First, referring to FIG. 8A, which shows an intermediate processing step after the LWL trench 80 (or working trench) is formed in the memory structure 50d, a channel layer 66 is deposited on the sidewalls of the trench 80. For example, the channel layer 66 is a semiconductor oxide layer such as indium gallium zinc oxide (IGZO). Next, a gate dielectric layer 67 is deposited on the channel layer 66. For example, the gate dielectric layer 67 is a ferroelectric polarization layer such as a doped hafnium oxide layer. Optionally, an interface layer 65 may be formed between the channel layer 66 and the gate dielectric layer 67. For example, the interface layer 65 may be an ultra-thin silicon nitride (Si3N4) layer, a silicon oxynitride layer, or an aluminum oxide (Al2O3) layer. Next, a liner layer 81 is deposited to cover the gate dielectric layer 67, and the remaining space in the trench 80 is filled with a sacrificial material 82. In one embodiment, liner layer 81 is a low temperature (less than 500° C.) silicon nitride layer or an undoped amorphous silicon layer, and sacrificial material 82 is silicon germanium. After the deposition step, excess material is removed from the top of memory structure 50c, for example using chemical mechanical polishing (CMP).

[0102] The steps of fabricating the memory structure 50d continue similarly as described with reference to Figures 4D-4O (or Figure 4O-1). However, in the process step of forming the local word line structures between the dielectric fill shafts 98 of Figure 4F, only the gate conductor layer 68 is formed since the gate dielectric layer 67 has already been formed in this process step. In forming the memory structure 50d, the thermal annealing of the gate dielectric layer 67 may be performed after the gate conductor layer 68 is deposited on the gate dielectric layer. In this case, the gate conductor layer 68 serves as a capping layer for the crystallization of the ferroelectric material used as the gate dielectric layer.

[0103] The resulting memory structure of this fabrication process is shown in FIG. 8B. Referring to FIG. 8B, memory structure 50c includes a channel layer 66 and a gate dielectric layer 67 extending along the Y direction between dielectric filled shafts 98. In the X direction, the gate dielectric layer 67 is not formed on the sides of the dielectric filled shafts 98. As a result, the ferroelectric storage transistor in memory structure 50d has a slightly wider transistor width (W) than the storage transistors of the memory structures described above. The larger the transistor width of the storage transistor in memory structure 50d, the higher the read current during a read operation.

[0104] Precharge Transistor

[0105] In an embodiment of the invention, a memory structure includes a three-dimensional array of NOR memory strings of junctionless ferroelectric storage transistors. The storage transistors in each NOR memory string share a common source line and a common drain line (common bit line). The voltage on each shared source line can be applied directly from one or both ends of each source line separately in the three-dimensional structure. In some embodiments, the shared common source line is electrically floating and the source voltage is applied from the common bit line using precharge transistors, eliminating the need for connector lines to the source lines in stepped portions of the three-dimensional structure. In one embodiment, the source voltage on a given source line is set to a desired voltage value (e.g., ground voltage) by a precharge operation using one or more precharge transistors formed along the memory string, and then the source line is left in an electrically floating state after the precharge operation. In particular, the precharge operation sets the common bit line to a desired voltage and then momentarily turns on the precharge transistor to short the common bit line to the common source line and transmit the bit line voltage to the source line. As a result, the common source line is charged from the voltage on the common bit line to a voltage equal to the bit line voltage. After the precharge operation is completed, the precharge transistor is turned off. The common source line maintains a relatively constant voltage due to parasitic capacitances at its source terminal, such as the parasitic capacitance between the source terminal and the local word line gate terminals of many of the storage transistors in the NOR memory string.

[0106] In embodiments of the present invention, various methods can be used to provide precharge transistors in the three-dimensional array of NOR memory strings described above.

[0107] In a first embodiment, a selected ferroelectric storage transistor in a NOR memory string is designated as a precharge transistor. FIG. 5A is a cross-sectional view of a portion of a memory structure in the XY plane showing a NOR memory string having a given precharge transistor in an embodiment of the present invention. Referring to FIG. 5A, a memory structure 200 includes an active stack adjacent to an operating trench in which a local word line is formed and an auxiliary trench used for metal replacement and channel isolation processes. The figure is a cross-sectional view taken at the location of a first conductive layer 62 of a given active layer in the active stack. The first conductive layer 62 forms a common bit line for the memory string. A ferroelectric storage transistor 220 is formed at each intersection of the common bit line 62 with a channel layer 66, a ferroelectric polarization layer 67, and a gate conductor 68. FIG. 5A shows four memory strings 210-1 to 210-4 formed to extend in the Y direction along four active stacks (represented by first conductive layers 62-1 to 62-4, respectively). For example, each memory string 210 includes a ferroelectric storage transistor 220 formed along the active stack 62 and intersecting every local word line structure along the active stack 62. The storage transistor 220 is insulated from other storage transistors 220 in the memory string by a dielectric fill shaft 98.

[0108] It should be noted that in the memory structure 200, a pair of memory strings 210 in each memory plane adjacent to an LWL trench have corresponding storage transistors that share a local word line structure. Thus, each local word line activates two ferroelectric storage transistors in the memory strings that border the LWL trench in each memory plane. In one embodiment, in response to the selection of the local word line 68-1, the ferroelectric storage transistors 220-1 and 220-2 associated with the respective memory strings 210-1 and 210-2 are activated. The common bit lines 621 and 62-2 are then selected to provide access, and appropriate voltages are provided to the activated ferroelectric storage transistors 220-1 and 220-2. In another embodiment, in response to the selection of the local word line 68-2, the ferroelectric storage transistors 220-3 and 220-4 associated with the respective memory strings 210-3 and 210-4 are activated. The common bit lines 623 and -4 are then selected to provide access and the appropriate voltages are supplied to the activated ferroelectric storage transistors 220-3 and 220-4. In some embodiments, when storage transistor 220-1 is erased, storage transistor 220-2, which may be in a programmed state, must also be protected from being erased. As an example of a typical erase operation for ferroelectric storage transistor 220-1, the erase operation requires application of 3.0 volts to its local word line 68-1 and 0.0 volts to its bit line 62-1. To prevent erasure of ferroelectric storage transistor 220-2 (which shares the same local word line 68-1 and therefore has the same 3.0 volts applied to its control gate), its bit line 62-2 must be connected to an inhibit voltage V close enough to 3.0 V to prevent reversal of the polarization state of ferroelectric storage transistor 220-2. inhb The same is true for all program and program inhibit operations, and also when avoiding disturbing the polarization states of ferroelectric storage transistors on different memory planes above or below the memory plane being accessed.

[0109] In this embodiment, a selected number of storage transistors 220 in each memory string 210 are designated for use as precharge transistors 230. In one embodiment, one storage transistor out of every 250 storage transistors along the memory string is designated as a precharge transistor 230. In a memory string of 2000 or more storage transistors, 8-10 storage transistors distributed throughout the memory string are designated as precharge transistors. FIG. 5A illustrates a portion of memory strings 210-1 through 210-4 in which two storage transistors 230 in each memory string 210 are designated as precharge transistors. In the entire memory string 210, there may be 8-10 storage transistors designated as precharge transistors.

[0110] In each precharge operation, one or more precharge transistors are activated to set the common source line voltage. In some embodiments, only a designated subset of precharge transistors are used in each precharge operation. For example, during a precharge operation, one or more designated precharge transistors in the memory string 210 are activated by the memory controller to perform the precharge operation. In one embodiment, the memory controller randomly selects or rotates the physical addresses of the designated precharge transistors from time to time such that a different subset of the precharge transistors in the memory string is selected during a memory operation. Randomizing the use of the precharge transistors in each memory string has the effect of reducing electrical stress experienced by each designated precharge transistor during repeated precharge operations. In one embodiment, after every X precharge operations or after a predetermined time interval, the memory controller changes the physical addresses of the precharge transistors used such that a different subset of the precharge transistors in the memory string is selected for use in the next set of X precharge operations. As used herein, a precharge operation can activate one or more precharge transistors, and a "subset" of precharge transistors refers to one or more precharge transistors as used herein.

[0111] In another embodiment, the memory controller determines the health of designated precharge transistors through periodic refresh operations, and if the memory controller determines through refresh operations that the health of certain precharge transistors is faulty or near failure (e.g., if the precharge transistors exhibit high leakage current), the memory controller can retire those precharge transistors and replace them with other designated precharge transistors in the respective memory strings.

[0112] In a second embodiment, the precharge transistor is preferably provided as a ferroelectric storage transistor with an increased channel width in each NOR memory string. FIG. 5B is a cross-sectional view of a portion of a memory structure in the XY plane showing a NOR memory string having a precharge transistor in an embodiment of the present invention. Similar components in FIG. 5A and FIG. 5B are given similar reference numerals and will not be described. Referring to FIG. 5B, the precharge transistor 250 is provided in each memory string as a ferroelectric storage transistor with an increased channel width. That is, the precharge transistor 250 in the memory string 210 is configured similarly to the storage transistor 220 in FIG. 5A, but with a width in the Y direction larger than that of the storage transistor 220. Several precharge transistors 250 can be provided in each memory string and distributed throughout each memory string. Increasing the channel width of the ferroelectric storage transistor reduces the on-current (I on ) thus increasing the on-current of precharge transistor 250 relative to the on-current of storage transistor 220. Precharge transistor 250 therefore has an increased on-current and increased drive for use during the precharge operation to effectively bias the common source line to the common bitline voltage.

[0113] In the third embodiment, a non-memory transistor is formed in each memory string and used as a pre-charge transistor. FIG. 5C is a cross-sectional view of a portion of a memory structure in the XY plane showing a NOR memory string having a pre-charge transistor in an embodiment of the present invention. The same components in FIG. 5A and FIG. 5C are given the same reference numerals and will not be described. Referring to FIG. 5C, a pre-charge transistor 270 is provided in each memory string 210 as a non-memory transistor. In this embodiment, the pre-charge transistor 270 is formed using the same semiconductor oxide channel layer 66 as the storage transistor, but is a junctionless transistor with a non-polarizable gate dielectric film 272 formed between the channel layer and the gate conductor 276. Several pre-charge transistors 270 can be provided in each memory string and distributed throughout each memory string.

[0114] To form the precharge transistor 270 in the memory structure 260 of FIG. 5C, a mask having openings exposing locations where the precharge transistor will be formed is applied to the memory structure 260, covering the entire memory string 210. Note that the precharge transistor 270 may be formed at an intermediate processing stage of the memory array. For example, the precharge transistor 270 may be formed in the memory structure 260 after forming the channel layer 66 (e.g., after the processing steps of FIG. 4C) and before creating the local word lines (e.g., before the processing steps of FIG. 4D).

[0115] Using a mask that defines the precharge transistor, the liner layer 81 and the sacrificial material 82 covering the channel layer 66 are removed, for example by one or more wet etching processes. A gate dielectric layer 272 is then deposited on the sidewalls of the cut cavity on the channel layer 66. In one embodiment, the gate dielectric layer 272 is a silicon oxide (SiO2) layer. In other embodiments, the gate dielectric layer 272 can be a hafnium oxide layer (HfO2), a sandwich of silicon oxide (SiO2) capped with silicon oxynitride (Si2NO3), or aluminum oxide (Al2O3). Next, a conductive layer is deposited that serves as the gate conductor of the precharge transistor 270. The gate conductor can include a conductive liner layer 274 and a low resistance conductor 276 deposited successively. In some embodiments, the conductive liner layer 274 is a titanium nitride (TiN) layer and the conductor 276 is a highly doped polysilicon layer or a tungsten (W) layer. Excess deposition material can be removed from the top of the memory structure by chemical mechanical polishing (CMP). The precharge transistor 270 thus formed is controlled by a conductor 276 as a control gate electrode. After forming the precharge transistor 270, the fabrication process continues with fabrication of the storage transistor by covering the precharge transistor 270 and exposing areas associated with the memory array. In some embodiments, the gate electrode of the precharge transistor 270 is connected to a global word line formed above the memory array that connects to control circuitry formed in CuA, thereby allowing the control circuitry or a memory controller connected thereto to select and activate the precharge transistor 270 to perform a precharge operation.

[0116] Improved fringe field effect

[0117] In the memory structure 10 of FIG. 1, the channel length of the ferroelectric storage transistor 20 thus formed is determined by the thickness L1 of the channel spacer dielectric layer 23. In an embodiment of the present invention, a shorter channel length, e.g., L1 less than 10 nm, can enhance the electric fringe field effect of the ferroelectric storage transistor, which enhances the polarization effect in the ferroelectric layer. Referring again to FIG. 1, when an erase or program voltage is applied between the bit line (BL) electrode 22 and the control gate electrode 28, an electric field between the electrodes is applied to the portion of the ferroelectric layer 27 directly facing the bit line (BL) electrode 22, thereby causing a desired change in the polarization of the ferroelectric layer 27. The electric field further includes a fringe field that extends into a portion of the channel 26.

[0118] In some embodiments, the fringe field can be further enhanced by biasing the bit line (BL) and the source line (SL) to the same voltage during an erase or program operation. In other words, the bit line (BL) and the source line (SL) of the ferroelectric storage transistor are used as a single electrode during an erase or write operation. When the bit line and the source line are biased as a single electrode, the fringe fields from both the bit line 22 and the source line 24 are applied into the channel 26 from both ends, and if the channel is short enough, the fringe fields overlap most or the entire length of the channel 26. To enhance the fringe field, the polarization of the ferroelectric layer is promoted by biasing the ferroelectric storage transistor in a single electrode mode, which can widen the threshold voltage window between the erased and programmed states.

[0119] In one embodiment, when the memory structure implements a floating source architecture, the precharge transistors described above can be used to facilitate equalization of the voltages on the bit line 22 and the source line 24 during erase or program operations, so that the bit line 22 and the source line 24 act as junction electrodes to maximize the fringe field coverage of the ferroelectric layer 27.

[0120] In another embodiment of the present invention, the fringe field is enhanced by using a high permittivity (high-K) dielectric layer in the channel spacer region adjacent to the bit line. Figures 6A, 6B, 6C, and 6D show a detailed structure of a junctionless ferroelectric storage transistor in another embodiment. Similar components in Figures 1 and 6A-6D are given similar reference numerals and will not be described. Referring first to Figure 6A, a ferroelectric storage transistor 300a includes a bit line 22 forming a common drain line of the NOR memory string and a source line 24 forming a common source line of the NOR memory string, the bit line 22 and the source line 24 being spaced apart from each other by a channel spacer dielectric layer 320a. The storage transistor 300a further includes a semiconductor oxide channel layer 26 formed vertically along the sidewall of the memory stack and contacting both the bit line 22 and the source line 24. A ferroelectric layer 27 and a gate conductor layer 28 are formed on the sidewall of the memory stack adjacent to the channel layer 26. In some embodiments, an interface layer 25 is optionally provided between the channel layer 26 and the ferroelectric layer 27. In this embodiment, the gate conductor layer 28 includes a conductive liner 28a as an adhesion layer and a low resistance conductor 28b. The storage transistor 300a is isolated from adjacent storage transistors in the stack by an interlayer insulating layer 15. The interlayer insulating layer 15 includes an air gap insulating layer 15a surrounded by a liner layer 15b. The storage transistor 300a thus configured is a junctionless ferroelectric storage transistor.

[0121] In an embodiment of the present invention, the channel spacer dielectric layer 320a includes a first dielectric layer 330 and a second dielectric layer 350. The second dielectric layer 350 is formed between the bit line 22 and the first dielectric layer 330. The second dielectric layer 350 has a higher dielectric constant than that of the first dielectric layer 330 and is referred to herein as a high-k (high-K) dielectric layer. In some embodiments, the term high-k dielectric layer or high-K dielectric as used herein refers to a dielectric layer having a higher dielectric constant than that of a silicon oxide layer. By providing the high-k dielectric layer 350 adjacent to the bit line 22, the fringe electric field between the bit line electrode 22 and the gate electrode 28 is concentrated in the portion of the channel 26 closest to the bit line 22, which can enhance the polarization effect of the ferroelectric polarization layer 27 during program and erase operations.

[0122] In some embodiments, the high-K dielectric layer 350 can be formed using silicon nitride (having a dielectric constant of about 6) or hafnium oxide (having a dielectric constant of about 19). Other high-k materials that can be used include silicon oxynitride (SiON). Meanwhile, the first dielectric layer 330 can be formed using silicon dioxide (having a dielectric constant of about 4). In some embodiments, the first dielectric layer 330 has a thickness L2, the high-K dielectric layer 350 has a thickness L3, and the effective channel length L1 of the ferroelectric storage transistor 300 is L2+L3. In one embodiment, the thickness L2 is 15 nm, the thickness L3 is 10 nm, and the effective channel length L1 of the storage transistor 300 is 25 nm. The step of forming the high-K dielectric layer 350 can be included in the deposition process of forming the multi-layer stack in the present fabrication process described with reference to FIG. 4A. Alternatively, the high-k dielectric layer 35 can be formed by first providing a sacrificial layer and then replacing the sacrificial layer with a high-k material.

[0123] The high dielectric constant of the high-K dielectric layer 350 serves to concentrate the fringe electric field that spreads over the channel 26 when a polarization voltage is applied between the bitline electrode 22 and the control gate electrode 28. The fringe electric field enhancement is particularly effective when the bitline conductive layer 22 is very thin (e.g., 20 nm or less), in which case the application of an electric field from the electric field fringes to the channel 26 enhances the polarization effect during an erase or program operation.

[0124] In the embodiment shown in FIG. 6A, the high-K dielectric layer 350 is adjacent only to the bitline conductive layer 22. In another embodiment, as shown in FIG. 6B, the channel spacer dielectric layer 320b formed in the ferroelectric storage transistor 300b includes two high-K dielectric sub-layers. Referring to FIG. 6B, the channel spacer dielectric layer 320b includes a first high-K dielectric layer 350 adjacent to the bitline conductive layer 22 and a second high-K dielectric layer 352 adjacent to the sourceline conductive layer 24. The first high-K dielectric layer 350 and the second high-K dielectric layer 352 are separated from each other by a narrow dielectric layer 330. In another embodiment, the entire channel spacer dielectric layer may be formed of a high-k dielectric layer, such as a dielectric layer having a higher dielectric constant than that of silicon oxide.

[0125] 6C and 6D show another configuration of a ferroelectric memory transistor including a virtual backgate in some embodiments. Referring to FIG. 6C, the ferroelectric memory transistor 300c includes a virtual backgate formed in a channel spacer layer 320c. In particular, the channel spacer layer 320c includes a first dielectric sublayer 330a adjacent to the bitline conductive layer (BL) 22 and a second dielectric sublayer 330b adjacent to the sourceline conductive layer (SL) 24. The channel spacer layer 320c further includes a third dielectric sublayer 360 between the dielectric sublayer 330a and the dielectric sublayer 330b, and the third dielectric sublayer 360 is electrically insulated from the bitline conductive layer 22 and the sourceline conductive layer 24. As a result, the third dielectric sublayer 360 is an electrically floating sublayer. The first dielectric sublayer 330a and the second dielectric sublayer 330b can be formed using any dielectric material, such as silicon dioxide or silicon nitride, or a high-k dielectric material, such as hafnium oxide. The third dielectric sublayer 360 can be formed using a material selected from semiconductors or low-resistivity materials, such as titanium nitride (TiN), tungsten, molybdenum, or other metallic materials. In some embodiments, the third dielectric sublayer 360 can be undoped silicon, P-type or N-type doped silicon, undoped polysilicon, or P-type or N-type doped polysilicon.

[0126] In some embodiments, the first dielectric sublayer 330a and the second dielectric sublayer 330b are silicon dioxide, and the third dielectric sublayer 360 can be, for example, an amorphous silicon layer, a polysilicon layer, or a silicon germanium layer. The third dielectric sublayer 360 can be undoped, doped with boron to form a P-type semiconductor layer, or doped with phosphorus to form an N-type semiconductor layer. The third dielectric sublayer 360 overlaps a channel portion 372 of the channel layer 26, which is an oxide semiconductor material such as IGZO. A dielectric interface layer 374 is provided between the sublayer 360 and the channel portion 372 to insulate the third dielectric sublayer 360 from the channel layer 26. In one embodiment, an ultra-thin (e.g., 0.5 nm to 2 nm thick) dielectric interface layer 374 is provided between the channel layer 26 and the third dielectric sublayer 360. In one embodiment, the dielectric interface layer is formed from a high dielectric constant material such as silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide.

[0127] The third dielectric sub-layer 360 thus configured is capacitively coupled to both the bit line conductive layer 22 and the source line conductive layer 24, as well as to the channel layer 26, as shown by respective capacitors C1 and C2 in FIG. 6C. During a program or erase operation of the ferroelectric memory transistor 300c, the voltages applied to the bit line and the source line can be made to track each other, for example, via a precharge transistor connected between the bit line and the source line. By biasing the bit line 22 and the source line 24 in this manner, the bit line and the source line also function to capacitively hold the voltage of the electrically floating third dielectric sub-layer 360. By operating in this manner, the third dielectric sub-layer 360 becomes a virtual backgate for the channel portion 372 of the channel layer 26. The term "virtual" is used herein to indicate that the third dielectric sub-layer 360 is electrically floating, i.e., the third dielectric sub-layer 360 is not hardwired to a voltage source. Instead, the voltage on the sublayer 360 is established by following the voltages of the capacitively coupled bit line, source line, and channel portion 372. This configuration of the ferroelectric memory transistor 300c, with the channel formed between the vertical front gate 28 and the horizontal back gate 360, enhances the polarization field between the hardwired front gate 28 and the floating virtual back gate 360, resulting in maximum polarization along the channel portion 372 of the channel region for both erased and programmed polarization states. In some embodiments, the doping type and concentration of the virtual back gate 360 ​​determines its work function relative to the channel layer 26, and therefore can function to shift the intrinsic threshold voltage of the ferroelectric memory transistor 300c.

[0128] In the ferroelectric memory transistor 300c, the first dielectric sublayer 330a, the third dielectric sublayer 360, and the second dielectric sublayer 330b define the channel length L1 of the transistor. In the embodiment shown in FIG. 6C, the three sublayers have approximately the same thickness in the Z direction between the bit line 22 and the source line 24. In other embodiments, the first dielectric sublayer 330a and the second dielectric sublayer 330b are formed thinner than the third dielectric sublayer 360, allowing the channel portion 372 to occupy the entire or nearly the entire channel length L1 of the transistor channel. In some embodiments, the first dielectric sublayer 330a and the second dielectric sublayer 330b have a thickness of about 1-7 nm, and the third dielectric sublayer 360 has a thickness several times thicker than the thickness of the first dielectric sublayer 330a and the second dielectric sublayer 330b. For example, each of the first dielectric sublayer 330a and the second dielectric sublayer 330b has a thickness of about 3 nm. Configured in this manner, the channel portion 372 of the virtual back gate 360 ​​can cover substantially the entire channel length L1 of the channel layer 26. Such an extended length of the virtual back gate formed by the third dielectric sub-layer 360 has the advantage of reducing the threshold voltage variation for the erased or programmed polarization states of the ferroelectric storage transistor 300c across a memory die or across a wafer of memory dies.

[0129] FIG. 6D illustrates another embodiment of a ferroelectric memory transistor including a virtual backgate. In the embodiment illustrated in FIG. 6D, the ferroelectric memory transistor 300d includes a channel spacer layer 320d including a dielectric sublayer 330c formed as a dielectric liner layer surrounding the sublayer 360 forming the virtual backgate. In particular, the dielectric sublayer 330c is a dielectric insulating liner layer formed of a high-k material such as silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, and hafnium oxide, and is formed along the vertical sidewall regions adjacent the bitline conductive layer 22, the sourceline conductive layer 22, and the channel layer 26 between the bitline 22 and the sourceline 24. In some embodiments, the dielectric liner layer 330c has a thickness of 1-10 nm, and in some examples typically has a thickness of 2 nm-5 nm. In some embodiments, the virtual backgate 360 ​​can be formed by access from an auxiliary trench. The sublayer 360 forming the virtual backgate can be formed using materials as described above with reference to FIG. 6C, such as undoped or doped semiconductors or low resistance materials. For example, as shown in FIG. 4H, after forming auxiliary trenches providing backside access to the active stack, a previously deposited sacrificial layer, such as sacrificial layer 63 of FIG. 4A, is removed by selective etching using access from the auxiliary trenches to form a cut cavity. After removing the sacrificial layer 63, a dielectric sublayer 330c can be formed on the sidewalls of the cut cavity by a deposition process, such as atomic layer deposition, again using access through the auxiliary trenches. As a result, the bitline 22, the channel layer 26, and the source line 24 can be insulated by the dielectric liner layer 330c deposited on the exposed sidewalls of the cut cavity. The remaining space in the cut cavity is then filled with a sublayer 360 deposited from the auxiliary trenches, forming a virtual backgate for the memory transistor 330d, as shown in FIG. 6D.As an example, if the back gate 360 ​​is formed by doped amorphous silicon and the desired length L1 of the back gate 360 ​​is 15 nm, the remaining space in the cut cavity can be filled by depositing doped amorphous silicon to a thickness of about 8-10 nm. In the deposition process, 8-10 nm of unwanted residual silicon is deposited on the sidewalls of the auxiliary trenches and other surrounding structures outside the cut cavity. Such residual silicon can be removed by controlled selective silicon etching, including atomic layer etching (ALE), which leaves the majority of the silicon in the cavity that forms the back gate 360 ​​intact while avoiding electrical shorts between the bit lines 22 and source lines 24 of adjacent memory planes of the memory stack (Z direction). In embodiments of the present disclosure, the back gate replacement process can be performed before or after the metal replacement process described above with reference to Figures 4I-4K.

[0130] In the memory transistor 300d configured in this manner, the channel portion 372 of the virtual backgate is formed to cover substantially the entire channel length L1 of the channel layer 26. When selected for erasing or programming, the transistor 300d operates as a virtual capacitor at the intersection of the vertical (Z-direction) gate conductor layer 28 as one capacitor electrode and the horizontal (Y-direction) virtual backgate 360 ​​with the bit line 22 and source line 24, which together constitute the other capacitor electrode. This virtual capacitor configuration enhances the polarization field applied to the ferroelectric layer 27, improving the polarization uniformity over the entire length of the channel 36. Note that the polarization uniformity depends primarily on the polarization fringe fields in each of the bit line 22 and source line 24 in the absence of the backgate 360. This configuration of the transistor 300d also improves the threshold voltage uniformity across the memory die and across the wafer of memory dies. This is because the polarization region 372 is substantially shielded on both sides by the polarization regions adjacent to the bit line 22 and source line 24 .

[0131] 6C and 6D, the voltage difference between the selected bit line BL and source line SL during an erase, program or read operation is kept at a sufficiently low voltage value to avoid injection of electrons from the bit line or source line into the floating backgate 360. For example, the voltage difference may be in the range of 0.05V to 0.5V.

[0132] In some embodiments, the voltage on the back gate 360 ​​is hardwired to an external voltage source by a conductive connector accessed through an auxiliary trench (not shown in FIGS. 6C, 6D). This allows for memory array configurations where an external voltage can be shared by the back gates 360 of multiple memory planes in a memory stack along the Z direction.

[0133] 6E and 6F show a detailed structure of a junctionless ferroelectric storage transistor in another embodiment. In particular, FIG. 6E and FIG. 6F show another embodiment of a junctionless ferroelectric storage transistor having a high dielectric constant (high-K) dielectric layer in the channel spacer region. Similar components in FIG. 1, FIG. 6A-FIG. 6B, and FIG. 6E-FIG. 6F are given similar reference numerals and will not be described. FIG. 6E shows a ferroelectric storage transistor 300e including a sidewall high-K dielectric layer 356 disposed between the bitline conductive layer 22 and the sourceline conductive layer 24 and adjacent to and in contact with the channel layer 26. FIG. 6F shows the ferroelectric storage transistor 300e at an intermediate processing step illustrating a method of forming a sidewall high-K dielectric layer in some embodiments.

[0134] Referring first to FIG. 6E, the ferroelectric storage transistor 300e includes a bit line 22 forming a common drain line of the NOR memory string and a source line 24 forming a common source line of the NOR memory string, the bit line 22 and the source line 24 being spaced apart from each other by a channel spacer dielectric layer 320e. The storage transistor 300e further includes a semiconductor oxide channel layer 26 formed vertically along the sidewall of the memory stack and contacting both the bit line 22 and the source line 24. A ferroelectric layer 27 and a gate conductor layer 28 are formed on the sidewall of the memory stack adjacent to the channel layer 26. In some embodiments, an interface layer 25 is optionally provided between the channel layer 26 and the ferroelectric layer 27. In this embodiment, the gate conductor layer 28 includes a conductive liner 28a as an adhesion layer and a low resistance conductor 28b. The storage transistor 300e is insulated from adjacent storage transistors in the stack by an interlayer dielectric layer 15. The interlayer dielectric layer includes an air gap insulation 15a surrounded by a liner layer 15b.The storage transistor 300e thus configured is a junctionless ferroelectric storage transistor.

[0135] In embodiments of the present invention, the channel spacer dielectric layer 320e includes a first dielectric layer 330 and a second dielectric layer 356. The second dielectric layer 356, also referred to as a sidewall high-K dielectric layer, is formed adjacent to the channel layer 26 between the bit line 22 and the source line 24 and is in physical and electrical contact with the channel layer 26. The second dielectric layer 356 is a high-K dielectric layer having a dielectric constant higher than that of the first dielectric layer 330. In some embodiments, the term high-k dielectric layer or high-K dielectric layer as used herein refers to a dielectric layer having a dielectric constant higher than that of a silicon oxide layer. In some embodiments, the second dielectric layer has a thickness in the X-direction that is 3-10% of the thickness of the first dielectric layer. By providing the high dielectric constant dielectric layer 356 on the sidewall of the channel layer 26 between the bit line 22 and the source line 24, the fringe electric field from the bit line electrode 22 and the source line electrode 24 is concentrated in the portion of the channel 26 in the channel spacer region, thereby acting as a back gate to enhance the polarization effect of the ferroelectric polarization layer 27 during program and erase operations.

[0136] In some embodiments, the high-k dielectric layer 356 may be formed using silicon nitride or hafnium oxide (HfO2) or silicon oxynitride (SiON), while the first dielectric layer 330 may be formed using silicon dioxide. In some embodiments, the first dielectric layer 330 and the sidewall high-K dielectric layer 356 have a Z-thickness of 20-25 nm, which establishes the effective channel length of the ferroelectric storage transistor 300e.

[0137] In some embodiments, the sidewall high-K dielectric layer 356 can be provided in the fabrication process by forming a recess in the channel spacer insulating layer and etching a conformally deposited high-K dielectric layer. In some implementations, after the deposition process of the multilayer stack (e.g., FIG. 4A) and patterning of the multilayer stack to form the local wordline trenches 80 (e.g., FIG. 4B), a recess is formed in the channel spacer dielectric layer 330, such as using an atomic layer etching (ALE) process, as shown in FIG. 6F. In some embodiments, the channel spacer dielectric layer 330 is silicon oxide and is recessed by 2-6 nm. Next, referring to FIG. 6F, a conformal layer of high-K dielectric material 355 is deposited on the sidewalls of the trench to fill the recess in the channel spacer dielectric layer 330. In some embodiments, the high-k layer 355 is a hafnium oxide (HfO2) layer. After deposition of the high-K dielectric layer 355, the high-K dielectric layer 355 is anisotropically etched back relative to the sidewalls of the trench 80, as shown by the dotted line 357. The high-k dielectric layer remaining in the recess of the channel spacer dielectric layer forms a sidewall high-k dielectric layer 356 (FIG. 6E). In some embodiments, the conformally deposited high-k dielectric layer 355 has a thickness of about twice the thickness of the recess formed in the channel spacer dielectric layer. For example, if the channel spacer dielectric layer is recessed by 2-6 nm, the conformally deposited high-K dielectric layer 355 has a thickness of 4-12 nm. In this manner, the high-K dielectric layer 355 formed on the trench sidewalls can be etched back while remaining in the recess. The fabrication process of the ferroelectric storage transistor continues with the deposition of the channel layer and the formation of the local word line structures as described above with reference to FIGS. 4C-4P. In this manner, a ferroelectric storage transistor 300e including a sidewall high-K dielectric layer 356 is formed as shown in FIG. 6E.

[0138] In some embodiments, the ferroelectric memory transistors 300c and 300d can be formed using the fabrication process described above with reference to Figures 4A-4P. For example, the dielectric sub-layers 300a and 300b, as well as the sub-layer 360, may be provided in the fabrication process by including the sub-layers in a deposition process forming a multi-layer stack, as described with reference to Figure 4A. Alternatively, the sub-layers may be initially provided as sacrificial layers and then selectively replaced by materials suitable for the dielectric sub-layers 330a and 300b, as well as the virtual back gate sub-layer 360.

[0139] FIG. 7 is a cross-sectional view of a memory structure including a three-dimensional array of NOR memory strings in another embodiment of the present invention. Referring to FIG. 7, the memory structure 400 is constructed in substantially the same manner as described above, and for brevity, the structure and construction method will not be described again. Similar components in FIG. 7 and the above-mentioned figures are given similar reference numerals and will not be described. In this embodiment, the memory structure 400 is constructed using metal bracing to provide anchoring and support for the memory stack thus formed. Metal bracing is particularly beneficial when the memory structure includes multiple memory planes, such as 16 or 32 or more memory planes (or active layers). In some embodiments, the memory structure 400 includes a base metal layer 410 formed at the bottom of the active layer and attached to the insulating layer 54, providing metal bracing and anchoring of the gate conductor 68 in the LWL trench formed thereon, thereby anchoring the active layer 51 formed adjacent to the LWL trench. In this embodiment, the base metal layer 410 is a dummy metal layer formed similarly to one of the first and second conductive layers that will become the drain and source lines of the storage transistor, as described above with reference to Figures 4A to 4P. For example, the base metal layer 410 can be formed by a metal replacement process in which an initially formed sacrificial layer is removed and replaced with a metal layer.

[0140] More specifically, as shown and described in FIG. 4A, during the deposition of the thin films forming the multilayer film 51 and the interlayer sacrificial layer 70, the base metal layer 410 can be introduced as an additional sacrificial layer 71. That is, an additional metal replacement sacrificial layer can be deposited on the insulating layer 54 before the remaining thin film layers are deposited. In a subsequent process, the additional sacrificial layer is replaced with a metal layer, such as tungsten, titanium nitride lined tungsten, or tungsten nitride lined tungsten, to form the dummy metal layer 61, as shown in FIG. 4K.

[0141] In this embodiment, the memory structure 400 further includes a metal bracing in the Z direction provided by the metal pillars of the gate conductor 68. During fabrication to form the gate conductor layer, such as during the step shown in FIG. 4F, after removing the sacrificial material 82 and the liner 81, the cut cavity can be anisotropically etched to punch the bottom of the LWL shaft through the insulating layer 54. Subsequent deposition of the gate conductor layer 68 includes a portion 420 of the gate conductor formed in the insulating layer 54. By extending the gate conductor layer 68 into the insulating layer 54, the gate conductor layer 68 is anchored in the insulating layer, which provides additional support for the memory stacks formed on either side of the gate conductor. In some embodiments, the insulating layer 54 is a silicon oxycarbide (SiOC) layer.

[0142] In this description, the dimensions, thicknesses, or materials of the layers used to form the 3D NOR memory string of ferroelectric storage transistors are exemplary only and are not intended to be limiting. In other embodiments, other dimensions, thicknesses, or materials can be used to form the memory structures of the present invention.

[0143] The memory structures disclosed herein are described above as being formed by arranging junction-less ferroelectric storage transistors in a three-dimensional horizontal NOR memory string. In other embodiments, substantially the same principles or methods as those disclosed herein may be applied to form memory structures by arranging ferroelectric storage transistors in a three-dimensional vertical NOR memory string. Vertical NOR memory strings are described in co-pending and commonly assigned U.S. patent application Ser. No. 17 / 559,101, entitled "Vertical NOR Thin-film Transistor Strings and Fabrication Thereof," filed Dec. 22, 2021. In some embodiments, the storage transistors of the memory strings are arranged along a direction substantially perpendicular to the plane of the semiconductor substrate to form a vertical NOR memory string of junction-less ferroelectric storage transistors.

[0144] Figures 10A-10H illustrate another process for fabricating a memory structure including an HNOR memory string according to an embodiment of the present invention. Figures 10A-10H show a memory structure 50e constructed in a manner similar to that described above. Similar components in Figures 10A-10H and the above-described figures are given similar reference numerals and will not be described again.

[0145] Referring first to FIG. 10A, a memory structure 50e is shown including an interlayer sacrificial layer 70 and an active layer 51 formed successively on an insulating layer 54 on a semiconductor substrate 52 at an intermediate processing step after forming an LWL (or working) trench 80 in the memory structure. A channel layer 66 is conformally deposited on the sidewalls of the trench 80. For example, the channel layer 66 is a semiconductor oxide layer such as indium gallium zinc oxide (IGZO). A liner layer 81 is then deposited to cover the channel layer 66, and the remaining space in the trench 80 is then filled with a sacrificial material 82. In one embodiment, the liner layer 81 is a silicon nitride layer or an undoped amorphous silicon layer, and the sacrificial material 82 is silicon germanium or carbon. After the deposition step, excess material is removed from the top of the memory structure 50e, for example using chemical mechanical polishing (CMP). The resulting memory structure 50e is shown in FIG. 10A. In this figure, trench 80 is shown as having tapered sidewalls to more particularly illustrate actual fabrication process conditions where a trench opening may have smaller dimensions toward the bottom or depth of the opening in the semiconductor structure as a result of the high aspect ratio etch to form the trench opening.

[0146] In this embodiment, the memory structure 50e further includes a top interlayer sacrificial layer 70 and a dummy dielectric layer 610 formed on the top interlayer sacrificial layer 70. The top interlayer sacrificial layer 70 is then replaced with an interlayer insulating layer, such as an air gap insulating layer. The dummy dielectric layer 610 serves as a capping layer for the top interlayer sacrificial layer 70 during the replacement process. In particular, during a subsequent processing step, the top interlayer sacrificial layer 70 is removed, thereby forming an access opening to the backside of the channel layer 66. The channel layer 66 is selectively etched through the access opening. This isolates the channel layer 66 from the storage transistors of each layer. The dummy dielectric layer 610 is used to isolate the channel layer 66 from subsequently formed global word line contacts, as described in more detail below.

[0147] The memory structure 50e is then patterned to form local word line structures. Referring to FIG. 10A, a mask 620 (e.g., an amorphous hard mask) is applied to the memory structure 50e. The memory structure 50e has openings that expose regions for forming deep shafts used to isolate storage transistors formed along the memory strings (in the Y direction). In this embodiment, the mask 620 is configured in a line-and-space pattern, including lines that cover the regions to be protected and spaces or openings that expose the regions to be etched to form the deep shafts. The lines of the mask 620 have a dimension d2 and a spacing d1 in the Y direction to define a pitch d3 of global word line conductors formed above the memory array (not shown) to connect to subsequently formed local word line gate conductors. With the mask 620 defining the openings, the exposed sacrificial material 82 is removed, such as by a selective anisotropic etching process. The exposed liner layer 81 is then removed, such as by a selective wet etching process. The semiconductor oxide channel layer 66 in the areas defined by the openings (i.e., between the lines of the mask 620) is then removed, such as by selective anisotropic dry etching, atomic layer etching (ALE), or a controlled selective wet etching process. As a result, as shown in FIG. 10B, a shaft 88 is formed in the LWL trench between the areas where the LWL structures will subsequently be formed. In particular, the openings in the mask 620 overlap the mesas of the memory structure 50e, and the etching process is self-aligned to the edges of the capping layer 76, forming the shaft 88 only in the areas of the LWL trenches.

[0148] In this embodiment, after removing the sacrificial material 82 and the liner layer 81, the exposed channel material 66 is partially etched by a controlled etch such that the channel layer 66 is not etched through its entire thickness, but rather a much thinner remaining channel material remains along the exposed sidewalls in the shaft 88 as shown by the dotted circle 99 in view (i) of FIG. 10B. The channel layer 66 is partially etched in the shaft region, substantially reducing its effect as a parasitic channel conductor between adjacent LWL structures formed in the LWL trench. The partial etching of the channel layer 66 also prevents unintended lateral etching into the active stack of the active layer 51 in the plane of the vertical sidewalls of the LWL trench. By removing all or part of the channel material in the shaft 88, physical or electrical isolation (isolation) of the storage transistors formed in the Y direction along each memory string is achieved.

[0149] Referring to FIG. 10C, the shaft 88 is filled with a dielectric material to form a dielectric filled shaft 98. For example, the dielectric material can be a low dielectric constant oxide such as silicon oxide (SiO2). The dielectric filled shaft 98 serves as a dielectric isolation between adjacent local word lines or gate conductors formed in the LWL trenches. Storage transistors are formed in the spaces between adjacent dielectric filled shafts 98 along each active stack adjacent to the LWL trench (Y direction).

[0150] To form the local word line structure, the sacrificial material 82 and the liner layer 81 are selectively etched away from the regions between the dielectric fill shafts 98 to expose the channel layer 66 remaining on the sidewalls of the mesa. The fabrication process then proceeds to form the gate insulation layer of the storage transistor. Referring to FIG. 10D, a gate dielectric layer 67 is deposited on the channel layer 66 formed on the sidewalls of the cut cavity in the LWL trench. For example, the gate dielectric layer 67 can be deposited using atomic layer deposition. In this embodiment, the gate dielectric layer 67 is a ferroelectric polarization layer, such as a doped hafnium oxide layer. Optionally, an interface layer 65 may be formed between the channel layer 66 and the gate dielectric layer 67. For example, the interface layer 65 may be an ultra-thin silicon nitride (Si3N4) layer, a silicon oxynitride layer, or an aluminum oxide (Al2O3) layer. In some embodiments, an optional interface layer (not shown) similar to the interface layer 65 may be deposited on the gate dielectric layer 67.

[0151] Next, a gate conductor layer 68 is deposited in the remaining space of the cut cavity. For example, the gate conductor layer 68 is deposited on the gate dielectric layer 67. After the deposition step, excess material is removed from the top of the memory structure 50e, for example using chemical mechanical polishing (CMP). The resulting memory structure 50e is shown in FIG. 10D. Between each pair of dielectric-filled trenches 89, a conductive layer 68 provides a vertical local word line (LWL) that serves as a gate electrode for each vertically aligned storage transistor in the same active stack. In an embodiment of the present disclosure, the gate conductor layer 68 is a metal layer. In one embodiment, the gate conductor layer 68 can be a single conductive layer, such as a titanium nitride (TiN) layer or a tungsten nitride (WN) layer.

[0152] In this embodiment, the gate conductor 68 is formed using a two-step deposition process that deposits two types of conductive materials. For example, the gate conductor 68 can be formed by a first step (deposition step) of forming a metal capping layer 68a, such as a titanium nitride (TiN) layer or a tungsten nitride (WN) liner, on the ferroelectric polarization layer 67. The deposition of the metal capping layer 68a does not completely fill the trench. This process is followed by a second step of depositing a metal fill layer 68b, such as a tungsten layer, on the metal capping layer to fill the remaining space in each LWL trench. The metal fill layer 68b may be formed from other metals or conductive materials, such as molybdenum (Mo) or heavily doped n-type or p-type polysilicon.

[0153] During the deposition of the interfacial layer 65, the ferroelectric polarization layer 67, and the metal capping layer 68a, it is preferred that these depositions be performed without breaking vacuum as much as possible, or at least to minimize the time between depositions that may cause undesirable surface oxidation of exposed surfaces. Similarly, it is important that the deposition temperature, ambient chemicals present during deposition, and pre- and post-deposition annealing conditions are optimized to maximize orthorhombic crystallization of the ferroelectric gate dielectric layer.

[0154] The process of forming the memory structure 50e continues in the same manner as described above with reference to Figures 4F-4P. For example, with reference to Figure 10E, a mask is applied to form auxiliary trenches 84 between the already formed LWL trenches. Using the auxiliary trenches 84 thus formed, the fabrication process performs a metal replacement to remove the first sacrificial layer 72 and the second sacrificial layer 74 and replace them with the first conductive layer 62 and the second conductive layer 64, respectively.

[0155] After the metal replacement process, auxiliary trenches 84 are used to separate the channel layer 66 between each active layer 51 in a process called channel isolation. Referring to FIG. 10F, the fabrication process uses auxiliary trenches 84 to expose the interlayer sacrificial layer 70 from the side of the active stack, removing the interlayer sacrificial layer 70 and forming a cavity 180 where the interlayer sacrificial layer 70 was once located. The cavity 180 thus formed exposes a backside portion of the channel layer 66 between the multilayers 51 of the active stack. The auxiliary trenches 84 and the cavity are then used to remove the exposed portion of the channel layer 66 that spans two adjacent multilayers 51 in the active stack (in the Z direction). As a result, the channel layer 66 is separated in the Z direction for each multilayer 51.

[0156] 10G, in this embodiment, the exposed portions of the channel layer 66 between two adjacent (in the Z direction) multilayers 51 in the active stack are partially removed, leaving a thin portion of the channel material between the adjacent multilayers 51, as indicated by the dotted circle 181. The partially etched channel layer does not effectively function as a parasitic channel conductor, so that adjacent multilayers 51 are effectively isolated. Also, unintentional undercutting of the channel layer relative to the multilayer is avoided.

[0157] 10H, after the channel isolation process, the exposed surfaces of memory structure 50e may be passivated, such as by forming a thin dielectric liner layer 92. Liner layer 92 may be a silicon oxide, silicon nitride layer, or an aluminum oxide layer. Liner layer 92 serves to passivate or seal the exposed surfaces in the cavity and auxiliary trenches 84.

[0158] In some embodiments, the remaining cavity 93 of the memory structure 50e may be filled with a low-K dielectric material, such as silicon oxide. In the embodiment shown in FIG. 10H, the cavity 93 is left unfilled to form an air gap isolation. A dielectric layer 96 is formed on top of the auxiliary trenches 84, such as by non-conformal deposition of a dielectric layer. A cap oxide layer 606 may be formed over the completed memory structure 50e. In some embodiments, the cap oxide layer 606 may be a silicon oxide layer. In other embodiments, a two-level air gap isolation may be used, as shown in FIG. 4O-1.

[0159] The memory structure 50e thus formed includes storage transistors arranged in a NOR memory string in multiple planes. In particular, the storage transistor has substantially the same structure as the storage transistor 20 described in FIG. 1. Vias and interconnects are formed in and on the cap oxide layer 606 to provide interconnects between the storage transistors and control circuitry, such as CuA, formed in the semiconductor substrate 52. For example, a global word line metallization layer 614 is formed on the cap oxide layer 606 and is connected to a local word line 68 formed in the memory structure through a via 612 formed in the cap oxide layer 606. The memory structure 50e thus configured includes a ferroelectric storage transistor having desired ferroelectric properties in the ferroelectric polarization layer. In particular, crystallization of the ferroelectric polarization layer is achieved by using the gate conductor layer 68 as a capping layer that provides a desired tensile stress to promote beneficial crystallization of the ferroelectric polarization layer into a ferroelectric orthorhombic phase. In some embodiments, the crystallization is performed in situ during deposition of the gate conductor capping layer.

[0160] Note that the channel layer 66 for the top memory string in memory structure 50e is insulated by a top insulating layer formed below dummy dielectric layer 610. Vias 612 can be formed to contact the local word lines (gate conductor layer 668) without concern for possible electrical shorts to the channel layer. Each global word line 614 is connected to the local word lines through vias 612 and provides control signals to gate electrodes of storage transistors formed in multiple memory planes associated with the respective vertical local word lines.

[0161] In this detailed description, a process step described in one embodiment can be used in another embodiment even if not explicitly described in another embodiment. When referring to a method including two or more defined steps herein, the defined steps can be performed in any order or simultaneously, unless the context dictates or a specific indication is provided otherwise herein. Furthermore, unless the context dictates or an explicit indication is provided otherwise, the method can also include one or more other steps performed before any defined step, between two defined steps, or after all defined steps. For example, the formation of an auxiliary ("back array") trench may be performed partially or entirely after the formation of an operating ("LWL") trench or before the formation of an operating trench. Similarly, the formation of a precharge transistor may be performed before or after the formation of an operating trench.

[0162] In this detailed description, various embodiments or examples of the invention may be implemented in various forms, such as processes, devices, systems, and compositions of matter. A detailed description of one or more embodiments of the invention has been provided above, along with accompanying drawings illustrating the principles of the invention. Although the invention has been described in connection with such embodiments, the invention is not limited to any embodiment. Various changes and modifications are possible within the scope of the invention. The scope of the invention is limited only by the appended claims, and the invention encompasses various alternatives, modifications, and equivalents. Numerous specific details have been described herein in order to provide a thorough understanding of the invention. These details have been provided for illustrative purposes, and the invention may be practiced according to the claims without some or all of these specific details. For the sake of clarity, technical matters known in the art related to the invention have not been described in detail so as not to unnecessarily obscure the invention. The invention is defined by the appended claims.

Claims

1. A three-dimensional memory structure formed on a planar surface of a semiconductor substrate, comprising: a plurality of memory stacks arranged along a first direction generally parallel to the plane of the semiconductor substrate, each memory stack being separated from adjacent memory stacks along the first direction by trenches, each memory stack and each trench extending in a second direction orthogonal to the first direction and generally parallel to the plane of the semiconductor substrate, (i) each memory stack including at least one active layer, the active layer including a first conductive layer and a second conductive layer spaced apart from each other by a first insulating layer, and (ii) the trenches including a first type of trench and a second type of trench alternately arranged along the first direction; a plurality of gate electrode structures disposed within the first type of trench and spaced apart from one another in the second direction, the gate electrode structures extending in a third direction generally perpendicular to the plane of the semiconductor substrate, each gate electrode structure including: (i) a semiconductor oxide layer formed on a sidewall of the first type of trench and in contact with the first conductive layer and the second conductive layer, (ii) a ferroelectric layer disposed adjacent to the semiconductor oxide layer, and (iii) a gate conductor layer formed adjacent to the ferroelectric layer; an insulating material disposed within the second type of trenches; each said active layer in said memory stack forms a plurality of thin-film ferroelectric memory transistors arranged as a NOR memory string; each said thin film ferroelectric memory transistor being formed at an intersection of said active layer and said gate electrode structure; The three-dimensional memory structure, wherein the plurality of memory stacks form a plurality of NOR memory strings within the first type of trenches.

2. 2. The three-dimensional memory structure of claim 1, each of the thin-film ferroelectric memory transistors of each of the NOR memory strings shares the first conductive layer that functions as a common drain line and the second conductive layer that functions as a common source line; the semiconductor oxide layer located between and in contact with the first conductive layer and the second conductive layer serves as a junctionless channel region for each of the thin-film ferroelectric memory transistors of each of the NOR memory strings.

3. 3. The three-dimensional memory structure of claim 2, A three dimensional memory structure, wherein the common source line is electrically floating.

4. 3. The three-dimensional memory structure of claim 2, each of the memory stacks includes a plurality of active layers stacked along the third direction and separated from one another by a second insulating layer; The three-dimensional memory structure, wherein the plurality of memory stacks form a plurality of stacks of the respective NOR memory strings of the thin-film ferroelectric memory transistors within the first type of trenches.

5. 5. The three-dimensional memory structure of claim 4, a first NOR memory string having a junctionless channel region of the thin-film ferroelectric memory transistor of a second NOR memory string adjacent to the first NOR memory string in the third direction by the second insulating layer, the first NOR memory string having a junctionless channel region of the thin-film ferroelectric memory transistor of a first NOR memory string in the memory stack of the NOR memory strings being separated from the junctionless channel region of the thin-film ferroelectric memory transistor of a second NOR memory string adjacent to the first NOR memory string in the third direction by the second insulating layer.

6. 6. The three-dimensional memory structure of claim 5, the semiconductor oxide layer is removed from a region between two of the active layers adjacent to each other in the third direction within the memory stack of the NOR memory string.

7. 6. The three-dimensional memory structure of claim 5, a third direction, a third direction of the active layer, and a fourth direction of the active layer.

8. 6. The three-dimensional memory structure of claim 5, The second insulating layer includes an air gap cavity.

9. 2. The three-dimensional memory structure of claim 1, the insulating material disposed in the trenches of the second type comprises a silicon oxide layer.

10. 2. The three-dimensional memory structure of claim 1, The three-dimensional memory structure, wherein the ferroelectric layer comprises a doped hafnium oxide layer.

11. 2. The three-dimensional memory structure of claim 1, The three-dimensional memory structure further comprising an interfacial layer formed between the semiconductor oxide layer and the ferroelectric layer.

12. 2. The three-dimensional memory structure of claim 1, The three-dimensional memory structure, wherein the semiconductor oxide layer comprises one of an indium gallium zinc oxide (IGZO) layer, an indium zinc oxide (IZO) layer, an indium tungsten oxide (IWO) layer, and an indium tin oxide (ITO) layer.

13. 13. The three-dimensional memory structure of claim 12, the semiconductor oxide layer includes a first semiconductor oxide layer and a second semiconductor oxide layer; The first semiconductor oxide layer is disposed in contact with the first conductive layer and the second conductive layer, providing a contact resistance to the first conductive layer and the second conductive layer that is lower than a contact resistance of the second semiconductor oxide layer.

14. 2. The three-dimensional memory structure of claim 1, The three dimensional memory structure of claim 1 , wherein the first conductive layer and the second conductive layer comprise metal layers.

15. 2. The three-dimensional memory structure of claim 1, The three-dimensional memory structure, wherein the first insulating layer comprises a silicon oxide layer.

16. 2. The three-dimensional memory structure of claim 1, A three-dimensional memory structure, wherein a channel length of each of the memory transistors is a function of a thickness of the first insulating layer in the third direction.

17. 17. The three-dimensional memory structure of claim 16, The three-dimensional memory structure, wherein the thickness of the first insulating layer in the third direction is in the range of 5 to 10 nm.

18. 2. The three-dimensional memory structure of claim 1, a first group of the thin-film ferroelectric memory transistors in each of the NOR memory strings are designated as precharge transistors; the precharge transistor is activated during a precharge operation to electrically connect the first conductive layer and the second conductive layer in each of the NOR memory strings to each other and make a voltage on the second conductive layer equal to a voltage on the first conductive layer.

19. 20. The three-dimensional memory structure of claim 18, A three dimensional memory structure wherein, in each said NOR memory string, the first group of said thin film ferroelectric memory transistors are selected substantially randomly to act as precharge transistors for said NOR memory string.

20. 20. The three-dimensional memory structure of claim 18, A three dimensional memory structure, wherein in each of the NOR memory strings, each of the memory transistors of the first group is selected in sequence to operate as a precharge transistor for a predetermined number of precharge operations or for a predetermined period of time.

21. 20. The three-dimensional memory structure of claim 18, determining a health state of the first group of thin-film ferroelectric memory transistors selected to operate as precharge transistors in each of the NOR memory strings, and if the memory transistor is determined to be faulty, retiring the memory transistor in response to the determination and selecting another memory transistor in the first group to operate as the precharge transistor for the NOR memory string.

22. 2. The three-dimensional memory structure of claim 1, each of the memory transistors in each of the NOR memory strings has a first transistor width; each of the NOR memory strings further includes a second group of memory transistors having a second transistor width greater than the first transistor width; the memory transistors in the second group are designated as precharge transistors; the precharge transistor is activated during a precharge operation to electrically connect the first conductive layer and the second conductive layer in each of the NOR memory strings to each other and make a voltage on the second conductive layer equal to a voltage on the first conductive layer.

23. 2. The three-dimensional memory structure of claim 1, a plurality of non-memory transistors formed within each of the NOR memory strings; the non-memory transistor is designated as a precharge transistor; the precharge transistor is activated during a precharge operation to electrically connect the first conductive layer and the second conductive layer in each of the NOR memory strings to each other and make a voltage on the second conductive layer equal to a voltage on the first conductive layer.

24. 24. The three-dimensional memory structure of claim 23, a first NOR memory string having a first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer being a first gate dielectric layer and the second gate dielectric layer being a second gate dielectric layer;

25. 3. The three-dimensional memory structure of claim 2, A three-dimensional memory structure, wherein for each of the memory transistors in the NOR memory string, the common drain line and the common source line are biased to substantially the same voltage during a program or erase operation of the thin-film ferroelectric memory transistor.

26. 2. The three-dimensional memory structure of claim 1, the first insulating layer includes a first dielectric layer having a first dielectric constant formed adjacent to the first conductive layer, and a second dielectric layer having a second dielectric constant less than the first dielectric constant formed adjacent to the second conductive layer.

27. 2. The three-dimensional memory structure of claim 1, the first insulating layer includes a first dielectric layer having a first dielectric constant formed adjacent to the first conductive layer, a second dielectric layer having a second dielectric constant formed adjacent to the second conductive layer, and a third dielectric layer formed between the first dielectric layer and the second dielectric layer, the third dielectric constant being less than the first dielectric constant and the second dielectric constant.

28. 2. The three-dimensional memory structure of claim 1, The three-dimensional memory structure, wherein the first insulating layer comprises a dielectric layer having a dielectric constant greater than a dielectric constant of silicon oxide.

29. 2. The three-dimensional memory structure of claim 1, the thin-film ferroelectric memory transistor having a front gate electrode formed by the gate conductor layer and an electrically floating back gate electrode formed by a back gate layer disposed on the first insulating layer;

30. 30. The three-dimensional memory structure of claim 29, the electrically floating back gate electrode in each of the memory transistors has a voltage controlled by capacitive coupling to a voltage applied to the first conductive layer, the second conductive layer, and a portion of the semiconductor oxide layer.

31. 30. The three-dimensional memory structure of claim 29, the first insulating layer includes a first dielectric layer formed adjacent to the first conductive layer, a second dielectric layer formed adjacent to the second conductive layer, and a third layer formed between the first dielectric layer and the second dielectric layer and serving as a back gate layer insulated from the first conductive layer and the second conductive layer; the third layer cooperates with a portion of the semiconductor oxide layer to form the electrically floating back gate electrode for each of the memory transistors.

32. 32. The three-dimensional memory structure of claim 31, the first conductive layer and the second conductive layer are spaced apart in the third direction by a first distance, the first distance being a channel length of the thin-film ferroelectric memory transistor; A three-dimensional memory structure, wherein the thickness of the third layer in the third direction is equal to a portion of or approximately the entire length of the channel length.

33. 32. The three-dimensional memory structure of claim 31, The three dimensional memory structure, wherein each of the first dielectric layer and the second dielectric layer is formed from a material selected from silicon dioxide, silicon nitride, hafnium oxide, or a high dielectric constant material.

34. 32. The three-dimensional memory structure of claim 31, The three-dimensional memory structure, wherein the third layer is formed from a material selected from a semiconductor, a low resistance material, or a metallic material.

35. 32. The three-dimensional memory structure of claim 31, The three-dimensional memory structure, wherein the third layer is formed from a material selected from undoped silicon, P-type or N-type doped silicon, undoped polysilicon, P-type or N-type doped polysilicon, silicon germanium, titanium nitride, tungsten, or molybdenum.

36. 30. The three-dimensional memory structure of claim 29, the first insulating layer includes a dielectric liner layer formed adjacent to the first conductive layer, the semiconductor oxide layer, and the second conductive layer, and a third layer as the back gate layer surrounded by the dielectric liner layer and insulated from the first conductive layer and the second conductive layer; the third layer cooperates with a portion of the semiconductor oxide layer to form the electrically floating back gate electrode for each of the memory transistors.

37. 37. The three-dimensional memory structure of claim 36, the first conductive layer and the second conductive layer are spaced apart in the third direction by a first distance, the first distance being a channel length of the thin-film ferroelectric memory transistor; A three-dimensional memory structure, wherein the third layer has a thickness in the third direction equal to approximately the entire length of the channel.

38. 37. The three-dimensional memory structure of claim 36, The three-dimensional memory structure, wherein the dielectric liner layer is formed from a material selected from silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or a high dielectric constant material.

39. 37. The three-dimensional memory structure of claim 36, The three-dimensional memory structure, wherein the third layer is formed from a material selected from a semiconductor, a low resistance material, or a metallic material.

40. 37. The three-dimensional memory structure of claim 36, The three-dimensional memory structure, wherein the third layer is formed from a material selected from undoped silicon, P-type or N-type doped silicon, undoped polysilicon, P-type or N-type doped polysilicon, silicon germanium, titanium nitride, tungsten, or molybdenum.

41. 30. The three-dimensional memory structure of claim 29, a first conductive layer, together with the second conductive layer and the back gate layer, acting substantially as the back gate electrode of each of the thin film ferroelectric memory transistors;

42. 42. The three-dimensional memory structure of claim 41, The three-dimensional memory structure, wherein for each said thin-film ferroelectric memory transistor, a region of said ferroelectric layer between said front-gate electrode and said back-gate electrode is a region of maximum polarization for the programmed and erased states of said thin-film ferroelectric memory transistor.

43. 2. The three-dimensional memory structure of claim 1, A three-dimensional memory structure wherein support circuitry for supporting memory operations of said thin-film ferroelectric memory transistors is formed in said plane of said semiconductor substrate substantially beneath said memory stacks.

44. 44. The three-dimensional memory structure of claim 43, comprising: a plurality of connectors for providing data path signals from the support circuitry to support memory operations of each of the NOR memory strings; the connector is connected to a corresponding connector of a memory controller circuit formed on a second semiconductor substrate separate from the semiconductor substrate on which the three-dimensional memory structure is formed; The three dimensional memory structure, wherein the memory controller circuitry includes memory control circuitry that accesses and operates the thin film ferroelectric memory transistors in each of the NOR memory strings in the three dimensional memory structure.

45. 45. The three-dimensional memory structure of claim 44, comprising: the second semiconductor substrate includes a logic integrated circuit including a processor core; The memory controller circuit is formed in a portion of the second semiconductor substrate.

46. 3. The three-dimensional memory structure of claim 2, a gate conductor layer in each of the gate electrode structures activates a first of the thin-film ferroelectric memory transistors and a second of the thin-film ferroelectric memory transistors in each of the active layers in a first NOR memory string and a second NOR memory string adjacent to the gate electrode structure in the NOR memory strings.

47. 47. The three-dimensional memory structure of claim 46, comprising: a gate conductor layer biased to a first potential to program or erase the first of the thin-film ferroelectric memory transistors, an inhibit voltage is applied to the common drain line associated with the second of the thin-film ferroelectric memory transistors such that the second of the thin-film ferroelectric memory transistors is not programmed or erased.

48. 3. The three-dimensional memory structure of claim 2, The three-dimensional memory structure, wherein the gate conductor layer includes a first type metal layer formed on the ferroelectric layer.

49. 49. The three-dimensional memory structure of claim 48, comprising: The three-dimensional memory structure, wherein the gate conductor layer comprises a conductive layer selected from titanium nitride or tungsten nitride.

50. 3. The three-dimensional memory structure of claim 2, The gate conductor layer includes a first metal layer formed on the ferroelectric layer and a second metal layer formed on the first metal layer.

51. 51. The three-dimensional memory structure of claim 50, the first metal layer comprises a metal layer selected from titanium nitride or tungsten nitride; The three-dimensional memory structure, wherein the second metal layer comprises a metal layer selected from tungsten or molybdenum.

52. 6. The three-dimensional memory structure of claim 5, A three-dimensional memory structure, wherein in the first type of trenches, the semiconductor oxide layer is removed from a region between two of the gate electrode structures that are adjacent to each other in the second direction.

53. 6. The three-dimensional memory structure of claim 5, Within the first type of trench, a portion of the semiconductor oxide layer is removed from a region between two of the gate electrode structures adjacent to each other in the second direction; At least a portion of the semiconductor oxide layer is left in a region between two adjacent gate electrode structures.

54. 2. The three-dimensional memory structure of claim 1, the three-dimensional memory structure, wherein each of the plurality of memory stacks in each of the NOR memory strings further includes a third conductive layer formed between a bottom active layer and the semiconductor substrate.

55. 2. The three-dimensional memory structure of claim 1, A three-dimensional memory structure, wherein for each of the gate electrode structures, the gate conductor layer extends into the semiconductor substrate.

56. 2. The three-dimensional memory structure of claim 1, the semiconductor oxide layer is a continuous layer that continues in the second direction on the sidewalls of the first type of trenches.

57. 1. A method suitable for use in manufacturing a memory structure comprising storage transistors of a NOR memory string on a planar surface of a semiconductor substrate, comprising: depositing alternating multilayers and interlayer sacrificial layers on the planar surface of the semiconductor substrate, the multilayers including a first sacrificial layer, a second sacrificial layer, and a first insulating layer interposed between the first sacrificial layer and the second sacrificial layer; forming a plurality of first trenches in the multilayer and the interlayer sacrificial layer, the first trenches having (i) a depth extending along a first direction generally orthogonal to the plane of the semiconductor substrate, (ii) a length extending along a second direction generally parallel to the plane of the semiconductor substrate, and (iii) a width extending along a third direction generally orthogonal to the first direction and the second direction, the length of the first trenches being substantially greater than the width of the first trenches; forming a semiconductor oxide layer on sidewalls of the first trench; forming a dielectric filled shaft in the first trench; forming a local wordline structure in the first trench, the local wordline structure being formed between adjacent pairs of the dielectric filled shafts, the local wordline structure including: (i) a ferroelectric layer formed on a sidewall of an opening between a pair of adjacent pairs of the dielectric filled shafts; and (ii) a gate conductor layer formed in the opening in the ferroelectric layer; forming a plurality of second trenches in the multilayer and the interlayer sacrificial layer, the second trenches having substantially the same depth, length and width as the first trenches, the first trenches and the second trenches dividing the multilayer into a plurality of stacks of multilayer strips, the stacks being separated from adjacent stacks by one of the first trenches and the second trenches; replacing the first sacrificial layer and the second sacrificial layer with a first conductive layer and a second conductive layer using access through the second trench; removing the interlayer sacrificial layer through the second trench to expose a portion of the semiconductor oxide layer formed on the sidewall of the first trench; and removing at least a portion of the exposed portion of the semiconductor oxide layer with access through the second trench.

58. 58. The method of claim 57, The method further includes forming a first dielectric liner layer over an exposed surface of the memory structure including a cavity exposed by removing the interlayer sacrificial layer and a cavity exposed by the second trench.

59. 58. The method of claim 57, filling the first trench with a sacrificial fill material after forming the semiconductor oxide layer on the sidewalls of the first trench; defining a plurality of openings along the first trench; removing the sacrificial filler through the opening to remove at least a portion of the semiconductor oxide layer in the first trench; filling the opening into the first trench with a dielectric layer to form a dielectric filled shaft.

60. 60. The method of claim 59, The step of forming the local word line structure in the first trench comprises: removing the sacrificial filler from the first trench between the dielectric filled shafts; depositing a ferroelectric layer contacting the semiconductor oxide layer on the sidewalls of the first trench; and depositing a gate conductor layer into the cut cavities between adjacent said dielectric filled shafts to form said local word line structures.

61. 58. The method of claim 57, The method further comprising forming an interfacial layer between the semiconductor oxide layer and the ferroelectric layer.

62. 62. The method of claim 61 , The steps of depositing the ferroelectric layer and forming the interface layer include: depositing the interfacial layer and the ferroelectric layer on the sidewalls of the first trench using atomic layer deposition.

63. 58. The method of claim 57, A method comprising subjecting the memory structure to one or more thermal annealing processes, wherein when the thermal annealing process is performed at a temperature above 550° C., the thermal annealing process is performed by a pulse anneal having a duration of less than 10 minutes.

64. 58. The method of claim 57, The method further comprising, after removing the exposed portions of the semiconductor oxide layer, removing the ferroelectric layer exposed by the exposed portions of the semiconductor oxide layer.

65. 58. The method of claim 57, the first insulating layer of the multi-layer includes a third sacrificial layer between the first sacrificial layer and the second sacrificial layer; The method comprises: after forming the second trench in the multilayer and the interlayer sacrificial layer, removing the third sacrificial layer using access through the second trench to form a cut cavity between the first sacrificial layer and the second sacrificial layer or between the first conductive layer and the second conductive layer; forming a second dielectric liner layer on an exposed surface of the memory structure including the cut cavity exposed by removing the third sacrificial layer and the sidewalls of the second trench; depositing a back gate layer over the exposed surface of the memory structure including the cut cavity lined with the second dielectric liner layer and the sidewalls of the second trench, the back gate layer filling the cut cavity and being surrounded by the second dielectric liner layer; removing excess deposition material from the sidewalls of the second trench.

66. 66. The method of claim 65, The method of claim 1, wherein the step of removing the third sacrificial layer with access through the second trench occurs after replacing the first sacrificial layer and the second sacrificial layer with the first conductive layer and the second conductive layer.

67. 66. The method of claim 65, The method of claim 1, wherein the second dielectric liner layer is formed from a material selected from silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or a high dielectric constant material.

68. 66. The method of claim 65, The method of claim 1, wherein the back gate layer is formed from a material selected from a semiconductor, a low resistance material, or a metallic material.

69. 66. The method of claim 65, The method of claim 1, wherein the back gate layer is formed from a material selected from undoped silicon, P-type or N-type doped silicon, undoped polysilicon, P-type or N-type doped polysilicon, silicon germanium, titanium nitride, tungsten, or molybdenum.

70. 58. The method of claim 57, The step of forming the local word line structure in the first trench comprises: depositing the ferroelectric layer on the sidewalls of the opening between a pair of adjacent dielectric-filled shafts; depositing a gate conductor layer in the opening surrounded by the ferroelectric layer, the gate conductor layer including a first metal layer that is a capping layer for the ferroelectric layer to induce crystallization of the ferroelectric layer into a desired ferroelectric crystallization phase.

71. 71. The method of claim 70, The method of claim 1, wherein the first metal layer comprises a metal layer selected from titanium nitride or tungsten nitride.

72. 71. The method of claim 70, The step of depositing the gate conductor layer comprises: depositing a first metal layer as a capping layer for the ferroelectric layer; and depositing a second metal layer over the first metal layer.

73. 73. The method of claim 72, comprising: the first metal layer comprises a metal layer selected from titanium nitride or tungsten nitride; The method of claim 1, wherein the second metal layer comprises a metal layer selected from tungsten or molybdenum.

74. 58. The method of claim 57, the step of removing at least a portion of the exposed portion of the semiconductor oxide layer comprises completely removing the exposed portion of the semiconductor oxide layer with access through the second trench.

75. 58. The method of claim 57, The step of forming the dielectric filled shaft in the first trench comprises: removing at least a portion of the semiconductor oxide layer formed on the sidewalls of the first trench within the dielectric filled shaft; depositing a dielectric layer within the dielectric filled shaft to form a dielectric filled shaft.

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