Semiconductor package having creep extension structure - Patents.com

Abstract

Semiconductor packages and, in particular, semiconductor packages having increased power handling capabilities are disclosed. The semiconductor package may include a lead frame structure and a corresponding housing incorporating a semiconductor die. To promote increased current and voltage capabilities, an exemplary semiconductor package includes one or more arrangements of creep extension structures, lead frame structures that may include integral thermal pads, additional thermal elements, and combinations thereof. The creep extension structures may be disposed as part of the top side of the semiconductor package along with the thermal pads of the lead frame structure and the additional thermal elements. The creep extension structures may also be disposed as part of the top side and along one or more peripheral edges of the semiconductor package to promote further increased power handling.

Description

[Technical field]

[0001] This application claims priority to U.S. Patent Application No. 17 / 670,174, filed February 11, 2022, the disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor packages, and more particularly, to semiconductor packages having increased power handling capabilities and / or smart sensing capabilities. [Background technology]

[0003] Semiconductor devices such as transistors and diodes are ubiquitous in modern electronic devices. Wide bandgap semiconductor material systems such as gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC) are increasingly being utilized in semiconductor devices to push the boundaries of device performance in areas such as switching speed, power handling capability, and thermal conductivity. Exemplary power semiconductor dies include metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), Schottky barrier diodes, PiN diodes, thyristors, and high electron mobility transistors (HEMTs).

[0004] With regard to the packaging of such power semiconductor dies, the packaging technology plays an important role in their performance. For example, the packaging of a power semiconductor device may limit the ability of the semiconductor die in the package to dissipate heat, to conduct current, and even to switch at a certain speed (e.g., due to stray inductance). In this regard, the packaging technology may become a bottleneck in the performance of packaged power semiconductor devices having high-performance power semiconductor dies, including semiconductor dies based on silicon carbide material systems, among others.

[0005] Technology continues to seek improvements in packaging for power semiconductor devices that can overcome the challenges associated with conventional semiconductor devices. Summary of the Invention [Means for solving the problem]

[0006] The present disclosure relates to semiconductor packages, and in particular to semiconductor packages having increased power handling capabilities. The semiconductor package may include a lead frame structure and a corresponding housing incorporating a semiconductor die. To enhance the increased current and voltage capabilities, an exemplary semiconductor package may include one or more arrangements of creep extension structures, a lead frame structure that may include an integral thermal pad, additional thermal elements, and combinations thereof. The creep extension structures may be provided as part of the top side of the semiconductor package, along with the thermal pad of the lead frame structure and additional thermal elements. The creep extension structures may also be provided as part of the top side and along one or more peripheral edges of the semiconductor package to enhance further increased power handling.

[0007] In one aspect, a semiconductor package comprises: a semiconductor die; a housing for the semiconductor die, the housing including a first side, a second side, and a creepage extension structure that is a part of the first side; and a first lead electrically connected to the semiconductor die, the first lead including a thermal pad and at least one pin extending away from the thermal pad, the thermal pad disposed adjacent the creepage extension structure on the first side. In certain embodiments, the first side is a top side of the housing and the second side is a bottom side of the housing that forms a mounting surface of the housing. The semiconductor device may further comprise a second lead electrically connected to the semiconductor die, the creepage extension structure being disposed between the thermal pad and the second lead.

[0008] In certain embodiments, the semiconductor die is a metal-oxide-semiconductor field effect transistor (MOSFET), the first lead is electrically coupled to a drain of the MOSFET, and the second lead is electrically coupled to a source of the MOSFET. The semiconductor package may further include a third lead electrically coupled to a gate of the MOSFET, and the creep extension structure is disposed between the thermal pad and the third lead. The semiconductor package may further include a fourth lead, the creep extension structure is disposed between the thermal pad and the fourth lead, and the fourth lead is electrically coupled to a current sensor or a temperature sensor of the MOSFET. In certain embodiments, the MOSFET is a silicon carbide (SiC) based MOSFET. In certain embodiments, the semiconductor die is a Schottky diode, the first lead is electrically coupled to a first contact of the Schottky diode, and the second lead is electrically coupled to a second contact of the Schottky diode.

[0009] In certain embodiments, the housing forms a protrusion such that the first side includes a first width and a second width narrower than the first width, the thermal pad is disposed within the first width, and the creep extension structure is disposed to extend from the first width to the second width. In certain embodiments, the creep extension structure includes one or more trenches extending to a first peripheral edge of the housing. In certain embodiments, the one or more trenches are bounded laterally on the first side of the housing by an outer surface of the housing. In certain embodiments, the one or more trenches are disposed to extend along one or more peripheral edges of the housing. In certain embodiments, the one or more trenches are disposed to extend across an entire width of the first side as measured between two opposing peripheral edges of the housing. The semiconductor package may further include an electrically insulating plate disposed on the thermal pad. In certain embodiments, the electrically insulating plate includes a direct bond copper plate. In certain embodiments, the thermal pad is integral with the first side.

[0010] In another aspect, a semiconductor package includes: a semiconductor die; a first lead in electrical communication with the semiconductor die; a second lead in electrical communication with the semiconductor die; and a housing for the semiconductor die, the housing comprising: a first side, a second side, a plurality of peripheral edges disposed between the first side and the second side; and a creep extension structure that is a portion of the first peripheral edge of the plurality of peripheral edges. In certain embodiments, the creep extension structure includes one or more trenches that extend to the first peripheral edge. In certain embodiments, the creep extension structure is further a portion of a second peripheral edge of the plurality of peripheral edges, the second peripheral edge facing the first peripheral edge. In certain embodiments, the creep extension structure is further a portion of the first side of the housing. In certain embodiments, the creep extension structure includes at least one trench that extends to the first peripheral edge and to the first side of the housing. In certain embodiments, the first lead comprises a thermal pad and at least one pin extending away from the thermal pad, the thermal pad being disposed adjacent the creepage extension structure on the first side. The semiconductor package may further comprise an electrically insulating plate disposed on the thermal pad. In certain embodiments, the electrically insulating plate comprises a direct-connect copper plate. In certain embodiments, the semiconductor die is a metal-oxide-semiconductor field effect transistor (MOSFET), the first lead is electrically coupled to a drain of the MOSFET, and the second lead is electrically coupled to a source of the MOSFET. In certain embodiments, the semiconductor die is a Schottky diode, the first lead is electrically coupled to a first contact of the Schottky diode, and the second lead is electrically coupled to a second contact of the Schottky diode.

[0011] In another aspect, a semiconductor package comprises: a semiconductor die; a first lead in electrical communication with the semiconductor die; a second lead in electrical communication with the semiconductor die; and a housing for the semiconductor die, the housing including a first side, a second side, and a creep extension structure that is a part of the housing, the creep extension structure forming a number of trenches that extend into the housing to provide a creep distance between the first lead and the second lead that is in the range of 12 millimeters (mm) to 20 mm. In certain embodiments, the number of trenches is at least one. In certain embodiments, the number of trenches is six or less. In certain embodiments, the creep extension structure is a part of the first side of the housing. In certain embodiments, the creep extension structure is a part of one or more peripheral edges of the housing. In certain embodiments, the creep extension structure is a part of the second side of the housing.

[0012] In another aspect, any of the above aspects, individually or together, and / or various other aspects and features as described herein may be combined to further advantage. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements, unless otherwise indicated herein to the contrary.

[0013] Those skilled in the art will appreciate the scope of the present disclosure, and realize additional aspects of the present disclosure, after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawing figures.

[0014] The accompanying drawing figures, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure. [Brief description of the drawings]

[0015] [Figure 1]1 is a top perspective view of a semiconductor package including a housing having a creep extension structure formed herein in accordance with the principles of the present disclosure; [Diagram 2] 2 is a bottom perspective view of the semiconductor package of FIG. 1. [Diagram 3] 2 is another bottom perspective view of the semiconductor package of FIG. 1 with the housing shown transparent for illustrative purposes. [Figure 4] 4 is a cross-sectional perspective view of the semiconductor package taken along section line 4-4 of FIG. 1. [Diagram 5] 2 is a top view of the semiconductor package of FIG. 1 illustrating the relative dimensions of the creepage extension structures along a first side of the housing. [Figure 6] 2 is a top perspective view of a semiconductor package similar to that of FIG. 1 and including an array of creepage extension structures extending beyond a first side of a housing. [Figure 7] FIG. 7 is a bottom perspective view of the semiconductor package of FIG. [Figure 8] 7 is a bottom perspective view of the semiconductor package of FIG. 6 with the housing shown transparent for purposes of illustration. [Figure 9] 9 is a cross-sectional perspective view of the semiconductor package taken along section line 9-9 of FIG. 6. [Figure 10] 7 is a top view of the semiconductor package of FIG. 6 illustrating the relative dimensions of the creepage extension structures along a first side of the housing. [Figure 11] FIG. 7 is a top perspective view of a semiconductor package similar to that of FIG. 6 and further including an electrically insulating plate disposed on the thermal pad of the first lead. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The embodiments described below provide the necessary information to enable one skilled in the art to practice the embodiments and to illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, one skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not specifically addressed herein. It is to be understood that these concepts and applications fall within the scope of the disclosure and the appended claims.

[0017] Although the terms first, second, etc. are used herein to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0018] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it will be understood that it may be directly on or extending directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements. Similarly, when an element, such as a layer, region, or substrate, is referred to as being "over" or extending "over" another element, it will be understood that it may be directly over or extending directly over the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "over" or extending "directly over" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or directly coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0019] Relationship terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It will be understood that these terms, and those discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used herein, the singular forms "a," "an," and "the" include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0021] Unless otherwise specified, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted to have a meaning consistent with their meaning in the context of this specification and in the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0022] The embodiments are described herein with reference to schematic diagrams of the disclosed embodiments. As such, actual dimensions of layers and elements may vary and variations from the shapes of the figures are expected, for example, as a result of manufacturing techniques and / or tolerances. For example, a region shown or described as a square or rectangle may have a rounded or curved profile, and a region shown as a straight line may have some irregularity. As such, the regions shown in the figures are schematic, and the shapes are not intended to illustrate the precise shape of the regions of the device, and are not intended to limit the scope of the disclosure. In addition, the size of structures or regions may be exaggerated relative to other structures or regions for illustration purposes, and thus are provided to illustrate the general structure of the subject matter, and may or may not be drawn to scale. Common elements between the figures may be indicated herein with common element numbers and may not be described again thereafter.

[0023] Discrete semiconductor packages containing semiconductor dies such as metal-oxide-semiconductor field effect transistors (MOSFETs) or Schottky diodes have been developed. Such semiconductor packages with MOSFETs may be utilized in a variety of applications to enable higher switching frequencies with associated loss reduction, higher blocking voltages, and improved avalanche capabilities. Exemplary applications include high performance industrial power supplies, server / telecom power, electric vehicle charging systems, energy storage systems, uninterruptible power supplies, high voltage DC / DC converters, and battery management systems. Discrete semiconductor packages with Schottky diodes may be utilized in many of the same high performance power applications described above for MOSFETs, sometimes in systems that also include separate power packages of MOSFETs. As discussed above, packaging technology for semiconductor devices plays a significant role in determining their performance. In particular, packaging for semiconductor devices is often the limiting factor for the semiconductor die within the package to dissipate heat, conduct current, and even switch at a particular speed.

[0024] The present disclosure relates to semiconductor packages, and in particular to semiconductor packages with increased power handling capabilities. In certain aspects, an exemplary semiconductor package may include a power semiconductor package including a power semiconductor die. The semiconductor package may include a lead frame structure and a corresponding housing incorporating the semiconductor die. To enhance the increased current and voltage capabilities, the exemplary semiconductor package may include one or more arrangements of creep extension structures, lead frame structures that may include integral thermal pads, additional thermal elements, and combinations thereof. The creep extension structures may be included anywhere as part of the semiconductor package. For example, the creep extension structures may be part of the top side of the semiconductor package along with the thermal pads and additional thermal elements of the lead frame structure. The creep extension structures may also be located as part of the top side and along or as part of one or more peripheral edges of the semiconductor package to enhance further increased power handling.

[0025] FIG. 1 is a top perspective view of a semiconductor package 10 including a housing 12 having a creepage extension structure 14 formed therein. The semiconductor package 10 may be arranged to accommodate and provide external electrical connections to a semiconductor die, such as a MOSFET or Schottky diode, disposed within the housing 12. The semiconductor package 10 may be arranged as a surface mount technology (SMT) package such that a first side 12', or top side, of the housing 12 faces an external surface, such as a printed circuit board (PCB), upon which the semiconductor package 10 is mounted. Thus, a second side 12" of the housing 12, or bottom side opposite the top side, forms a mounting surface for the semiconductor package 10 to be mounted to an external surface. A plurality of peripheral edges 12 E1 From 12 E4The housing 12 may be disposed between the first side 12' and the second side 12". The housing 12 may be formed by a molding process such that the housing 12 is disposed around a portion of the first lead 16 and the one or more second leads 18. In certain embodiments, the housing 12 may comprise a material capable of high temperature operation, such as a temperature of about 200° C. Exemplary materials for the housing include an epoxy material or an epoxy mold compound (EMC).

[0026] External electrical connections for the semiconductor package 10 and the semiconductor die contained therein may be provided by a lead frame structure including a first lead 16 and one or more second leads 18. In certain embodiments, the first lead 16 is coupled to a thermal pad 16. TP A plurality of integral pins 16 extending away from P Thermal pad 16 integrally formed with TP Includes .Pin 16 P 16. As shown, the thermal pad 16 may aid in flexibility in making an external electrical connection for the first lead 16. TP The thermal pad 16 is disposed on or integral with the first side 12' of the housing 12. TP The pins 16 can provide a heat dissipation path away from the second side 12″ or mounting surface of the housing 12. Thus, heat generated by the semiconductor die can be directed away from the mounting surface of the semiconductor package 10, thereby reducing heat concentration. P Includes 16 heat pads TP 1 along the first side 12' of the housing 12 and along the peripheral edge 12 before being bent to extend downward. E3 In this manner, when the semiconductor package 10 is mounted on an exterior surface, the pins 16 P may be electrically coupled to one or more electrical connections on the exterior surface.

[0027] The creep extension structure 14 is formed as part of the first side 12' of the housing 12 at a location between a portion of the first lead 16 and one or more second leads 18. In this manner, the creep extension structure 14 may be configured to improve voltage isolation between the first lead 16 and the second lead 18. Voltage isolation becomes increasingly challenging in semiconductor packages, especially as package sizes continue to shrink. The creep extension structure 14 effectively increases the surface distance, or creep distance, along the housing 12 between the first lead 16 and the second lead 18 without spacing the first lead 16 and the second lead 18 further apart, thereby allowing for a smaller overall footprint of the semiconductor package 10. In certain embodiments, the creep distance may be provided within a range of 5 millimeters (mm) to 20 mm, or within a range of 10 mm to 20 mm, or within a range of 12 mm to 20 mm, or within a range of 12 mm to 15 mm, depending on the power handling capability of the semiconductor package 10. As shown, the creep extension structure 14 may be formed as a number of slots or trenches 14' that extend into the housing 12 from the first side 12'. The creep extension structure 14 may also be referred to as having a number of ribs or protrusions that are formed by the portions of the housing 12 that are between the trenches 14'. The creep extension structure 14 may be formed simultaneously with molding of the housing 12 around the leads 16, 18. In certain embodiments, the creep extension structure 14 is disposed as part of the first side 12' and only along the shortest path of the housing 12 between the first lead 16 and one or more second leads 18.

[0028] 2 is a bottom perspective view of the semiconductor package 10 of FIG. 1. A second side 12″ of the housing 12 may be configured as a mounting side or surface for the semiconductor package 10. A thermal pad 16 TP And when the creep extension structure 14 is provided on the first side 12' as shown in FIG. 1, the second side 12'' may be substantially flat for ease of mounting as shown in FIG. 2.

[0029] 3 is a bottom perspective view of the semiconductor package 10 of FIG. 1 with the housing 12 shown transparent for purposes of illustration. As shown, the semiconductor die 20 is secured to the thermal pad 16 of the first lead 16. TP In certain embodiments, the semiconductor die 20 may be attached to the first lead 16 using a die attach material such as silver (Ag) sintered, gold-tin (AuSn) solder, and lead (Pb) based solder, among others. In this manner, heat generated by the semiconductor die 20 is transferred to the thermal pad 16. TP 1 through the first side 12' to the exterior of the housing 12. As indicated above, the semiconductor die 20 may embody any number of power transistors or diodes, such as MOSFETs or Schottky diodes. In certain aspects, the semiconductor die 20 may be referred to as a power semiconductor die and the semiconductor package 10 may be referred to as a power semiconductor package. In certain embodiments, the semiconductor die 20 may embody a silicon carbide (SiC) based MOSFET or Schottky diode. For the power handling and heat dissipation capabilities described herein, the semiconductor die 20 may be provided in a larger die size, such as a 7 mm by 7 mm die, although the disclosed principles are applicable to many different die sizes, for example, die sizes as small as 1 mm by 1 mm and even larger die sizes, such as 7 mm by 9 mm.

[0030] The first lead 16 comprises a plurality of integral pins 16 extending outside the housing 12 for increased current handling. P In certain embodiments, the first lead 16 may further include a semiconductor die 20 and a thermal pad 16. TPThe second lead 18 may be electrically coupled to a first contact 22 of the semiconductor die 20 located at the interface between the first and second leads 18 and the semiconductor die 20. The second lead 18 may be electrically coupled to one or more second contacts 24 of the included semiconductor die 20. In the context of a MOSFET die, the first contact 22 may embody a drain contact, while the one or more second contacts 24 embody a source contact of the MOSFET. In the context of a Schottky die, the first and second contacts 22, 24 may embody different ones of the anode and cathode contacts of the Schottky die. When multiple second contacts 24 are provided, a wire bond 26 may be provided that is electrically coupled to the second lead 18 and is utilized to interconnect with the second contacts 24 on the semiconductor die 20. The second lead 18 may include a bulged portion within the housing 12, which facilitates flexibility of bonding locations for the wire bonds 26. For increased current handling, the second lead 18 may include a plurality of second pins 18 extending outside the housing 12. P may include:

[0031] Depending on the application, the corresponding pin 28 P , 30 P , 32 P , 34 P , and 36 P A number of additional leads 28, 30, 32, 34 and 36 are connected to the second pin 18. PThe leads 30, 32, 34, and 36 may be arranged to extend out of the same end of the housing 12 as the lead 28. Some of the leads 30, 32, 34, and 36 may be electrically coupled to various portions of the semiconductor die 20. For example, the lead 28 may be coupled to a third contact 38 that embodies a gate contact of a MOSFET. In yet further embodiments, regardless of the type of semiconductor die 20, the other leads 30, 32, 34, and 36 may be electrically coupled to the semiconductor die 20 for other functions, including smart sensing capabilities, such as current sensing, temperature sensing, and / or sensing of other electrical signals. For example, the leads 30 and 32 may be electrically coupled to a portion of the second contact 24 to provide current sensing and / or Kelvin sensing, while the leads 34, 36 may be electrically coupled to other contacts 40, such as temperature sensing contacts, integrated with the semiconductor die 20. For high power applications, the wire bonds 26 for one or more of the second contacts 24 may be thicker than the wire bonds 42 for the other leads 28, 30, 32, 34 and 36. In yet further embodiments, any one or even all of the leads 18, 28, 30, 32, 34 and 36 may be electrically coupled to the semiconductor die 20 using metal clip interconnects, such as metal ribbons or copper (Cu) clips.

[0032] 4 is a perspective view of a cross section of the semiconductor package 10 taken along section line 4-4 of FIG. 1. As shown, the creep extension structure 14 is merely disposed as part of the first side 12' of the housing 12 to extend the creep distance along the surface of the housing 12 between the second lead 18 and the first lead 16. The creep distance also extends between the first lead 16 and any of the other leads 28, 30, 32, 34, and 36 as illustrated in FIG. 3. The creep extension structure 14 may include a plurality of slots or trenches 14' that extend from the first side 12' into the housing 12 to a location in the housing 12 that is above the lead 18 and above any of the other leads 28, 30, 32, 34, and 36 as illustrated in FIG. 3. The relative number and size of the trenches 14' of the creep extension structure 14 may be determined based on industry adopted standards for a particular device voltage-current rating. 4, the creep extension structure 14 includes six trenches 14' extending from the first side 12' into the housing 12. In other embodiments, a single trench 14' may be sufficient, while in still other embodiments, it may be necessary to have two or more trenches 14', or a number in the range of 2 to 10 trenches 14', or 2 to 15 trenches 14', based on, among other things, the intended power handling of the device. The trenches 14' may be confined to the first side 12' such that an outer surface of the first side 12' laterally bounds each of the trenches 14'.

[0033] 5 is a top view of the semiconductor package 10 of FIG. 1 illustrating the relative dimensions of the creep extension structures 14 along the first side 12′ of the housing 12. As shown, the semiconductor package 10 has two opposing peripheral edges 12′ of the housing 12. E1 , 12 E2 The first width W1 is measured between the pins 16 P and 18 P Two other opposing peripheral ends 12 each extend outside the housing 12. E3 , 12 E4The first width W1 extends between the thermal pads 16 TP and corresponds to a portion of first side 12' that includes the underlying semiconductor die (20 in FIG. 3). Semiconductor package 10 also has a second width W2 as measured in the same direction as first width W1, where second width W2 is narrower than first width W1. Second width W2 is spaced apart from protrusion 12 of housing 12, including a portion of creep extension structure 14. PR As shown, the thermal pad 16 TP The creep extension structure 14 occupies a width greater than the creep extension structure 14 as measured in the same direction as the first width W1 and the second width W2. The creep extension structure 14 is disposed adjacent the thermal pad 16. TP The first lead 18 may extend across the first side 12' of the housing from one location within the first width W1 adjacent or adjacent to the first lead 18 to another location within the second width W2 adjacent or adjacent to the second lead 18.

[0034] Projection 12 PR effectively forms an extension of the housing 12 to accommodate at least a portion of the creep extension structure 14. The protrusion 12 having a narrow second width W2 PR By forming a protrusion 12, the overall amount of material for the housing 12 may be reduced while still maintaining sufficient space for the creep extension structure 14. Such an arrangement may advantageously provide lighter weight, lower package cost, and improved moisture sensitivity characteristics. With respect to moisture sensitivity characteristics, the material of the housing 12, such as the EMC, may be hygroscopic. When the package is mounted to an external surface, such as a PCB, the associated heating required for reflow to connect the solder to the lead frame structure may cause moisture within the material of the housing 12 to leak out. If the distance for moisture to leak is too long within the housing 12, internal pressure may cause delamination during the reflow process. Thus, the protrusion 12 PR The narrower width W2 is defined to accommodate the creep extension structure 14 without adding excessive and unnecessary housing 12 material.

[0035] In certain semiconductor packages, the structure of the housing can create the shortest creep distance across the peripheral edges of the housing. This may be due to the relative location of the leads extending from the housing, the location of the creep extension structures, and combinations thereof. In such cases, high voltages between the package leads may be conducted along one or more peripheral edges of the housing even if the creep extension structures are present on the top or bottom side of the housing. According to aspects of the present disclosure, the creep extension structures may be disposed along one or more peripheral edges of the housing. In further aspects, the creep extension structures may be disposed as part of the first and / or second sides of the housing as well as part of one or more peripheral edges of the housing, thereby extending the creep distance along multiple ends and / or sides of the housing.

[0036] 6 is a top perspective view of a semiconductor package 44 that is similar to the semiconductor package 10 of FIG. 1 and includes an array of creep extension structures 14 that extend beyond the first side 12' of the housing 12. FIG. 7 is a bottom perspective view of the semiconductor package 44 of FIG. 6. In certain embodiments, the creep extension structures 14 are disposed as part of the first side 12' of the housing 12 and at two or more opposing ends 12. E1 , 12 E2 In particular, the two opposing ends 12 where the creep extension structure 14 is present E1 , 12 E2 The portion may be located between the first lead 16 and the second lead 18 (or any of the other leads 28-36 as shown in FIG. 3). As shown, the trench 14' of the creep extension structure 14 extends to the first side 12' and to the opposing end 12. E1 , 12 E2 Depending on the arrangement of the first lead 16 and the second lead 18 (or any of the other leads 28-36 as shown in FIG. 3), the creep extension structure 14 may extend from a single peripheral edge 12 of the housing 12 to a single peripheral edge 12 of the housing 12. E1 or 12 E2 In addition, the first lead 16 may be provided as part of the thermal pad 16TP For embodiments not including the above, the arrangement of the first lead 16 and the second lead 18 (or any of the other leads 28-36 as shown in FIG. 3) is such that the creep extension structure 14 is positioned at the end 12 of the housing 12. E1 , 12 E2 In yet a further embodiment, the creep extension structure 14 is disposed on only a portion of one or more of the first side 12', the second side 12" and the end 12 of the housing 12. E1 , 12 E2 It may be part of both.

[0037] Figure 8 is a bottom perspective view of the semiconductor package 44 of Figure 6 with the housing 12 depicted as transparent for purposes of illustration. As such, the view of the semiconductor package 44 provided in Figure 8 is similar to the view of the semiconductor package 10 provided in Figure 3. Differences include the placement of the creep extension structure 14 as described above with respect to Figure 6, and the relative dimensions of the lead frame structure based on the targeted power handling capability for the semiconductor package 44. For example, one or more, or even all, of the leads 16, 18, 28, 30, 32, 34, and 36 may be formed with a thickness greater than that of the semiconductor package 10 of Figure 3. In the context of semiconductor package 44, such thickness values ​​may be measured in a vertical direction from first side 12' to second side 12". In certain embodiments, the thickness of one or more of leads 16, 18, 28, 30, 32, 34, and 36 may be in the range of greater than 0.75 mm to 2 mm, or in the range of 0.75 mm to 1.5 mm. In contrast, the same thickness dimension for semiconductor package 10 of FIG. 3 may be less than 0.75 mm, such as in the range of 0.4 mm to 0.6 mm. By providing a greater thickness for one or more portions of the lead frame structure in combination with the placement of creep extension structure 14 as described above with respect to FIG. 6, semiconductor package 44 may exhibit even greater power handling and heat dissipation than semiconductor package 10 of FIG. 3.

[0038] 9 is a perspective view of a cross section of semiconductor package 44 taken along section line 9-9 of FIG. 6. As described above with respect to FIG. 6, creep extension structure 14 for semiconductor package 44 is formed on first side 12' of housing 12 and its peripheral edge (12 in FIG. 6). E1 , 12 E2 6). When creep extension structure 14 is limited only to first side 12', the limitations of the mold for housing 12 may only allow for a certain depth for trench 14'. From first side 12' and to the peripheral edge (12 in FIG. 6), E1 , 12 E2 Increasing the freedom of molding options for the housing 12 by extending the creep extension structures 14 along one or more of the conductors 14, 16, 18 may allow the trenches 14' to be formed deeper into the housing 12. In this regard, a greater depth for the trenches 14' may reduce the number of trenches 14' required to maintain the same creep distance. For example, only five trenches 14' or only three trenches 14' may provide a creep distance between the leads 16, 18 that is in the range of 10 mm to 20 mm, or in the range of 12 mm to 15 mm. As illustrated in FIG. 9, three trenches 14' are provided. In other embodiments and depending on the power handling requirements, any number of trenches 14' may be provided, such as in the range of 2 to 20 trenches 14', or in the range of 2 to 10 trenches 14', or in the range of 2 to 5 trenches 14', while still providing the desired power handling capability. Additionally, a greater depth for trench 14' may also allow for a reduced footprint for semiconductor package 44 while maintaining a targeted creep distance. In certain embodiments, the bottom of trench 14' in housing 12 may be formed with rounded surfaces for increased flexibility in molding options.

[0039] 10 is a top view of the semiconductor package 44 of FIG. 6 illustrating the relative dimensions of the creep extension structures 14 along the first side 12′ of the housing 12. In a similar manner as described above with respect to FIG. 5, the first width W1 is the width between the two opposing ends 12′ of the housing 12. E1 , 12 E2 These ends are defined as the distance between pin 16 P and 18 P The other two opposing ends 12 extend outside the housing 12. E3 , 12 E4 The creep extension structure 14 may also be defined by a first width W1, since the creep extension structure 14 extends across the entirety of the first side 12'. The top view provided by FIG. 10 also illustrates how the trench 14' is recessed into the peripheral edge 12 of the housing 12. E1 , 12 E2 The thermal pad 16 is also shown extending from the TP For embodiments including the creep extension structure 14, the thermal pad 16 TP 1 and may be along a portion of first side 12 ′ that is adjacent or adjacent to and between first lead 16 and second lead 18 .

[0040] FIG. 11 is similar to the semiconductor package 44 of FIG. 6 and illustrates the thermal pad 16 of the first lead 16. TP 1 is a top perspective view of a semiconductor package 46 further including an electrically insulating plate 48 disposed thereon. The electrically insulating plate 48 may comprise a thermally conductive material, such as a ceramic including aluminum nitride and / or aluminum oxide, or a direct bonded copper (DBC) plate. In this regard, the electrically insulating plate 48 may serve to further enhance heat dissipation from the first side 12' while also providing electrical isolation along the first side 12'. In such a configuration, the external electrical connection for the first lead 16 is provided to the pin 16. P11 , the semiconductor package 46 may be received by a central ceramic layer 16 of the semiconductor package 10 of FIG. 1 in a similar manner. In the context of a DBC plate including a central ceramic layer sandwiched between two surfaces of copper, the central ceramic layer thus provides electrical isolation along the first side 12'. While an electrically insulating plate 48 is provided in the context of FIG. 11 , the electrically insulating plate 48 may also be provided in a similar manner to the thermal pad 16 of the semiconductor package 10 of FIG. TP It may also be provided on the

[0041] As described above with respect to the embodiments of Figures 1-11, exemplary structures for semiconductor packages are disclosed that enable increased power handling. Such structures include an array of creep extension structures, a lead frame structure that may include an integral thermal pad, and additional thermal elements such as an electrically insulating plate. In the context of a power semiconductor package having a MOSFET, such as a SiC-based MOSFET, the power handling for any of the embodiments of Figures 1-11 may include a voltage-current rating in the range of 1700 volts (V) to 1900 V with currents up to about 250 amperes (A), or up to about 400 A. The voltage range may relate to package size and / or creep distance, while the current rating may relate to the selection of interconnect structures, including wire bonds, metal ribbons, and / or metal clips.

[0042] It is contemplated that any of the above aspects and / or various separate aspects and features as described herein may be combined for additional advantage. Any of the various embodiments as disclosed herein may be combined with one or more of the other disclosed embodiments, unless otherwise indicated herein.

[0043] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure, and all such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the accompanying claims.

Claims

1. A semiconductor die; a housing for the semiconductor die, the housing including a first side, a second side, and a creep extension structure that is a part of the first side; a first lead electrically connected to the semiconductor die, the first lead including a thermal pad and at least one pin extending away from the thermal pad, the thermal pad disposed adjacent the creepage extension structure on the first side; A semiconductor package comprising:

2. 2. The semiconductor package of claim 1, wherein the first side is a top side of the housing and the second side is a bottom side of the housing that forms a mounting surface of the housing.

3. 3. The semiconductor package of claim 1, further comprising a second lead electrically connected to the semiconductor die, the creep extension structure being disposed between the thermal pad and the second lead.

4. 4. The semiconductor package of claim 3, wherein the semiconductor die is a metal-oxide-semiconductor field effect transistor (MOSFET), the first lead is electrically coupled to a drain of the MOSFET, and the second lead is electrically coupled to a source of the MOSFET.

5. 5. The semiconductor package of claim 4, further comprising a third lead electrically coupled to a gate of said MOSFET, said creep extension structure being disposed between said thermal pad and said third lead.

6. 6. The semiconductor package of claim 5, further comprising a fourth lead, the creepage extension structure being disposed between the thermal pad and the fourth lead, the fourth lead being electrically coupled to a current sensor or a temperature sensor of the MOSFET.

7. The semiconductor device according to claim 4 , wherein the MOSFET is a silicon carbide (SiC) based MOSFET.

8. 4. The semiconductor package of claim 3, wherein the semiconductor die is a Schottky diode, the first lead is electrically coupled to a first contact of the Schottky diode, and the second lead is electrically coupled to a second contact of the Schottky diode.

9. 9. The semiconductor package of claim 1, wherein the housing forms a protrusion such that the first side includes a first width and a second width narrower than the first width, the thermal pad is disposed within the first width, and the creep extension structure is disposed to extend from the first width to the second width.

10. The semiconductor package of claim 1 , wherein the creep extension structure comprises one or more trenches extending to a first peripheral edge of the housing.

11. The semiconductor package of claim 10 , wherein the one or more trenches are laterally bounded by an outer surface of the housing on the first side of the housing.

12. The semiconductor package of claim 10 , wherein the one or more trenches are disposed to extend along one or more peripheral edges of the housing.

13. 11. The semiconductor package of claim 10, wherein the one or more trenches are disposed to extend across an entire width of the first side as measured between two opposing peripheral edges of the housing.

14. The semiconductor package of claim 1 , further comprising an electrically insulating plate disposed on the thermal pad.

15. 15. The semiconductor package of claim 14, wherein the electrically insulating plate comprises a direct bond copper plate.

16. 16. The semiconductor package of claim 1, wherein the thermal pad is integral with the first side.

17. A semiconductor die; a first lead in electrical communication with the semiconductor die; a second lead in electrical communication with the semiconductor die; A housing for the semiconductor die, the housing comprising: a first side, a second side, and a number of peripheral edges disposed between the first side and the second side; and a creep extension structure that is a portion of a first peripheral edge of the plurality of peripheral edges; A housing comprising: A semiconductor package comprising:

18. 20. The semiconductor package of claim 17, wherein the creep extension structure includes one or more trenches that extend to the first peripheral edge.

19. 19. The semiconductor package of claim 17 or 18, wherein the creep extension structure is further a portion of a second peripheral edge of the plurality of peripheral edges, the second peripheral edge being opposite the first peripheral edge.

20. 20. The semiconductor package of claim 17, wherein the creep extension structure is also part of the first side of the housing.

21. 21. The semiconductor package of claim 20, wherein the creep extension structure includes at least one trench that extends to the first peripheral edge and to the first side of the housing.

22. 22. The semiconductor package of claim 20 or 21, wherein the first lead comprises a thermal pad and at least one pin extending away from the thermal pad, the thermal pad being disposed adjacent the creepage extension structure on the first side.

23. 23. The semiconductor package of claim 22, further comprising an electrically insulating plate disposed on said thermal pad.

24. 24. The semiconductor package of claim 23, wherein the electrically insulating plate comprises a direct bond copper plate.

25. 25. The semiconductor package of claim 17, wherein the semiconductor die is a metal-oxide-semiconductor field effect transistor (MOSFET), the first lead is electrically connected to a drain of the MOSFET, and the second lead is electrically connected to a source of the MOSFET.

26. 25. The semiconductor package of claim 17, wherein the semiconductor die is a Schottky diode, the first lead is electrically coupled to a first contact of the Schottky diode, and the second lead is electrically coupled to a second contact of the Schottky diode.

27. A semiconductor die; a first lead in electrical communication with the semiconductor die; a second lead in electrical communication with the semiconductor die; a housing for the semiconductor die, the housing including a first side, a second side, and a creep extension structure that is a part of the housing, the creep extension structure forming a number of trenches that extend into the housing to provide a creep distance between the first lead and the second lead that is in the range of 12 millimeters (mm) to 20 mm; A semiconductor package comprising:

28. 28. The semiconductor package of claim 27, wherein the number of trenches is at least one.

29. 30. The semiconductor package of claim 28, wherein the number of trenches is six or less.

30. 30. The semiconductor package of claim 27, wherein the creep extension structure is part of the first side of the housing.

31. 31. The semiconductor package of claim 30, wherein the creep extension structure is further a part of one or more peripheral edges of the housing.

32. 32. The semiconductor package of claim 31, wherein the creep extension structure is also part of the second side of the housing.

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